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13 #ifndef LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
14 #define LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
19 #define GET_INSTRINFO_HEADER
20 #include "ARCGenInstrInfo.inc"
28 virtual void anchor();
56 bool AllowModify)
const override;
61 int *BytesAdded =
nullptr)
const override;
64 int *BytesRemoved =
nullptr)
const override;
68 bool KillSrc)
const override;
92 unsigned &OffsetPos)
const override;
103 #endif // LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
This is an optimization pass for GlobalISel generic memory operations.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Reg
All possible values of the reg field in the ModR/M byte.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned const TargetRegisterInfo * TRI
bool isPostIncrement(const MachineInstr &MI) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
Representation of each machine instruction.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
const ARCRegisterInfo & getRegisterInfo() const
ARCInstrInfo(const ARCSubtarget &)
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &, int *BytesAdded=nullptr) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
SmallVector< MachineOperand, 4 > Cond
Wrapper class representing virtual and physical registers.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Return the inverse opcode of the specified Branch instruction.
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
bool isPreIncrement(const MachineInstr &MI) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
LLVM Value Representation.
Wrapper class representing physical registers. Should be passed by value.