LLVM  12.0.0git
RISCVMCCodeEmitter.cpp
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1 //===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCVMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
16 #include "Utils/RISCVBaseInfo.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/Register.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstBuilder.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/Support/Casting.h"
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "mccodeemitter"
35 
36 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
37 STATISTIC(MCNumFixups, "Number of MC fixups created");
38 
39 namespace {
40 class RISCVMCCodeEmitter : public MCCodeEmitter {
41  RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;
42  void operator=(const RISCVMCCodeEmitter &) = delete;
43  MCContext &Ctx;
44  MCInstrInfo const &MCII;
45 
46 public:
47  RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
48  : Ctx(ctx), MCII(MCII) {}
49 
50  ~RISCVMCCodeEmitter() override {}
51 
52  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
54  const MCSubtargetInfo &STI) const override;
55 
56  void expandFunctionCall(const MCInst &MI, raw_ostream &OS,
58  const MCSubtargetInfo &STI) const;
59 
60  void expandAddTPRel(const MCInst &MI, raw_ostream &OS,
62  const MCSubtargetInfo &STI) const;
63 
64  /// TableGen'erated function for getting the binary encoding for an
65  /// instruction.
66  uint64_t getBinaryCodeForInstr(const MCInst &MI,
68  const MCSubtargetInfo &STI) const;
69 
70  /// Return binary encoding of operand. If the machine operand requires
71  /// relocation, record the relocation and return zero.
72  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
74  const MCSubtargetInfo &STI) const;
75 
76  unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
78  const MCSubtargetInfo &STI) const;
79 
80  unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
82  const MCSubtargetInfo &STI) const;
83 
84  unsigned getVMaskReg(const MCInst &MI, unsigned OpNo,
86  const MCSubtargetInfo &STI) const;
87 };
88 } // end anonymous namespace
89 
91  const MCRegisterInfo &MRI,
92  MCContext &Ctx) {
93  return new RISCVMCCodeEmitter(Ctx, MCII);
94 }
95 
96 // Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
97 // relocation types. We expand those pseudo-instructions while encoding them,
98 // meaning AUIPC and JALR won't go through RISCV MC to MC compressed
99 // instruction transformation. This is acceptable because AUIPC has no 16-bit
100 // form and C_JALR has no immediate operand field. We let linker relaxation
101 // deal with it. When linker relaxation is enabled, AUIPC and JALR have a
102 // chance to relax to JAL.
103 // If the C extension is enabled, JAL has a chance relax to C_JAL.
104 void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
106  const MCSubtargetInfo &STI) const {
107  MCInst TmpInst;
108  MCOperand Func;
109  Register Ra;
110  if (MI.getOpcode() == RISCV::PseudoTAIL) {
111  Func = MI.getOperand(0);
112  Ra = RISCV::X6;
113  } else if (MI.getOpcode() == RISCV::PseudoCALLReg) {
114  Func = MI.getOperand(1);
115  Ra = MI.getOperand(0).getReg();
116  } else if (MI.getOpcode() == RISCV::PseudoCALL) {
117  Func = MI.getOperand(0);
118  Ra = RISCV::X1;
119  } else if (MI.getOpcode() == RISCV::PseudoJump) {
120  Func = MI.getOperand(1);
121  Ra = MI.getOperand(0).getReg();
122  }
123  uint32_t Binary;
124 
125  assert(Func.isExpr() && "Expected expression");
126 
127  const MCExpr *CallExpr = Func.getExpr();
128 
129  // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
130  TmpInst = MCInstBuilder(RISCV::AUIPC)
131  .addReg(Ra)
132  .addOperand(MCOperand::createExpr(CallExpr));
133  Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
135 
136  if (MI.getOpcode() == RISCV::PseudoTAIL ||
137  MI.getOpcode() == RISCV::PseudoJump)
138  // Emit JALR X0, Ra, 0
139  TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
140  else
141  // Emit JALR Ra, Ra, 0
142  TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
143  Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
145 }
146 
147 // Expand PseudoAddTPRel to a simple ADD with the correct relocation.
148 void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS,
149  SmallVectorImpl<MCFixup> &Fixups,
150  const MCSubtargetInfo &STI) const {
151  MCOperand DestReg = MI.getOperand(0);
152  MCOperand SrcReg = MI.getOperand(1);
153  MCOperand TPReg = MI.getOperand(2);
154  assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 &&
155  "Expected thread pointer as second input to TP-relative add");
156 
157  MCOperand SrcSymbol = MI.getOperand(3);
158  assert(SrcSymbol.isExpr() &&
159  "Expected expression as third input to TP-relative add");
160 
161  const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
162  assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD &&
163  "Expected tprel_add relocation on TP-relative symbol");
164 
165  // Emit the correct tprel_add relocation for the symbol.
166  Fixups.push_back(MCFixup::create(
168 
169  // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled.
170  if (STI.getFeatureBits()[RISCV::FeatureRelax]) {
172  Fixups.push_back(MCFixup::create(
173  0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc()));
174  }
175 
176  // Emit a normal ADD instruction with the given operands.
177  MCInst TmpInst = MCInstBuilder(RISCV::ADD)
178  .addOperand(DestReg)
179  .addOperand(SrcReg)
180  .addOperand(TPReg);
181  uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
183 }
184 
185 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
186  SmallVectorImpl<MCFixup> &Fixups,
187  const MCSubtargetInfo &STI) const {
188  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
189  // Get byte count of instruction.
190  unsigned Size = Desc.getSize();
191 
192  // RISCVInstrInfo::getInstSizeInBytes hard-codes the number of expanded
193  // instructions for each pseudo, and must be updated when adding new pseudos
194  // or changing existing ones.
195  if (MI.getOpcode() == RISCV::PseudoCALLReg ||
196  MI.getOpcode() == RISCV::PseudoCALL ||
197  MI.getOpcode() == RISCV::PseudoTAIL ||
198  MI.getOpcode() == RISCV::PseudoJump) {
199  expandFunctionCall(MI, OS, Fixups, STI);
200  MCNumEmitted += 2;
201  return;
202  }
203 
204  if (MI.getOpcode() == RISCV::PseudoAddTPRel) {
205  expandAddTPRel(MI, OS, Fixups, STI);
206  MCNumEmitted += 1;
207  return;
208  }
209 
210  switch (Size) {
211  default:
212  llvm_unreachable("Unhandled encodeInstruction length!");
213  case 2: {
214  uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
215  support::endian::write<uint16_t>(OS, Bits, support::little);
216  break;
217  }
218  case 4: {
219  uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
221  break;
222  }
223  }
224 
225  ++MCNumEmitted; // Keep track of the # of mi's emitted.
226 }
227 
228 unsigned
229 RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
230  SmallVectorImpl<MCFixup> &Fixups,
231  const MCSubtargetInfo &STI) const {
232 
233  if (MO.isReg())
234  return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
235 
236  if (MO.isImm())
237  return static_cast<unsigned>(MO.getImm());
238 
239  llvm_unreachable("Unhandled expression!");
240  return 0;
241 }
242 
243 unsigned
244 RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
245  SmallVectorImpl<MCFixup> &Fixups,
246  const MCSubtargetInfo &STI) const {
247  const MCOperand &MO = MI.getOperand(OpNo);
248 
249  if (MO.isImm()) {
250  unsigned Res = MO.getImm();
251  assert((Res & 1) == 0 && "LSB is non-zero");
252  return Res >> 1;
253  }
254 
255  return getImmOpValue(MI, OpNo, Fixups, STI);
256 }
257 
258 unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
259  SmallVectorImpl<MCFixup> &Fixups,
260  const MCSubtargetInfo &STI) const {
261  bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax];
262  const MCOperand &MO = MI.getOperand(OpNo);
263 
264  MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
265  unsigned MIFrm = Desc.TSFlags & RISCVII::InstFormatMask;
266 
267  // If the destination is an immediate, there is nothing to do.
268  if (MO.isImm())
269  return MO.getImm();
270 
271  assert(MO.isExpr() &&
272  "getImmOpValue expects only expressions or immediates");
273  const MCExpr *Expr = MO.getExpr();
274  MCExpr::ExprKind Kind = Expr->getKind();
276  bool RelaxCandidate = false;
277  if (Kind == MCExpr::Target) {
278  const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
279 
280  switch (RVExpr->getKind()) {
284  llvm_unreachable("Unhandled fixup kind!");
286  // tprel_add is only used to indicate that a relocation should be emitted
287  // for an add instruction used in TP-relative addressing. It should not be
288  // expanded as if representing an actual instruction operand and so to
289  // encounter it here is an error.
291  "VK_RISCV_TPREL_ADD should not represent an instruction operand");
293  if (MIFrm == RISCVII::InstFormatI)
294  FixupKind = RISCV::fixup_riscv_lo12_i;
295  else if (MIFrm == RISCVII::InstFormatS)
296  FixupKind = RISCV::fixup_riscv_lo12_s;
297  else
298  llvm_unreachable("VK_RISCV_LO used with unexpected instruction format");
299  RelaxCandidate = true;
300  break;
302  FixupKind = RISCV::fixup_riscv_hi20;
303  RelaxCandidate = true;
304  break;
306  if (MIFrm == RISCVII::InstFormatI)
308  else if (MIFrm == RISCVII::InstFormatS)
310  else
312  "VK_RISCV_PCREL_LO used with unexpected instruction format");
313  RelaxCandidate = true;
314  break;
316  FixupKind = RISCV::fixup_riscv_pcrel_hi20;
317  RelaxCandidate = true;
318  break;
320  FixupKind = RISCV::fixup_riscv_got_hi20;
321  break;
323  if (MIFrm == RISCVII::InstFormatI)
325  else if (MIFrm == RISCVII::InstFormatS)
327  else
329  "VK_RISCV_TPREL_LO used with unexpected instruction format");
330  RelaxCandidate = true;
331  break;
333  FixupKind = RISCV::fixup_riscv_tprel_hi20;
334  RelaxCandidate = true;
335  break;
338  break;
340  FixupKind = RISCV::fixup_riscv_tls_gd_hi20;
341  break;
343  FixupKind = RISCV::fixup_riscv_call;
344  RelaxCandidate = true;
345  break;
347  FixupKind = RISCV::fixup_riscv_call_plt;
348  RelaxCandidate = true;
349  break;
350  }
351  } else if (Kind == MCExpr::SymbolRef &&
352  cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
353  if (Desc.getOpcode() == RISCV::JAL) {
354  FixupKind = RISCV::fixup_riscv_jal;
355  } else if (MIFrm == RISCVII::InstFormatB) {
356  FixupKind = RISCV::fixup_riscv_branch;
357  } else if (MIFrm == RISCVII::InstFormatCJ) {
358  FixupKind = RISCV::fixup_riscv_rvc_jump;
359  } else if (MIFrm == RISCVII::InstFormatCB) {
360  FixupKind = RISCV::fixup_riscv_rvc_branch;
361  }
362  }
363 
364  assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
365 
366  Fixups.push_back(
367  MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
368  ++MCNumFixups;
369 
370  // Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is
371  // enabled and the current fixup will result in a relocation that may be
372  // relaxed.
373  if (EnableRelax && RelaxCandidate) {
375  Fixups.push_back(
377  MI.getLoc()));
378  ++MCNumFixups;
379  }
380 
381  return 0;
382 }
383 
384 unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo,
385  SmallVectorImpl<MCFixup> &Fixups,
386  const MCSubtargetInfo &STI) const {
387  MCOperand MO = MI.getOperand(OpNo);
388  assert(MO.isReg() && "Expected a register.");
389 
390  switch (MO.getReg()) {
391  default:
392  llvm_unreachable("Invalid mask register.");
393  case RISCV::V0:
394  return 0;
395  case RISCV::NoRegister:
396  return 1;
397  }
398 }
399 
400 #include "RISCVGenMCCodeEmitter.inc"
bool isImm() const
Definition: MCInst.h:58
LLVM_NODISCARD std::enable_if_t< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type > dyn_cast(const Y &Val)
Definition: Casting.h:334
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:187
bool isReg() const
Definition: MCInst.h:57
VariantKind getKind() const
Definition: RISCVMCExpr.h:56
STATISTIC(NumFunctions, "Total number of functions")
static Lanai::Fixups FixupKind(const MCExpr *Expr)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:186
Target specific expression.
Definition: MCExpr.h:42
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
Context object for machine code objects.
Definition: MCContext.h:67
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:223
const MCExpr * getExpr() const
Definition: MCInst.h:95
MCInstBuilder & addOperand(const MCOperand &Op)
Add an operand.
Definition: MCInstBuilder.h:61
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition: Endian.h:97
int64_t getImm() const
Definition: MCInst.h:75
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
unsigned const MachineRegisterInfo * MRI
References to labels and assigned expressions.
Definition: MCExpr.h:40
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:22
bool isExpr() const
Definition: MCInst.h:60
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:98
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:180
SMLoc getLoc() const
Definition: MCInst.h:178
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:213
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
IRTranslator LLVM IR MI
unsigned getOpcode() const
Definition: MCInst.h:172
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:608