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28 #define DEBUG_TYPE "csky-isel-lowering"
30 STATISTIC(NumTailCalls,
"Number of tail calls");
32 #include "CSKYGenCallingConv.inc"
93 if (!Subtarget.
hasE2()) {
100 if (!Subtarget.
has2E3()) {
123 for (
auto VT : AllVTy) {
128 for (
auto CC : FPCCToExtend)
130 for (
auto Op : FPOpToExpand)
153 const Align FunctionAlignment(2);
160 switch (
Op.getOpcode()) {
164 return LowerGlobalAddress(
Op, DAG);
166 return LowerExternalSymbol(
Op, DAG);
168 return LowerGlobalTLSAddress(
Op, DAG);
170 return LowerJumpTable(
Op, DAG);
172 return LowerBlockAddress(
Op, DAG);
174 return LowerVASTART(
Op, DAG);
176 return LowerFRAMEADDR(
Op, DAG);
178 return LowerRETURNADDR(
Op, DAG);
233 RC = &CSKY::GPRRegClass;
237 : &CSKY::FPR32RegClass;
241 : &CSKY::FPR64RegClass;
274 ExtType,
DL, LocVT, Chain, FIN,
318 SDValue CSKYTargetLowering::LowerFormalArguments(
334 std::vector<SDValue> OutChains;
340 CCInfo.AnalyzeFormalArguments(
Ins, CCAssignFnForCall(CallConv, IsVarArg));
342 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
355 InVals.push_back(ArgValue);
359 const unsigned XLenInBytes = 4;
363 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
372 int VaArgOffset, VarArgsSaveSize;
376 if (ArgRegs.
size() == Idx) {
377 VaArgOffset = CCInfo.getNextStackOffset();
380 VarArgsSaveSize = XLenInBytes * (ArgRegs.
size() - Idx);
381 VaArgOffset = -VarArgsSaveSize;
391 for (
unsigned I = Idx;
I < ArgRegs.
size();
392 ++
I, VaArgOffset += XLenInBytes) {
400 cast<StoreSDNode>(
Store.getNode())
402 ->setValue((
Value *)
nullptr);
403 OutChains.push_back(
Store);
410 if (!OutChains.empty()) {
411 OutChains.push_back(Chain);
418 bool CSKYTargetLowering::CanLowerReturn(
423 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
438 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
444 for (
unsigned i = 0,
e = CSKYLocs.size();
i <
e; ++
i) {
460 assert(RegLo < CSKY::R31 &&
"Invalid register pair");
484 RetOps.push_back(Glue);
496 SDValue CSKYTargetLowering::LowerCall(CallLoweringInfo &CLI,
505 bool &IsTailCall = CLI.IsTailCall;
507 bool IsVarArg = CLI.IsVarArg;
517 ArgCCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, IsVarArg));
525 else if (CLI.CB && CLI.CB->isMustTailCall())
527 "site marked musttail");
530 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
534 for (
unsigned i = 0,
e = Outs.size();
i !=
e; ++
i) {
552 ByValArgs.push_back(FIPtr);
562 for (
unsigned i = 0,
j = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
577 RegsToPass.push_back(std::make_pair(RegLo, Lo));
579 if (RegLo == CSKY::R3) {
585 MemOpChains.push_back(
589 assert(RegLo < CSKY::R31 &&
"Invalid register pair");
591 RegsToPass.push_back(std::make_pair(RegHigh, Hi));
600 ArgValue = ByValArgs[
j++];
604 RegsToPass.push_back(std::make_pair(VA.
getLocReg(), ArgValue));
607 assert(!IsTailCall &&
"Tail call not allowed if stack is used "
608 "for passing parameters");
618 MemOpChains.push_back(
624 if (!MemOpChains.empty())
630 for (
auto &
Reg : RegsToPass) {
637 bool IsRegCall =
false;
639 Ops.push_back(Chain);
648 Ops.push_back(getAddr<GlobalAddressSDNode, true>(
S, DAG, IsLocal));
650 Ops.push_back(getTargetNode(cast<GlobalAddressSDNode>(Callee),
DL, Ty,
652 Ops.push_back(getTargetConstantPoolValue(
661 Ops.push_back(getAddr<ExternalSymbolSDNode, true>(
S, DAG, IsLocal));
663 Ops.push_back(getTargetNode(cast<ExternalSymbolSDNode>(Callee),
DL, Ty,
665 Ops.push_back(getTargetConstantPoolValue(
670 Ops.push_back(Callee);
675 for (
auto &
Reg : RegsToPass)
682 assert(
Mask &&
"Missing call preserved mask for calling convention");
712 RetCCInfo.AnalyzeCallResult(
Ins, CCAssignFnForReturn(CallConv, IsVarArg));
715 for (
auto &VA : CSKYLocs) {
732 RetValue, RetValue2);
737 InVals.push_back(RetValue);
744 bool IsVarArg)
const {
746 return RetCC_CSKY_ABIV2_SOFT;
748 return RetCC_CSKY_ABIV2_FP;
752 bool IsVarArg)
const {
754 return CC_CSKY_ABIV2_SOFT;
756 return CC_CSKY_ABIV2_FP;
772 assert(0 &&
"unknown CSKYII Modifier");
779 unsigned Flags)
const {
787 CSKYTargetLowering::getConstraintType(
StringRef Constraint)
const {
788 if (Constraint.
size() == 1) {
789 switch (Constraint[0]) {
808 std::pair<unsigned, const TargetRegisterClass *>
812 if (Constraint.
size() == 1) {
813 switch (Constraint[0]) {
815 return std::make_pair(0U, &CSKY::GPRRegClass);
817 return std::make_pair(0U, &CSKY::mGPRRegClass);
819 return std::make_pair(0U, &CSKY::sGPRRegClass);
821 return std::make_pair(CSKY::R14, &CSKY::GPRRegClass);
823 return std::make_pair(
CSKY::C, &CSKY::CARRYRegClass);
828 return std::make_pair(0U, &CSKY::sFPR32RegClass);
832 return std::make_pair(0U, &CSKY::sFPR64RegClass);
836 return std::make_pair(0U, &CSKY::sFPR32RegClass);
838 return std::make_pair(0U, &CSKY::FPR32RegClass);
840 return std::make_pair(0U, &CSKY::sFPR64RegClass);
842 return std::make_pair(0U, &CSKY::FPR64RegClass);
849 if (Constraint ==
"{c}")
850 return std::make_pair(
CSKY::C, &CSKY::CARRYRegClass);
857 .
Case(
"{a0}", CSKY::R0)
858 .
Case(
"{a1}", CSKY::R1)
860 .
Case(
"{a3}", CSKY::R3)
862 .
Case(
"{l1}", CSKY::R5)
864 .
Case(
"{l3}", CSKY::R7)
865 .
Case(
"{l4}", CSKY::R8)
866 .
Case(
"{l5}", CSKY::R9)
867 .
Case(
"{l6}", CSKY::R10)
868 .
Case(
"{l7}", CSKY::R11)
869 .
Case(
"{t0}", CSKY::R12)
870 .
Case(
"{t1}", CSKY::R13)
871 .
Case(
"{sp}", CSKY::R14)
872 .
Case(
"{lr}", CSKY::R15)
873 .
Case(
"{l8}", CSKY::R16)
874 .
Case(
"{l9}", CSKY::R17)
875 .
Case(
"{t2}", CSKY::R18)
876 .
Case(
"{t3}", CSKY::R19)
877 .
Case(
"{t4}", CSKY::R20)
878 .
Case(
"{t5}", CSKY::R21)
879 .
Case(
"{t6}", CSKY::R22)
880 .
Cases(
"{t7}",
"{fp}", CSKY::R23)
881 .
Cases(
"{t8}",
"{top}", CSKY::R24)
882 .
Cases(
"{t9}",
"{bsp}", CSKY::R25)
883 .
Case(
"{r26}", CSKY::R26)
884 .
Case(
"{r27}", CSKY::R27)
885 .
Cases(
"{gb}",
"{rgb}",
"{rdb}", CSKY::R28)
886 .
Cases(
"{tb}",
"{rtb}", CSKY::R29)
887 .
Case(
"{svbr}", CSKY::R30)
888 .
Case(
"{tls}", CSKY::R31)
891 if (XRegFromAlias != CSKY::NoRegister)
892 return std::make_pair(XRegFromAlias, &CSKY::GPRRegClass);
903 .
Cases(
"{fr0}",
"{vr0}", CSKY::F0_32)
904 .
Cases(
"{fr1}",
"{vr1}", CSKY::F1_32)
905 .
Cases(
"{fr2}",
"{vr2}", CSKY::F2_32)
906 .
Cases(
"{fr3}",
"{vr3}", CSKY::F3_32)
907 .
Cases(
"{fr4}",
"{vr4}", CSKY::F4_32)
908 .
Cases(
"{fr5}",
"{vr5}", CSKY::F5_32)
909 .
Cases(
"{fr6}",
"{vr6}", CSKY::F6_32)
910 .
Cases(
"{fr7}",
"{vr7}", CSKY::F7_32)
911 .
Cases(
"{fr8}",
"{vr8}", CSKY::F8_32)
912 .
Cases(
"{fr9}",
"{vr9}", CSKY::F9_32)
913 .
Cases(
"{fr10}",
"{vr10}", CSKY::F10_32)
914 .
Cases(
"{fr11}",
"{vr11}", CSKY::F11_32)
915 .
Cases(
"{fr12}",
"{vr12}", CSKY::F12_32)
916 .
Cases(
"{fr13}",
"{vr13}", CSKY::F13_32)
917 .
Cases(
"{fr14}",
"{vr14}", CSKY::F14_32)
918 .
Cases(
"{fr15}",
"{vr15}", CSKY::F15_32)
919 .
Cases(
"{fr16}",
"{vr16}", CSKY::F16_32)
920 .
Cases(
"{fr17}",
"{vr17}", CSKY::F17_32)
921 .
Cases(
"{fr18}",
"{vr18}", CSKY::F18_32)
922 .
Cases(
"{fr19}",
"{vr19}", CSKY::F19_32)
923 .
Cases(
"{fr20}",
"{vr20}", CSKY::F20_32)
924 .
Cases(
"{fr21}",
"{vr21}", CSKY::F21_32)
925 .
Cases(
"{fr22}",
"{vr22}", CSKY::F22_32)
926 .
Cases(
"{fr23}",
"{vr23}", CSKY::F23_32)
927 .
Cases(
"{fr24}",
"{vr24}", CSKY::F24_32)
928 .
Cases(
"{fr25}",
"{vr25}", CSKY::F25_32)
929 .
Cases(
"{fr26}",
"{vr26}", CSKY::F26_32)
930 .
Cases(
"{fr27}",
"{vr27}", CSKY::F27_32)
931 .
Cases(
"{fr28}",
"{vr28}", CSKY::F28_32)
932 .
Cases(
"{fr29}",
"{vr29}", CSKY::F29_32)
933 .
Cases(
"{fr30}",
"{vr30}", CSKY::F30_32)
934 .
Cases(
"{fr31}",
"{vr31}", CSKY::F31_32)
936 if (FReg != CSKY::NoRegister) {
937 assert(CSKY::F0_32 <= FReg && FReg <= CSKY::F31_32 &&
"Unknown fp-reg");
938 unsigned RegNo = FReg - CSKY::F0_32;
939 unsigned DReg = CSKY::F0_64 + RegNo;
942 return std::make_pair(
DReg, &CSKY::sFPR64RegClass);
944 return std::make_pair(
DReg, &CSKY::FPR64RegClass);
946 return std::make_pair(FReg, &CSKY::sFPR32RegClass);
948 return std::make_pair(FReg, &CSKY::FPR32RegClass);
977 F->insert(It, copyMBB);
978 F->insert(It, sinkMBB);
986 BB->addSuccessor(copyMBB);
987 BB->addSuccessor(sinkMBB);
1000 BB->addSuccessor(sinkMBB);
1013 MI.eraseFromParent();
1019 CSKYTargetLowering::EmitInstrWithCustomInserter(
MachineInstr &
MI,
1021 switch (
MI.getOpcode()) {
1026 if (Subtarget.
hasE2())
1040 unsigned Flags)
const {
1051 unsigned Flags)
const {
1061 unsigned Flags)
const {
1070 unsigned Flags)
const {
1076 unsigned Flags)
const {
1082 unsigned Flags)
const {
1088 unsigned Flags)
const {
1093 const char *CSKYTargetLowering::getTargetNodeName(
unsigned Opcode)
const {
1098 return "CSKYISD::NIE";
1100 return "CSKYISD::NIR";
1102 return "CSKYISD::RET";
1104 return "CSKYISD::CALL";
1106 return "CSKYISD::CALLReg";
1108 return "CSKYISD::TAIL";
1110 return "CSKYISD::TAILReg";
1112 return "CSKYISD::LOAD_ADDR";
1114 return "CSKYISD::BITCAST_TO_LOHI";
1116 return "CSKYISD::BITCAST_FROM_LOHI";
1123 EVT Ty =
Op.getValueType();
1125 int64_t
Offset =
N->getOffset();
1129 SDValue Addr = getAddr<GlobalAddressSDNode, false>(
N, DAG, IsLocal);
1145 return getAddr(
N, DAG,
false);
1152 return getAddr<JumpTableSDNode, false>(
N, DAG);
1159 return getAddr(
N, DAG);
1172 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
1184 EVT VT =
Op.getValueType();
1186 unsigned Depth = cast<ConstantSDNode>(
Op.getOperand(0))->getZExtValue();
1205 EVT VT =
Op.getValueType();
1207 unsigned Depth = cast<ConstantSDNode>(
Op.getOperand(0))->getZExtValue();
1209 SDValue FrameAddr = LowerFRAMEADDR(
Op, DAG);
1221 Register CSKYTargetLowering::getExceptionPointerRegister(
1222 const Constant *PersonalityFn)
const {
1226 Register CSKYTargetLowering::getExceptionSelectorRegister(
1227 const Constant *PersonalityFn)
const {
1234 EVT Ty =
Op.getValueType();
1236 int64_t
Offset =
N->getOffset();
1243 Addr = getStaticTLSAddr(
N, DAG,
false);
1246 Addr = getStaticTLSAddr(
N, DAG,
true);
1250 Addr = getDynamicTLSAddr(
N, DAG);
1266 bool UseGOT)
const {
1276 bool AddCurrentAddr = UseGOT ?
true :
false;
1277 unsigned char PCAjust = UseGOT ? 4 : 0;
1281 Flag, AddCurrentAddr, CSKYPCLabelIndex);
1330 Args.push_back(Entry);
StringSwitch & Case(StringLiteral S, T Value)
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
This is an optimization pass for GlobalISel generic memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void setReturnAddressIsTaken(bool s)
static CSKYConstantPoolJT * Create(Type *Ty, int JTI, unsigned PCAdj, CSKYCP::CSKYCPModifier Modifier)
@ BR_JT
BR_JT - Jumptable branch.
void addNoMergeSiteInfo(const SDNode *Node, bool NoMerge)
Set NoMergeSiteInfo to be associated with Node if NoMerge is true.
CCState - This class holds information needed while lowering arguments and return values.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
SDNode * getNode() const
get the SDNode which holds the desired result
@ BSWAP
Byte Swap and Counting operators.
LLVM_NODISCARD R Default(T Value)
static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
static CSKYConstantPoolConstant * Create(const Constant *C, CSKYCP::CSKYCPKind Kind, unsigned PCAdjust, CSKYCP::CSKYCPModifier Modifier, bool AddCurrentAddress, unsigned ID=0)
Reg
All possible values of the reg field in the ModR/M byte.
void setVarArgsSaveSize(int Size)
static CSKYCP::CSKYCPModifier getModifier(unsigned Flags)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isPositionIndependent() const
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
void setVarArgsFrameIndex(int v)
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
unsigned const TargetRegisterInfo * TRI
static IntegerType * getInt32Ty(LLVMContext &C)
LLVMContext * getContext() const
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
SDValue getRegister(unsigned Reg, EVT VT)
LLVM Basic Block Representation.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
@ BR_CC
BR_CC - Conditional branch.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
TargetInstrInfo - Interface to description of machine instruction set.
CCValAssign - Represent assignment of one arg/retval to a location.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
bool hasFPUv2SingleFloat() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
void setOperationAction(ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Register getLocReg() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
(vector float) vec_cmpeq(*A, *B) C
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
int getVarArgsFrameIndex()
@ ZeroOrNegativeOneBooleanContent
const HexagonInstrInfo * TII
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Class to represent integer types.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
STATISTIC(NumFunctions, "Total number of functions")
LocInfo getLocInfo() const
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
const CSKYRegisterInfo * getRegisterInfo() const override
unsigned getLocMemOffset() const
This struct is a compact representation of a valid (non-zero power of two) alignment.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static const MCPhysReg GPRArgRegs[]
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
static CSKYConstantPoolSymbol * Create(Type *Ty, const char *S, unsigned PCAdjust, CSKYCP::CSKYCPModifier Modifier)
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
This is an important base class in LLVM.
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Representation of each machine instruction.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Module * getParent()
Get the module that this global value is contained inside of...
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
This class contains a discriminated union of information about pointers in memory operands,...
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
This is an important class for using LLVM in a threaded context.
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
CSKYConstantPoolValue - CSKY specific constantpool value.
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
bool useHardFloat() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
unsigned createPICLabelUId()
LLVM_NODISCARD std::string lower() const
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
void setHasTailCall(bool V=true)
SDValue getValue(unsigned R) const
This structure contains all information that is necessary for lowering calls.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static SDValue unpack64(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
bool useHardFloatABI() const
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0)
static SDValue unpackFromRegLoc(const CSKYSubtarget &Subtarget, SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool isVector() const
Return true if this is a vector value type.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
StringRef - Represent a constant reference to a string, i.e.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Register getFrameRegister(const MachineFunction &MF) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
C - The default llvm calling convention, compatible with C.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
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@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
StringSwitch & Cases(StringLiteral S0, StringLiteral S1, T Value)
Wrapper class representing virtual and physical registers.
std::vector< ArgListEntry > ArgListTy
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
amdgpu Simplify well known AMD library false FunctionCallee Callee
const TargetMachine & getTargetMachine() const
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
unsigned getByValSize() const
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
Function & getFunction()
Return the LLVM function that this machine code represents.
Iterator for intrusive lists based on ilist_node.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
const DataLayout & getDataLayout() const
bool hasFPUv3SingleFloat() const
bool hasFPUv2DoubleFloat() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool hasFPUv3DoubleFloat() const
static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ ADD
Simple integer binary arithmetic operators.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Align getNonZeroByValAlign() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
SDValue getRegisterMask(const uint32_t *RegMask)
size_t size() const
size - Get the array size.
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
CSKYTargetLowering(const TargetMachine &TM, const CSKYSubtarget &STI)
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
void setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
A switch()-like statement whose cases are string literals.
const char LLVMTargetMachineRef TM
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
MachineFunction & getMachineFunction() const
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
SDValue getExternalSymbol(const char *Sym, EVT VT)
void setFrameAddressIsTaken(bool T)
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
LLVM Value Representation.
static MachineBasicBlock * emitSelectPseudo(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode)
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static MVT getIntegerVT(unsigned BitWidth)
@ UndefinedBooleanContent