LLVM 19.0.0git
CSKYISelLowering.cpp
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1//===-- CSKYISelLowering.cpp - CSKY DAG Lowering Implementation ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that CSKY uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "CSKYISelLowering.h"
15#include "CSKYCallingConv.h"
18#include "CSKYRegisterInfo.h"
19#include "CSKYSubtarget.h"
20#include "llvm/ADT/Statistic.h"
24#include "llvm/Support/Debug.h"
25
26using namespace llvm;
27
28#define DEBUG_TYPE "csky-isel-lowering"
29
30STATISTIC(NumTailCalls, "Number of tail calls");
31
32#include "CSKYGenCallingConv.inc"
33
34static const MCPhysReg GPRArgRegs[] = {CSKY::R0, CSKY::R1, CSKY::R2, CSKY::R3};
35
37 const CSKYSubtarget &STI)
38 : TargetLowering(TM), Subtarget(STI) {
39 // Register Class
40 addRegisterClass(MVT::i32, &CSKY::GPRRegClass);
41
42 if (STI.useHardFloat()) {
43 if (STI.hasFPUv2SingleFloat())
44 addRegisterClass(MVT::f32, &CSKY::sFPR32RegClass);
45 else if (STI.hasFPUv3SingleFloat())
46 addRegisterClass(MVT::f32, &CSKY::FPR32RegClass);
47
48 if (STI.hasFPUv2DoubleFloat())
49 addRegisterClass(MVT::f64, &CSKY::sFPR64RegClass);
50 else if (STI.hasFPUv3DoubleFloat())
51 addRegisterClass(MVT::f64, &CSKY::FPR64RegClass);
52 }
53
57
80
81 setLoadExtAction(ISD::EXTLOAD, MVT::i32, MVT::i1, Promote);
82 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i1, Promote);
83 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, MVT::i1, Promote);
84
89 if (!Subtarget.hasE2()) {
91 }
94
95 if (!Subtarget.hasE2()) {
96 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i8, Expand);
97 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i16, Expand);
100 }
101
102 if (!Subtarget.has2E3()) {
108 }
109
111
112 // Float
113
114 ISD::CondCode FPCCToExtend[] = {
117 };
118
119 ISD::NodeType FPOpToExpand[] = {
122
123 if (STI.useHardFloat()) {
124
125 MVT AllVTy[] = {MVT::f32, MVT::f64};
126
127 for (auto VT : AllVTy) {
131
132 for (auto CC : FPCCToExtend)
134 for (auto Op : FPOpToExpand)
136 }
137
138 if (STI.hasFPUv2SingleFloat() || STI.hasFPUv3SingleFloat()) {
140 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
141 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
142 }
143 if (STI.hasFPUv2DoubleFloat() || STI.hasFPUv3DoubleFloat()) {
144 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
145 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
146 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
147 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
148 }
149 }
150
151 // Compute derived properties from the register classes.
153
156
157 // TODO: Add atomic support fully.
159
163}
164
166 SelectionDAG &DAG) const {
167 switch (Op.getOpcode()) {
168 default:
169 llvm_unreachable("unimplemented op");
171 return LowerGlobalAddress(Op, DAG);
173 return LowerExternalSymbol(Op, DAG);
175 return LowerGlobalTLSAddress(Op, DAG);
176 case ISD::JumpTable:
177 return LowerJumpTable(Op, DAG);
179 return LowerBlockAddress(Op, DAG);
181 return LowerConstantPool(Op, DAG);
182 case ISD::VASTART:
183 return LowerVASTART(Op, DAG);
184 case ISD::FRAMEADDR:
185 return LowerFRAMEADDR(Op, DAG);
186 case ISD::RETURNADDR:
187 return LowerRETURNADDR(Op, DAG);
188 }
189}
190
192 LLVMContext &Context, EVT VT) const {
193 if (!VT.isVector())
194 return MVT::i32;
195
197}
198
200 const CCValAssign &VA, const SDLoc &DL) {
201 EVT LocVT = VA.getLocVT();
202
203 switch (VA.getLocInfo()) {
204 default:
205 llvm_unreachable("Unexpected CCValAssign::LocInfo");
207 break;
209 Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val);
210 break;
211 }
212 return Val;
213}
214
216 const CCValAssign &VA, const SDLoc &DL) {
217 switch (VA.getLocInfo()) {
218 default:
219 llvm_unreachable("Unexpected CCValAssign::LocInfo");
221 break;
223 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
224 break;
225 }
226 return Val;
227}
228
229static SDValue unpackFromRegLoc(const CSKYSubtarget &Subtarget,
230 SelectionDAG &DAG, SDValue Chain,
231 const CCValAssign &VA, const SDLoc &DL) {
234 EVT LocVT = VA.getLocVT();
235 SDValue Val;
236 const TargetRegisterClass *RC;
237
238 switch (LocVT.getSimpleVT().SimpleTy) {
239 default:
240 llvm_unreachable("Unexpected register type");
241 case MVT::i32:
242 RC = &CSKY::GPRRegClass;
243 break;
244 case MVT::f32:
245 RC = Subtarget.hasFPUv2SingleFloat() ? &CSKY::sFPR32RegClass
246 : &CSKY::FPR32RegClass;
247 break;
248 case MVT::f64:
249 RC = Subtarget.hasFPUv2DoubleFloat() ? &CSKY::sFPR64RegClass
250 : &CSKY::FPR64RegClass;
251 break;
252 }
253
254 Register VReg = RegInfo.createVirtualRegister(RC);
255 RegInfo.addLiveIn(VA.getLocReg(), VReg);
256 Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
257
258 return convertLocVTToValVT(DAG, Val, VA, DL);
259}
260
262 const CCValAssign &VA, const SDLoc &DL) {
264 MachineFrameInfo &MFI = MF.getFrameInfo();
265 EVT LocVT = VA.getLocVT();
266 EVT ValVT = VA.getValVT();
268 int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
269 VA.getLocMemOffset(), /*Immutable=*/true);
270 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
271 SDValue Val;
272
273 ISD::LoadExtType ExtType;
274 switch (VA.getLocInfo()) {
275 default:
276 llvm_unreachable("Unexpected CCValAssign::LocInfo");
279 ExtType = ISD::NON_EXTLOAD;
280 break;
281 }
282 Val = DAG.getExtLoad(
283 ExtType, DL, LocVT, Chain, FIN,
285 return Val;
286}
287
288static SDValue unpack64(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA,
289 const SDLoc &DL) {
290 assert(VA.getLocVT() == MVT::i32 &&
291 (VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::i64) &&
292 "Unexpected VA");
294 MachineFrameInfo &MFI = MF.getFrameInfo();
296
297 if (VA.isMemLoc()) {
298 // f64/i64 is passed on the stack.
299 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), /*Immutable=*/true);
300 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
301 return DAG.getLoad(VA.getValVT(), DL, Chain, FIN,
303 }
304
305 assert(VA.isRegLoc() && "Expected register VA assignment");
306
307 Register LoVReg = RegInfo.createVirtualRegister(&CSKY::GPRRegClass);
308 RegInfo.addLiveIn(VA.getLocReg(), LoVReg);
309 SDValue Lo = DAG.getCopyFromReg(Chain, DL, LoVReg, MVT::i32);
310 SDValue Hi;
311 if (VA.getLocReg() == CSKY::R3) {
312 // Second half of f64/i64 is passed on the stack.
313 int FI = MFI.CreateFixedObject(4, 0, /*Immutable=*/true);
314 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
315 Hi = DAG.getLoad(MVT::i32, DL, Chain, FIN,
317 } else {
318 // Second half of f64/i64 is passed in another GPR.
319 Register HiVReg = RegInfo.createVirtualRegister(&CSKY::GPRRegClass);
320 RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg);
321 Hi = DAG.getCopyFromReg(Chain, DL, HiVReg, MVT::i32);
322 }
323 return DAG.getNode(CSKYISD::BITCAST_FROM_LOHI, DL, VA.getValVT(), Lo, Hi);
324}
325
326// Transform physical registers into virtual registers.
327SDValue CSKYTargetLowering::LowerFormalArguments(
328 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
329 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
330 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
331
332 switch (CallConv) {
333 default:
334 report_fatal_error("Unsupported calling convention");
335 case CallingConv::C:
337 break;
338 }
339
341
342 // Used with vargs to acumulate store chains.
343 std::vector<SDValue> OutChains;
344
345 // Assign locations to all of the incoming arguments.
347 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
348
349 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, IsVarArg));
350
351 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
352 CCValAssign &VA = ArgLocs[i];
353 SDValue ArgValue;
354
355 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
356
357 if (IsF64OnCSKY)
358 ArgValue = unpack64(DAG, Chain, VA, DL);
359 else if (VA.isRegLoc())
360 ArgValue = unpackFromRegLoc(Subtarget, DAG, Chain, VA, DL);
361 else
362 ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);
363
364 InVals.push_back(ArgValue);
365 }
366
367 if (IsVarArg) {
368 const unsigned XLenInBytes = 4;
369 const MVT XLenVT = MVT::i32;
370
372 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
373 const TargetRegisterClass *RC = &CSKY::GPRRegClass;
374 MachineFrameInfo &MFI = MF.getFrameInfo();
377
378 // Offset of the first variable argument from stack pointer, and size of
379 // the vararg save area. For now, the varargs save area is either zero or
380 // large enough to hold a0-a4.
381 int VaArgOffset, VarArgsSaveSize;
382
383 // If all registers are allocated, then all varargs must be passed on the
384 // stack and we don't need to save any argregs.
385 if (ArgRegs.size() == Idx) {
386 VaArgOffset = CCInfo.getStackSize();
387 VarArgsSaveSize = 0;
388 } else {
389 VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);
390 VaArgOffset = -VarArgsSaveSize;
391 }
392
393 // Record the frame index of the first variable argument
394 // which is a value necessary to VASTART.
395 int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
396 CSKYFI->setVarArgsFrameIndex(FI);
397
398 // Copy the integer registers that may have been used for passing varargs
399 // to the vararg save area.
400 for (unsigned I = Idx; I < ArgRegs.size();
401 ++I, VaArgOffset += XLenInBytes) {
402 const Register Reg = RegInfo.createVirtualRegister(RC);
403 RegInfo.addLiveIn(ArgRegs[I], Reg);
404 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT);
405 FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
406 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
407 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
409 cast<StoreSDNode>(Store.getNode())
410 ->getMemOperand()
411 ->setValue((Value *)nullptr);
412 OutChains.push_back(Store);
413 }
414 CSKYFI->setVarArgsSaveSize(VarArgsSaveSize);
415 }
416
417 // All stores are grouped in one node to allow the matching between
418 // the size of Ins and InVals. This only happens for vararg functions.
419 if (!OutChains.empty()) {
420 OutChains.push_back(Chain);
421 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
422 }
423
424 return Chain;
425}
426
427bool CSKYTargetLowering::CanLowerReturn(
428 CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
429 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
431 CCState CCInfo(CallConv, IsVarArg, MF, CSKYLocs, Context);
432 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
433}
434
436CSKYTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
437 bool IsVarArg,
439 const SmallVectorImpl<SDValue> &OutVals,
440 const SDLoc &DL, SelectionDAG &DAG) const {
441 // Stores the assignment of the return value to a location.
443
444 // Info about the registers and stack slot.
445 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), CSKYLocs,
446 *DAG.getContext());
447 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
448
449 SDValue Glue;
450 SmallVector<SDValue, 4> RetOps(1, Chain);
451
452 // Copy the result values into the output registers.
453 for (unsigned i = 0, e = CSKYLocs.size(); i < e; ++i) {
454 SDValue Val = OutVals[i];
455 CCValAssign &VA = CSKYLocs[i];
456 assert(VA.isRegLoc() && "Can only return in registers!");
457
458 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
459
460 if (IsF64OnCSKY) {
461
462 assert(VA.isRegLoc() && "Expected return via registers");
464 DAG.getVTList(MVT::i32, MVT::i32), Val);
465 SDValue Lo = Split64.getValue(0);
466 SDValue Hi = Split64.getValue(1);
467
468 Register RegLo = VA.getLocReg();
469 assert(RegLo < CSKY::R31 && "Invalid register pair");
470 Register RegHi = RegLo + 1;
471
472 Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);
473 Glue = Chain.getValue(1);
474 RetOps.push_back(DAG.getRegister(RegLo, MVT::i32));
475 Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue);
476 Glue = Chain.getValue(1);
477 RetOps.push_back(DAG.getRegister(RegHi, MVT::i32));
478 } else {
479 // Handle a 'normal' return.
480 Val = convertValVTToLocVT(DAG, Val, VA, DL);
481 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);
482
483 // Guarantee that all emitted copies are stuck together.
484 Glue = Chain.getValue(1);
485 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
486 }
487 }
488
489 RetOps[0] = Chain; // Update chain.
490
491 // Add the glue node if we have it.
492 if (Glue.getNode()) {
493 RetOps.push_back(Glue);
494 }
495
496 // Interrupt service routines use different return instructions.
497 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt"))
498 return DAG.getNode(CSKYISD::NIR, DL, MVT::Other, RetOps);
499
500 return DAG.getNode(CSKYISD::RET, DL, MVT::Other, RetOps);
501}
502
503// Lower a call to a callseq_start + CALL + callseq_end chain, and add input
504// and output parameter nodes.
505SDValue CSKYTargetLowering::LowerCall(CallLoweringInfo &CLI,
506 SmallVectorImpl<SDValue> &InVals) const {
507 SelectionDAG &DAG = CLI.DAG;
508 SDLoc &DL = CLI.DL;
509 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
510 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
512 SDValue Chain = CLI.Chain;
513 SDValue Callee = CLI.Callee;
514 bool &IsTailCall = CLI.IsTailCall;
515 CallingConv::ID CallConv = CLI.CallConv;
516 bool IsVarArg = CLI.IsVarArg;
517 EVT PtrVT = getPointerTy(DAG.getDataLayout());
518 MVT XLenVT = MVT::i32;
519
521
522 // Analyze the operands of the call, assigning locations to each operand.
524 CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
525
526 ArgCCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, IsVarArg));
527
528 // Check if it's really possible to do a tail call.
529 if (IsTailCall)
530 IsTailCall = false; // TODO: TailCallOptimization;
531
532 if (IsTailCall)
533 ++NumTailCalls;
534 else if (CLI.CB && CLI.CB->isMustTailCall())
535 report_fatal_error("failed to perform tail call elimination on a call "
536 "site marked musttail");
537
538 // Get a count of how many bytes are to be pushed on the stack.
539 unsigned NumBytes = ArgCCInfo.getStackSize();
540
541 // Create local copies for byval args
542 SmallVector<SDValue, 8> ByValArgs;
543 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
544 ISD::ArgFlagsTy Flags = Outs[i].Flags;
545 if (!Flags.isByVal())
546 continue;
547
548 SDValue Arg = OutVals[i];
549 unsigned Size = Flags.getByValSize();
550 Align Alignment = Flags.getNonZeroByValAlign();
551
552 int FI =
553 MF.getFrameInfo().CreateStackObject(Size, Alignment, /*isSS=*/false);
554 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
555 SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT);
556
557 Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,
558 /*IsVolatile=*/false,
559 /*AlwaysInline=*/false, IsTailCall,
561 ByValArgs.push_back(FIPtr);
562 }
563
564 if (!IsTailCall)
565 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
566
567 // Copy argument values to their designated locations.
569 SmallVector<SDValue, 8> MemOpChains;
571 for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) {
572 CCValAssign &VA = ArgLocs[i];
573 SDValue ArgValue = OutVals[i];
574 ISD::ArgFlagsTy Flags = Outs[i].Flags;
575
576 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
577
578 if (IsF64OnCSKY && VA.isRegLoc()) {
579 SDValue Split64 =
581 DAG.getVTList(MVT::i32, MVT::i32), ArgValue);
582 SDValue Lo = Split64.getValue(0);
583 SDValue Hi = Split64.getValue(1);
584
585 Register RegLo = VA.getLocReg();
586 RegsToPass.push_back(std::make_pair(RegLo, Lo));
587
588 if (RegLo == CSKY::R3) {
589 // Second half of f64/i64 is passed on the stack.
590 // Work out the address of the stack slot.
591 if (!StackPtr.getNode())
592 StackPtr = DAG.getCopyFromReg(Chain, DL, CSKY::R14, PtrVT);
593 // Emit the store.
594 MemOpChains.push_back(
595 DAG.getStore(Chain, DL, Hi, StackPtr, MachinePointerInfo()));
596 } else {
597 // Second half of f64/i64 is passed in another GPR.
598 assert(RegLo < CSKY::R31 && "Invalid register pair");
599 Register RegHigh = RegLo + 1;
600 RegsToPass.push_back(std::make_pair(RegHigh, Hi));
601 }
602 continue;
603 }
604
605 ArgValue = convertValVTToLocVT(DAG, ArgValue, VA, DL);
606
607 // Use local copy if it is a byval arg.
608 if (Flags.isByVal())
609 ArgValue = ByValArgs[j++];
610
611 if (VA.isRegLoc()) {
612 // Queue up the argument copies and emit them at the end.
613 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
614 } else {
615 assert(VA.isMemLoc() && "Argument not register or memory");
616 assert(!IsTailCall && "Tail call not allowed if stack is used "
617 "for passing parameters");
618
619 // Work out the address of the stack slot.
620 if (!StackPtr.getNode())
621 StackPtr = DAG.getCopyFromReg(Chain, DL, CSKY::R14, PtrVT);
623 DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
625
626 // Emit the store.
627 MemOpChains.push_back(
628 DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
629 }
630 }
631
632 // Join the stores, which are independent of one another.
633 if (!MemOpChains.empty())
634 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
635
636 SDValue Glue;
637
638 // Build a sequence of copy-to-reg nodes, chained and glued together.
639 for (auto &Reg : RegsToPass) {
640 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
641 Glue = Chain.getValue(1);
642 }
643
645 EVT Ty = getPointerTy(DAG.getDataLayout());
646 bool IsRegCall = false;
647
648 Ops.push_back(Chain);
649
650 if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) {
651 const GlobalValue *GV = S->getGlobal();
652 bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(GV);
653
654 if (isPositionIndependent() || !Subtarget.has2E3()) {
655 IsRegCall = true;
656 Ops.push_back(getAddr<GlobalAddressSDNode, true>(S, DAG, IsLocal));
657 } else {
658 Ops.push_back(getTargetNode(cast<GlobalAddressSDNode>(Callee), DL, Ty,
659 DAG, CSKYII::MO_None));
660 Ops.push_back(getTargetConstantPoolValue(
661 cast<GlobalAddressSDNode>(Callee), Ty, DAG, CSKYII::MO_None));
662 }
663 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
664 bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(nullptr);
665
666 if (isPositionIndependent() || !Subtarget.has2E3()) {
667 IsRegCall = true;
668 Ops.push_back(getAddr<ExternalSymbolSDNode, true>(S, DAG, IsLocal));
669 } else {
670 Ops.push_back(getTargetNode(cast<ExternalSymbolSDNode>(Callee), DL, Ty,
671 DAG, CSKYII::MO_None));
672 Ops.push_back(getTargetConstantPoolValue(
673 cast<ExternalSymbolSDNode>(Callee), Ty, DAG, CSKYII::MO_None));
674 }
675 } else {
676 IsRegCall = true;
677 Ops.push_back(Callee);
678 }
679
680 // Add argument registers to the end of the list so that they are
681 // known live into the call.
682 for (auto &Reg : RegsToPass)
683 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
684
685 if (!IsTailCall) {
686 // Add a register mask operand representing the call-preserved registers.
687 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
688 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
689 assert(Mask && "Missing call preserved mask for calling convention");
690 Ops.push_back(DAG.getRegisterMask(Mask));
691 }
692
693 // Glue the call to the argument copies, if any.
694 if (Glue.getNode())
695 Ops.push_back(Glue);
696
697 // Emit the call.
698 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
699
700 if (IsTailCall) {
702 return DAG.getNode(IsRegCall ? CSKYISD::TAILReg : CSKYISD::TAIL, DL,
703 NodeTys, Ops);
704 }
705
706 Chain = DAG.getNode(IsRegCall ? CSKYISD::CALLReg : CSKYISD::CALL, DL, NodeTys,
707 Ops);
708 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
709 Glue = Chain.getValue(1);
710
711 // Mark the end of the call, which is glued to the call itself.
712 Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, Glue, DL);
713 Glue = Chain.getValue(1);
714
715 // Assign locations to each value returned by this call.
717 CCState RetCCInfo(CallConv, IsVarArg, MF, CSKYLocs, *DAG.getContext());
718 RetCCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, IsVarArg));
719
720 // Copy all of the result registers out of their specified physreg.
721 for (auto &VA : CSKYLocs) {
722 // Copy the value out
723 SDValue RetValue =
724 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue);
725 // Glue the RetValue to the end of the call sequence
726 Chain = RetValue.getValue(1);
727 Glue = RetValue.getValue(2);
728
729 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
730
731 if (IsF64OnCSKY) {
732 assert(VA.getLocReg() == GPRArgRegs[0] && "Unexpected reg assignment");
733 SDValue RetValue2 =
734 DAG.getCopyFromReg(Chain, DL, GPRArgRegs[1], MVT::i32, Glue);
735 Chain = RetValue2.getValue(1);
736 Glue = RetValue2.getValue(2);
737 RetValue = DAG.getNode(CSKYISD::BITCAST_FROM_LOHI, DL, VA.getValVT(),
738 RetValue, RetValue2);
739 }
740
741 RetValue = convertLocVTToValVT(DAG, RetValue, VA, DL);
742
743 InVals.push_back(RetValue);
744 }
745
746 return Chain;
747}
748
749CCAssignFn *CSKYTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
750 bool IsVarArg) const {
751 if (IsVarArg || !Subtarget.useHardFloatABI())
752 return RetCC_CSKY_ABIV2_SOFT;
753 else
754 return RetCC_CSKY_ABIV2_FP;
755}
756
757CCAssignFn *CSKYTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
758 bool IsVarArg) const {
759 if (IsVarArg || !Subtarget.useHardFloatABI())
760 return CC_CSKY_ABIV2_SOFT;
761 else
762 return CC_CSKY_ABIV2_FP;
763}
764
765static CSKYCP::CSKYCPModifier getModifier(unsigned Flags) {
766
767 if (Flags == CSKYII::MO_ADDR32)
768 return CSKYCP::ADDR;
769 else if (Flags == CSKYII::MO_GOT32)
770 return CSKYCP::GOT;
771 else if (Flags == CSKYII::MO_GOTOFF)
772 return CSKYCP::GOTOFF;
773 else if (Flags == CSKYII::MO_PLT32)
774 return CSKYCP::PLT;
775 else if (Flags == CSKYII::MO_None)
776 return CSKYCP::NO_MOD;
777 else
778 assert(0 && "unknown CSKYII Modifier");
779 return CSKYCP::NO_MOD;
780}
781
782SDValue CSKYTargetLowering::getTargetConstantPoolValue(GlobalAddressSDNode *N,
783 EVT Ty,
784 SelectionDAG &DAG,
785 unsigned Flags) const {
787 N->getGlobal(), CSKYCP::CPValue, 0, getModifier(Flags), false);
788
789 return DAG.getTargetConstantPool(CPV, Ty);
790}
791
793CSKYTargetLowering::getConstraintType(StringRef Constraint) const {
794 if (Constraint.size() == 1) {
795 switch (Constraint[0]) {
796 default:
797 break;
798 case 'a':
799 case 'b':
800 case 'v':
801 case 'w':
802 case 'y':
803 return C_RegisterClass;
804 case 'c':
805 case 'l':
806 case 'h':
807 case 'z':
808 return C_Register;
809 }
810 }
811 return TargetLowering::getConstraintType(Constraint);
812}
813
814std::pair<unsigned, const TargetRegisterClass *>
815CSKYTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
816 StringRef Constraint,
817 MVT VT) const {
818 if (Constraint.size() == 1) {
819 switch (Constraint[0]) {
820 case 'r':
821 return std::make_pair(0U, &CSKY::GPRRegClass);
822 case 'a':
823 return std::make_pair(0U, &CSKY::mGPRRegClass);
824 case 'b':
825 return std::make_pair(0U, &CSKY::sGPRRegClass);
826 case 'z':
827 return std::make_pair(CSKY::R14, &CSKY::GPRRegClass);
828 case 'c':
829 return std::make_pair(CSKY::C, &CSKY::CARRYRegClass);
830 case 'w':
831 if ((Subtarget.hasFPUv2SingleFloat() ||
832 Subtarget.hasFPUv3SingleFloat()) &&
833 VT == MVT::f32)
834 return std::make_pair(0U, &CSKY::sFPR32RegClass);
835 if ((Subtarget.hasFPUv2DoubleFloat() ||
836 Subtarget.hasFPUv3DoubleFloat()) &&
837 VT == MVT::f64)
838 return std::make_pair(0U, &CSKY::sFPR64RegClass);
839 break;
840 case 'v':
841 if (Subtarget.hasFPUv2SingleFloat() && VT == MVT::f32)
842 return std::make_pair(0U, &CSKY::sFPR32RegClass);
843 if (Subtarget.hasFPUv3SingleFloat() && VT == MVT::f32)
844 return std::make_pair(0U, &CSKY::FPR32RegClass);
845 if (Subtarget.hasFPUv2DoubleFloat() && VT == MVT::f64)
846 return std::make_pair(0U, &CSKY::sFPR64RegClass);
847 if (Subtarget.hasFPUv3DoubleFloat() && VT == MVT::f64)
848 return std::make_pair(0U, &CSKY::FPR64RegClass);
849 break;
850 default:
851 break;
852 }
853 }
854
855 if (Constraint == "{c}")
856 return std::make_pair(CSKY::C, &CSKY::CARRYRegClass);
857
858 // Clang will correctly decode the usage of register name aliases into their
859 // official names. However, other frontends like `rustc` do not. This allows
860 // users of these frontends to use the ABI names for registers in LLVM-style
861 // register constraints.
862 unsigned XRegFromAlias = StringSwitch<unsigned>(Constraint.lower())
863 .Case("{a0}", CSKY::R0)
864 .Case("{a1}", CSKY::R1)
865 .Case("{a2}", CSKY::R2)
866 .Case("{a3}", CSKY::R3)
867 .Case("{l0}", CSKY::R4)
868 .Case("{l1}", CSKY::R5)
869 .Case("{l2}", CSKY::R6)
870 .Case("{l3}", CSKY::R7)
871 .Case("{l4}", CSKY::R8)
872 .Case("{l5}", CSKY::R9)
873 .Case("{l6}", CSKY::R10)
874 .Case("{l7}", CSKY::R11)
875 .Case("{t0}", CSKY::R12)
876 .Case("{t1}", CSKY::R13)
877 .Case("{sp}", CSKY::R14)
878 .Case("{lr}", CSKY::R15)
879 .Case("{l8}", CSKY::R16)
880 .Case("{l9}", CSKY::R17)
881 .Case("{t2}", CSKY::R18)
882 .Case("{t3}", CSKY::R19)
883 .Case("{t4}", CSKY::R20)
884 .Case("{t5}", CSKY::R21)
885 .Case("{t6}", CSKY::R22)
886 .Cases("{t7}", "{fp}", CSKY::R23)
887 .Cases("{t8}", "{top}", CSKY::R24)
888 .Cases("{t9}", "{bsp}", CSKY::R25)
889 .Case("{r26}", CSKY::R26)
890 .Case("{r27}", CSKY::R27)
891 .Cases("{gb}", "{rgb}", "{rdb}", CSKY::R28)
892 .Cases("{tb}", "{rtb}", CSKY::R29)
893 .Case("{svbr}", CSKY::R30)
894 .Case("{tls}", CSKY::R31)
895 .Default(CSKY::NoRegister);
896
897 if (XRegFromAlias != CSKY::NoRegister)
898 return std::make_pair(XRegFromAlias, &CSKY::GPRRegClass);
899
900 // Since TargetLowering::getRegForInlineAsmConstraint uses the name of the
901 // TableGen record rather than the AsmName to choose registers for InlineAsm
902 // constraints, plus we want to match those names to the widest floating point
903 // register type available, manually select floating point registers here.
904 //
905 // The second case is the ABI name of the register, so that frontends can also
906 // use the ABI names in register constraint lists.
907 if (Subtarget.useHardFloat()) {
908 unsigned FReg = StringSwitch<unsigned>(Constraint.lower())
909 .Cases("{fr0}", "{vr0}", CSKY::F0_32)
910 .Cases("{fr1}", "{vr1}", CSKY::F1_32)
911 .Cases("{fr2}", "{vr2}", CSKY::F2_32)
912 .Cases("{fr3}", "{vr3}", CSKY::F3_32)
913 .Cases("{fr4}", "{vr4}", CSKY::F4_32)
914 .Cases("{fr5}", "{vr5}", CSKY::F5_32)
915 .Cases("{fr6}", "{vr6}", CSKY::F6_32)
916 .Cases("{fr7}", "{vr7}", CSKY::F7_32)
917 .Cases("{fr8}", "{vr8}", CSKY::F8_32)
918 .Cases("{fr9}", "{vr9}", CSKY::F9_32)
919 .Cases("{fr10}", "{vr10}", CSKY::F10_32)
920 .Cases("{fr11}", "{vr11}", CSKY::F11_32)
921 .Cases("{fr12}", "{vr12}", CSKY::F12_32)
922 .Cases("{fr13}", "{vr13}", CSKY::F13_32)
923 .Cases("{fr14}", "{vr14}", CSKY::F14_32)
924 .Cases("{fr15}", "{vr15}", CSKY::F15_32)
925 .Cases("{fr16}", "{vr16}", CSKY::F16_32)
926 .Cases("{fr17}", "{vr17}", CSKY::F17_32)
927 .Cases("{fr18}", "{vr18}", CSKY::F18_32)
928 .Cases("{fr19}", "{vr19}", CSKY::F19_32)
929 .Cases("{fr20}", "{vr20}", CSKY::F20_32)
930 .Cases("{fr21}", "{vr21}", CSKY::F21_32)
931 .Cases("{fr22}", "{vr22}", CSKY::F22_32)
932 .Cases("{fr23}", "{vr23}", CSKY::F23_32)
933 .Cases("{fr24}", "{vr24}", CSKY::F24_32)
934 .Cases("{fr25}", "{vr25}", CSKY::F25_32)
935 .Cases("{fr26}", "{vr26}", CSKY::F26_32)
936 .Cases("{fr27}", "{vr27}", CSKY::F27_32)
937 .Cases("{fr28}", "{vr28}", CSKY::F28_32)
938 .Cases("{fr29}", "{vr29}", CSKY::F29_32)
939 .Cases("{fr30}", "{vr30}", CSKY::F30_32)
940 .Cases("{fr31}", "{vr31}", CSKY::F31_32)
941 .Default(CSKY::NoRegister);
942 if (FReg != CSKY::NoRegister) {
943 assert(CSKY::F0_32 <= FReg && FReg <= CSKY::F31_32 && "Unknown fp-reg");
944 unsigned RegNo = FReg - CSKY::F0_32;
945 unsigned DReg = CSKY::F0_64 + RegNo;
946
947 if (Subtarget.hasFPUv2DoubleFloat())
948 return std::make_pair(DReg, &CSKY::sFPR64RegClass);
949 else if (Subtarget.hasFPUv3DoubleFloat())
950 return std::make_pair(DReg, &CSKY::FPR64RegClass);
951 else if (Subtarget.hasFPUv2SingleFloat())
952 return std::make_pair(FReg, &CSKY::sFPR32RegClass);
953 else if (Subtarget.hasFPUv3SingleFloat())
954 return std::make_pair(FReg, &CSKY::FPR32RegClass);
955 }
956 }
957
959}
960
961static MachineBasicBlock *
963
965 DebugLoc DL = MI.getDebugLoc();
966
967 // To "insert" a SELECT instruction, we actually have to insert the
968 // diamond control-flow pattern. The incoming instruction knows the
969 // destination vreg to set, the condition code register to branch on, the
970 // true/false values to select between, and a branch opcode to use.
971 const BasicBlock *LLVM_BB = BB->getBasicBlock();
973
974 // thisMBB:
975 // ...
976 // TrueVal = ...
977 // bt32 c, sinkMBB
978 // fallthrough --> copyMBB
979 MachineBasicBlock *thisMBB = BB;
980 MachineFunction *F = BB->getParent();
981 MachineBasicBlock *copyMBB = F->CreateMachineBasicBlock(LLVM_BB);
982 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
983 F->insert(It, copyMBB);
984 F->insert(It, sinkMBB);
985
986 // Transfer the remainder of BB and its successor edges to sinkMBB.
987 sinkMBB->splice(sinkMBB->begin(), BB,
988 std::next(MachineBasicBlock::iterator(MI)), BB->end());
990
991 // Next, add the true and fallthrough blocks as its successors.
992 BB->addSuccessor(copyMBB);
993 BB->addSuccessor(sinkMBB);
994
995 // bt32 condition, sinkMBB
996 BuildMI(BB, DL, TII.get(Opcode))
997 .addReg(MI.getOperand(1).getReg())
998 .addMBB(sinkMBB);
999
1000 // copyMBB:
1001 // %FalseValue = ...
1002 // # fallthrough to sinkMBB
1003 BB = copyMBB;
1004
1005 // Update machine-CFG edges
1006 BB->addSuccessor(sinkMBB);
1007
1008 // sinkMBB:
1009 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copyMBB ]
1010 // ...
1011 BB = sinkMBB;
1012
1013 BuildMI(*BB, BB->begin(), DL, TII.get(CSKY::PHI), MI.getOperand(0).getReg())
1014 .addReg(MI.getOperand(2).getReg())
1015 .addMBB(thisMBB)
1016 .addReg(MI.getOperand(3).getReg())
1017 .addMBB(copyMBB);
1018
1019 MI.eraseFromParent(); // The pseudo instruction is gone now.
1020
1021 return BB;
1022}
1023
1025CSKYTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1026 MachineBasicBlock *BB) const {
1027 switch (MI.getOpcode()) {
1028 default:
1029 llvm_unreachable("Unexpected instr type to insert");
1030 case CSKY::FSELS:
1031 case CSKY::FSELD:
1032 if (Subtarget.hasE2())
1033 return emitSelectPseudo(MI, BB, CSKY::BT32);
1034 else
1035 return emitSelectPseudo(MI, BB, CSKY::BT16);
1036 case CSKY::ISEL32:
1037 return emitSelectPseudo(MI, BB, CSKY::BT32);
1038 case CSKY::ISEL16:
1039 return emitSelectPseudo(MI, BB, CSKY::BT16);
1040 }
1041}
1042
1043SDValue CSKYTargetLowering::getTargetConstantPoolValue(ExternalSymbolSDNode *N,
1044 EVT Ty,
1045 SelectionDAG &DAG,
1046 unsigned Flags) const {
1049 N->getSymbol(), 0, getModifier(Flags));
1050
1051 return DAG.getTargetConstantPool(CPV, Ty);
1052}
1053
1054SDValue CSKYTargetLowering::getTargetConstantPoolValue(JumpTableSDNode *N,
1055 EVT Ty,
1056 SelectionDAG &DAG,
1057 unsigned Flags) const {
1060 N->getIndex(), 0, getModifier(Flags));
1061 return DAG.getTargetConstantPool(CPV, Ty);
1062}
1063
1064SDValue CSKYTargetLowering::getTargetConstantPoolValue(BlockAddressSDNode *N,
1065 EVT Ty,
1066 SelectionDAG &DAG,
1067 unsigned Flags) const {
1068 assert(N->getOffset() == 0);
1070 N->getBlockAddress(), CSKYCP::CPBlockAddress, 0, getModifier(Flags),
1071 false);
1072 return DAG.getTargetConstantPool(CPV, Ty);
1073}
1074
1075SDValue CSKYTargetLowering::getTargetConstantPoolValue(ConstantPoolSDNode *N,
1076 EVT Ty,
1077 SelectionDAG &DAG,
1078 unsigned Flags) const {
1079 assert(N->getOffset() == 0);
1081 N->getConstVal(), Type::getInt32Ty(*DAG.getContext()),
1082 CSKYCP::CPConstPool, 0, getModifier(Flags), false);
1083 return DAG.getTargetConstantPool(CPV, Ty);
1084}
1085
1086SDValue CSKYTargetLowering::getTargetNode(GlobalAddressSDNode *N, SDLoc DL,
1087 EVT Ty, SelectionDAG &DAG,
1088 unsigned Flags) const {
1089 return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
1090}
1091
1092SDValue CSKYTargetLowering::getTargetNode(ExternalSymbolSDNode *N, SDLoc DL,
1093 EVT Ty, SelectionDAG &DAG,
1094 unsigned Flags) const {
1095 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flags);
1096}
1097
1098SDValue CSKYTargetLowering::getTargetNode(JumpTableSDNode *N, SDLoc DL, EVT Ty,
1099 SelectionDAG &DAG,
1100 unsigned Flags) const {
1101 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flags);
1102}
1103
1104SDValue CSKYTargetLowering::getTargetNode(BlockAddressSDNode *N, SDLoc DL,
1105 EVT Ty, SelectionDAG &DAG,
1106 unsigned Flags) const {
1107 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, N->getOffset(),
1108 Flags);
1109}
1110
1111SDValue CSKYTargetLowering::getTargetNode(ConstantPoolSDNode *N, SDLoc DL,
1112 EVT Ty, SelectionDAG &DAG,
1113 unsigned Flags) const {
1114
1115 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(),
1116 N->getOffset(), Flags);
1117}
1118
1119const char *CSKYTargetLowering::getTargetNodeName(unsigned Opcode) const {
1120 switch (Opcode) {
1121 default:
1122 llvm_unreachable("unknown CSKYISD node");
1123 case CSKYISD::NIE:
1124 return "CSKYISD::NIE";
1125 case CSKYISD::NIR:
1126 return "CSKYISD::NIR";
1127 case CSKYISD::RET:
1128 return "CSKYISD::RET";
1129 case CSKYISD::CALL:
1130 return "CSKYISD::CALL";
1131 case CSKYISD::CALLReg:
1132 return "CSKYISD::CALLReg";
1133 case CSKYISD::TAIL:
1134 return "CSKYISD::TAIL";
1135 case CSKYISD::TAILReg:
1136 return "CSKYISD::TAILReg";
1137 case CSKYISD::LOAD_ADDR:
1138 return "CSKYISD::LOAD_ADDR";
1140 return "CSKYISD::BITCAST_TO_LOHI";
1142 return "CSKYISD::BITCAST_FROM_LOHI";
1143 }
1144}
1145
1146SDValue CSKYTargetLowering::LowerGlobalAddress(SDValue Op,
1147 SelectionDAG &DAG) const {
1148 SDLoc DL(Op);
1149 EVT Ty = Op.getValueType();
1150 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1151 int64_t Offset = N->getOffset();
1152
1153 const GlobalValue *GV = N->getGlobal();
1154 bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(GV);
1155 SDValue Addr = getAddr<GlobalAddressSDNode, false>(N, DAG, IsLocal);
1156
1157 // In order to maximise the opportunity for common subexpression elimination,
1158 // emit a separate ADD node for the global address offset instead of folding
1159 // it in the global address node. Later peephole optimisations may choose to
1160 // fold it back in when profitable.
1161 if (Offset != 0)
1162 return DAG.getNode(ISD::ADD, DL, Ty, Addr,
1163 DAG.getConstant(Offset, DL, MVT::i32));
1164 return Addr;
1165}
1166
1167SDValue CSKYTargetLowering::LowerExternalSymbol(SDValue Op,
1168 SelectionDAG &DAG) const {
1169 ExternalSymbolSDNode *N = cast<ExternalSymbolSDNode>(Op);
1170
1171 return getAddr(N, DAG, false);
1172}
1173
1174SDValue CSKYTargetLowering::LowerJumpTable(SDValue Op,
1175 SelectionDAG &DAG) const {
1176 JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
1177
1178 return getAddr<JumpTableSDNode, false>(N, DAG);
1179}
1180
1181SDValue CSKYTargetLowering::LowerBlockAddress(SDValue Op,
1182 SelectionDAG &DAG) const {
1183 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
1184
1185 return getAddr(N, DAG);
1186}
1187
1188SDValue CSKYTargetLowering::LowerConstantPool(SDValue Op,
1189 SelectionDAG &DAG) const {
1190 assert(!Subtarget.hasE2());
1191 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1192
1193 return getAddr(N, DAG);
1194}
1195
1196SDValue CSKYTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1199
1200 SDLoc DL(Op);
1201 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1203
1204 // vastart just stores the address of the VarArgsFrameIndex slot into the
1205 // memory location argument.
1206 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1207 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1208 MachinePointerInfo(SV));
1209}
1210
1211SDValue CSKYTargetLowering::LowerFRAMEADDR(SDValue Op,
1212 SelectionDAG &DAG) const {
1213 const CSKYRegisterInfo &RI = *Subtarget.getRegisterInfo();
1215 MachineFrameInfo &MFI = MF.getFrameInfo();
1216 MFI.setFrameAddressIsTaken(true);
1217
1218 EVT VT = Op.getValueType();
1219 SDLoc dl(Op);
1220 unsigned Depth = Op.getConstantOperandVal(0);
1221 Register FrameReg = RI.getFrameRegister(MF);
1222 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1223 while (Depth--)
1224 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1226 return FrameAddr;
1227}
1228
1229SDValue CSKYTargetLowering::LowerRETURNADDR(SDValue Op,
1230 SelectionDAG &DAG) const {
1231 const CSKYRegisterInfo &RI = *Subtarget.getRegisterInfo();
1233 MachineFrameInfo &MFI = MF.getFrameInfo();
1234 MFI.setReturnAddressIsTaken(true);
1235
1237 return SDValue();
1238
1239 EVT VT = Op.getValueType();
1240 SDLoc dl(Op);
1241 unsigned Depth = Op.getConstantOperandVal(0);
1242 if (Depth) {
1243 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1244 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1245 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1246 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1248 }
1249 // Return the value of the return address register, marking it an implicit
1250 // live-in.
1251 unsigned Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(MVT::i32));
1252 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1253}
1254
1255Register CSKYTargetLowering::getExceptionPointerRegister(
1256 const Constant *PersonalityFn) const {
1257 return CSKY::R0;
1258}
1259
1260Register CSKYTargetLowering::getExceptionSelectorRegister(
1261 const Constant *PersonalityFn) const {
1262 return CSKY::R1;
1263}
1264
1265SDValue CSKYTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1266 SelectionDAG &DAG) const {
1267 SDLoc DL(Op);
1268 EVT Ty = Op.getValueType();
1269 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1270 int64_t Offset = N->getOffset();
1271 MVT XLenVT = MVT::i32;
1272
1274 SDValue Addr;
1275 switch (Model) {
1277 Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/false);
1278 break;
1280 Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/true);
1281 break;
1284 Addr = getDynamicTLSAddr(N, DAG);
1285 break;
1286 }
1287
1288 // In order to maximise the opportunity for common subexpression elimination,
1289 // emit a separate ADD node for the global address offset instead of folding
1290 // it in the global address node. Later peephole optimisations may choose to
1291 // fold it back in when profitable.
1292 if (Offset != 0)
1293 return DAG.getNode(ISD::ADD, DL, Ty, Addr,
1294 DAG.getConstant(Offset, DL, XLenVT));
1295 return Addr;
1296}
1297
1298SDValue CSKYTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,
1299 SelectionDAG &DAG,
1300 bool UseGOT) const {
1303
1304 unsigned CSKYPCLabelIndex = CFI->createPICLabelUId();
1305
1306 SDLoc DL(N);
1307 EVT Ty = getPointerTy(DAG.getDataLayout());
1308
1310 bool AddCurrentAddr = UseGOT ? true : false;
1311 unsigned char PCAjust = UseGOT ? 4 : 0;
1312
1314 CSKYConstantPoolConstant::Create(N->getGlobal(), CSKYCP::CPValue, PCAjust,
1315 Flag, AddCurrentAddr, CSKYPCLabelIndex);
1316 SDValue CAddr = DAG.getTargetConstantPool(CPV, Ty);
1317
1318 SDValue Load;
1319 if (UseGOT) {
1320 SDValue PICLabel = DAG.getTargetConstant(CSKYPCLabelIndex, DL, MVT::i32);
1321 auto *LRWGRS = DAG.getMachineNode(CSKY::PseudoTLSLA32, DL, {Ty, Ty},
1322 {CAddr, PICLabel});
1323 auto LRWADDGRS =
1324 DAG.getNode(ISD::ADD, DL, Ty, SDValue(LRWGRS, 0), SDValue(LRWGRS, 1));
1325 Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), LRWADDGRS,
1326 MachinePointerInfo(N->getGlobal()));
1327 } else {
1328 Load = SDValue(DAG.getMachineNode(CSKY::LRW32, DL, Ty, CAddr), 0);
1329 }
1330
1331 // Add the thread pointer.
1332 SDValue TPReg = DAG.getRegister(CSKY::R31, MVT::i32);
1333 return DAG.getNode(ISD::ADD, DL, Ty, Load, TPReg);
1334}
1335
1336SDValue CSKYTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,
1337 SelectionDAG &DAG) const {
1340
1341 unsigned CSKYPCLabelIndex = CFI->createPICLabelUId();
1342
1343 SDLoc DL(N);
1344 EVT Ty = getPointerTy(DAG.getDataLayout());
1345 IntegerType *CallTy = Type::getIntNTy(*DAG.getContext(), Ty.getSizeInBits());
1346
1349 CSKYCP::TLSGD, true, CSKYPCLabelIndex);
1350 SDValue Addr = DAG.getTargetConstantPool(CPV, Ty);
1351 SDValue PICLabel = DAG.getTargetConstant(CSKYPCLabelIndex, DL, MVT::i32);
1352
1353 auto *LRWGRS =
1354 DAG.getMachineNode(CSKY::PseudoTLSLA32, DL, {Ty, Ty}, {Addr, PICLabel});
1355
1356 auto Load =
1357 DAG.getNode(ISD::ADD, DL, Ty, SDValue(LRWGRS, 0), SDValue(LRWGRS, 1));
1358
1359 // Prepare argument list to generate call.
1361 ArgListEntry Entry;
1362 Entry.Node = Load;
1363 Entry.Ty = CallTy;
1364 Args.push_back(Entry);
1365
1366 // Setup call to __tls_get_addr.
1368 CLI.setDebugLoc(DL)
1369 .setChain(DAG.getEntryNode())
1370 .setLibCallee(CallingConv::C, CallTy,
1371 DAG.getExternalSymbol("__tls_get_addr", Ty),
1372 std::move(Args));
1373 SDValue V = LowerCallTo(CLI).first;
1374
1375 return V;
1376}
1377
1378bool CSKYTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
1379 SDValue C) const {
1380 if (!VT.isScalarInteger())
1381 return false;
1382
1383 // Omit if data size exceeds.
1384 if (VT.getSizeInBits() > Subtarget.XLen)
1385 return false;
1386
1387 if (auto *ConstNode = dyn_cast<ConstantSDNode>(C.getNode())) {
1388 const APInt &Imm = ConstNode->getAPIntValue();
1389 // Break MULT to LSLI + ADDU/SUBU.
1390 if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2() ||
1391 (1 - Imm).isPowerOf2())
1392 return true;
1393 // Only break MULT for sub targets without MULT32, since an extra
1394 // instruction will be generated against the above 3 cases. We leave it
1395 // unchanged on sub targets with MULT32, since not sure it is better.
1396 if (!Subtarget.hasE2() && (-1 - Imm).isPowerOf2())
1397 return true;
1398 // Break (MULT x, imm) to ([IXH32|IXW32|IXD32] (LSLI32 x, i0), x) when
1399 // imm=(1<<i0)+[2|4|8] and imm has to be composed via a MOVIH32/ORI32 pair.
1400 if (Imm.ugt(0xffff) && ((Imm - 2).isPowerOf2() || (Imm - 4).isPowerOf2()) &&
1401 Subtarget.hasE2())
1402 return true;
1403 if (Imm.ugt(0xffff) && (Imm - 8).isPowerOf2() && Subtarget.has2E3())
1404 return true;
1405 }
1406
1407 return false;
1408}
1409
1410bool CSKYTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
1411 return Subtarget.has2E3();
1412}
1413
1414bool CSKYTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
1415 return Subtarget.hasE2();
1416}
static const MCPhysReg GPRArgRegs[]
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
basic Basic Alias true
static SDValue unpack64(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static const MCPhysReg GPRArgRegs[]
static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
static CSKYCP::CSKYCPModifier getModifier(unsigned Flags)
static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
static MachineBasicBlock * emitSelectPseudo(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode)
static SDValue unpackFromRegLoc(const CSKYSubtarget &Subtarget, SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Addr
uint64_t Size
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:167
Class for arbitrary precision integers.
Definition: APInt.h:77
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
LLVM Basic Block Representation.
Definition: BasicBlock.h:60
CCState - This class holds information needed while lowering arguments and return values.
CCValAssign - Represent assignment of one arg/retval to a location.
bool isRegLoc() const
Register getLocReg() const
LocInfo getLocInfo() const
bool isMemLoc() const
int64_t getLocMemOffset() const
static CSKYConstantPoolConstant * Create(const Constant *C, CSKYCP::CSKYCPKind Kind, unsigned PCAdjust, CSKYCP::CSKYCPModifier Modifier, bool AddCurrentAddress, unsigned ID=0)
static CSKYConstantPoolJT * Create(Type *Ty, int JTI, unsigned PCAdj, CSKYCP::CSKYCPModifier Modifier)
static CSKYConstantPoolSymbol * Create(Type *Ty, const char *S, unsigned PCAdjust, CSKYCP::CSKYCPModifier Modifier)
CSKYConstantPoolValue - CSKY specific constantpool value.
Register getFrameRegister(const MachineFunction &MF) const override
bool hasFPUv2SingleFloat() const
bool hasFPUv3SingleFloat() const
const CSKYRegisterInfo * getRegisterInfo() const override
const unsigned XLen
bool hasE2() const
bool hasFPUv2DoubleFloat() const
bool useHardFloatABI() const
bool useHardFloat() const
bool hasFPUv3DoubleFloat() const
bool has2E3() const
CSKYTargetLowering(const TargetMachine &TM, const CSKYSubtarget &STI)
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:410
A debug info location.
Definition: DebugLoc.h:33
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:680
Class to represent integer types.
Definition: DerivedTypes.h:40
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Machine Value Type.
SimpleValueType SimpleTy
static MVT getIntegerVT(unsigned BitWidth)
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:227
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:736
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
void addNoMergeSiteInfo(const SDNode *Node, bool NoMerge)
Set NoMergeSiteInfo to be associated with Node if NoMerge is true.
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:746
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:486
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getExternalSymbol(const char *Sym, EVT VT)
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:787
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:690
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:782
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:481
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:813
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getRegisterMask(const uint32_t *RegMask)
LLVMContext * getContext() const
Definition: SelectionDAG.h:499
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:753
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:568
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
std::string lower() const
Definition: StringRef.cpp:111
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
StringSwitch & Cases(StringLiteral S0, StringLiteral S1, T Value)
Definition: StringSwitch.h:90
TargetInstrInfo - Interface to description of machine instruction set.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
const TargetMachine & getTargetMachine() const
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
std::vector< ArgListEntry > ArgListTy
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isPositionIndependent() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
bool shouldAssumeDSOLocal(const GlobalValue *GV) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetInstrInfo * getInstrInfo() const
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
static IntegerType * getInt32Ty(LLVMContext &C)
LLVM Value Representation.
Definition: Value.h:74
self_iterator getIterator()
Definition: ilist_node.h:132
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:121
@ Entry
Definition: COFF.h:811
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1141
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1137
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:251
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:722
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1170
@ ConstantFP
Definition: ISDOpcodes.h:77
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:240
@ RETURNADDR
Definition: ISDOpcodes.h:95
@ GlobalAddress
Definition: ISDOpcodes.h:78
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:696
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:1248
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:256
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
Definition: ISDOpcodes.h:921
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:911
@ GlobalTLSAddress
Definition: ISDOpcodes.h:79
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:1003
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1092
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:1071
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1166
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:653
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:750
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:1056
@ ConstantPool
Definition: ISDOpcodes.h:82
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:304
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition: ISDOpcodes.h:94
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
@ ExternalSymbol
Definition: ISDOpcodes.h:83
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1161
@ BlockAddress
Definition: ISDOpcodes.h:84
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:771
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:495
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1548
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1528
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:148
@ GeneralDynamic
Definition: CodeGen.h:46
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
Definition: ValueTypes.h:93
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:358
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:306
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:167
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:156
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This structure contains all information that is necessary for lowering calls.