28#define DEBUG_TYPE "csky-isel-lowering"
32#include "CSKYGenCallingConv.inc"
89 if (!Subtarget.
hasE2()) {
95 if (!Subtarget.
hasE2()) {
102 if (!Subtarget.
has2E3()) {
125 MVT AllVTy[] = {MVT::f32, MVT::f64};
127 for (
auto VT : AllVTy) {
132 for (
auto CC : FPCCToExtend)
134 for (
auto Op : FPOpToExpand)
167 switch (
Op.getOpcode()) {
171 return LowerGlobalAddress(
Op, DAG);
173 return LowerExternalSymbol(
Op, DAG);
175 return LowerGlobalTLSAddress(
Op, DAG);
177 return LowerJumpTable(
Op, DAG);
179 return LowerBlockAddress(
Op, DAG);
181 return LowerConstantPool(
Op, DAG);
183 return LowerVASTART(
Op, DAG);
185 return LowerFRAMEADDR(
Op, DAG);
187 return LowerRETURNADDR(
Op, DAG);
242 RC = &CSKY::GPRRegClass;
246 : &CSKY::FPR32RegClass;
250 : &CSKY::FPR64RegClass;
283 ExtType,
DL, LocVT, Chain, FIN,
327SDValue CSKYTargetLowering::LowerFormalArguments(
343 std::vector<SDValue> OutChains;
349 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, IsVarArg));
351 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
368 const unsigned XLenInBytes = 4;
369 const MVT XLenVT = MVT::i32;
372 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
381 int VaArgOffset, VarArgsSaveSize;
386 VaArgOffset = CCInfo.getStackSize();
389 VarArgsSaveSize = XLenInBytes * (ArgRegs.
size() -
Idx);
390 VaArgOffset = -VarArgsSaveSize;
400 for (
unsigned I =
Idx;
I < ArgRegs.
size();
401 ++
I, VaArgOffset += XLenInBytes) {
409 cast<StoreSDNode>(
Store.getNode())
411 ->setValue((
Value *)
nullptr);
412 OutChains.push_back(Store);
419 if (!OutChains.empty()) {
420 OutChains.push_back(Chain);
427bool CSKYTargetLowering::CanLowerReturn(
431 CCState CCInfo(CallConv, IsVarArg, MF, CSKYLocs, Context);
432 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
447 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
453 for (
unsigned i = 0, e = CSKYLocs.
size(); i < e; ++i) {
469 assert(RegLo < CSKY::R31 &&
"Invalid register pair");
474 RetOps.push_back(DAG.
getRegister(RegLo, MVT::i32));
477 RetOps.push_back(DAG.
getRegister(RegHi, MVT::i32));
493 RetOps.push_back(Glue);
505SDValue CSKYTargetLowering::LowerCall(CallLoweringInfo &CLI,
514 bool &IsTailCall = CLI.IsTailCall;
516 bool IsVarArg = CLI.IsVarArg;
518 MVT XLenVT = MVT::i32;
526 ArgCCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, IsVarArg));
534 else if (CLI.CB && CLI.CB->isMustTailCall())
536 "site marked musttail");
539 unsigned NumBytes = ArgCCInfo.getStackSize();
543 for (
unsigned i = 0, e = Outs.
size(); i != e; ++i) {
545 if (!
Flags.isByVal())
550 Align Alignment =
Flags.getNonZeroByValAlign();
557 Chain = DAG.
getMemcpy(Chain,
DL, FIPtr, Arg, SizeNode, Alignment,
559 false,
nullptr, IsTailCall,
571 for (
unsigned i = 0, j = 0, e = ArgLocs.
size(); i != e; ++i) {
581 DAG.
getVTList(MVT::i32, MVT::i32), ArgValue);
588 if (RegLo == CSKY::R3) {
598 assert(RegLo < CSKY::R31 &&
"Invalid register pair");
609 ArgValue = ByValArgs[
j++];
616 assert(!IsTailCall &&
"Tail call not allowed if stack is used "
617 "for passing parameters");
633 if (!MemOpChains.
empty())
639 for (
auto &Reg : RegsToPass) {
646 bool IsRegCall =
false;
656 Ops.
push_back(getAddr<GlobalAddressSDNode, true>(S, DAG, IsLocal));
658 Ops.
push_back(getTargetNode(cast<GlobalAddressSDNode>(Callee),
DL, Ty,
660 Ops.
push_back(getTargetConstantPoolValue(
668 Ops.
push_back(getAddr<ExternalSymbolSDNode, true>(S, DAG, IsLocal));
670 Ops.
push_back(getTargetNode(cast<ExternalSymbolSDNode>(Callee),
DL, Ty,
672 Ops.
push_back(getTargetConstantPoolValue(
682 for (
auto &Reg : RegsToPass)
689 assert(Mask &&
"Missing call preserved mask for calling convention");
718 RetCCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, IsVarArg));
721 for (
auto &VA : CSKYLocs) {
738 RetValue, RetValue2);
750 bool IsVarArg)
const {
752 return RetCC_CSKY_ABIV2_SOFT;
754 return RetCC_CSKY_ABIV2_FP;
758 bool IsVarArg)
const {
760 return CC_CSKY_ABIV2_SOFT;
762 return CC_CSKY_ABIV2_FP;
778 assert(0 &&
"unknown CSKYII Modifier");
785 unsigned Flags)
const {
793CSKYTargetLowering::getConstraintType(
StringRef Constraint)
const {
794 if (Constraint.
size() == 1) {
795 switch (Constraint[0]) {
814std::pair<unsigned, const TargetRegisterClass *>
818 if (Constraint.
size() == 1) {
819 switch (Constraint[0]) {
821 return std::make_pair(0U, &CSKY::GPRRegClass);
823 return std::make_pair(0U, &CSKY::mGPRRegClass);
825 return std::make_pair(0U, &CSKY::sGPRRegClass);
827 return std::make_pair(CSKY::R14, &CSKY::GPRRegClass);
829 return std::make_pair(CSKY::C, &CSKY::CARRYRegClass);
834 return std::make_pair(0U, &CSKY::sFPR32RegClass);
838 return std::make_pair(0U, &CSKY::sFPR64RegClass);
842 return std::make_pair(0U, &CSKY::sFPR32RegClass);
844 return std::make_pair(0U, &CSKY::FPR32RegClass);
846 return std::make_pair(0U, &CSKY::sFPR64RegClass);
848 return std::make_pair(0U, &CSKY::FPR64RegClass);
855 if (Constraint ==
"{c}")
856 return std::make_pair(CSKY::C, &CSKY::CARRYRegClass);
863 .
Case(
"{a0}", CSKY::R0)
864 .
Case(
"{a1}", CSKY::R1)
865 .
Case(
"{a2}", CSKY::R2)
866 .
Case(
"{a3}", CSKY::R3)
867 .
Case(
"{l0}", CSKY::R4)
868 .
Case(
"{l1}", CSKY::R5)
869 .
Case(
"{l2}", CSKY::R6)
870 .
Case(
"{l3}", CSKY::R7)
871 .
Case(
"{l4}", CSKY::R8)
872 .
Case(
"{l5}", CSKY::R9)
873 .
Case(
"{l6}", CSKY::R10)
874 .
Case(
"{l7}", CSKY::R11)
875 .
Case(
"{t0}", CSKY::R12)
876 .
Case(
"{t1}", CSKY::R13)
877 .
Case(
"{sp}", CSKY::R14)
878 .
Case(
"{lr}", CSKY::R15)
879 .
Case(
"{l8}", CSKY::R16)
880 .
Case(
"{l9}", CSKY::R17)
881 .
Case(
"{t2}", CSKY::R18)
882 .
Case(
"{t3}", CSKY::R19)
883 .
Case(
"{t4}", CSKY::R20)
884 .
Case(
"{t5}", CSKY::R21)
885 .
Case(
"{t6}", CSKY::R22)
886 .
Cases(
"{t7}",
"{fp}", CSKY::R23)
887 .
Cases(
"{t8}",
"{top}", CSKY::R24)
888 .
Cases(
"{t9}",
"{bsp}", CSKY::R25)
889 .
Case(
"{r26}", CSKY::R26)
890 .
Case(
"{r27}", CSKY::R27)
891 .
Cases(
"{gb}",
"{rgb}",
"{rdb}", CSKY::R28)
892 .
Cases(
"{tb}",
"{rtb}", CSKY::R29)
893 .
Case(
"{svbr}", CSKY::R30)
894 .
Case(
"{tls}", CSKY::R31)
897 if (XRegFromAlias != CSKY::NoRegister)
898 return std::make_pair(XRegFromAlias, &CSKY::GPRRegClass);
909 .
Cases(
"{fr0}",
"{vr0}", CSKY::F0_32)
910 .
Cases(
"{fr1}",
"{vr1}", CSKY::F1_32)
911 .
Cases(
"{fr2}",
"{vr2}", CSKY::F2_32)
912 .
Cases(
"{fr3}",
"{vr3}", CSKY::F3_32)
913 .
Cases(
"{fr4}",
"{vr4}", CSKY::F4_32)
914 .
Cases(
"{fr5}",
"{vr5}", CSKY::F5_32)
915 .
Cases(
"{fr6}",
"{vr6}", CSKY::F6_32)
916 .
Cases(
"{fr7}",
"{vr7}", CSKY::F7_32)
917 .
Cases(
"{fr8}",
"{vr8}", CSKY::F8_32)
918 .
Cases(
"{fr9}",
"{vr9}", CSKY::F9_32)
919 .
Cases(
"{fr10}",
"{vr10}", CSKY::F10_32)
920 .
Cases(
"{fr11}",
"{vr11}", CSKY::F11_32)
921 .
Cases(
"{fr12}",
"{vr12}", CSKY::F12_32)
922 .
Cases(
"{fr13}",
"{vr13}", CSKY::F13_32)
923 .
Cases(
"{fr14}",
"{vr14}", CSKY::F14_32)
924 .
Cases(
"{fr15}",
"{vr15}", CSKY::F15_32)
925 .
Cases(
"{fr16}",
"{vr16}", CSKY::F16_32)
926 .
Cases(
"{fr17}",
"{vr17}", CSKY::F17_32)
927 .
Cases(
"{fr18}",
"{vr18}", CSKY::F18_32)
928 .
Cases(
"{fr19}",
"{vr19}", CSKY::F19_32)
929 .
Cases(
"{fr20}",
"{vr20}", CSKY::F20_32)
930 .
Cases(
"{fr21}",
"{vr21}", CSKY::F21_32)
931 .
Cases(
"{fr22}",
"{vr22}", CSKY::F22_32)
932 .
Cases(
"{fr23}",
"{vr23}", CSKY::F23_32)
933 .
Cases(
"{fr24}",
"{vr24}", CSKY::F24_32)
934 .
Cases(
"{fr25}",
"{vr25}", CSKY::F25_32)
935 .
Cases(
"{fr26}",
"{vr26}", CSKY::F26_32)
936 .
Cases(
"{fr27}",
"{vr27}", CSKY::F27_32)
937 .
Cases(
"{fr28}",
"{vr28}", CSKY::F28_32)
938 .
Cases(
"{fr29}",
"{vr29}", CSKY::F29_32)
939 .
Cases(
"{fr30}",
"{vr30}", CSKY::F30_32)
940 .
Cases(
"{fr31}",
"{vr31}", CSKY::F31_32)
942 if (FReg != CSKY::NoRegister) {
943 assert(CSKY::F0_32 <= FReg && FReg <= CSKY::F31_32 &&
"Unknown fp-reg");
944 unsigned RegNo = FReg - CSKY::F0_32;
945 unsigned DReg = CSKY::F0_64 + RegNo;
948 return std::make_pair(DReg, &CSKY::sFPR64RegClass);
950 return std::make_pair(DReg, &CSKY::FPR64RegClass);
952 return std::make_pair(FReg, &CSKY::sFPR32RegClass);
954 return std::make_pair(FReg, &CSKY::FPR32RegClass);
983 F->insert(It, copyMBB);
984 F->insert(It, sinkMBB);
1019 MI.eraseFromParent();
1027 switch (
MI.getOpcode()) {
1032 if (Subtarget.
hasE2())
1046 unsigned Flags)
const {
1057 unsigned Flags)
const {
1067 unsigned Flags)
const {
1078 unsigned Flags)
const {
1088 unsigned Flags)
const {
1094 unsigned Flags)
const {
1100 unsigned Flags)
const {
1106 unsigned Flags)
const {
1113 unsigned Flags)
const {
1116 N->getOffset(), Flags);
1119const char *CSKYTargetLowering::getTargetNodeName(
unsigned Opcode)
const {
1124 return "CSKYISD::NIE";
1126 return "CSKYISD::NIR";
1128 return "CSKYISD::RET";
1130 return "CSKYISD::CALL";
1132 return "CSKYISD::CALLReg";
1134 return "CSKYISD::TAIL";
1136 return "CSKYISD::TAILReg";
1138 return "CSKYISD::LOAD_ADDR";
1140 return "CSKYISD::BITCAST_TO_LOHI";
1142 return "CSKYISD::BITCAST_FROM_LOHI";
1149 EVT Ty =
Op.getValueType();
1151 int64_t
Offset =
N->getOffset();
1155 SDValue Addr = getAddr<GlobalAddressSDNode, false>(
N, DAG, IsLocal);
1171 return getAddr(
N, DAG,
false);
1178 return getAddr<JumpTableSDNode, false>(
N, DAG);
1185 return getAddr(
N, DAG);
1193 return getAddr(
N, DAG);
1206 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
1218 EVT VT =
Op.getValueType();
1220 unsigned Depth =
Op.getConstantOperandVal(0);
1239 EVT VT =
Op.getValueType();
1241 unsigned Depth =
Op.getConstantOperandVal(0);
1243 SDValue FrameAddr = LowerFRAMEADDR(
Op, DAG);
1255Register CSKYTargetLowering::getExceptionPointerRegister(
1256 const Constant *PersonalityFn)
const {
1260Register CSKYTargetLowering::getExceptionSelectorRegister(
1261 const Constant *PersonalityFn)
const {
1268 EVT Ty =
Op.getValueType();
1270 int64_t
Offset =
N->getOffset();
1271 MVT XLenVT = MVT::i32;
1277 Addr = getStaticTLSAddr(
N, DAG,
false);
1280 Addr = getStaticTLSAddr(
N, DAG,
true);
1284 Addr = getDynamicTLSAddr(
N, DAG);
1300 bool UseGOT)
const {
1310 bool AddCurrentAddr = UseGOT ?
true :
false;
1311 unsigned char PCAjust = UseGOT ? 4 : 0;
1315 Flag, AddCurrentAddr, CSKYPCLabelIndex);
1364 Args.push_back(Entry);
1378bool CSKYTargetLowering::decomposeMulByConstant(
LLVMContext &Context,
EVT VT,
1387 if (
auto *ConstNode = dyn_cast<ConstantSDNode>(
C.getNode())) {
1388 const APInt &
Imm = ConstNode->getAPIntValue();
1390 if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2() ||
1391 (1 - Imm).isPowerOf2())
1396 if (!Subtarget.
hasE2() && (-1 - Imm).isPowerOf2())
1400 if (
Imm.ugt(0xffff) && ((Imm - 2).isPowerOf2() || (Imm - 4).isPowerOf2()) &&
1403 if (
Imm.ugt(0xffff) && (Imm - 8).isPowerOf2() && Subtarget.
has2E3())
1410bool CSKYTargetLowering::isCheapToSpeculateCttz(
Type *Ty)
const {
1411 return Subtarget.
has2E3();
1414bool CSKYTargetLowering::isCheapToSpeculateCtlz(
Type *Ty)
const {
1415 return Subtarget.
hasE2();
static const MCPhysReg GPRArgRegs[]
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static SDValue unpack64(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static const MCPhysReg GPRArgRegs[]
static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
static CSKYCP::CSKYCPModifier getModifier(unsigned Flags)
static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
static MachineBasicBlock * emitSelectPseudo(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode)
static SDValue unpackFromRegLoc(const CSKYSubtarget &Subtarget, SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Class for arbitrary precision integers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
CCState - This class holds information needed while lowering arguments and return values.
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
int64_t getLocMemOffset() const
static CSKYConstantPoolConstant * Create(const Constant *C, CSKYCP::CSKYCPKind Kind, unsigned PCAdjust, CSKYCP::CSKYCPModifier Modifier, bool AddCurrentAddress, unsigned ID=0)
static CSKYConstantPoolJT * Create(Type *Ty, int JTI, unsigned PCAdj, CSKYCP::CSKYCPModifier Modifier)
static CSKYConstantPoolSymbol * Create(Type *Ty, const char *S, unsigned PCAdjust, CSKYCP::CSKYCPModifier Modifier)
CSKYConstantPoolValue - CSKY specific constantpool value.
unsigned createPICLabelUId()
int getVarArgsFrameIndex()
void setVarArgsFrameIndex(int v)
void setVarArgsSaveSize(int Size)
Register getFrameRegister(const MachineFunction &MF) const override
bool hasFPUv2SingleFloat() const
bool hasFPUv3SingleFloat() const
const CSKYRegisterInfo * getRegisterInfo() const override
bool hasFPUv2DoubleFloat() const
bool useHardFloatABI() const
bool useHardFloat() const
bool hasFPUv3DoubleFloat() const
CSKYTargetLowering(const TargetMachine &TM, const CSKYSubtarget &STI)
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This is an important base class in LLVM.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Class to represent integer types.
This is an important class for using LLVM in a threaded context.
static MVT getIntegerVT(unsigned BitWidth)
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
void addNoMergeSiteInfo(const SDNode *Node, bool NoMerge)
Set NoMergeSiteInfo to be associated with Node if NoMerge is true.
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getExternalSymbol(const char *Sym, EVT VT)
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getRegisterMask(const uint32_t *RegMask)
LLVMContext * getContext() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
constexpr size_t size() const
size - Get the string size.
std::string lower() const
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
StringSwitch & Cases(StringLiteral S0, StringLiteral S1, T Value)
TargetInstrInfo - Interface to description of machine instruction set.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
const TargetMachine & getTargetMachine() const
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ UndefinedBooleanContent
@ ZeroOrNegativeOneBooleanContent
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
std::vector< ArgListEntry > ArgListTy
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isPositionIndependent() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
Primary interface to the complete machine description for the target machine.
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
bool shouldAssumeDSOLocal(const GlobalValue *GV) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetInstrInfo * getInstrInfo() const
The instances of the Type class are immutable: once they are created, they are never changed.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
static IntegerType * getInt32Ty(LLVMContext &C)
LLVM Value Representation.
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ADD
Simple integer binary arithmetic operators.
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ BR_CC
BR_CC - Conditional branch.
@ BR_JT
BR_JT - Jumptable branch.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
This struct is a compact representation of a valid (non-zero power of two) alignment.
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
bool isVector() const
Return true if this is a vector value type.
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This structure contains all information that is necessary for lowering calls.