LLVM  16.0.0git
CSKYISelLowering.cpp
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1 //===-- CSKYISelLowering.cpp - CSKY DAG Lowering Implementation ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that CSKY uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "CSKYISelLowering.h"
15 #include "CSKYCallingConv.h"
16 #include "CSKYConstantPoolValue.h"
18 #include "CSKYRegisterInfo.h"
19 #include "CSKYSubtarget.h"
20 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Support/Debug.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "csky-isel-lowering"
29 
30 STATISTIC(NumTailCalls, "Number of tail calls");
31 
32 #include "CSKYGenCallingConv.inc"
33 
34 static const MCPhysReg GPRArgRegs[] = {CSKY::R0, CSKY::R1, CSKY::R2, CSKY::R3};
35 
37  const CSKYSubtarget &STI)
38  : TargetLowering(TM), Subtarget(STI) {
39  // Register Class
40  addRegisterClass(MVT::i32, &CSKY::GPRRegClass);
41 
42  if (STI.useHardFloat()) {
43  if (STI.hasFPUv2SingleFloat())
44  addRegisterClass(MVT::f32, &CSKY::sFPR32RegClass);
45  else if (STI.hasFPUv3SingleFloat())
46  addRegisterClass(MVT::f32, &CSKY::FPR32RegClass);
47 
48  if (STI.hasFPUv2DoubleFloat())
49  addRegisterClass(MVT::f64, &CSKY::sFPR64RegClass);
50  else if (STI.hasFPUv3DoubleFloat())
51  addRegisterClass(MVT::f64, &CSKY::FPR64RegClass);
52  }
53 
57 
81 
85 
90  if (!Subtarget.hasE2()) {
92  }
95 
96  if (!Subtarget.hasE2()) {
101  }
102 
103  if (!Subtarget.has2E3()) {
108  }
109 
111 
112  // Float
113 
114  ISD::CondCode FPCCToExtend[] = {
117  };
118 
119  ISD::NodeType FPOpToExpand[] = {ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
121 
122  if (STI.useHardFloat()) {
123 
124  MVT AllVTy[] = {MVT::f32, MVT::f64};
125 
126  for (auto VT : AllVTy) {
130 
131  for (auto CC : FPCCToExtend)
133  for (auto Op : FPOpToExpand)
135  }
136 
137  if (STI.hasFPUv2SingleFloat() || STI.hasFPUv3SingleFloat()) {
139  }
140  if (STI.hasFPUv2DoubleFloat() || STI.hasFPUv3DoubleFloat()) {
143  }
144  }
145 
146  // Compute derived properties from the register classes.
148 
151 
152  // TODO: Add atomic support fully.
154 
156  const Align FunctionAlignment(2);
157  setMinFunctionAlignment(FunctionAlignment);
159 }
160 
162  SelectionDAG &DAG) const {
163  switch (Op.getOpcode()) {
164  default:
165  llvm_unreachable("unimplemented op");
166  case ISD::GlobalAddress:
167  return LowerGlobalAddress(Op, DAG);
168  case ISD::ExternalSymbol:
169  return LowerExternalSymbol(Op, DAG);
171  return LowerGlobalTLSAddress(Op, DAG);
172  case ISD::JumpTable:
173  return LowerJumpTable(Op, DAG);
174  case ISD::BlockAddress:
175  return LowerBlockAddress(Op, DAG);
176  case ISD::ConstantPool:
177  return LowerConstantPool(Op, DAG);
178  case ISD::VASTART:
179  return LowerVASTART(Op, DAG);
180  case ISD::FRAMEADDR:
181  return LowerFRAMEADDR(Op, DAG);
182  case ISD::RETURNADDR:
183  return LowerRETURNADDR(Op, DAG);
184  }
185 }
186 
188  LLVMContext &Context, EVT VT) const {
189  if (!VT.isVector())
190  return MVT::i32;
191 
193 }
194 
196  const CCValAssign &VA, const SDLoc &DL) {
197  EVT LocVT = VA.getLocVT();
198 
199  switch (VA.getLocInfo()) {
200  default:
201  llvm_unreachable("Unexpected CCValAssign::LocInfo");
202  case CCValAssign::Full:
203  break;
204  case CCValAssign::BCvt:
205  Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val);
206  break;
207  }
208  return Val;
209 }
210 
212  const CCValAssign &VA, const SDLoc &DL) {
213  switch (VA.getLocInfo()) {
214  default:
215  llvm_unreachable("Unexpected CCValAssign::LocInfo");
216  case CCValAssign::Full:
217  break;
218  case CCValAssign::BCvt:
219  Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
220  break;
221  }
222  return Val;
223 }
224 
225 static SDValue unpackFromRegLoc(const CSKYSubtarget &Subtarget,
226  SelectionDAG &DAG, SDValue Chain,
227  const CCValAssign &VA, const SDLoc &DL) {
229  MachineRegisterInfo &RegInfo = MF.getRegInfo();
230  EVT LocVT = VA.getLocVT();
231  SDValue Val;
232  const TargetRegisterClass *RC;
233 
234  switch (LocVT.getSimpleVT().SimpleTy) {
235  default:
236  llvm_unreachable("Unexpected register type");
237  case MVT::i32:
238  RC = &CSKY::GPRRegClass;
239  break;
240  case MVT::f32:
241  RC = Subtarget.hasFPUv2SingleFloat() ? &CSKY::sFPR32RegClass
242  : &CSKY::FPR32RegClass;
243  break;
244  case MVT::f64:
245  RC = Subtarget.hasFPUv2DoubleFloat() ? &CSKY::sFPR64RegClass
246  : &CSKY::FPR64RegClass;
247  break;
248  }
249 
250  Register VReg = RegInfo.createVirtualRegister(RC);
251  RegInfo.addLiveIn(VA.getLocReg(), VReg);
252  Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
253 
254  return convertLocVTToValVT(DAG, Val, VA, DL);
255 }
256 
258  const CCValAssign &VA, const SDLoc &DL) {
260  MachineFrameInfo &MFI = MF.getFrameInfo();
261  EVT LocVT = VA.getLocVT();
262  EVT ValVT = VA.getValVT();
264  int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
265  VA.getLocMemOffset(), /*Immutable=*/true);
266  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
267  SDValue Val;
268 
269  ISD::LoadExtType ExtType;
270  switch (VA.getLocInfo()) {
271  default:
272  llvm_unreachable("Unexpected CCValAssign::LocInfo");
273  case CCValAssign::Full:
274  case CCValAssign::BCvt:
275  ExtType = ISD::NON_EXTLOAD;
276  break;
277  }
278  Val = DAG.getExtLoad(
279  ExtType, DL, LocVT, Chain, FIN,
281  return Val;
282 }
283 
284 static SDValue unpack64(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA,
285  const SDLoc &DL) {
286  assert(VA.getLocVT() == MVT::i32 &&
287  (VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::i64) &&
288  "Unexpected VA");
290  MachineFrameInfo &MFI = MF.getFrameInfo();
291  MachineRegisterInfo &RegInfo = MF.getRegInfo();
292 
293  if (VA.isMemLoc()) {
294  // f64/i64 is passed on the stack.
295  int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), /*Immutable=*/true);
296  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
297  return DAG.getLoad(VA.getValVT(), DL, Chain, FIN,
299  }
300 
301  assert(VA.isRegLoc() && "Expected register VA assignment");
302 
303  Register LoVReg = RegInfo.createVirtualRegister(&CSKY::GPRRegClass);
304  RegInfo.addLiveIn(VA.getLocReg(), LoVReg);
305  SDValue Lo = DAG.getCopyFromReg(Chain, DL, LoVReg, MVT::i32);
306  SDValue Hi;
307  if (VA.getLocReg() == CSKY::R3) {
308  // Second half of f64/i64 is passed on the stack.
309  int FI = MFI.CreateFixedObject(4, 0, /*Immutable=*/true);
310  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
311  Hi = DAG.getLoad(MVT::i32, DL, Chain, FIN,
313  } else {
314  // Second half of f64/i64 is passed in another GPR.
315  Register HiVReg = RegInfo.createVirtualRegister(&CSKY::GPRRegClass);
316  RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg);
317  Hi = DAG.getCopyFromReg(Chain, DL, HiVReg, MVT::i32);
318  }
319  return DAG.getNode(CSKYISD::BITCAST_FROM_LOHI, DL, VA.getValVT(), Lo, Hi);
320 }
321 
322 // Transform physical registers into virtual registers.
323 SDValue CSKYTargetLowering::LowerFormalArguments(
324  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
326  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
327 
328  switch (CallConv) {
329  default:
330  report_fatal_error("Unsupported calling convention");
331  case CallingConv::C:
332  case CallingConv::Fast:
333  break;
334  }
335 
337 
338  // Used with vargs to acumulate store chains.
339  std::vector<SDValue> OutChains;
340 
341  // Assign locations to all of the incoming arguments.
343  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
344 
345  CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, IsVarArg));
346 
347  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
348  CCValAssign &VA = ArgLocs[i];
349  SDValue ArgValue;
350 
351  bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
352 
353  if (IsF64OnCSKY)
354  ArgValue = unpack64(DAG, Chain, VA, DL);
355  else if (VA.isRegLoc())
356  ArgValue = unpackFromRegLoc(Subtarget, DAG, Chain, VA, DL);
357  else
358  ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);
359 
360  InVals.push_back(ArgValue);
361  }
362 
363  if (IsVarArg) {
364  const unsigned XLenInBytes = 4;
365  const MVT XLenVT = MVT::i32;
366 
368  unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
369  const TargetRegisterClass *RC = &CSKY::GPRRegClass;
370  MachineFrameInfo &MFI = MF.getFrameInfo();
371  MachineRegisterInfo &RegInfo = MF.getRegInfo();
373 
374  // Offset of the first variable argument from stack pointer, and size of
375  // the vararg save area. For now, the varargs save area is either zero or
376  // large enough to hold a0-a4.
377  int VaArgOffset, VarArgsSaveSize;
378 
379  // If all registers are allocated, then all varargs must be passed on the
380  // stack and we don't need to save any argregs.
381  if (ArgRegs.size() == Idx) {
382  VaArgOffset = CCInfo.getNextStackOffset();
383  VarArgsSaveSize = 0;
384  } else {
385  VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);
386  VaArgOffset = -VarArgsSaveSize;
387  }
388 
389  // Record the frame index of the first variable argument
390  // which is a value necessary to VASTART.
391  int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
392  CSKYFI->setVarArgsFrameIndex(FI);
393 
394  // Copy the integer registers that may have been used for passing varargs
395  // to the vararg save area.
396  for (unsigned I = Idx; I < ArgRegs.size();
397  ++I, VaArgOffset += XLenInBytes) {
398  const Register Reg = RegInfo.createVirtualRegister(RC);
399  RegInfo.addLiveIn(ArgRegs[I], Reg);
400  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT);
401  FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
402  SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
403  SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
405  cast<StoreSDNode>(Store.getNode())
406  ->getMemOperand()
407  ->setValue((Value *)nullptr);
408  OutChains.push_back(Store);
409  }
410  CSKYFI->setVarArgsSaveSize(VarArgsSaveSize);
411  }
412 
413  // All stores are grouped in one node to allow the matching between
414  // the size of Ins and InVals. This only happens for vararg functions.
415  if (!OutChains.empty()) {
416  OutChains.push_back(Chain);
417  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
418  }
419 
420  return Chain;
421 }
422 
423 bool CSKYTargetLowering::CanLowerReturn(
424  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
427  CCState CCInfo(CallConv, IsVarArg, MF, CSKYLocs, Context);
428  return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
429 }
430 
431 SDValue
432 CSKYTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
433  bool IsVarArg,
435  const SmallVectorImpl<SDValue> &OutVals,
436  const SDLoc &DL, SelectionDAG &DAG) const {
437  // Stores the assignment of the return value to a location.
439 
440  // Info about the registers and stack slot.
441  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), CSKYLocs,
442  *DAG.getContext());
443  CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
444 
445  SDValue Glue;
446  SmallVector<SDValue, 4> RetOps(1, Chain);
447 
448  // Copy the result values into the output registers.
449  for (unsigned i = 0, e = CSKYLocs.size(); i < e; ++i) {
450  SDValue Val = OutVals[i];
451  CCValAssign &VA = CSKYLocs[i];
452  assert(VA.isRegLoc() && "Can only return in registers!");
453 
454  bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
455 
456  if (IsF64OnCSKY) {
457 
458  assert(VA.isRegLoc() && "Expected return via registers");
460  DAG.getVTList(MVT::i32, MVT::i32), Val);
461  SDValue Lo = Split64.getValue(0);
462  SDValue Hi = Split64.getValue(1);
463 
464  Register RegLo = VA.getLocReg();
465  assert(RegLo < CSKY::R31 && "Invalid register pair");
466  Register RegHi = RegLo + 1;
467 
468  Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);
469  Glue = Chain.getValue(1);
470  RetOps.push_back(DAG.getRegister(RegLo, MVT::i32));
471  Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue);
472  Glue = Chain.getValue(1);
473  RetOps.push_back(DAG.getRegister(RegHi, MVT::i32));
474  } else {
475  // Handle a 'normal' return.
476  Val = convertValVTToLocVT(DAG, Val, VA, DL);
477  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);
478 
479  // Guarantee that all emitted copies are stuck together.
480  Glue = Chain.getValue(1);
481  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
482  }
483  }
484 
485  RetOps[0] = Chain; // Update chain.
486 
487  // Add the glue node if we have it.
488  if (Glue.getNode()) {
489  RetOps.push_back(Glue);
490  }
491 
492  // Interrupt service routines use different return instructions.
493  if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt"))
494  return DAG.getNode(CSKYISD::NIR, DL, MVT::Other, RetOps);
495 
496  return DAG.getNode(CSKYISD::RET, DL, MVT::Other, RetOps);
497 }
498 
499 // Lower a call to a callseq_start + CALL + callseq_end chain, and add input
500 // and output parameter nodes.
501 SDValue CSKYTargetLowering::LowerCall(CallLoweringInfo &CLI,
502  SmallVectorImpl<SDValue> &InVals) const {
503  SelectionDAG &DAG = CLI.DAG;
504  SDLoc &DL = CLI.DL;
505  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
506  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
508  SDValue Chain = CLI.Chain;
509  SDValue Callee = CLI.Callee;
510  bool &IsTailCall = CLI.IsTailCall;
511  CallingConv::ID CallConv = CLI.CallConv;
512  bool IsVarArg = CLI.IsVarArg;
513  EVT PtrVT = getPointerTy(DAG.getDataLayout());
514  MVT XLenVT = MVT::i32;
515 
517 
518  // Analyze the operands of the call, assigning locations to each operand.
520  CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
521 
522  ArgCCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, IsVarArg));
523 
524  // Check if it's really possible to do a tail call.
525  if (IsTailCall)
526  IsTailCall = false; // TODO: TailCallOptimization;
527 
528  if (IsTailCall)
529  ++NumTailCalls;
530  else if (CLI.CB && CLI.CB->isMustTailCall())
531  report_fatal_error("failed to perform tail call elimination on a call "
532  "site marked musttail");
533 
534  // Get a count of how many bytes are to be pushed on the stack.
535  unsigned NumBytes = ArgCCInfo.getNextStackOffset();
536 
537  // Create local copies for byval args
538  SmallVector<SDValue, 8> ByValArgs;
539  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
540  ISD::ArgFlagsTy Flags = Outs[i].Flags;
541  if (!Flags.isByVal())
542  continue;
543 
544  SDValue Arg = OutVals[i];
545  unsigned Size = Flags.getByValSize();
546  Align Alignment = Flags.getNonZeroByValAlign();
547 
548  int FI =
549  MF.getFrameInfo().CreateStackObject(Size, Alignment, /*isSS=*/false);
550  SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
551  SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT);
552 
553  Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,
554  /*IsVolatile=*/false,
555  /*AlwaysInline=*/false, IsTailCall,
557  ByValArgs.push_back(FIPtr);
558  }
559 
560  if (!IsTailCall)
561  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
562 
563  // Copy argument values to their designated locations.
565  SmallVector<SDValue, 8> MemOpChains;
567  for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) {
568  CCValAssign &VA = ArgLocs[i];
569  SDValue ArgValue = OutVals[i];
570  ISD::ArgFlagsTy Flags = Outs[i].Flags;
571 
572  bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
573 
574  if (IsF64OnCSKY && VA.isRegLoc()) {
575  SDValue Split64 =
577  DAG.getVTList(MVT::i32, MVT::i32), ArgValue);
578  SDValue Lo = Split64.getValue(0);
579  SDValue Hi = Split64.getValue(1);
580 
581  Register RegLo = VA.getLocReg();
582  RegsToPass.push_back(std::make_pair(RegLo, Lo));
583 
584  if (RegLo == CSKY::R3) {
585  // Second half of f64/i64 is passed on the stack.
586  // Work out the address of the stack slot.
587  if (!StackPtr.getNode())
588  StackPtr = DAG.getCopyFromReg(Chain, DL, CSKY::R14, PtrVT);
589  // Emit the store.
590  MemOpChains.push_back(
591  DAG.getStore(Chain, DL, Hi, StackPtr, MachinePointerInfo()));
592  } else {
593  // Second half of f64/i64 is passed in another GPR.
594  assert(RegLo < CSKY::R31 && "Invalid register pair");
595  Register RegHigh = RegLo + 1;
596  RegsToPass.push_back(std::make_pair(RegHigh, Hi));
597  }
598  continue;
599  }
600 
601  ArgValue = convertValVTToLocVT(DAG, ArgValue, VA, DL);
602 
603  // Use local copy if it is a byval arg.
604  if (Flags.isByVal())
605  ArgValue = ByValArgs[j++];
606 
607  if (VA.isRegLoc()) {
608  // Queue up the argument copies and emit them at the end.
609  RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
610  } else {
611  assert(VA.isMemLoc() && "Argument not register or memory");
612  assert(!IsTailCall && "Tail call not allowed if stack is used "
613  "for passing parameters");
614 
615  // Work out the address of the stack slot.
616  if (!StackPtr.getNode())
617  StackPtr = DAG.getCopyFromReg(Chain, DL, CSKY::R14, PtrVT);
618  SDValue Address =
619  DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
621 
622  // Emit the store.
623  MemOpChains.push_back(
624  DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
625  }
626  }
627 
628  // Join the stores, which are independent of one another.
629  if (!MemOpChains.empty())
630  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
631 
632  SDValue Glue;
633 
634  // Build a sequence of copy-to-reg nodes, chained and glued together.
635  for (auto &Reg : RegsToPass) {
636  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
637  Glue = Chain.getValue(1);
638  }
639 
641  EVT Ty = getPointerTy(DAG.getDataLayout());
642  bool IsRegCall = false;
643 
644  Ops.push_back(Chain);
645 
646  if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) {
647  const GlobalValue *GV = S->getGlobal();
648  bool IsLocal =
650 
651  if (isPositionIndependent() || !Subtarget.has2E3()) {
652  IsRegCall = true;
653  Ops.push_back(getAddr<GlobalAddressSDNode, true>(S, DAG, IsLocal));
654  } else {
655  Ops.push_back(getTargetNode(cast<GlobalAddressSDNode>(Callee), DL, Ty,
656  DAG, CSKYII::MO_None));
657  Ops.push_back(getTargetConstantPoolValue(
658  cast<GlobalAddressSDNode>(Callee), Ty, DAG, CSKYII::MO_None));
659  }
660  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
661  bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(
662  *MF.getFunction().getParent(), nullptr);
663 
664  if (isPositionIndependent() || !Subtarget.has2E3()) {
665  IsRegCall = true;
666  Ops.push_back(getAddr<ExternalSymbolSDNode, true>(S, DAG, IsLocal));
667  } else {
668  Ops.push_back(getTargetNode(cast<ExternalSymbolSDNode>(Callee), DL, Ty,
669  DAG, CSKYII::MO_None));
670  Ops.push_back(getTargetConstantPoolValue(
671  cast<ExternalSymbolSDNode>(Callee), Ty, DAG, CSKYII::MO_None));
672  }
673  } else {
674  IsRegCall = true;
675  Ops.push_back(Callee);
676  }
677 
678  // Add argument registers to the end of the list so that they are
679  // known live into the call.
680  for (auto &Reg : RegsToPass)
681  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
682 
683  if (!IsTailCall) {
684  // Add a register mask operand representing the call-preserved registers.
685  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
686  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
687  assert(Mask && "Missing call preserved mask for calling convention");
688  Ops.push_back(DAG.getRegisterMask(Mask));
689  }
690 
691  // Glue the call to the argument copies, if any.
692  if (Glue.getNode())
693  Ops.push_back(Glue);
694 
695  // Emit the call.
696  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
697 
698  if (IsTailCall) {
700  return DAG.getNode(IsRegCall ? CSKYISD::TAILReg : CSKYISD::TAIL, DL,
701  NodeTys, Ops);
702  }
703 
704  Chain = DAG.getNode(IsRegCall ? CSKYISD::CALLReg : CSKYISD::CALL, DL, NodeTys,
705  Ops);
706  DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
707  Glue = Chain.getValue(1);
708 
709  // Mark the end of the call, which is glued to the call itself.
710  Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, Glue, DL);
711  Glue = Chain.getValue(1);
712 
713  // Assign locations to each value returned by this call.
715  CCState RetCCInfo(CallConv, IsVarArg, MF, CSKYLocs, *DAG.getContext());
716  RetCCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, IsVarArg));
717 
718  // Copy all of the result registers out of their specified physreg.
719  for (auto &VA : CSKYLocs) {
720  // Copy the value out
721  SDValue RetValue =
722  DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue);
723  // Glue the RetValue to the end of the call sequence
724  Chain = RetValue.getValue(1);
725  Glue = RetValue.getValue(2);
726 
727  bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
728 
729  if (IsF64OnCSKY) {
730  assert(VA.getLocReg() == GPRArgRegs[0] && "Unexpected reg assignment");
731  SDValue RetValue2 =
732  DAG.getCopyFromReg(Chain, DL, GPRArgRegs[1], MVT::i32, Glue);
733  Chain = RetValue2.getValue(1);
734  Glue = RetValue2.getValue(2);
735  RetValue = DAG.getNode(CSKYISD::BITCAST_FROM_LOHI, DL, VA.getValVT(),
736  RetValue, RetValue2);
737  }
738 
739  RetValue = convertLocVTToValVT(DAG, RetValue, VA, DL);
740 
741  InVals.push_back(RetValue);
742  }
743 
744  return Chain;
745 }
746 
747 CCAssignFn *CSKYTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
748  bool IsVarArg) const {
749  if (IsVarArg || !Subtarget.useHardFloatABI())
750  return RetCC_CSKY_ABIV2_SOFT;
751  else
752  return RetCC_CSKY_ABIV2_FP;
753 }
754 
755 CCAssignFn *CSKYTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
756  bool IsVarArg) const {
757  if (IsVarArg || !Subtarget.useHardFloatABI())
758  return CC_CSKY_ABIV2_SOFT;
759  else
760  return CC_CSKY_ABIV2_FP;
761 }
762 
763 static CSKYCP::CSKYCPModifier getModifier(unsigned Flags) {
764 
765  if (Flags == CSKYII::MO_ADDR32)
766  return CSKYCP::ADDR;
767  else if (Flags == CSKYII::MO_GOT32)
768  return CSKYCP::GOT;
769  else if (Flags == CSKYII::MO_GOTOFF)
770  return CSKYCP::GOTOFF;
771  else if (Flags == CSKYII::MO_PLT32)
772  return CSKYCP::PLT;
773  else if (Flags == CSKYII::MO_None)
774  return CSKYCP::NO_MOD;
775  else
776  assert(0 && "unknown CSKYII Modifier");
777  return CSKYCP::NO_MOD;
778 }
779 
780 SDValue CSKYTargetLowering::getTargetConstantPoolValue(GlobalAddressSDNode *N,
781  EVT Ty,
782  SelectionDAG &DAG,
783  unsigned Flags) const {
785  N->getGlobal(), CSKYCP::CPValue, 0, getModifier(Flags), false);
786 
787  return DAG.getTargetConstantPool(CPV, Ty);
788 }
789 
791 CSKYTargetLowering::getConstraintType(StringRef Constraint) const {
792  if (Constraint.size() == 1) {
793  switch (Constraint[0]) {
794  default:
795  break;
796  case 'a':
797  case 'b':
798  case 'v':
799  case 'w':
800  case 'y':
801  return C_RegisterClass;
802  case 'c':
803  case 'l':
804  case 'h':
805  case 'z':
806  return C_Register;
807  }
808  }
809  return TargetLowering::getConstraintType(Constraint);
810 }
811 
812 std::pair<unsigned, const TargetRegisterClass *>
813 CSKYTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
814  StringRef Constraint,
815  MVT VT) const {
816  if (Constraint.size() == 1) {
817  switch (Constraint[0]) {
818  case 'r':
819  return std::make_pair(0U, &CSKY::GPRRegClass);
820  case 'a':
821  return std::make_pair(0U, &CSKY::mGPRRegClass);
822  case 'b':
823  return std::make_pair(0U, &CSKY::sGPRRegClass);
824  case 'z':
825  return std::make_pair(CSKY::R14, &CSKY::GPRRegClass);
826  case 'c':
827  return std::make_pair(CSKY::C, &CSKY::CARRYRegClass);
828  case 'w':
829  if ((Subtarget.hasFPUv2SingleFloat() ||
830  Subtarget.hasFPUv3SingleFloat()) &&
831  VT == MVT::f32)
832  return std::make_pair(0U, &CSKY::sFPR32RegClass);
833  if ((Subtarget.hasFPUv2DoubleFloat() ||
834  Subtarget.hasFPUv3DoubleFloat()) &&
835  VT == MVT::f64)
836  return std::make_pair(0U, &CSKY::sFPR64RegClass);
837  break;
838  case 'v':
839  if (Subtarget.hasFPUv2SingleFloat() && VT == MVT::f32)
840  return std::make_pair(0U, &CSKY::sFPR32RegClass);
841  if (Subtarget.hasFPUv3SingleFloat() && VT == MVT::f32)
842  return std::make_pair(0U, &CSKY::FPR32RegClass);
843  if (Subtarget.hasFPUv2DoubleFloat() && VT == MVT::f64)
844  return std::make_pair(0U, &CSKY::sFPR64RegClass);
845  if (Subtarget.hasFPUv3DoubleFloat() && VT == MVT::f64)
846  return std::make_pair(0U, &CSKY::FPR64RegClass);
847  break;
848  default:
849  break;
850  }
851  }
852 
853  if (Constraint == "{c}")
854  return std::make_pair(CSKY::C, &CSKY::CARRYRegClass);
855 
856  // Clang will correctly decode the usage of register name aliases into their
857  // official names. However, other frontends like `rustc` do not. This allows
858  // users of these frontends to use the ABI names for registers in LLVM-style
859  // register constraints.
860  unsigned XRegFromAlias = StringSwitch<unsigned>(Constraint.lower())
861  .Case("{a0}", CSKY::R0)
862  .Case("{a1}", CSKY::R1)
863  .Case("{a2}", CSKY::R2)
864  .Case("{a3}", CSKY::R3)
865  .Case("{l0}", CSKY::R4)
866  .Case("{l1}", CSKY::R5)
867  .Case("{l2}", CSKY::R6)
868  .Case("{l3}", CSKY::R7)
869  .Case("{l4}", CSKY::R8)
870  .Case("{l5}", CSKY::R9)
871  .Case("{l6}", CSKY::R10)
872  .Case("{l7}", CSKY::R11)
873  .Case("{t0}", CSKY::R12)
874  .Case("{t1}", CSKY::R13)
875  .Case("{sp}", CSKY::R14)
876  .Case("{lr}", CSKY::R15)
877  .Case("{l8}", CSKY::R16)
878  .Case("{l9}", CSKY::R17)
879  .Case("{t2}", CSKY::R18)
880  .Case("{t3}", CSKY::R19)
881  .Case("{t4}", CSKY::R20)
882  .Case("{t5}", CSKY::R21)
883  .Case("{t6}", CSKY::R22)
884  .Cases("{t7}", "{fp}", CSKY::R23)
885  .Cases("{t8}", "{top}", CSKY::R24)
886  .Cases("{t9}", "{bsp}", CSKY::R25)
887  .Case("{r26}", CSKY::R26)
888  .Case("{r27}", CSKY::R27)
889  .Cases("{gb}", "{rgb}", "{rdb}", CSKY::R28)
890  .Cases("{tb}", "{rtb}", CSKY::R29)
891  .Case("{svbr}", CSKY::R30)
892  .Case("{tls}", CSKY::R31)
893  .Default(CSKY::NoRegister);
894 
895  if (XRegFromAlias != CSKY::NoRegister)
896  return std::make_pair(XRegFromAlias, &CSKY::GPRRegClass);
897 
898  // Since TargetLowering::getRegForInlineAsmConstraint uses the name of the
899  // TableGen record rather than the AsmName to choose registers for InlineAsm
900  // constraints, plus we want to match those names to the widest floating point
901  // register type available, manually select floating point registers here.
902  //
903  // The second case is the ABI name of the register, so that frontends can also
904  // use the ABI names in register constraint lists.
905  if (Subtarget.useHardFloat()) {
906  unsigned FReg = StringSwitch<unsigned>(Constraint.lower())
907  .Cases("{fr0}", "{vr0}", CSKY::F0_32)
908  .Cases("{fr1}", "{vr1}", CSKY::F1_32)
909  .Cases("{fr2}", "{vr2}", CSKY::F2_32)
910  .Cases("{fr3}", "{vr3}", CSKY::F3_32)
911  .Cases("{fr4}", "{vr4}", CSKY::F4_32)
912  .Cases("{fr5}", "{vr5}", CSKY::F5_32)
913  .Cases("{fr6}", "{vr6}", CSKY::F6_32)
914  .Cases("{fr7}", "{vr7}", CSKY::F7_32)
915  .Cases("{fr8}", "{vr8}", CSKY::F8_32)
916  .Cases("{fr9}", "{vr9}", CSKY::F9_32)
917  .Cases("{fr10}", "{vr10}", CSKY::F10_32)
918  .Cases("{fr11}", "{vr11}", CSKY::F11_32)
919  .Cases("{fr12}", "{vr12}", CSKY::F12_32)
920  .Cases("{fr13}", "{vr13}", CSKY::F13_32)
921  .Cases("{fr14}", "{vr14}", CSKY::F14_32)
922  .Cases("{fr15}", "{vr15}", CSKY::F15_32)
923  .Cases("{fr16}", "{vr16}", CSKY::F16_32)
924  .Cases("{fr17}", "{vr17}", CSKY::F17_32)
925  .Cases("{fr18}", "{vr18}", CSKY::F18_32)
926  .Cases("{fr19}", "{vr19}", CSKY::F19_32)
927  .Cases("{fr20}", "{vr20}", CSKY::F20_32)
928  .Cases("{fr21}", "{vr21}", CSKY::F21_32)
929  .Cases("{fr22}", "{vr22}", CSKY::F22_32)
930  .Cases("{fr23}", "{vr23}", CSKY::F23_32)
931  .Cases("{fr24}", "{vr24}", CSKY::F24_32)
932  .Cases("{fr25}", "{vr25}", CSKY::F25_32)
933  .Cases("{fr26}", "{vr26}", CSKY::F26_32)
934  .Cases("{fr27}", "{vr27}", CSKY::F27_32)
935  .Cases("{fr28}", "{vr28}", CSKY::F28_32)
936  .Cases("{fr29}", "{vr29}", CSKY::F29_32)
937  .Cases("{fr30}", "{vr30}", CSKY::F30_32)
938  .Cases("{fr31}", "{vr31}", CSKY::F31_32)
939  .Default(CSKY::NoRegister);
940  if (FReg != CSKY::NoRegister) {
941  assert(CSKY::F0_32 <= FReg && FReg <= CSKY::F31_32 && "Unknown fp-reg");
942  unsigned RegNo = FReg - CSKY::F0_32;
943  unsigned DReg = CSKY::F0_64 + RegNo;
944 
945  if (Subtarget.hasFPUv2DoubleFloat())
946  return std::make_pair(DReg, &CSKY::sFPR64RegClass);
947  else if (Subtarget.hasFPUv3DoubleFloat())
948  return std::make_pair(DReg, &CSKY::FPR64RegClass);
949  else if (Subtarget.hasFPUv2SingleFloat())
950  return std::make_pair(FReg, &CSKY::sFPR32RegClass);
951  else if (Subtarget.hasFPUv3SingleFloat())
952  return std::make_pair(FReg, &CSKY::FPR32RegClass);
953  }
954  }
955 
956  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
957 }
958 
959 static MachineBasicBlock *
961 
962  const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
963  DebugLoc DL = MI.getDebugLoc();
964 
965  // To "insert" a SELECT instruction, we actually have to insert the
966  // diamond control-flow pattern. The incoming instruction knows the
967  // destination vreg to set, the condition code register to branch on, the
968  // true/false values to select between, and a branch opcode to use.
969  const BasicBlock *LLVM_BB = BB->getBasicBlock();
970  MachineFunction::iterator It = ++BB->getIterator();
971 
972  // thisMBB:
973  // ...
974  // TrueVal = ...
975  // bt32 c, sinkMBB
976  // fallthrough --> copyMBB
977  MachineBasicBlock *thisMBB = BB;
978  MachineFunction *F = BB->getParent();
979  MachineBasicBlock *copyMBB = F->CreateMachineBasicBlock(LLVM_BB);
980  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
981  F->insert(It, copyMBB);
982  F->insert(It, sinkMBB);
983 
984  // Transfer the remainder of BB and its successor edges to sinkMBB.
985  sinkMBB->splice(sinkMBB->begin(), BB,
986  std::next(MachineBasicBlock::iterator(MI)), BB->end());
988 
989  // Next, add the true and fallthrough blocks as its successors.
990  BB->addSuccessor(copyMBB);
991  BB->addSuccessor(sinkMBB);
992 
993  // bt32 condition, sinkMBB
994  BuildMI(BB, DL, TII.get(Opcode))
995  .addReg(MI.getOperand(1).getReg())
996  .addMBB(sinkMBB);
997 
998  // copyMBB:
999  // %FalseValue = ...
1000  // # fallthrough to sinkMBB
1001  BB = copyMBB;
1002 
1003  // Update machine-CFG edges
1004  BB->addSuccessor(sinkMBB);
1005 
1006  // sinkMBB:
1007  // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copyMBB ]
1008  // ...
1009  BB = sinkMBB;
1010 
1011  BuildMI(*BB, BB->begin(), DL, TII.get(CSKY::PHI), MI.getOperand(0).getReg())
1012  .addReg(MI.getOperand(2).getReg())
1013  .addMBB(thisMBB)
1014  .addReg(MI.getOperand(3).getReg())
1015  .addMBB(copyMBB);
1016 
1017  MI.eraseFromParent(); // The pseudo instruction is gone now.
1018 
1019  return BB;
1020 }
1021 
1023 CSKYTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1024  MachineBasicBlock *BB) const {
1025  switch (MI.getOpcode()) {
1026  default:
1027  llvm_unreachable("Unexpected instr type to insert");
1028  case CSKY::FSELS:
1029  case CSKY::FSELD:
1030  if (Subtarget.hasE2())
1031  return emitSelectPseudo(MI, BB, CSKY::BT32);
1032  else
1033  return emitSelectPseudo(MI, BB, CSKY::BT16);
1034  case CSKY::ISEL32:
1035  return emitSelectPseudo(MI, BB, CSKY::BT32);
1036  case CSKY::ISEL16:
1037  return emitSelectPseudo(MI, BB, CSKY::BT16);
1038  }
1039 }
1040 
1041 SDValue CSKYTargetLowering::getTargetConstantPoolValue(ExternalSymbolSDNode *N,
1042  EVT Ty,
1043  SelectionDAG &DAG,
1044  unsigned Flags) const {
1045  CSKYConstantPoolValue *CPV =
1047  N->getSymbol(), 0, getModifier(Flags));
1048 
1049  return DAG.getTargetConstantPool(CPV, Ty);
1050 }
1051 
1052 SDValue CSKYTargetLowering::getTargetConstantPoolValue(JumpTableSDNode *N,
1053  EVT Ty,
1054  SelectionDAG &DAG,
1055  unsigned Flags) const {
1056  CSKYConstantPoolValue *CPV =
1058  N->getIndex(), 0, getModifier(Flags));
1059  return DAG.getTargetConstantPool(CPV, Ty);
1060 }
1061 
1062 SDValue CSKYTargetLowering::getTargetConstantPoolValue(BlockAddressSDNode *N,
1063  EVT Ty,
1064  SelectionDAG &DAG,
1065  unsigned Flags) const {
1066  assert(N->getOffset() == 0);
1068  N->getBlockAddress(), CSKYCP::CPBlockAddress, 0, getModifier(Flags),
1069  false);
1070  return DAG.getTargetConstantPool(CPV, Ty);
1071 }
1072 
1073 SDValue CSKYTargetLowering::getTargetConstantPoolValue(ConstantPoolSDNode *N,
1074  EVT Ty,
1075  SelectionDAG &DAG,
1076  unsigned Flags) const {
1077  assert(N->getOffset() == 0);
1079  N->getConstVal(), Type::getInt32Ty(*DAG.getContext()),
1080  CSKYCP::CPConstPool, 0, getModifier(Flags), false);
1081  return DAG.getTargetConstantPool(CPV, Ty);
1082 }
1083 
1084 SDValue CSKYTargetLowering::getTargetNode(GlobalAddressSDNode *N, SDLoc DL,
1085  EVT Ty, SelectionDAG &DAG,
1086  unsigned Flags) const {
1087  return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
1088 }
1089 
1090 SDValue CSKYTargetLowering::getTargetNode(ExternalSymbolSDNode *N, SDLoc DL,
1091  EVT Ty, SelectionDAG &DAG,
1092  unsigned Flags) const {
1093  return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flags);
1094 }
1095 
1096 SDValue CSKYTargetLowering::getTargetNode(JumpTableSDNode *N, SDLoc DL, EVT Ty,
1097  SelectionDAG &DAG,
1098  unsigned Flags) const {
1099  return DAG.getTargetJumpTable(N->getIndex(), Ty, Flags);
1100 }
1101 
1102 SDValue CSKYTargetLowering::getTargetNode(BlockAddressSDNode *N, SDLoc DL,
1103  EVT Ty, SelectionDAG &DAG,
1104  unsigned Flags) const {
1105  return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, N->getOffset(),
1106  Flags);
1107 }
1108 
1109 SDValue CSKYTargetLowering::getTargetNode(ConstantPoolSDNode *N, SDLoc DL,
1110  EVT Ty, SelectionDAG &DAG,
1111  unsigned Flags) const {
1112 
1113  return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(),
1114  N->getOffset(), Flags);
1115 }
1116 
1117 const char *CSKYTargetLowering::getTargetNodeName(unsigned Opcode) const {
1118  switch (Opcode) {
1119  default:
1120  llvm_unreachable("unknown CSKYISD node");
1121  case CSKYISD::NIE:
1122  return "CSKYISD::NIE";
1123  case CSKYISD::NIR:
1124  return "CSKYISD::NIR";
1125  case CSKYISD::RET:
1126  return "CSKYISD::RET";
1127  case CSKYISD::CALL:
1128  return "CSKYISD::CALL";
1129  case CSKYISD::CALLReg:
1130  return "CSKYISD::CALLReg";
1131  case CSKYISD::TAIL:
1132  return "CSKYISD::TAIL";
1133  case CSKYISD::TAILReg:
1134  return "CSKYISD::TAILReg";
1135  case CSKYISD::LOAD_ADDR:
1136  return "CSKYISD::LOAD_ADDR";
1138  return "CSKYISD::BITCAST_TO_LOHI";
1140  return "CSKYISD::BITCAST_FROM_LOHI";
1141  }
1142 }
1143 
1144 SDValue CSKYTargetLowering::LowerGlobalAddress(SDValue Op,
1145  SelectionDAG &DAG) const {
1146  SDLoc DL(Op);
1147  EVT Ty = Op.getValueType();
1148  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1149  int64_t Offset = N->getOffset();
1150 
1151  const GlobalValue *GV = N->getGlobal();
1152  bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1153  SDValue Addr = getAddr<GlobalAddressSDNode, false>(N, DAG, IsLocal);
1154 
1155  // In order to maximise the opportunity for common subexpression elimination,
1156  // emit a separate ADD node for the global address offset instead of folding
1157  // it in the global address node. Later peephole optimisations may choose to
1158  // fold it back in when profitable.
1159  if (Offset != 0)
1160  return DAG.getNode(ISD::ADD, DL, Ty, Addr,
1161  DAG.getConstant(Offset, DL, MVT::i32));
1162  return Addr;
1163 }
1164 
1165 SDValue CSKYTargetLowering::LowerExternalSymbol(SDValue Op,
1166  SelectionDAG &DAG) const {
1167  ExternalSymbolSDNode *N = cast<ExternalSymbolSDNode>(Op);
1168 
1169  return getAddr(N, DAG, false);
1170 }
1171 
1172 SDValue CSKYTargetLowering::LowerJumpTable(SDValue Op,
1173  SelectionDAG &DAG) const {
1174  JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
1175 
1176  return getAddr<JumpTableSDNode, false>(N, DAG);
1177 }
1178 
1179 SDValue CSKYTargetLowering::LowerBlockAddress(SDValue Op,
1180  SelectionDAG &DAG) const {
1181  BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
1182 
1183  return getAddr(N, DAG);
1184 }
1185 
1186 SDValue CSKYTargetLowering::LowerConstantPool(SDValue Op,
1187  SelectionDAG &DAG) const {
1188  assert(!Subtarget.hasE2());
1189  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1190 
1191  return getAddr(N, DAG);
1192 }
1193 
1194 SDValue CSKYTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1195  MachineFunction &MF = DAG.getMachineFunction();
1197 
1198  SDLoc DL(Op);
1199  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1200  getPointerTy(MF.getDataLayout()));
1201 
1202  // vastart just stores the address of the VarArgsFrameIndex slot into the
1203  // memory location argument.
1204  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1205  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1206  MachinePointerInfo(SV));
1207 }
1208 
1209 SDValue CSKYTargetLowering::LowerFRAMEADDR(SDValue Op,
1210  SelectionDAG &DAG) const {
1211  const CSKYRegisterInfo &RI = *Subtarget.getRegisterInfo();
1212  MachineFunction &MF = DAG.getMachineFunction();
1213  MachineFrameInfo &MFI = MF.getFrameInfo();
1214  MFI.setFrameAddressIsTaken(true);
1215 
1216  EVT VT = Op.getValueType();
1217  SDLoc dl(Op);
1218  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1219  Register FrameReg = RI.getFrameRegister(MF);
1220  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1221  while (Depth--)
1222  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1223  MachinePointerInfo());
1224  return FrameAddr;
1225 }
1226 
1227 SDValue CSKYTargetLowering::LowerRETURNADDR(SDValue Op,
1228  SelectionDAG &DAG) const {
1229  const CSKYRegisterInfo &RI = *Subtarget.getRegisterInfo();
1230  MachineFunction &MF = DAG.getMachineFunction();
1231  MachineFrameInfo &MFI = MF.getFrameInfo();
1232  MFI.setReturnAddressIsTaken(true);
1233 
1235  return SDValue();
1236 
1237  EVT VT = Op.getValueType();
1238  SDLoc dl(Op);
1239  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1240  if (Depth) {
1241  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1242  SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1243  return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1244  DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1245  MachinePointerInfo());
1246  }
1247  // Return the value of the return address register, marking it an implicit
1248  // live-in.
1249  unsigned Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(MVT::i32));
1250  return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1251 }
1252 
1253 Register CSKYTargetLowering::getExceptionPointerRegister(
1254  const Constant *PersonalityFn) const {
1255  return CSKY::R0;
1256 }
1257 
1258 Register CSKYTargetLowering::getExceptionSelectorRegister(
1259  const Constant *PersonalityFn) const {
1260  return CSKY::R1;
1261 }
1262 
1263 SDValue CSKYTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1264  SelectionDAG &DAG) const {
1265  SDLoc DL(Op);
1266  EVT Ty = Op.getValueType();
1267  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1268  int64_t Offset = N->getOffset();
1269  MVT XLenVT = MVT::i32;
1270 
1272  SDValue Addr;
1273  switch (Model) {
1274  case TLSModel::LocalExec:
1275  Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/false);
1276  break;
1277  case TLSModel::InitialExec:
1278  Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/true);
1279  break;
1282  Addr = getDynamicTLSAddr(N, DAG);
1283  break;
1284  }
1285 
1286  // In order to maximise the opportunity for common subexpression elimination,
1287  // emit a separate ADD node for the global address offset instead of folding
1288  // it in the global address node. Later peephole optimisations may choose to
1289  // fold it back in when profitable.
1290  if (Offset != 0)
1291  return DAG.getNode(ISD::ADD, DL, Ty, Addr,
1292  DAG.getConstant(Offset, DL, XLenVT));
1293  return Addr;
1294 }
1295 
1296 SDValue CSKYTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,
1297  SelectionDAG &DAG,
1298  bool UseGOT) const {
1299  MachineFunction &MF = DAG.getMachineFunction();
1301 
1302  unsigned CSKYPCLabelIndex = CFI->createPICLabelUId();
1303 
1304  SDLoc DL(N);
1305  EVT Ty = getPointerTy(DAG.getDataLayout());
1306 
1308  bool AddCurrentAddr = UseGOT ? true : false;
1309  unsigned char PCAjust = UseGOT ? 4 : 0;
1310 
1311  CSKYConstantPoolValue *CPV =
1312  CSKYConstantPoolConstant::Create(N->getGlobal(), CSKYCP::CPValue, PCAjust,
1313  Flag, AddCurrentAddr, CSKYPCLabelIndex);
1314  SDValue CAddr = DAG.getTargetConstantPool(CPV, Ty);
1315 
1316  SDValue Load;
1317  if (UseGOT) {
1318  SDValue PICLabel = DAG.getTargetConstant(CSKYPCLabelIndex, DL, MVT::i32);
1319  auto *LRWGRS = DAG.getMachineNode(CSKY::PseudoTLSLA32, DL, {Ty, Ty},
1320  {CAddr, PICLabel});
1321  auto LRWADDGRS =
1322  DAG.getNode(ISD::ADD, DL, Ty, SDValue(LRWGRS, 0), SDValue(LRWGRS, 1));
1323  Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), LRWADDGRS,
1324  MachinePointerInfo(N->getGlobal()));
1325  } else {
1326  Load = SDValue(DAG.getMachineNode(CSKY::LRW32, DL, Ty, CAddr), 0);
1327  }
1328 
1329  // Add the thread pointer.
1330  SDValue TPReg = DAG.getRegister(CSKY::R31, MVT::i32);
1331  return DAG.getNode(ISD::ADD, DL, Ty, Load, TPReg);
1332 }
1333 
1334 SDValue CSKYTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,
1335  SelectionDAG &DAG) const {
1336  MachineFunction &MF = DAG.getMachineFunction();
1338 
1339  unsigned CSKYPCLabelIndex = CFI->createPICLabelUId();
1340 
1341  SDLoc DL(N);
1342  EVT Ty = getPointerTy(DAG.getDataLayout());
1343  IntegerType *CallTy = Type::getIntNTy(*DAG.getContext(), Ty.getSizeInBits());
1344 
1345  CSKYConstantPoolValue *CPV =
1347  CSKYCP::TLSGD, true, CSKYPCLabelIndex);
1348  SDValue Addr = DAG.getTargetConstantPool(CPV, Ty);
1349  SDValue PICLabel = DAG.getTargetConstant(CSKYPCLabelIndex, DL, MVT::i32);
1350 
1351  auto *LRWGRS =
1352  DAG.getMachineNode(CSKY::PseudoTLSLA32, DL, {Ty, Ty}, {Addr, PICLabel});
1353 
1354  auto Load =
1355  DAG.getNode(ISD::ADD, DL, Ty, SDValue(LRWGRS, 0), SDValue(LRWGRS, 1));
1356 
1357  // Prepare argument list to generate call.
1358  ArgListTy Args;
1359  ArgListEntry Entry;
1360  Entry.Node = Load;
1361  Entry.Ty = CallTy;
1362  Args.push_back(Entry);
1363 
1364  // Setup call to __tls_get_addr.
1366  CLI.setDebugLoc(DL)
1367  .setChain(DAG.getEntryNode())
1368  .setLibCallee(CallingConv::C, CallTy,
1369  DAG.getExternalSymbol("__tls_get_addr", Ty),
1370  std::move(Args));
1371  SDValue V = LowerCallTo(CLI).first;
1372 
1373  return V;
1374 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:77
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:70
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:151
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:959
llvm::SelectionDAG::getMemcpy
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
Definition: SelectionDAG.cpp:7330
i
i
Definition: README.txt:29
llvm::ISD::ExternalSymbol
@ ExternalSymbol
Definition: ISDOpcodes.h:83
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1437
llvm::TargetLoweringBase::setSchedulingPreference
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
Definition: TargetLowering.h:2296
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:988
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::CSKYCP::PLT
@ PLT
Definition: CSKYConstantPoolValue.h:40
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::ISD::JumpTable
@ JumpTable
Definition: ISDOpcodes.h:81
llvm::CSKYCP::TLSGD
@ TLSGD
Definition: CSKYConstantPoolValue.h:40
CSKYConstantPoolValue.h
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1106
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:34
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:196
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
CSKYCallingConv.h
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:886
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::MachineFrameInfo::setReturnAddressIsTaken
void setReturnAddressIsTaken(bool s)
Definition: MachineFrameInfo.h:378
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4554
llvm::CSKYConstantPoolJT::Create
static CSKYConstantPoolJT * Create(Type *Ty, int JTI, unsigned PCAdj, CSKYCP::CSKYCPModifier Modifier)
Definition: CSKYConstantPoolValue.cpp:209
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:991
PHI
Rewrite undef for PHI
Definition: AMDGPURewriteUndefForPHI.cpp:101
llvm::SelectionDAG::addNoMergeSiteInfo
void addNoMergeSiteInfo(const SDNode *Node, bool NoMerge)
Set NoMergeSiteInfo to be associated with Node if NoMerge is true.
Definition: SelectionDAG.h:2249
llvm::CSKYCP::CPBlockAddress
@ CPBlockAddress
Definition: CSKYConstantPoolValue.h:34
llvm::ISD::NON_EXTLOAD
@ NON_EXTLOAD
Definition: ISDOpcodes.h:1404
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:767
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:159
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
CSKYRegisterInfo.h
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:700
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
convertValVTToLocVT
static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
Definition: CSKYISelLowering.cpp:195
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:976
llvm::TLSModel::GeneralDynamic
@ GeneralDynamic
Definition: CodeGen.h:43
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1739
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
Statistic.h
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1057
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:9378
llvm::CSKYISD::NIR
@ NIR
Definition: CSKYISelLowering.h:28
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
llvm::CSKYConstantPoolConstant::Create
static CSKYConstantPoolConstant * Create(const Constant *C, CSKYCP::CSKYCPKind Kind, unsigned PCAdjust, CSKYCP::CSKYCPModifier Modifier, bool AddCurrentAddress, unsigned ID=0)
Definition: CSKYConstantPoolValue.cpp:86
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::CSKYMachineFunctionInfo::setVarArgsSaveSize
void setVarArgsSaveSize(int Size)
Definition: CSKYMachineFunctionInfo.h:53
llvm::CSKYMachineFunctionInfo
Definition: CSKYMachineFunctionInfo.h:20
getModifier
static CSKYCP::CSKYCPModifier getModifier(unsigned Flags)
Definition: CSKYISelLowering.cpp:763
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:282
R4
#define R4(n)
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::TargetLowering::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetLowering.cpp:46
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1793
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1439
MachineJumpTableInfo.h
llvm::CSKYISD::CALL
@ CALL
Definition: CSKYISelLowering.h:30
llvm::CSKYRegisterInfo
Definition: CSKYRegisterInfo.h:24
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:749
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:8038
llvm::CSKYCP::GOT
@ GOT
Definition: CSKYConstantPoolValue.h:40
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:44
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2506
llvm::TargetLowering::LowerCallTo
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
Definition: SelectionDAGBuilder.cpp:9814
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::CSKYMachineFunctionInfo::setVarArgsFrameIndex
void setVarArgsFrameIndex(int v)
Definition: CSKYMachineFunctionInfo.h:49
llvm::codeview::EncodedFramePtrReg::StackPtr
@ StackPtr
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1086
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1404
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2195
llvm::CSKYISD::RET
@ RET
Definition: CSKYISelLowering.h:29
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::CSKYCP::CPConstPool
@ CPConstPool
Definition: CSKYConstantPoolValue.h:37
llvm::Type::getInt32Ty
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:239
llvm::ISD::SETUEQ
@ SETUEQ
Definition: ISDOpcodes.h:1435
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:479
llvm::ISD::ADDCARRY
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:303
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:2121
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::MipsISD::Hi
@ Hi
Definition: MipsISelLowering.h:75
llvm::CSKYTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: CSKYISelLowering.cpp:187
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1404
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1008
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7988
R2
#define R2(n)
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::CSKYII::MO_GOT32
@ MO_GOT32
Definition: CSKYBaseInfo.h:43
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:728
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2237
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:702
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::CSKYSubtarget::hasFPUv2SingleFloat
bool hasFPUv2SingleFloat() const
Definition: CSKYSubtarget.h:139
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::SelectionDAG::getTargetBlockAddress
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:762
llvm::ISD::ABS
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:674
CSKYSubtarget.h
llvm::CSKYCP::NO_MOD
@ NO_MOD
Definition: CSKYConstantPoolValue.h:40
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:148
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:58
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1514
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1862
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3490
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
unpackFromMemLoc
static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
Definition: CSKYISelLowering.cpp:257
llvm::CSKYMachineFunctionInfo::getVarArgsFrameIndex
int getVarArgsFrameIndex()
Definition: CSKYMachineFunctionInfo.h:50
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:341
llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
Definition: TargetLowering.h:233
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2343
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::IntegerType
Class to represent integer types.
Definition: DerivedTypes.h:40
llvm::CallingConv::C
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::TargetLowering::C_Register
@ C_Register
Definition: TargetLowering.h:4555
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:153
llvm::ISD::FSINCOS
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:960
llvm::CSKYSubtarget::getRegisterInfo
const CSKYRegisterInfo * getRegisterInfo() const override
Definition: CSKYSubtarget.h:119
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:149
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::TargetLoweringBase::setBooleanVectorContents
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Definition: TargetLowering.h:2291
llvm::EVT::changeVectorElementTypeToInteger
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
Definition: ValueTypes.h:93
llvm::CSKYSubtarget
Definition: CSKYSubtarget.h:30
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:143
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1436
GPRArgRegs
static const MCPhysReg GPRArgRegs[]
Definition: CSKYISelLowering.cpp:34
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:715
llvm::CSKYISD::LOAD_ADDR
@ LOAD_ADDR
Definition: CSKYISelLowering.h:34
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
llvm::ISD::FPOW
@ FPOW
Definition: ISDOpcodes.h:918
llvm::CSKYConstantPoolSymbol::Create
static CSKYConstantPoolSymbol * Create(Type *Ty, const char *S, unsigned PCAdjust, CSKYCP::CSKYCPModifier Modifier)
Definition: CSKYConstantPoolValue.cpp:143
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2360
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:629
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::pdb::PDB_ColorItem::Address
@ Address
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::CSKYII::MO_GOTOFF
@ MO_GOTOFF
Definition: CSKYBaseInfo.h:44
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:416
llvm::CSKYTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: CSKYISelLowering.cpp:161
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::ISD::ATOMIC_FENCE
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:1155
llvm::TLSModel::LocalDynamic
@ LocalDynamic
Definition: CodeGen.h:44
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:652
llvm::TargetLowering::verifyReturnAddressArgumentIsConstant
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
Definition: TargetLowering.cpp:6653
llvm::CSKYII::MO_None
@ MO_None
Definition: CSKYBaseInfo.h:41
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Definition: SelectionDAG.cpp:1634
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:197
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:793
llvm::CSKYConstantPoolValue
CSKYConstantPoolValue - CSKY specific constantpool value.
Definition: CSKYConstantPoolValue.h:46
llvm::CSKYCP::GOTOFF
@ GOTOFF
Definition: CSKYConstantPoolValue.h:40
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2309
llvm::CSKYSubtarget::useHardFloat
bool useHardFloat() const
Definition: CSKYSubtarget.h:138
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:9072
llvm::CSKYCP::ADDR
@ ADDR
Definition: CSKYConstantPoolValue.h:40
llvm::CSKYMachineFunctionInfo::createPICLabelUId
unsigned createPICLabelUId()
Definition: CSKYMachineFunctionInfo.h:61
llvm::StringRef::lower
std::string lower() const
Definition: StringRef.cpp:112
llvm::ISD::FCOPYSIGN
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:492
llvm::TargetMachine::getTLSModel
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
Definition: TargetMachine.cpp:154
llvm::MachineFrameInfo::setHasTailCall
void setHasTailCall(bool V=true)
Definition: MachineFrameInfo.h:639
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1404
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:179
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:4138
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:638
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1438
llvm::CSKYCP::CPValue
@ CPValue
Definition: CSKYConstantPoolValue.h:32
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1424
llvm::SelectionDAG::getMachineNode
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
Definition: SelectionDAG.cpp:9816
llvm::ISD::RETURNADDR
@ RETURNADDR
Definition: ISDOpcodes.h:95
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::ISD::SUBCARRY
@ SUBCARRY
Definition: ISDOpcodes.h:304
llvm::CSKYISD::BITCAST_FROM_LOHI
@ BITCAST_FROM_LOHI
Definition: CSKYISelLowering.h:38
R6
#define R6(n)
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:750
unpack64
static SDValue unpack64(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
Definition: CSKYISelLowering.cpp:284
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1087
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::SelectionDAG::getCALLSEQ_END
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
Definition: SelectionDAG.h:1000
llvm::CSKYSubtarget::useHardFloatABI
bool useHardFloatABI() const
Definition: CSKYSubtarget.cpp:96
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:679
llvm::ISD::ConstantPool
@ ConstantPool
Definition: ISDOpcodes.h:82
llvm::ISD::GlobalTLSAddress
@ GlobalTLSAddress
Definition: ISDOpcodes.h:79
llvm::CSKYCP::TLSLE
@ TLSLE
Definition: CSKYConstantPoolValue.h:40
llvm::SelectionDAG::getTargetConstantPool
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:731
unpackFromRegLoc
static SDValue unpackFromRegLoc(const CSKYSubtarget &Subtarget, SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
Definition: CSKYISelLowering.cpp:225
llvm::Sched::Source
@ Source
Definition: TargetLowering.h:99
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1883
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:1009
llvm::CSKYCP::CSKYCPModifier
CSKYCPModifier
Definition: CSKYConstantPoolValue.h:40
llvm::CSKYRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: CSKYRegisterInfo.cpp:40
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
uint32_t
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::CSKYISD::TAILReg
@ TAILReg
Definition: CSKYISelLowering.h:33
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Definition: TargetLowering.cpp:5254
llvm::TargetMachine::shouldAssumeDSOLocal
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
Definition: TargetMachine.cpp:88
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition: TargetLowering.h:2399
CSKYISelLowering.h
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:79
llvm::StringSwitch::Cases
StringSwitch & Cases(StringLiteral S0, StringLiteral S1, T Value)
Definition: StringSwitch.h:91
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1404
llvm::TargetLowering::C_RegisterClass
@ C_RegisterClass
Definition: TargetLowering.h:4556
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:314
llvm::SelectionDAG::getTargetJumpTable
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:725
llvm::ISD::FRAMEADDR
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition: ISDOpcodes.h:94
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:187
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:349
j
return j(j<< 16)
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:144
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2377
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1759
llvm::Type::getIntNTy
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
Definition: Type.cpp:243
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
CallingConvLower.h
llvm::CSKYISD::CALLReg
@ CALLReg
Definition: CSKYISelLowering.h:31
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::ISD::FCOS
@ FCOS
Definition: ISDOpcodes.h:916
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:548
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::ISD::FSIN
@ FSIN
Definition: ISDOpcodes.h:915
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:469
llvm::CSKYSubtarget::hasFPUv3SingleFloat
bool hasFPUv3SingleFloat() const
Definition: CSKYSubtarget.h:144
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:200
llvm::CSKYSubtarget::hasFPUv2DoubleFloat
bool hasFPUv2DoubleFloat() const
Definition: CSKYSubtarget.h:140
llvm::SelectionDAG::getTargetExternalSymbol
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:1889
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
llvm::CSKYSubtarget::hasFPUv3DoubleFloat
bool hasFPUv3DoubleFloat() const
Definition: CSKYSubtarget.h:145
convertLocVTToValVT
static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
Definition: CSKYISelLowering.cpp:211
CSKYMachineFunctionInfo.h
llvm::TLSModel::Model
Model
Definition: CodeGen.h:42
llvm::CSKYISD::TAIL
@ TAIL
Definition: CSKYISelLowering.h:32
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1082
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:751
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::TLSModel::InitialExec
@ InitialExec
Definition: CodeGen.h:45
llvm::M68kBeads::DReg
@ DReg
Definition: M68kBaseInfo.h:61
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2277
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::ISD::FREM
@ FREM
Definition: ISDOpcodes.h:394
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1019
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:198
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:141
llvm::CallingConv::Fast
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1284
llvm::ISD::BITREVERSE
@ BITREVERSE
Definition: ISDOpcodes.h:704
llvm::TargetLoweringBase::setMaxAtomicSizeInBitsSupported
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Definition: TargetLowering.h:2533
llvm::CSKYII::MO_ADDR32
@ MO_ADDR32
Definition: CSKYBaseInfo.h:42
llvm::SelectionDAG::getRegisterMask
SDValue getRegisterMask(const uint32_t *RegMask)
Definition: SelectionDAG.cpp:2136
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::TargetLoweringBase::setCondCodeAction
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
Definition: TargetLowering.h:2460
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:701
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:896
llvm::CSKYTargetLowering::CSKYTargetLowering
CSKYTargetLowering(const TargetMachine &TM, const CSKYSubtarget &STI)
Definition: CSKYISelLowering.cpp:36
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:285
llvm::CSKYCP::TLSIE
@ TLSIE
Definition: CSKYConstantPoolValue.h:40
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::ISD::MULHU
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:637
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:901
llvm::StringSwitch::Default
R Default(T Value)
Definition: StringSwitch.h:183
llvm::CSKYSubtarget::hasE2
bool hasE2() const
Definition: CSKYSubtarget.h:187
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:669
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:45
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::ISD::SETONE
@ SETONE
Definition: ISDOpcodes.h:1432
llvm::DataLayout::getPointerSizeInBits
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:412
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:47
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:466
llvm::omp::RTLDependInfoFields::Flags
@ Flags
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1077
llvm::ISD::SDIVREM
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
llvm::SelectionDAG::getExternalSymbol
SDValue getExternalSymbol(const char *Sym, EVT VT)
Definition: SelectionDAG.cpp:1872
llvm::CSKYISD::NIE
@ NIE
Definition: CSKYISelLowering.h:27
llvm::CSKYII::MO_PLT32
@ MO_PLT32
Definition: CSKYBaseInfo.h:45
llvm::CSKYISD::BITCAST_TO_LOHI
@ BITCAST_TO_LOHI
Definition: CSKYISelLowering.h:36
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::CSKYSubtarget::has2E3
bool has2E3() const
Definition: CSKYSubtarget.h:188
llvm::MachineFrameInfo::setFrameAddressIsTaken
void setFrameAddressIsTaken(bool T)
Definition: MachineFrameInfo.h:372
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::ISD::STACKSAVE
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1053
llvm::SelectionDAG::getExtLoad
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Definition: SelectionDAG.cpp:8005
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:57
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:695
Debug.h
emitSelectPseudo
static MachineBasicBlock * emitSelectPseudo(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode)
Definition: CSKYISelLowering.cpp:960
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:483
llvm::TargetLowering::getConstraintType
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Definition: TargetLowering.cpp:5109
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:356
llvm::ISD::CTPOP
@ CTPOP
Definition: ISDOpcodes.h:703
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:288
llvm::TLSModel::LocalExec
@ LocalExec
Definition: CodeGen.h:46
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1240
llvm::TargetLoweringBase::UndefinedBooleanContent
@ UndefinedBooleanContent
Definition: TargetLowering.h:231