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21 #define GET_REGINFO_TARGET_DESC
22 #include "CSKYGenRegisterInfo.inc"
34 return CSR_GPR_FPR64_RegMask;
36 return CSR_GPR_FPR32_RegMask;
37 return CSR_I32_RegMask;
42 return TFI->
hasFP(MF) ? CSKY::R8 : CSKY::R14;
59 for (
unsigned i = 0;
i < 6;
i++)
67 for (
unsigned i = 0;
i < 10;
i++)
83 return CSR_NoRegs_RegMask;
91 return CSR_GPR_FPR64v3_ISR_SaveList;
93 return CSR_GPR_FPR32v3_ISR_SaveList;
95 return CSR_GPR_FPR64_ISR_SaveList;
97 return CSR_GPR_FPR32_ISR_SaveList;
98 return CSR_GPR_ISR_SaveList;
102 return CSR_GPR_FPR64_SaveList;
104 return CSR_GPR_FPR32_SaveList;
105 return CSR_I32_SaveList;
113 for (; !
MI->getOperand(
i).isFI(); ++
i) {
115 "Instr doesn't have FrameIndex operand!");
118 if (
MI->getOpcode() == CSKY::ADDI32) {
122 MI->setDesc(
TII->get(CSKY::SUBI32));
129 if (
MI->getOpcode() == CSKY::ADDI16XZ)
135 unsigned NumBits = 0;
171 if ((
Offset & (Scale - 1)) != 0)
174 unsigned Mask = (1 << NumBits) - 1;
183 int SPAdj,
unsigned FIOperandNum,
185 assert(SPAdj == 0 &&
"Unexpected non-zero SPAdj value");
195 switch (
MI->getOpcode()) {
198 case CSKY::RESTORE_CARRY: {
204 .
add(
MI->getOperand(1))
205 .
add(
MI->getOperand(2))
209 MI->getOperand(0).getReg())
218 case CSKY::SPILL_CARRY: {
223 .
add(
MI->getOperand(0));
232 .
addReg(
MI->getOperand(0).getReg());
241 .
add(
MI->getOperand(1))
242 .
add(
MI->getOperand(2))
251 int FrameIndex =
MI->getOperand(FIOperandNum).getIndex();
253 int Offset = getFrameLowering(MF)
254 ->getFrameIndexReference(MF,
FrameIndex, FrameReg)
256 MI->getOperand(FIOperandNum + 1).getImm();
260 "Frame offsets outside of the signed 32-bit range not supported");
262 bool FrameRegIsKill =
false;
270 TII->get(STI.
hasE2() ? CSKY::ADDU32 : CSKY::ADDU16XZ), ScratchReg)
275 FrameReg = ScratchReg;
276 FrameRegIsKill =
true;
280 (
MI->getOpcode() == CSKY::ADDI32 ||
MI->getOpcode() == CSKY::ADDI16XZ)) {
281 MI->setDesc(
TII->get(TargetOpcode::COPY));
282 MI->getOperand(FIOperandNum)
283 .ChangeToRegister(FrameReg,
false,
false, FrameRegIsKill);
284 MI->removeOperand(FIOperandNum + 1);
286 MI->getOperand(FIOperandNum)
287 .ChangeToRegister(FrameReg,
false,
false, FrameRegIsKill);
288 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(
Offset);
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
Information about stack frame layout on the target.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MachineInstrBuilder & add(const MachineOperand &MO) const
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
BitVector getReservedRegs(const MachineFunction &MF) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool hasFPUv2SingleFloat() const
const uint32_t * getNoPreservedMask() const override
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool hasBP(const MachineFunction &MF) const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Representation of each machine instruction.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getFrameRegister(const MachineFunction &MF) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
Function & getFunction()
Return the LLVM function that this machine code represents.
bool hasFPUv3SingleFloat() const
bool hasFPUv2DoubleFloat() const
static bool IsLegalOffset(const CSKYInstrInfo *TII, MachineInstr *MI, int &Offset)
bool hasFPUv3DoubleFloat() const
@ Kill
The last use of a register.
unsigned getKillRegState(bool B)
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID id) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
APFloat abs(APFloat X)
Returns the absolute value of the argument.
@ Define
Register definition.
bool hasHighRegisters() const