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13 #ifndef LLVM_LIB_TARGET_CSKY_CSKYINSTRINFO_H
14 #define LLVM_LIB_TARGET_CSKY_CSKYINSTRINFO_H
19 #define GET_INSTRINFO_HEADER
20 #include "CSKYGenInstrInfo.inc"
56 bool KillSrc)
const override;
61 int *BytesAdded =
nullptr)
const override;
66 bool AllowModify =
false)
const override;
69 int *BytesRemoved =
nullptr)
const override;
88 #endif // LLVM_LIB_TARGET_CSKY_CSKYINSTRINFO_H
This is an optimization pass for GlobalISel generic memory operations.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
unsigned const TargetRegisterInfo * TRI
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Representation of each machine instruction.
Register getGlobalBaseReg(MachineFunction &MF) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
SmallVector< MachineOperand, 4 > Cond
MachineBasicBlock MachineBasicBlock::iterator MBBI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Wrapper class representing virtual and physical registers.
CSKYInstrInfo(CSKYSubtarget &STI)
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Register movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, int64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
const CSKYSubtarget & STI
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Wrapper class representing physical registers. Should be passed by value.