LLVM 19.0.0git
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#include "RISCVISelLowering.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVRegisterInfo.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/DiagnosticPrinter.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/InstructionCost.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <optional>
#include "RISCVGenAsmMatcher.inc"
#include "RISCVGenSearchableTables.inc"
Go to the source code of this file.
Classes | |
struct | VIDSequence |
Namespaces | |
namespace | llvm |
This is an optimization pass for GlobalISel generic memory operations. | |
namespace | llvm::RISCVVIntrinsicsTable |
Macros | |
#define | DEBUG_TYPE "riscv-lower" |
#define | OP_CASE(NODE) |
#define | VP_CASE(NODE) |
#define | NODE_NAME_CASE(NODE) |
#define | GET_REGISTER_MATCHER |
#define | GET_RISCVVIntrinsicsTable_IMPL |
Variables | |
static cl::opt< unsigned > | ExtensionMaxWebSize (DEBUG_TYPE "-ext-max-web-size", cl::Hidden, cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion"), cl::init(18)) |
static cl::opt< bool > | AllowSplatInVW_W (DEBUG_TYPE "-form-vw-w-with-splat", cl::Hidden, cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants"), cl::init(false)) |
static cl::opt< unsigned > | NumRepeatedDivisors (DEBUG_TYPE "-fp-repeated-divisors", cl::Hidden, cl::desc("Set the minimum number of repetitions of a divisor to allow " "transformation to multiplications by the reciprocal"), cl::init(2)) |
static cl::opt< int > | FPImmCost (DEBUG_TYPE "-fpimm-cost", cl::Hidden, cl::desc("Give the maximum number of instructions that we will " "use for creating a floating-point immediate value"), cl::init(2)) |
static cl::opt< bool > | RV64LegalI32 ("riscv-experimental-rv64-legal-i32", cl::ReallyHidden, cl::desc("Make i32 a legal type for SelectionDAG on RV64.")) |
static const MCPhysReg | ArgFPR16s [] |
static const MCPhysReg | ArgFPR32s [] |
static const MCPhysReg | ArgFPR64s [] |
static const MCPhysReg | ArgVRs [] |
static const MCPhysReg | ArgVRM2s [] |
static const MCPhysReg | ArgVRM4s [] |
static const MCPhysReg | ArgVRM8s [] = {RISCV::V8M8, RISCV::V16M8} |
static const Intrinsic::ID | FixedVlsegIntrIds [] |
static const Intrinsic::ID | FixedVssegIntrIds [] |
#define DEBUG_TYPE "riscv-lower" |
Definition at line 51 of file RISCVISelLowering.cpp.
#define GET_REGISTER_MATCHER |
Definition at line 21138 of file RISCVISelLowering.cpp.
#define GET_RISCVVIntrinsicsTable_IMPL |
Definition at line 21456 of file RISCVISelLowering.cpp.
#define NODE_NAME_CASE | ( | NODE | ) |
#define OP_CASE | ( | NODE | ) |
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Definition at line 18222 of file RISCVISelLowering.cpp.
References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), ArgGPRs, llvm::CCValAssign::Full, llvm::RISCV::getArgGPRs(), llvm::CCValAssign::getLocVT(), llvm::CCState::getMachineFunction(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getReg(), llvm::MachineFunction::getSubtarget(), llvm::RISCVSubtarget::getTargetABI(), llvm::CCValAssign::getValNo(), and llvm::CCValAssign::getValVT().
Referenced by llvm::RISCV::CC_RISCV().
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Definition at line 15201 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, CC, llvm::ISD::Constant, DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::RISCVSubtarget::getXLenVT(), llvm::Value::hasOneUse(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::isPowerOf2_64(), LHS, llvm::Log2_64(), llvm::SelectionDAG::MaskedValueIsZero(), RHS, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, translateSetCCForBranch(), tryDemorganOfBooleanCondition(), and llvm::ISD::XOR.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 13038 of file RISCVISelLowering.cpp.
References DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::ISD::SUB, and llvm::ISD::XOR.
Referenced by performADDCombine().
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Combine a binary operation to its equivalent VW or VW_W form.
The supported combines are: add | add_vl | or disjoint -> vwadd(u) | vwadd(u)_w sub | sub_vl -> vwsub(u) | vwsub(u)_w mul | mul_vl -> vwmul(u) | vwmul_su shl | shl_vl -> vwsll fadd_vl -> vfwadd | vfwadd_w fsub_vl -> vfwsub | vfwsub_w fmul_vl -> vfwmul vwadd_w(u) -> vwadd(u) vwsub_w(u) -> vwsub(u) vfwadd_w -> vfwadd vfwsub_w -> vfwsub
Definition at line 14406 of file RISCVISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorBase< Size_T >::empty(), ExtensionMaxWebSize, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), LHS, N, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SmallVectorImpl< T >::reserve(), RHS, llvm::SmallVectorBase< Size_T >::size(), and std::swap().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine(), and performVWADDSUBW_VLCombine().
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Perform two related transforms whose purpose is to incrementally recognize an explode_vector followed by scalar reduction as a vector reduction node.
This exists to recover from a deficiency in SLP which can't handle forests with multiple roots sharing common nodes. In some cases, one of the trees will be vectorized, and the other will remain (unprofitably) scalarized.
Definition at line 12583 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::SelectionDAG::getContext(), llvm::RISCVSubtarget::getELen(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::ISD::getVecReduceBaseOpcode(), getVecReduceOpcode(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::Value::hasOneUse(), llvm::RISCVSubtarget::hasVInstructions(), llvm::EVT::isInteger(), llvm::isNullConstant(), llvm::EVT::isScalableVector(), LHS, N, llvm::SelectionDAG::NewNodesMustHaveLegalTypes, RHS, and std::swap().
Referenced by performADDCombine(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performORCombine(), and performXORCombine().
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Definition at line 12996 of file RISCVISelLowering.cpp.
References llvm::CallingConv::C, llvm::SelectionDAG::getContext(), llvm::EVT::getHalfSizedIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), N, llvm::ISD::SIGN_EXTEND, llvm::ISD::SUB, and llvm::ISD::ZERO_EXTEND.
Referenced by performADDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performMULCombine(), and performSUBCombine().
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Definition at line 12679 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_SUBVECTOR, llvm::isNeutralConstant(), isNonZeroAVL(), llvm::isNullConstant(), llvm::SDNode::isUndef(), llvm_unreachable, lowerScalarInsert(), N, llvm::ISD::OR, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::RISCVISD::VECREDUCE_ADD_VL, llvm::RISCVISD::VECREDUCE_AND_VL, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::RISCVISD::VECREDUCE_OR_VL, llvm::RISCVISD::VECREDUCE_SMAX_VL, llvm::RISCVISD::VECREDUCE_SMIN_VL, llvm::RISCVISD::VECREDUCE_UMAX_VL, llvm::RISCVISD::VECREDUCE_UMIN_VL, llvm::RISCVISD::VECREDUCE_XOR_VL, llvm::RISCVISD::VFMV_S_F_VL, llvm::RISCVISD::VMV_S_X_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::ISD::XOR.
Referenced by performADDCombine(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performORCombine(), and performXORCombine().
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Definition at line 13154 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::ISD::OR, and llvm::ISD::XOR.
Referenced by performANDCombine(), and performORCombine().
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Definition at line 13264 of file RISCVISelLowering.cpp.
References assert(), Cond, llvm::RISCVISD::CZERO_EQZ, llvm::RISCVISD::CZERO_NEZ, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::isOneConstant(), N, llvm::ISD::OR, and llvm::ISD::XOR.
Referenced by performORCombine().
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Definition at line 12841 of file RISCVISelLowering.cpp.
References llvm::AllOnes, llvm::ISD::AND, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::hasConditionalMoveFusion(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::isNullConstant(), llvm::EVT::isVector(), isZeroOrAllOnes(), N, llvm::ISD::SELECT, llvm::RISCVISD::SELECT_CC, and std::swap().
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Definition at line 12906 of file RISCVISelLowering.cpp.
References llvm::AllOnes, combineSelectAndUse(), and N.
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Definition at line 7310 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, CC, DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SDNode::getAsAPIntVal(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::RISCVSubtarget::hasConditionalMoveFusion(), llvm::isAllOnesConstant(), llvm::isNullConstant(), LHS, matchSetCC(), N, llvm::ISD::OR, RHS, llvm::ISD::SETCC, and llvm::ISD::XOR.
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Definition at line 13083 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::EVT::isInteger(), llvm::isOneConstant(), llvm::APInt::isSignedIntN(), N, llvm::ISD::SETCC, and llvm::ISD::XOR.
Referenced by performSUBCombine().
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Definition at line 15717 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::RISCVISD::ADD_VL, assert(), DL, getDefaultScalableVLOps(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::isUndef(), N, std::swap(), llvm::RISCVISD::VWMACC_VL, llvm::RISCVISD::VWMACCSU_VL, llvm::RISCVISD::VWMACCU_VL, llvm::RISCVISD::VWMUL_VL, llvm::RISCVISD::VWMULSU_VL, and llvm::RISCVISD::VWMULU_VL.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 14931 of file RISCVISelLowering.cpp.
References A, B, llvm::CallingConv::C, llvm::RISCVISD::FNEG_VL, llvm::SelectionDAG::getNode(), N, negateFMAOpcode(), and llvm::Offset.
Referenced by performVFMADD_VLCombine().
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Definition at line 14504 of file RISCVISelLowering.cpp.
References assert(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::isConstantSplatVectorAllZeros(), llvm::isNullOrNullSplat(), llvm::SDValue::isUndef(), N, llvm::RISCVISD::VMERGE_VL, llvm::RISCVISD::VMSET_VL, llvm::ISD::VSELECT, llvm::RISCVISD::VWADD_W_VL, llvm::RISCVISD::VWADDU_W_VL, llvm::RISCVISD::VWSUB_W_VL, llvm::RISCVISD::VWSUBU_W_VL, X, and Y.
Referenced by performVWADDSUBW_VLCombine().
Definition at line 17080 of file RISCVISelLowering.cpp.
Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode().
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Definition at line 2650 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getXLenVT(), and llvm::EVT::isFixedLengthVector().
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Definition at line 18589 of file RISCVISelLowering.cpp.
References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertFromScalableVector(), DL, llvm::RISCVISD::FMV_H_X, llvm::RISCVISD::FMV_W_X_RV64, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::MVT::isScalableVector(), llvm_unreachable, RV64LegalI32, and llvm::ISD::TRUNCATE.
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Definition at line 2638 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::ISD::INSERT_SUBVECTOR, and llvm::EVT::isScalableVector().
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Definition at line 18653 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertToScalableVector(), DL, llvm::RISCVISD::FMV_X_ANYEXTH, llvm::RISCVISD::FMV_X_ANYEXTW_RV64, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::isFixedLengthVector(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm_unreachable, and RV64LegalI32.
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Definition at line 11804 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), getRISCVWOpcode(), N, and llvm::ISD::TRUNCATE.
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Definition at line 11817 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), N, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::TRUNCATE.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
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Definition at line 17488 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), llvm::HexagonInstrInfo::loadRegFromStackSlot(), MI, llvm::MachineMemOperand::MOStore, and TII.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 17890 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, llvm::RISCVSubtarget::is64Bit(), llvm_unreachable, MBB, MI, MRI, llvm::MachineInstr::NoFPExcept, llvm::MachineInstr::setFlag(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 17578 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::First, llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineOperand::getImm(), llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by emitSelectPseudo().
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Definition at line 17541 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::RegState::Kill, MI, MRI, llvm::MachineInstr::NoFPExcept, llvm::MachineInstr::setFlag(), and TII.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 17388 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getBasicBlock(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::insert(), MI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 17680 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::any_of(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), CC, llvm::MachineInstr::collectDebugValues(), llvm::SmallSet< T, N, C >::count(), DL, EmitLoweredCascadedSelect(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), I, llvm::SmallSet< T, N, C >::insert(), llvm::MachineBasicBlock::instr_end(), isSelectPseudo(), LHS, MI, llvm::next_nodbg(), llvm::MachineFunctionProperties::NoPHIs, llvm::MachineBasicBlock::push_back(), RHS, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
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Definition at line 17453 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), assert(), llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), MI, llvm::MachineMemOperand::MOLoad, llvm::HexagonInstrInfo::storeRegToStackSlot(), and TII.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 17827 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::RISCVII::getLMul(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::RISCVII::getSEWOpNum(), llvm::MachineFunction::getSubtarget(), llvm::RegState::Kill, lookupMaskedIntrinsic(), llvm::RISCV::RISCVMaskedPseudoInfo::MaskedPseudo, MI, MRI, TII, and TRI.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 13398 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::CallingConv::C, llvm::countr_zero(), DL, llvm::SelectionDAG::getConstant(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getXLenVT(), llvm::ConstantSDNode::getZExtValue(), llvm::Function::hasMinSize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isPowerOf2_64(), llvm::Log2_64(), N, llvm::Offset, llvm::ISD::SHL, llvm::RISCVISD::SHL_ADD, llvm::ISD::SUB, and X.
Referenced by performMULCombine().
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Definition at line 7386 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SDNode::getAsAPIntVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSelect(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::APInt::isAllOnes(), llvm::ConstantSDNode::isOpaque(), llvm::APInt::isZero(), llvm::ISD::SELECT, and std::swap().
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Definition at line 15344 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::BitWidth, Cond, llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::isNullConstant(), N, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by performSELECTCombine().
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Creates an all ones mask suitable for masking a vector of type VecTy with vector length VL.
Definition at line 2672 of file RISCVISelLowering.cpp.
References DL, getMaskTypeFor(), llvm::SelectionDAG::getNode(), and llvm::RISCVISD::VMSET_VL.
Referenced by getDefaultScalableVLOps(), getDefaultVLOps(), and lowerVectorIntrinsicScalars().
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Definition at line 2593 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVSubtarget::getELen(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalableVectorVT(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::isFixedLengthVector(), llvm::isPowerOf2_32(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::RISCV::RVVBitsPerBlock, llvm::MVT::SimpleTy, and useRVVForFixedLengthVectorVT().
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Definition at line 2627 of file RISCVISelLowering.cpp.
References getContainerForFixedLengthVector(), and llvm::SelectionDAG::getTargetLoweringInfo().
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Definition at line 2692 of file RISCVISelLowering.cpp.
References assert(), DL, getAllOnesMask(), llvm::SelectionDAG::getRegister(), llvm::RISCVSubtarget::getXLenVT(), and llvm::MVT::isScalableVector().
Referenced by combineToVWMACC(), and getDefaultVLOps().
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Definition at line 2714 of file RISCVISelLowering.cpp.
References assert(), DL, getDefaultScalableVLOps(), getDefaultVLOps(), llvm::MVT::getVectorNumElements(), llvm::MVT::isFixedLengthVector(), and llvm::MVT::isScalableVector().
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Definition at line 2701 of file RISCVISelLowering.cpp.
References assert(), DL, getAllOnesMask(), getVLOp(), and llvm::MVT::isScalableVector().
Referenced by getDefaultVLOps(), getDeinterleaveViaVNSRL(), getWideningInterleave(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerCttzElts(), lowerFMAXIMUM_FMINIMUM(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT(), matchSplatAsGather(), performFP_TO_INTCombine(), and llvm::RISCVTargetLowering::ReplaceNodeResults().
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Definition at line 4368 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementTypeToInteger(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::RISCVISD::VMV_V_X_VL, and llvm::RISCVISD::VNSRL_VL.
Referenced by lowerVECTOR_SHUFFLE().
Definition at line 3250 of file RISCVISelLowering.cpp.
References llvm::BitWidth, llvm::APFloat::convertToInteger(), llvm::APInt::extractBitsAsZExtValue(), llvm::APFloatBase::opInvalidOp, and llvm::TowardZero.
Referenced by isSimpleVIDSequence().
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Definition at line 18201 of file RISCVISelLowering.cpp.
References llvm::RISCVABI::ABI_ILP32E, and llvm::RISCVABI::ABI_LP64E.
Referenced by llvm::RISCV::CC_RISCV_FastCC().
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Definition at line 20254 of file RISCVISelLowering.cpp.
References llvm::AtomicRMWInst::Add, llvm_unreachable, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, and llvm::AtomicRMWInst::Xchg.
Definition at line 3236 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::getScalableVectorVT(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), and llvm::RISCV::RVVBitsPerBlock.
Referenced by getSmallestVTForIndex(), lowerBUILD_VECTOR(), llvm::RISCVTargetLowering::LowerOperation(), lowerReductionSeq(), lowerShuffleViaVRegSplitting(), and llvm::RISCVTargetLowering::PerformDAGCombine().
Return the type of the mask type suitable for masking the provided vector type.
This is simply an i1 element type vector of the same (possibly scalable) length.
Definition at line 2664 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), and llvm::MVT::isVector().
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Definition at line 19159 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), and llvm::EVT::getTypeForEVT().
Get a RISC-V target specified VL op for a given SDNode.
Definition at line 5732 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::RISCVISD::AND_VL, llvm::RISCVISD::CTLZ_VL, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::RISCVISD::CTTZ_VL, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::ISD::FMA, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::RISCVISD::FSQRT_VL, llvm::ISD::LLRINT, llvm_unreachable, llvm::ISD::LRINT, OP_CASE, llvm::ISD::OR, llvm::RISCVISD::OR_VL, ROTR, llvm::RISCVISD::SRA_VL, llvm::RISCVISD::SRL_VL, llvm::ISD::STRICT_FMA, llvm::RISCVISD::STRICT_VFMADD_VL, llvm::RISCVISD::VFCVT_RTZ_X_F_VL, llvm::RISCVISD::VFCVT_RTZ_XU_F_VL, llvm::RISCVISD::VFCVT_X_F_VL, llvm::RISCVISD::VFMADD_VL, llvm::RISCVISD::VFMAX_VL, llvm::RISCVISD::VFMIN_VL, llvm::RISCVISD::VMAND_VL, llvm::RISCVISD::VMERGE_VL, llvm::RISCVISD::VMOR_VL, llvm::RISCVISD::VMXOR_VL, VP_CASE, llvm::RISCVISD::VSEXT_VL, llvm::RISCVISD::VZEXT_VL, llvm::ISD::XOR, and llvm::RISCVISD::XOR_VL.
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Definition at line 11776 of file RISCVISelLowering.cpp.
References llvm::RISCVISD::DIVUW, llvm::RISCVISD::DIVW, llvm_unreachable, llvm::RISCVISD::REMUW, llvm::RISCVISD::ROLW, llvm::RISCVISD::RORW, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::RISCVISD::SLLW, llvm::ISD::SRA, llvm::RISCVISD::SRAW, llvm::ISD::SRL, llvm::RISCVISD::SRLW, llvm::ISD::UDIV, and llvm::ISD::UREM.
Referenced by customLegalizeToWOp().
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Definition at line 9625 of file RISCVISelLowering.cpp.
References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorIdxConstant(), llvm_unreachable, llvm::ISD::VECREDUCE_FADD, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::ISD::VECREDUCE_FMAX, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::ISD::VECREDUCE_FMAXIMUM, llvm::ISD::VECREDUCE_FMIN, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::ISD::VECREDUCE_FMINIMUM, llvm::ISD::VECREDUCE_SEQ_FADD, and llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL.
Definition at line 9411 of file RISCVISelLowering.cpp.
References llvm_unreachable, llvm::ISD::VECREDUCE_ADD, llvm::RISCVISD::VECREDUCE_ADD_VL, llvm::ISD::VECREDUCE_AND, llvm::RISCVISD::VECREDUCE_AND_VL, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::ISD::VECREDUCE_OR, llvm::RISCVISD::VECREDUCE_OR_VL, llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL, llvm::ISD::VECREDUCE_SMAX, llvm::RISCVISD::VECREDUCE_SMAX_VL, llvm::ISD::VECREDUCE_SMIN, llvm::RISCVISD::VECREDUCE_SMIN_VL, llvm::ISD::VECREDUCE_UMAX, llvm::RISCVISD::VECREDUCE_UMAX_VL, llvm::ISD::VECREDUCE_UMIN, llvm::RISCVISD::VECREDUCE_UMIN_VL, llvm::ISD::VECREDUCE_XOR, and llvm::RISCVISD::VECREDUCE_XOR_VL.
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Definition at line 8162 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::bitsGT(), llvm::MVT::getDoubleNumVectorElementsVT(), getLMUL1VT(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::isScalableVector(), and llvm::MVT::isValid().
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Definition at line 7039 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getTargetBlockAddress(), and N.
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Definition at line 7045 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getTargetConstantPool(), and N.
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Definition at line 7034 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getTargetGlobalAddress(), and N.
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Definition at line 7051 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getTargetJumpTable(), and N.
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Definition at line 9136 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getNode(), Operands, and processVCIXOperands().
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Definition at line 9099 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), DL, llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getSubtarget(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), Operands, and processVCIXOperands().
Given a binary operator, return the associative generic ISD::VECREDUCE_OP which corresponds to it.
Definition at line 12550 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::FADD, llvm_unreachable, llvm::ISD::OR, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_FADD, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, llvm::ISD::VECREDUCE_XOR, and llvm::ISD::XOR.
Referenced by combineBinOpOfExtractToReduceTree().
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Definition at line 2678 of file RISCVISelLowering.cpp.
References llvm::RISCVTargetLowering::computeVLMAXBounds(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getRegister(), and llvm::RISCVSubtarget::getXLenVT().
Referenced by getDefaultVLOps().
Definition at line 2508 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::VLOperand.
Referenced by lowerVectorIntrinsicScalars().
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Definition at line 3213 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVII::MASK_AGNOSTIC, Merge, llvm::Offset, llvm::RISCVII::TAIL_AGNOSTIC, and llvm::RISCVISD::VSLIDEDOWN_VL.
Referenced by lowerBUILD_VECTOR(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlidedown(), and llvm::RISCVTargetLowering::ReplaceNodeResults().
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Definition at line 3225 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVII::MASK_AGNOSTIC, Merge, llvm::Offset, llvm::RISCVII::TAIL_AGNOSTIC, and llvm::RISCVISD::VSLIDEUP_VL.
Referenced by lowerVECTOR_SHUFFLE(), and lowerVECTOR_SHUFFLEAsVSlideup().
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Definition at line 4602 of file RISCVISelLowering.cpp.
References llvm::RISCVISD::ADD_VL, assert(), llvm::MVT::changeTypeToInteger(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::SDValue::isUndef(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::multiplyCoefficientBy(), llvm::RISCVISD::SHL_VL, llvm::RISCVISD::VWADDU_VL, llvm::RISCVISD::VWADDU_W_VL, llvm::RISCVISD::VWMULU_VL, llvm::RISCVISD::VWSLL_VL, and llvm::RISCVISD::VZEXT_VL.
Referenced by lowerVECTOR_SHUFFLE().
Return true if a RISC-V target specified op has a mask operand.
Definition at line 5902 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVISD::FIRST_NUMBER, llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE, llvm::RISCVISD::FIRST_VL_VECTOR_OP, llvm::RISCVISD::LAST_RISCV_STRICTFP_OPCODE, llvm::RISCVISD::LAST_VL_VECTOR_OP, llvm::RISCVISD::SETCC_VL, llvm::RISCVISD::STRICT_FADD_VL, llvm::RISCVISD::STRICT_VFROUND_NOEXCEPT_VL, llvm::RISCVISD::TRUNCATE_VECTOR_VL, llvm::RISCVISD::VFIRST_VL, and llvm::RISCVISD::VRGATHER_VX_VL.
Return true if a RISC-V target specified op has a merge operand.
Definition at line 5876 of file RISCVISelLowering.cpp.
References llvm::RISCVISD::ADD_VL, assert(), llvm::RISCVISD::FCOPYSIGN_VL, llvm::RISCVISD::FIRST_NUMBER, llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE, llvm::RISCVISD::FIRST_VL_VECTOR_OP, llvm::RISCVISD::LAST_RISCV_STRICTFP_OPCODE, llvm::RISCVISD::LAST_VL_VECTOR_OP, llvm::RISCVISD::SETCC_VL, llvm::RISCVISD::STRICT_FADD_VL, llvm::RISCVISD::STRICT_FDIV_VL, llvm::RISCVISD::VFMAX_VL, llvm::RISCVISD::VFWSUB_W_VL, llvm::RISCVISD::VMERGE_VL, and llvm::RISCVISD::VWMUL_VL.
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Definition at line 4213 of file RISCVISelLowering.cpp.
References llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getConstantOperandVal(), llvm::RISCVSubtarget::getELen(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), and llvm::MVT::getScalarSizeInBits().
Referenced by lowerVECTOR_SHUFFLE().
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Match shuffles that concatenate two vectors, rotate the concatenation, and then extract the original number of elements from the rotated result.
This is equivalent to vector.splice or X86's PALIGNR instruction. The returned rotation amount is for a rotate right, where elements move from higher elements to lower elements. LoSrc
indicates the first source vector of the rotate or -1 for undef. HiSrc
indicates the second vector of the rotate or -1 for undef. At least one of LoSrc
and HiSrc
will be 0 or 1 if a rotation is found.
NOTE: We talk about rotate to the right which matches how bit shift and rotate instructions are described where LSBs are on the right, but LLVM IR and the table below write vectors with the lowest elements on the left.
Definition at line 4302 of file RISCVISelLowering.cpp.
References assert(), and Size.
Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal(), and lowerVECTOR_SHUFFLE().
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Is this shuffle interleaving contiguous elements from one vector into the even elements and contiguous elements from another vector into the odd elements.
EvenSrc
will contain the element that should be in the first even element. OddSrc
will contain the element that should be in the first odd element. These can be the first element in a source or the element half way through the source.
Definition at line 4258 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::ShuffleVectorInst::isInterleaveMask(), and Size.
Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal(), and lowerVECTOR_SHUFFLE().
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Definition at line 4754 of file RISCVISelLowering.cpp.
References DL, llvm::MVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::EVT::getScalarSizeInBits(), llvm::RISCVSubtarget::getTargetLowering(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ShuffleVectorInst::isBitRotateMask(), and llvm::TargetLoweringBase::isTypeLegal().
Referenced by lowerShuffleViaVRegSplitting(), and lowerVECTOR_SHUFFLEAsRotate().
Definition at line 9533 of file RISCVISelLowering.cpp.
Referenced by combineBinOpToReduce(), and lowerReductionSeq().
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Definition at line 17525 of file RISCVISelLowering.cpp.
References MI.
Referenced by emitSelectPseudo().
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Definition at line 3280 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, llvm::enumerate(), getExactInteger(), llvm::DWARFExpression::Operation::getNumOperands(), Idx, isConstant(), and llvm::SignExtend64().
Referenced by lowerBuildVectorOfConstants(), and llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 15789 of file RISCVISelLowering.cpp.
References llvm::EVT::bitsLT(), llvm::EVT::changeVectorElementType(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getSubtarget(), llvm::EVT::getVectorElementType(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::UNSIGNED_SCALED.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 17817 of file RISCVISelLowering.cpp.
References assert().
Referenced by emitVFROUND_NOEXCEPT_MASK().
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Definition at line 5444 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::ISD::MEMBARRIER, llvm::SequentiallyConsistent, llvm::SyncScope::SingleThread, and llvm::SyncScope::System.
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Definition at line 4702 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BITREVERSE, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getSimpleValueType(), llvm::RISCVSubtarget::getTargetLowering(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ISD::INSERT_SUBVECTOR, llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::ShuffleVectorInst::isReverseMask(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::PowerOf2Ceil(), llvm::ArrayRef< T >::size(), and llvm::ISD::SRL.
Referenced by lowerVECTOR_SHUFFLE().
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Definition at line 3831 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLE(), llvm::ISD::BUILD_VECTOR, llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), llvm::count_if(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getFixedSizeInBits(), llvm::RISCVSubtarget::getFLen(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::RISCVTargetLowering::getLMUL(), getLMUL1VT(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealVLen(), llvm::SelectionDAG::getSetCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplatBuildVector(), llvm::getSplatValue(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MVT::getVectorMinNumElements(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), getVSlidedown(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::isBuildVectorOfConstantFPSDNodes(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::RISCVII::LMUL_2, llvm::RISCVII::LMUL_4, llvm::RISCVII::LMUL_8, lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), llvm::RISCVII::MASK_AGNOSTIC, matchSplatAsGather(), llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::reserve(), llvm::ISD::SETNE, llvm::SmallVectorBase< Size_T >::size(), llvm::ArrayRef< T >::slice(), llvm::Splat, llvm::RISCVII::TAIL_AGNOSTIC, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VFSLIDE1DOWN_VL, llvm::RISCVISD::VMV_V_X_VL, llvm::ISD::VSELECT, and llvm::RISCVISD::VSLIDE1DOWN_VL.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 3530 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLE(), llvm::MVT::changeVectorElementType(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::SelectionDAG::ComputeNumSignBits(), convertFromScalableVector(), convertToScalableVector(), llvm::divideCeil(), DL, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getSizeInBits(), llvm::getSplatValue(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::ISD::INSERT_VECTOR_ELT, INT64_MIN, llvm::RISCVSubtarget::is64Bit(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), llvm::isPowerOf2_32(), llvm::isPowerOf2_64(), isSimpleVIDSequence(), llvm::Log2_64(), lowerBuildVectorViaDominantValues(), llvm::ISD::MUL, llvm::ISD::SHL, llvm::SelectionDAG::shouldOptForSize(), llvm::ISD::SINT_TO_FP, llvm::Splat, llvm::ISD::SRL, llvm::ISD::SUB, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VID_VL, llvm::RISCVISD::VMCLR_VL, llvm::RISCVISD::VMSET_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::RISCVISD::VSEXT_VL.
Referenced by lowerBUILD_VECTOR().
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Try and optimize BUILD_VECTORs with "dominant values" - these are values which constitute a large proportion of the elements.
In such cases we can splat a vector with the dominant element and make up the shortfall with INSERT_VECTOR_ELTs. Returns SDValue if not profitable. Note that this includes vectors of 2 elements by association. The upper-most element is the "dominant" one, allowing us to use a splat to "insert" the upper element, and an insert of the lower element at position 0, which improves codegen.
Definition at line 3423 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), llvm::count_if(), DL, llvm::enumerate(), llvm::SelectionDAG::getBuildVector(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::SelectionDAG::getSplatBuildVector(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::Log2_32(), llvm::SelectionDAG::shouldOptForSize(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::size(), llvm::transform(), llvm::RISCVISD::VFSLIDE1DOWN_VL, llvm::ISD::VSELECT, and llvm::RISCVISD::VSLIDE1DOWN_VL.
Referenced by lowerBUILD_VECTOR(), and lowerBuildVectorOfConstants().
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Definition at line 5404 of file RISCVISelLowering.cpp.
References assert(), llvm::SmallVectorBase< Size_T >::empty(), llvm::RISCVMatInt::generateInstSeq(), llvm::RISCVMatInt::generateTwoRegInstSeq(), llvm::RISCVSubtarget::getMaxBuildIntsCost(), llvm::SelectionDAG::shouldOptForSize(), llvm::SmallVectorBase< Size_T >::size(), and llvm::RISCVSubtarget::useConstantPoolForLargeInts().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 8730 of file RISCVISelLowering.cpp.
References convertToScalableVector(), DL, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getElementCount(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorElementCount(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::isOneConstant(), N, llvm::ISD::SETLT, and llvm::RISCVISD::VFIRST_VL.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
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Definition at line 5647 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), convertToScalableVector(), DL, llvm::RISCVISD::FMAX, llvm::ISD::FMAXIMUM, llvm::RISCVISD::FMIN, getContainerForFixedLengthVector(), getDefaultVLOps(), getMaskTypeFor(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::MVT::isVector(), llvm::RISCVISD::SETCC_VL, llvm::ISD::SETOEQ, llvm::RISCVISD::VFMAX_VL, llvm::RISCVISD::VFMIN_VL, llvm::RISCVISD::VMERGE_VL, X, and Y.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 2815 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::RISCVISD::FCVT_W_RV64, llvm::RISCVISD::FCVT_WU_RV64, llvm::RISCVISD::FCVT_X, llvm::RISCVISD::FCVT_XU, llvm::ISD::FP_EXTEND, llvm::RISCVISD::FP_EXTEND_VL, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::RISCVSubtarget::hasStdExtZfhOrZhinx(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), llvm::RISCVFPRndMode::RTZ, llvm::RISCVISD::SETCC_VL, llvm::ISD::SETUO, llvm::RISCVISD::VFCVT_RTZ_X_F_VL, llvm::RISCVISD::VFCVT_RTZ_XU_F_VL, llvm::RISCVISD::VMERGE_VL, and llvm::RISCVISD::VMV_V_X_VL.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 3160 of file RISCVISelLowering.cpp.
References llvm::APFloat::convertFromAPInt(), DL, llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::RISCVISD::FROUND, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isVector(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), and llvm::SelectionDAG::shouldOptForSize().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 8695 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::RISCVVType::encodeLMUL(), llvm::RISCVVType::encodeSEW(), llvm::RISCVSubtarget::getELen(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isPowerOf2_32(), N, llvm::RISCV::RVVBitsPerBlock, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
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Helper to lower a reduction sequence of the form: scalar = reduce_op vec, scalar_start.
Definition at line 9542 of file RISCVISelLowering.cpp.
References llvm::MVT::bitsLE(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), getLMUL1VT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INSERT_SUBVECTOR, isNonZeroAVL(), lowerScalarInsert(), Reduction, and llvm::RISCVII::TAIL_AGNOSTIC.
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Definition at line 5509 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, assert(), DL, llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getValueType(), LHS, RHS, RV64LegalI32, llvm::ISD::SADDO, llvm::ISD::SETNE, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SUB, and llvm::ISD::TRUNCATE.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 5473 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignedMinValue(), LHS, RHS, RV64LegalI32, llvm::ISD::SADDSAT, llvm::APInt::sext(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SUB, and llvm::ISD::TRUNCATE.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 4153 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLE(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INSERT_SUBVECTOR, llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::isNullConstant(), llvm::MVT::isScalableVector(), lowerScalarSplat(), llvm::ISD::SIGN_EXTEND, llvm::RISCVISD::VFMV_S_F_VL, and llvm::RISCVISD::VMV_S_X_VL.
Referenced by combineBinOpToReduce(), and lowerReductionSeq().
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Definition at line 4115 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFloatingPoint(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::SDValue::isUndef(), llvm::ISD::SIGN_EXTEND, splatSplitI64WithVL(), llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_S_X_VL, and llvm::RISCVISD::VMV_V_X_VL.
Referenced by lowerScalarInsert().
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Definition at line 4805 of file RISCVISelLowering.cpp.
References assert(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_SUBVECTOR, getContainerForFixedLengthVector(), llvm::MVT::getFixedSizeInBits(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getLMUL1VT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::RISCVSubtarget::getRealVLen(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MVT::getVectorMinNumElements(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), llvm::ISD::INSERT_SUBVECTOR, and isLegalBitRotate().
Referenced by lowerVECTOR_SHUFFLE().
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Definition at line 5530 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getValueType(), LHS, llvm::Mul, llvm::ISD::MUL, RHS, RV64LegalI32, llvm::ISD::SETNE, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::TRUNCATE.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 5494 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getNode(), LHS, RHS, RV64LegalI32, llvm::ISD::SIGN_EXTEND, and llvm::ISD::TRUNCATE.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 4887 of file RISCVISelLowering.cpp.
References llvm::all_of(), llvm::any_of(), assert(), llvm::MVT::bitsGT(), llvm::MVT::changeTypeToInteger(), llvm::MVT::changeVectorElementType(), llvm::ISD::CONCAT_VECTORS, convertFromScalableVector(), convertToScalableVector(), DL, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), getDeinterleaveViaVNSRL(), llvm::SelectionDAG::getExtLoad(), llvm::TypeSize::getFixed(), llvm::SDNode::getFlags(), llvm::MVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::SelectionDAG::getRegister(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getScalarType(), llvm::SelectionDAG::getSetCC(), llvm::MVT::getSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::MVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), getVSlidedown(), getVSlideup(), llvm::SelectionDAG::getVTList(), getWideningInterleave(), llvm::RISCVSubtarget::getXLenVT(), Idx, llvm::ISD::INTRINSIC_W_CHAIN, isDeinterleaveShuffle(), isElementRotate(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), isInterleaveShuffle(), llvm::ISD::isNormalLoad(), IsSelect(), llvm::ShuffleVectorSDNode::isSplat(), llvm::SelectionDAG::isSplatValue(), llvm::SDValue::isUndef(), lowerBitreverseShuffle(), lowerShuffleViaVRegSplitting(), lowerVECTOR_SHUFFLEAsRotate(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SETNE, llvm::ISD::SEXTLOAD, llvm::SmallVectorBase< Size_T >::size(), Size, llvm::Splat, std::swap(), llvm::RISCVII::TAIL_AGNOSTIC, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_V_X_VL, llvm::RISCVISD::VRGATHER_VV_VL, llvm::RISCVISD::VRGATHER_VX_VL, llvm::RISCVISD::VRGATHEREI16_VV_VL, llvm::ISD::VSELECT, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().
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Definition at line 4777 of file RISCVISelLowering.cpp.
References llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::getScalarType(), llvm::SDNode::getValueType(), isLegalBitRotate(), and llvm::ISD::ROTL.
Referenced by lowerVECTOR_SHUFFLE().
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Match v(f)slide1up/down idioms.
These operations involve sliding N-1 elements to make room for an inserted scalar at one end.
Definition at line 4548 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::sampleprof::Base, convertFromScalableVector(), convertToScalableVector(), DL, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFloatingPoint(), llvm::Offset, llvm::Splat, std::swap(), llvm::RISCVISD::VFSLIDE1DOWN_VL, llvm::RISCVISD::VFSLIDE1UP_VL, llvm::RISCVISD::VSLIDE1DOWN_VL, and llvm::RISCVISD::VSLIDE1UP_VL.
Referenced by lowerVECTOR_SHUFFLE().
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Definition at line 4427 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), getVSlidedown(), llvm::RISCVSubtarget::getXLenVT(), llvm::Offset, and llvm::SmallVectorBase< Size_T >::size().
Referenced by lowerVECTOR_SHUFFLE().
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Definition at line 4504 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorNumElements(), getVSlideup(), llvm::RISCVSubtarget::getXLenVT(), llvm::ShuffleVectorInst::isInsertSubvectorMask(), llvm::RISCVII::MASK_AGNOSTIC, llvm::RISCVII::TAIL_AGNOSTIC, llvm::RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED, and llvm::RISCVISD::VMV_V_V_VL.
Referenced by lowerVECTOR_SHUFFLE().
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Definition at line 2950 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::APFloat::convertFromAPInt(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::RISCVISD::FABS_VL, llvm::ISD::FCEIL, llvm::RISCVISD::FCOPYSIGN_VL, llvm::ISD::FFLOOR, llvm::ISD::FNEARBYINT, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FTRUNC, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstantFP(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getFreeze(), getMaskTypeFor(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVFPRndMode::Invalid, llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), llvm_unreachable, matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), llvm::RISCVISD::SETCC_VL, llvm::ISD::SETOLT, llvm::RISCVISD::SINT_TO_FP_VL, llvm::RISCVISD::VFCVT_RM_X_F_VL, llvm::RISCVISD::VFCVT_RTZ_X_F_VL, llvm::RISCVISD::VFCVT_X_F_VL, llvm::RISCVISD::VFMV_V_F_VL, and llvm::RISCVISD::VFROUND_NOEXCEPT_VL.
Referenced by lowerFTRUNC_FCEIL_FFLOOR_FROUND(), and llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 8507 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLT(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::RISCVTargetLowering::computeVLMAXBounds(), DL, llvm::RISCVVType::encodeSEW(), getAllOnesMask(), llvm::SDNode::getAsZExtVal(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), getVLOperand(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::hasScalarOperand(), llvm::RISCVSubtarget::hasVInstructions(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::MVT::isScalarInteger(), llvm::SDValue::isUndef(), Operands, llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::ScalarOperand, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, splatSplitI64WithVL(), llvm::SelectionDAG::SplitScalar(), llvm::RISCVII::TAIL_AGNOSTIC, llvm::ISD::TRUNCATE, llvm::RISCVISD::VMERGE_VL, llvm::RISCVISD::VSLIDE1DOWN_VL, and llvm::RISCVISD::VSLIDE1UP_VL.
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Definition at line 3059 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::APFloat::convertFromAPInt(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::RISCVISD::FABS_VL, llvm::RISCVISD::FCOPYSIGN_VL, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstantFP(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVFPRndMode::Invalid, llvm::MVT::isFixedLengthVector(), llvm_unreachable, matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), llvm::RISCVISD::SETCC_VL, llvm::ISD::SETOLT, llvm::RISCVISD::STRICT_FADD_VL, llvm::ISD::STRICT_FCEIL, llvm::ISD::STRICT_FFLOOR, llvm::ISD::STRICT_FNEARBYINT, llvm::ISD::STRICT_FROUND, llvm::ISD::STRICT_FROUNDEVEN, llvm::RISCVISD::STRICT_FSETCC_VL, llvm::ISD::STRICT_FTRUNC, llvm::RISCVISD::STRICT_SINT_TO_FP_VL, llvm::RISCVISD::STRICT_VFCVT_RM_X_F_VL, llvm::RISCVISD::STRICT_VFCVT_RTZ_X_F_VL, llvm::RISCVISD::STRICT_VFROUND_NOEXCEPT_VL, and llvm::RISCVISD::VFMV_V_F_VL.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 3188 of file RISCVISelLowering.cpp.
References assert(), convertFromScalableVector(), convertToScalableVector(), DL, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), and llvm::RISCVISD::VFCVT_X_F_VL.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Match the index vector of a scatter or gather node as the shuffle mask which performs the rearrangement if possible.
Will only match if all lanes are touched, and thus replacing the scatter or gather with a unit strided access and shuffle is legal.
Definition at line 15822 of file RISCVISelLowering.cpp.
References llvm::BitVector::all(), assert(), llvm::CallingConv::C, llvm::SmallVectorBase< Size_T >::empty(), llvm::EVT::getScalarStoreSize(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVectorAllOnes(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::BitVector::set().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Match the index of a gather or scatter operation as an operation with twice the element width and half the number of elements.
This is generally profitable (if legal) because these operations are linear in VL, so even if we cause some extract VTYPE/VL toggles, we still come out ahead.
Definition at line 15857 of file RISCVISelLowering.cpp.
References llvm::CallingConv::C, llvm::EVT::getScalarStoreSize(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVectorAllOnes(), and llvm::Last.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 2916 of file RISCVISelLowering.cpp.
References llvm::RISCVFPRndMode::DYN, llvm::ISD::FCEIL, llvm::ISD::FFLOOR, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FTRUNC, llvm::RISCVFPRndMode::Invalid, llvm::RISCVFPRndMode::RDN, llvm::RISCVFPRndMode::RMM, llvm::RISCVFPRndMode::RNE, llvm::RISCVFPRndMode::RTZ, llvm::RISCVFPRndMode::RUP, llvm::ISD::STRICT_FCEIL, llvm::ISD::STRICT_FFLOOR, llvm::ISD::STRICT_FROUND, llvm::ISD::STRICT_FROUNDEVEN, and llvm::ISD::STRICT_FTRUNC.
Referenced by lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), performFP_TO_INT_SATCombine(), and performFP_TO_INTCombine().
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Definition at line 7287 of file RISCVISelLowering.cpp.
References assert(), CC, llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::ISD::getSetCCSwappedOperands(), llvm::SDValue::getValueType(), LHS, RHS, and llvm::ISD::SETCC.
Referenced by combineSelectToBinOp().
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Definition at line 3381 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), Idx, llvm::MVT::isFixedLengthVector(), and llvm::RISCVISD::VRGATHER_VX_VL.
Referenced by lowerBUILD_VECTOR(), and llvm::RISCVTargetLowering::PerformDAGCombine().
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According to the property that indexed load/store instructions zero-extend their indices, try to narrow the type of index operand.
Definition at line 13564 of file RISCVISelLowering.cpp.
References llvm::EVT::bitsLT(), llvm::CallingConv::C, llvm::EVT::changeVectorElementType(), llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::countMaxActiveBits(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getRoundIntegerType(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::APInt::getZExtValue(), llvm::SDNode::hasOneUse(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVector(), N, llvm::SDNode::ops(), llvm::PowerOf2Ceil(), llvm::ISD::SHL, llvm::ISD::TRUNCATE, llvm::RISCVISD::VZEXT_VL, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
Definition at line 14893 of file RISCVISelLowering.cpp.
References llvm_unreachable, llvm::RISCVISD::STRICT_VFMADD_VL, llvm::RISCVISD::STRICT_VFMSUB_VL, llvm::RISCVISD::STRICT_VFNMADD_VL, llvm::RISCVISD::STRICT_VFNMSUB_VL, llvm::RISCVISD::VFMADD_VL, llvm::RISCVISD::VFMSUB_VL, llvm::RISCVISD::VFNMADD_VL, and llvm::RISCVISD::VFNMSUB_VL.
Referenced by combineFMA(), combineFMADDSUB(), combineVFMADD_VLWithVFNEG_VL(), and llvm::X86TargetLowering::getNegatedExpression().
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Definition at line 13062 of file RISCVISelLowering.cpp.
References combineAddOfBooleanXor(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBinOpToReduce(), combineSelectAndUseCommutative(), N, transformAddImmMulImm(), and transformAddShlImm().
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Definition at line 13224 of file RISCVISelLowering.cpp.
References llvm::And, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineDeMorganOfBoolean(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::isOneConstant(), N, RV64LegalI32, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
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Definition at line 14873 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVISD::BREV8, llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::EVT::isScalarInteger(), and N.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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If we have a build_vector where each lane is binop X, C, where C is a constant (but not necessarily the same constant on all lanes), form binop (build_vector x1, x2, ...), (build_vector c1, c2, c3, ..).
We assume that materializing a constant build vector will be no more expensive that performing O(n) binops.
Definition at line 15457 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::TargetLoweringBase::isBinOp(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::SelectionDAG::isSafeToSpeculativelyExecute(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), N, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 15587 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::MVT::changeVectorElementType(), DL, llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::LoadSDNode::getBasePtr(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNegative(), llvm::getOffset(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::RISCVTargetLowering::isLegalStridedLoadStore(), llvm::ISD::isNormalLoad(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::BaseIndexOffset::match(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::MemoryLocation::UnknownSize.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 14810 of file RISCVISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::RISCVISD::FCVT_W_RV64, llvm::RISCVISD::FCVT_WU_RV64, llvm::RISCVISD::FCVT_X, llvm::RISCVISD::FCVT_XU, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::RISCVFPRndMode::Invalid, llvm::TargetLoweringBase::isTypeLegal(), matchRoundingOp(), N, and llvm::ISD::SETUO.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 14707 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), convertToScalableVector(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::RISCVFPRndMode::DYN, llvm::RISCVISD::FCVT_W_RV64, llvm::RISCVISD::FCVT_WU_RV64, llvm::RISCVISD::FCVT_X, llvm::RISCVISD::FCVT_XU, llvm::ISD::FP_TO_SINT, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVFPRndMode::Invalid, llvm::EVT::isFixedLengthVector(), llvm::MVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), matchRoundingOp(), N, llvm::RISCVFPRndMode::RTZ, llvm::ISD::TRUNCATE, llvm::RISCVISD::VFCVT_RM_X_F_VL, llvm::RISCVISD::VFCVT_RM_XU_F_VL, llvm::RISCVISD::VFCVT_RTZ_X_F_VL, llvm::RISCVISD::VFCVT_RTZ_XU_F_VL, llvm::RISCVISD::VFCVT_X_F_VL, and llvm::RISCVISD::VFCVT_XU_F_VL.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 15515 of file RISCVISelLowering.cpp.
References llvm::SmallVectorImpl< T >::append(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_VECTOR_ELT, llvm::TargetLoweringBase::isBinOp(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::EVT::isScalableVector(), LHS, N, llvm::SDNode::op_begin(), llvm::SDNode::op_end(), and RHS.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 14620 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::DAG, getExtensionType(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemoryVT(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MachineFunction::getSubtarget(), llvm::Use::getUser(), llvm::LSBaseSDNode::isIndexed(), llvm::MemSDNode::isSimple(), llvm::ISD::LOAD, N, Ptr, tryMemPairCombine(), llvm::SDNode::use_begin(), and llvm::SDNode::use_end().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 13516 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, combineBinOpOfZExt(), DL, expandMul(), llvm::SelectionDAG::getNode(), llvm::isOneOrOneSplat(), llvm::EVT::isVector(), llvm::ISD::MUL, N, llvm::ISD::SUB, and std::swap().
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Definition at line 13298 of file RISCVISelLowering.cpp.
References combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineDeMorganOfBoolean(), combineOrOfCZERO(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), and N.
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Definition at line 15434 of file RISCVISelLowering.cpp.
References foldSelectOfCTTZOrCTLZ(), llvm::RISCVSubtarget::hasConditionalMoveFusion(), N, tryFoldSelectIntoOp(), and useInversedSetcc().
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Definition at line 13633 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, Cond, llvm::APInt::getActiveBits(), llvm::SelectionDAG::getBoolConstant(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::ISD::SETNE, llvm::APInt::sext(), llvm::ISD::SIGN_EXTEND_INREG, and llvm::APInt::trunc().
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Definition at line 13680 of file RISCVISelLowering.cpp.
References llvm::RISCVISD::FMV_X_ANYEXTH, llvm::RISCVISD::FMV_X_SIGNEXTH, llvm::SelectionDAG::getNode(), and N.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 15030 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::APInt::countr_zero(), DL, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getValueType(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), llvm::APInt::lshr(), N, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SUB, and llvm::SDNode::uses().
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Definition at line 13123 of file RISCVISelLowering.cpp.
References combineBinOpOfZExt(), combineSelectAndUse(), combineSubOfBoolean(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::hasOneUse(), llvm::isNullConstant(), N, llvm::ISD::SETCC, llvm::ISD::SETLT, and llvm::ISD::SRA.
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Definition at line 13198 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), N, RV64LegalI32, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 14968 of file RISCVISelLowering.cpp.
References combineVFMADD_VLWithVFNEG_VL(), llvm::RISCVISD::FP_EXTEND_VL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::hasNUsesOfValue(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::hasVInstructionsF16(), llvm::RISCVSubtarget::hasVInstructionsF16Minimal(), llvm_unreachable, N, llvm::RISCVISD::VFMADD_VL, llvm::RISCVISD::VFMSUB_VL, llvm::RISCVISD::VFNMADD_VL, llvm::RISCVISD::VFNMSUB_VL, llvm::RISCVISD::VFWMADD_VL, llvm::RISCVISD::VFWMSUB_VL, llvm::RISCVISD::VFWNMADD_VL, and llvm::RISCVISD::VFWNMSUB_VL.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 14546 of file RISCVISelLowering.cpp.
References assert(), combineBinOp_VLToVWBinOp_VL(), combineVWADDSUBWSelect(), llvm::TargetLowering::DAGCombinerInfo::DAG, N, llvm::RISCVISD::VWADD_W_VL, llvm::RISCVISD::VWADDU_W_VL, llvm::RISCVISD::VWSUB_W_VL, and llvm::RISCVISD::VWSUBU_W_VL.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 13325 of file RISCVISelLowering.cpp.
References llvm::And, llvm::ISD::ANY_EXTEND, CC, combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineSelectAndUseCommutative(), DL, llvm::get(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::TargetLoweringBase::isOperationLegal(), LHS, N, RHS, llvm::RISCVISD::ROLW, llvm::ISD::ROTL, RV64LegalI32, llvm::ISD::SETCC, llvm::ISD::SETLT, llvm::ISD::SHL, llvm::RISCVISD::SLLW, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
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Definition at line 18510 of file RISCVISelLowering.cpp.
References llvm::enumerate(), llvm::MVT::getVectorElementType(), and llvm::MVT::isVector().
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Definition at line 8791 of file RISCVISelLowering.cpp.
References convertToScalableVector(), llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getSubtarget(), llvm::MVT::getVectorVT(), Operands, and promoteVCIXScalar().
Referenced by getVCIXISDNodeVOID(), and getVCIXISDNodeWCHAIN().
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Definition at line 8753 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLT(), DL, llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::SDValue::getSimpleValueType(), llvm::MachineFunction::getSubtarget(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::hasScalarOperand(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::MVT::isScalarInteger(), Operands, llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::ScalarOperand, and llvm::ISD::SIGN_EXTEND.
Referenced by processVCIXOperands().
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Definition at line 4047 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BITCAST, DL, llvm::SDNode::getAsZExtVal(), llvm::SelectionDAG::getNode(), getReg(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::Hi, llvm::isAllOnesConstant(), llvm::Lo, llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, llvm::ISD::SRA, and llvm::RISCVISD::VMV_V_X_VL.
Referenced by splatSplitI64WithVL().
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Definition at line 4103 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::Hi, llvm::Lo, splatPartsI64WithVL(), and llvm::SelectionDAG::SplitScalar().
Referenced by lowerScalarSplat(), and lowerVectorIntrinsicScalars().
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Definition at line 5993 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), and llvm::SelectionDAG::SplitVector().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 5922 of file RISCVISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::SelectionDAG::GetSplitDestVTs(), and llvm::SelectionDAG::SplitVector().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 5978 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::Hi, llvm::Lo, llvm::SelectionDAG::SplitEVL(), and llvm::SelectionDAG::SplitVector().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 5947 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::ISD::getVPExplicitVectorLengthIdx(), llvm::ISD::isVPOpcode(), llvm::SelectionDAG::SplitEVL(), and llvm::SelectionDAG::SplitVector().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
STATISTIC | ( | NumTailCalls | , |
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Definition at line 12936 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::EVT::isVector(), llvm::ISD::MUL, and N.
Referenced by performADDCombine().
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Definition at line 12785 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::EVT::isVector(), N, NL, and llvm::ISD::SHL.
Referenced by performADDCombine().
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Definition at line 2302 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::bit_width(), llvm::CallingConv::C, CC, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::getSetCCSwappedOperands(), llvm::Value::hasOneUse(), llvm::isMask_64(), llvm::isNullConstant(), llvm::isPowerOf2_64(), LHS, llvm::Log2_64(), RHS, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SHL, and std::swap().
Referenced by combine_CC().
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Definition at line 15142 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, Cond, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::EVT::isScalarInteger(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETLT, std::swap(), llvm::Xor, and llvm::ISD::XOR.
Referenced by combine_CC().
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Definition at line 15294 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNeutralElement(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SDNode::getValueType(), N, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, std::swap(), and llvm::ISD::XOR.
Referenced by performSELECTCombine().
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Definition at line 14562 of file RISCVISelLowering.cpp.
References llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MachineMemOperand::getPointerInfo(), llvm::MachineFunction::getSubtarget(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDNode::hasPredecessorHelper(), llvm::ISD::LOAD, llvm::SelectionDAG::ReplaceAllUsesWith(), llvm::RISCVISD::TH_LDD, llvm::RISCVISD::TH_LWD, llvm::RISCVISD::TH_LWUD, llvm::RISCVISD::TH_SDD, llvm::RISCVISD::TH_SWD, and llvm::ISD::ZEXTLOAD.
Referenced by performMemPairCombine().
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Definition at line 18720 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVISD::BuildPairF64, llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::SelectionDAG::getCopyFromReg(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getRegInfo(), llvm::CCValAssign::getValVT(), llvm::Hi, llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), and llvm::Lo.
Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().
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Definition at line 18686 of file RISCVISelLowering.cpp.
References llvm::CCValAssign::BCvt, llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::CCValAssign::Full, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MVT::getIntegerVT(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::DataLayout::getPointerSizeInBits(), llvm::EVT::getStoreSize(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, llvm::EVT::isScalableVector(), llvm_unreachable, and llvm::ISD::NON_EXTLOAD.
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Definition at line 18620 of file RISCVISelLowering.cpp.
References llvm::RISCVMachineFunctionInfo::addSExt32Register(), llvm::BitWidth, convertLocVTToValVT(), DL, llvm::Function::getArg(), llvm::SelectionDAG::getCopyFromReg(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::Type::getIntegerBitWidth(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MachineFunction::getRegInfo(), llvm::EVT::getSimpleVT(), llvm::RISCVTargetLowering::getSubtarget(), llvm::Value::getType(), llvm::CCValAssign::Indirect, and llvm::Type::isIntegerTy().
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Definition at line 15403 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, CC, Cond, DL, llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::isNullConstant(), llvm::APInt::isPowerOf2(), llvm::EVT::isScalarInteger(), llvm::APInt::isSignedIntN(), LHS, N, RHS, llvm::ISD::SETCC, llvm::ISD::SETEQ, and llvm::ISD::SETNE.
Referenced by performSELECTCombine().
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Definition at line 2521 of file RISCVISelLowering.cpp.
References assert(), llvm::divideCeil(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getFixedSizeInBits(), llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::hasVInstructionsF16Minimal(), llvm::RISCVSubtarget::hasVInstructionsF32(), llvm::RISCVSubtarget::hasVInstructionsF64(), llvm::RISCVSubtarget::hasVInstructionsI64(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isPow2VectorType(), llvm::MVT::SimpleTy, and llvm::RISCVSubtarget::useRVVForFixedLengthVectors().
Referenced by getContainerForFixedLengthVector().
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Definition at line 20845 of file RISCVISelLowering.cpp.
References llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateConstGEP1_32(), llvm::Intrinsic::getDeclaration(), llvm::IRBuilderBase::GetInsertBlock(), llvm::IRBuilderBase::getInt8Ty(), llvm::GlobalValue::getParent(), llvm::BasicBlock::getParent(), and llvm::Offset.
Referenced by llvm::RISCVTargetLowering::getIRStackGuard().
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Definition at line 10085 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementType(), DL, llvm::SmallVectorTemplateCommon< T, typename >::front(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), I, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SETNE, llvm::SmallVectorBase< Size_T >::size(), and llvm::ISD::ZERO_EXTEND.
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Definition at line 18161 of file RISCVISelLowering.cpp.
Referenced by llvm::RISCV::CC_RISCV().
Definition at line 18165 of file RISCVISelLowering.cpp.
Definition at line 18169 of file RISCVISelLowering.cpp.
Definition at line 18178 of file RISCVISelLowering.cpp.
Definition at line 18181 of file RISCVISelLowering.cpp.
Definition at line 18183 of file RISCVISelLowering.cpp.
Definition at line 18174 of file RISCVISelLowering.cpp.
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Referenced by combineBinOp_VLToVWBinOp_VL().
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Definition at line 20915 of file RISCVISelLowering.cpp.
Referenced by llvm::RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(), and llvm::RISCVTargetLowering::lowerInterleavedLoad().
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Definition at line 20963 of file RISCVISelLowering.cpp.
Referenced by llvm::RISCVTargetLowering::lowerInterleavedStore(), and llvm::RISCVTargetLowering::lowerInterleaveIntrinsicToStore().
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Referenced by llvm::RISCVTargetLowering::isFPImmLegal().
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Referenced by convertLocVTToValVT(), convertValVTToLocVT(), llvm::RISCVTargetLowering::getRegisterTypeForCallingConv(), llvm::RISCVTargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::RISCVTargetLowering::LowerOperation(), lowerSADDO_SSUBO(), lowerSADDSAT_SSUBSAT(), lowerSMULO(), lowerUADDSAT_USUBSAT(), performANDCombine(), performTRUNCATECombine(), performXORCombine(), and llvm::RISCVTargetLowering::RISCVTargetLowering().