LLVM  16.0.0git
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RISCVISelLowering.cpp File Reference
#include "RISCVISelLowering.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVRegisterInfo.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/DiagnosticPrinter.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <optional>
#include "RISCVGenAsmMatcher.inc"
#include "RISCVGenSearchableTables.inc"
Include dependency graph for RISCVISelLowering.cpp:

Go to the source code of this file.

Classes

struct  VIDSequence
 

Namespaces

 llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
 llvm::RISCVVIntrinsicsTable
 

Macros

#define DEBUG_TYPE   "riscv-lower"
 
#define NODE_NAME_CASE(NODE)
 
#define GET_REGISTER_MATCHER
 
#define GET_RISCVVIntrinsicsTable_IMPL
 

Functions

 STATISTIC (NumTailCalls, "Number of tail calls")
 
static void translateSetCCForBranch (const SDLoc &DL, SDValue &LHS, SDValue &RHS, ISD::CondCode &CC, SelectionDAG &DAG)
 
static SDValue getVLOperand (SDValue Op)
 
static bool useRVVForFixedLengthVectorVT (MVT VT, const RISCVSubtarget &Subtarget)
 
static MVT getContainerForFixedLengthVector (const TargetLowering &TLI, MVT VT, const RISCVSubtarget &Subtarget)
 
static MVT getContainerForFixedLengthVector (SelectionDAG &DAG, MVT VT, const RISCVSubtarget &Subtarget)
 
static SDValue convertToScalableVector (EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue convertFromScalableVector (EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static MVT getMaskTypeFor (MVT VecVT)
 Return the type of the mask type suitable for masking the provided vector type. More...
 
static SDValue getAllOnesMask (MVT VecVT, SDValue VL, SDLoc DL, SelectionDAG &DAG)
 Creates an all ones mask suitable for masking a vector of type VecTy with vector length VL. More...
 
static SDValue getVLOp (uint64_t NumElts, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static std::pair< SDValue, SDValuegetDefaultVLOps (uint64_t NumElts, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static std::pair< SDValue, SDValuegetDefaultVLOps (MVT VecVT, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static std::pair< SDValue, SDValuegetDefaultScalableVLOps (MVT VecVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerFP_TO_INT_SAT (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static RISCVFPRndMode::RoundingMode matchRoundingOp (unsigned Opc)
 
static SDValue lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerFTRUNC_FCEIL_FFLOOR_FROUND (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static std::optional< uint64_tgetExactInteger (const APFloat &APF, uint32_t BitWidth)
 
static std::optional< VIDSequenceisSimpleVIDSequence (SDValue Op)
 
static SDValue matchSplatAsGather (SDValue SplatVal, MVT VT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerBUILD_VECTOR (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue splatPartsI64WithVL (const SDLoc &DL, MVT VT, SDValue Passthru, SDValue Lo, SDValue Hi, SDValue VL, SelectionDAG &DAG)
 
static SDValue splatSplitI64WithVL (const SDLoc &DL, MVT VT, SDValue Passthru, SDValue Scalar, SDValue VL, SelectionDAG &DAG)
 
static SDValue lowerScalarSplat (SDValue Passthru, SDValue Scalar, SDValue VL, MVT VT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static bool isInterleaveShuffle (ArrayRef< int > Mask, MVT VT, bool &SwapSources, const RISCVSubtarget &Subtarget)
 
static int isElementRotate (int &LoSrc, int &HiSrc, ArrayRef< int > Mask)
 Match shuffles that concatenate two vectors, rotate the concatenation, and then extract the original number of elements from the rotated result. More...
 
static SDValue lowerVECTOR_SHUFFLEAsVNSRL (const SDLoc &DL, MVT VT, MVT ContainerVT, SDValue V1, SDValue V2, SDValue TrueMask, SDValue VL, ArrayRef< int > Mask, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
 
static SDValue lowerVECTOR_SHUFFLEAsVSlidedown (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
 
static SDValue lowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerCTLZ_CTTZ_ZERO_UNDEF (SDValue Op, SelectionDAG &DAG)
 
static SDValue lowerConstant (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue getTargetNode (GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (BlockAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (ConstantPoolSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (JumpTableSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue lowerVectorIntrinsicScalars (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static MVT getLMUL1VT (MVT VT)
 
static unsigned getRVVReductionOp (unsigned ISDOpcode)
 
static std::tuple< unsigned, SDValue, SDValuegetRVVFPReductionOpAndOperands (SDValue Op, SelectionDAG &DAG, EVT EltVT)
 
static unsigned getRVVVPReductionOp (unsigned ISDOpcode)
 
static RISCVISD::NodeType getRISCVWOpcode (unsigned Opcode)
 
static SDValue customLegalizeToWOp (SDNode *N, SelectionDAG &DAG, unsigned ExtOpc=ISD::ANY_EXTEND)
 
static SDValue customLegalizeToWOpWithSExt (SDNode *N, SelectionDAG &DAG)
 
static SDValue combineBinOpToReduce (SDNode *N, SelectionDAG &DAG)
 
static SDValue transformAddShlImm (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue combineSelectAndUse (SDNode *N, SDValue Slct, SDValue OtherOp, SelectionDAG &DAG, bool AllOnes, const RISCVSubtarget &Subtarget)
 
static SDValue combineSelectAndUseCommutative (SDNode *N, SelectionDAG &DAG, bool AllOnes, const RISCVSubtarget &Subtarget)
 
static SDValue transformAddImmMulImm (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue performADDCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue combineSubOfBoolean (SDNode *N, SelectionDAG &DAG)
 
static SDValue performSUBCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue combineDeMorganOfBoolean (SDNode *N, SelectionDAG &DAG)
 
static SDValue performTRUNCATECombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue performANDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static SDValue performORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static SDValue performXORCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue performSETCCCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue performSIGN_EXTEND_INREGCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue combineBinOp_VLToVWBinOp_VL (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 Combine a binary operation to its equivalent VW or VW_W form. More...
 
static SDValue performFP_TO_INTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static SDValue performFP_TO_INT_SATCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static SDValue performBITREVERSECombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static unsigned negateFMAOpcode (unsigned Opcode, bool NegMul, bool NegAcc)
 
static SDValue performSRACombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue tryDemorganOfBooleanCondition (SDValue Cond, SelectionDAG &DAG)
 
static bool combine_CC (SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static uint64_t computeGREVOrGORC (uint64_t x, unsigned ShAmt, bool IsGORC)
 
static MachineBasicBlockemitReadCycleWidePseudo (MachineInstr &MI, MachineBasicBlock *BB)
 
static MachineBasicBlockemitSplitF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB)
 
static MachineBasicBlockemitBuildPairF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB)
 
static bool isSelectPseudo (MachineInstr &MI)
 
static MachineBasicBlockemitQuietFCMP (MachineInstr &MI, MachineBasicBlock *BB, unsigned RelOpcode, unsigned EqOpcode, const RISCVSubtarget &Subtarget)
 
static MachineBasicBlockEmitLoweredCascadedSelect (MachineInstr &First, MachineInstr &Second, MachineBasicBlock *ThisMBB, const RISCVSubtarget &Subtarget)
 
static MachineBasicBlockemitSelectPseudo (MachineInstr &MI, MachineBasicBlock *BB, const RISCVSubtarget &Subtarget)
 
static MachineBasicBlockemitVFCVT_RM_MASK (MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode)
 
static MachineBasicBlockemitVFROUND_NOEXCEPT_MASK (MachineInstr &MI, MachineBasicBlock *BB, unsigned CVTXOpc, unsigned CVTFOpc)
 
static MachineBasicBlockemitFROUND (MachineInstr &MI, MachineBasicBlock *MBB, const RISCVSubtarget &Subtarget)
 
static bool CC_RISCVAssign2XLen (unsigned XLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
 
static unsigned allocateRVVReg (MVT ValVT, unsigned ValNo, std::optional< unsigned > FirstMaskArgument, CCState &State, const RISCVTargetLowering &TLI)
 
static bool CC_RISCV (const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
 
template<typename ArgTy >
static std::optional< unsigned > preAssignMask (const ArgTy &Args)
 
static SDValue convertLocVTToValVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget)
 
static SDValue unpackFromRegLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const ISD::InputArg &In, const RISCVTargetLowering &TLI)
 
static SDValue convertValVTToLocVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget)
 
static SDValue unpackFromMemLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
 
static SDValue unpackF64OnRV32DSoftABI (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
 
static bool CC_RISCV_FastCC (const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
 
static bool CC_RISCV_GHC (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
 
static Align getPrefTypeAlign (EVT VT, SelectionDAG &DAG)
 
static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp (unsigned XLen, AtomicRMWInst::BinOp BinOp)
 

Variables

static cl::opt< unsigned > ExtensionMaxWebSize (DEBUG_TYPE "-ext-max-web-size", cl::Hidden, cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion"), cl::init(18))
 
static cl::opt< bool > AllowSplatInVW_W (DEBUG_TYPE "-form-vw-w-with-splat", cl::Hidden, cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants"), cl::init(false))
 
static const MCPhysReg ArgGPRs []
 
static const MCPhysReg ArgFPR16s []
 
static const MCPhysReg ArgFPR32s []
 
static const MCPhysReg ArgFPR64s []
 
static const MCPhysReg ArgVRs []
 
static const MCPhysReg ArgVRM2s []
 
static const MCPhysReg ArgVRM4s []
 
static const MCPhysReg ArgVRM8s [] = {RISCV::V8M8, RISCV::V16M8}
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "riscv-lower"

Definition at line 46 of file RISCVISelLowering.cpp.

◆ GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 13517 of file RISCVISelLowering.cpp.

◆ GET_RISCVVIntrinsicsTable_IMPL

#define GET_RISCVVIntrinsicsTable_IMPL

Definition at line 13538 of file RISCVISelLowering.cpp.

◆ NODE_NAME_CASE

#define NODE_NAME_CASE (   NODE)
Value:
return "RISCVISD::" #NODE;

Function Documentation

◆ allocateRVVReg()

static unsigned allocateRVVReg ( MVT  ValVT,
unsigned  ValNo,
std::optional< unsigned >  FirstMaskArgument,
CCState State,
const RISCVTargetLowering TLI 
)
static

◆ CC_RISCV()

static bool CC_RISCV ( const DataLayout DL,
RISCVABI::ABI  ABI,
unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState State,
bool  IsFixed,
bool  IsRet,
Type OrigTy,
const RISCVTargetLowering TLI,
std::optional< unsigned >  FirstMaskArgument 
)
static

Definition at line 11305 of file RISCVISelLowering.cpp.

References ABI, llvm::RISCVABI::ABI_ILP32, llvm::RISCVABI::ABI_ILP32D, llvm::RISCVABI::ABI_ILP32F, llvm::RISCVABI::ABI_LP64, llvm::RISCVABI::ABI_LP64D, llvm::RISCVABI::ABI_LP64F, llvm::CCState::addLoc(), Align, llvm::CCState::AllocateReg(), allocateRVVReg(), llvm::CCState::AllocateStack(), ArgFPR16s, ArgFPR32s, ArgFPR64s, ArgGPRs, assert(), llvm::CCValAssign::BCvt, CC_RISCVAssign2XLen(), llvm::SmallVectorImpl< T >::clear(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::CCValAssign::Full, llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), llvm::CCState::getFirstUnallocated(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getPending(), llvm::CCState::getPendingArgFlags(), llvm::CCState::getPendingLocs(), llvm::CCValAssign::getReg(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getStoreSize(), llvm::RISCVTargetLowering::getSubtarget(), llvm::RISCVSubtarget::hasVInstructions(), llvm::MVT::i32, llvm::MVT::i64, llvm::CCValAssign::Indirect, llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::ISD::ArgFlagsTy::isNest(), llvm::MVT::isScalableVector(), llvm::MVT::isScalarInteger(), llvm::ISD::ArgFlagsTy::isSplit(), llvm::ISD::ArgFlagsTy::isSplitEnd(), llvm::MVT::isVector(), llvm_unreachable, size, and llvm::MaybeAlign::valueOrOne().

Referenced by llvm::RISCVTargetLowering::CanLowerReturn(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerFormalArguments(), and llvm::RISCVTargetLowering::LowerReturn().

◆ CC_RISCV_FastCC()

static bool CC_RISCV_FastCC ( const DataLayout DL,
RISCVABI::ABI  ABI,
unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState State,
bool  IsFixed,
bool  IsRet,
Type OrigTy,
const RISCVTargetLowering TLI,
std::optional< unsigned >  FirstMaskArgument 
)
static

◆ CC_RISCV_GHC()

static bool CC_RISCV_GHC ( unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState State 
)
static

◆ CC_RISCVAssign2XLen()

static bool CC_RISCVAssign2XLen ( unsigned  XLen,
CCState State,
CCValAssign  VA1,
ISD::ArgFlagsTy  ArgFlags1,
unsigned  ValNo2,
MVT  ValVT2,
MVT  LocVT2,
ISD::ArgFlagsTy  ArgFlags2 
)
static

◆ combine_CC()

static bool combine_CC ( SDValue LHS,
SDValue RHS,
SDValue CC,
const SDLoc DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ combineBinOp_VLToVWBinOp_VL()

static SDValue combineBinOp_VLToVWBinOp_VL ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

Combine a binary operation to its equivalent VW or VW_W form.

The supported combines are: add_vl -> vwadd(u) | vwadd(u)_w sub_vl -> vwsub(u) | vwsub(u)_w mul_vl -> vwmul(u) | vwmul_su vwadd_w(u) -> vwadd(u) vwub_w(u) -> vwadd(u)

Definition at line 9034 of file RISCVISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SmallVectorImpl< T >::emplace_back(), ExtensionMaxWebSize, isCommutative(), LHS, N, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SmallVectorImpl< T >::reserve(), RHS, and std::swap().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ combineBinOpToReduce()

static SDValue combineBinOpToReduce ( SDNode N,
SelectionDAG DAG 
)
static

◆ combineDeMorganOfBoolean()

static SDValue combineDeMorganOfBoolean ( SDNode N,
SelectionDAG DAG 
)
static

◆ combineSelectAndUse()

static SDValue combineSelectAndUse ( SDNode N,
SDValue  Slct,
SDValue  OtherOp,
SelectionDAG DAG,
bool  AllOnes,
const RISCVSubtarget Subtarget 
)
static

◆ combineSelectAndUseCommutative()

static SDValue combineSelectAndUseCommutative ( SDNode N,
SelectionDAG DAG,
bool  AllOnes,
const RISCVSubtarget Subtarget 
)
static

◆ combineSubOfBoolean()

static SDValue combineSubOfBoolean ( SDNode N,
SelectionDAG DAG 
)
static

◆ computeGREVOrGORC()

static uint64_t computeGREVOrGORC ( uint64_t  x,
unsigned  ShAmt,
bool  IsGORC 
)
static

◆ convertFromScalableVector()

static SDValue convertFromScalableVector ( EVT  VT,
SDValue  V,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ convertLocVTToValVT()

static SDValue convertLocVTToValVT ( SelectionDAG DAG,
SDValue  Val,
const CCValAssign VA,
const SDLoc DL,
const RISCVSubtarget Subtarget 
)
static

◆ convertToScalableVector()

static SDValue convertToScalableVector ( EVT  VT,
SDValue  V,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ convertValVTToLocVT()

static SDValue convertValVTToLocVT ( SelectionDAG DAG,
SDValue  Val,
const CCValAssign VA,
const SDLoc DL,
const RISCVSubtarget Subtarget 
)
static

◆ customLegalizeToWOp()

static SDValue customLegalizeToWOp ( SDNode N,
SelectionDAG DAG,
unsigned  ExtOpc = ISD::ANY_EXTEND 
)
static

◆ customLegalizeToWOpWithSExt()

static SDValue customLegalizeToWOpWithSExt ( SDNode N,
SelectionDAG DAG 
)
static

◆ emitBuildPairF64Pseudo()

static MachineBasicBlock* emitBuildPairF64Pseudo ( MachineInstr MI,
MachineBasicBlock BB 
)
static

◆ emitFROUND()

static MachineBasicBlock* emitFROUND ( MachineInstr MI,
MachineBasicBlock MBB,
const RISCVSubtarget Subtarget 
)
static

◆ EmitLoweredCascadedSelect()

static MachineBasicBlock* EmitLoweredCascadedSelect ( MachineInstr First,
MachineInstr Second,
MachineBasicBlock ThisMBB,
const RISCVSubtarget Subtarget 
)
static

◆ emitQuietFCMP()

static MachineBasicBlock* emitQuietFCMP ( MachineInstr MI,
MachineBasicBlock BB,
unsigned  RelOpcode,
unsigned  EqOpcode,
const RISCVSubtarget Subtarget 
)
static

◆ emitReadCycleWidePseudo()

static MachineBasicBlock* emitReadCycleWidePseudo ( MachineInstr MI,
MachineBasicBlock BB 
)
static

◆ emitSelectPseudo()

static MachineBasicBlock* emitSelectPseudo ( MachineInstr MI,
MachineBasicBlock BB,
const RISCVSubtarget Subtarget 
)
static

◆ emitSplitF64Pseudo()

static MachineBasicBlock* emitSplitF64Pseudo ( MachineInstr MI,
MachineBasicBlock BB 
)
static

◆ emitVFCVT_RM_MASK()

static MachineBasicBlock* emitVFCVT_RM_MASK ( MachineInstr MI,
MachineBasicBlock BB,
unsigned  Opcode 
)
static

◆ emitVFROUND_NOEXCEPT_MASK()

static MachineBasicBlock* emitVFROUND_NOEXCEPT_MASK ( MachineInstr MI,
MachineBasicBlock BB,
unsigned  CVTXOpc,
unsigned  CVTFOpc 
)
static

◆ getAllOnesMask()

static SDValue getAllOnesMask ( MVT  VecVT,
SDValue  VL,
SDLoc  DL,
SelectionDAG DAG 
)
static

Creates an all ones mask suitable for masking a vector of type VecTy with vector length VL.

Definition at line 1892 of file RISCVISelLowering.cpp.

References DL, getMaskTypeFor(), llvm::SelectionDAG::getNode(), and llvm::RISCVISD::VMSET_VL.

Referenced by getDefaultVLOps(), lowerVECTOR_SHUFFLE(), and lowerVectorIntrinsicScalars().

◆ getContainerForFixedLengthVector() [1/2]

static MVT getContainerForFixedLengthVector ( const TargetLowering TLI,
MVT  VT,
const RISCVSubtarget Subtarget 
)
static

◆ getContainerForFixedLengthVector() [2/2]

static MVT getContainerForFixedLengthVector ( SelectionDAG DAG,
MVT  VT,
const RISCVSubtarget Subtarget 
)
static

◆ getDefaultScalableVLOps()

static std::pair<SDValue, SDValue> getDefaultScalableVLOps ( MVT  VecVT,
SDLoc  DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

Definition at line 1930 of file RISCVISelLowering.cpp.

References assert(), DL, getDefaultVLOps(), and llvm::MVT::isScalableVector().

◆ getDefaultVLOps() [1/2]

static std::pair<SDValue, SDValue> getDefaultVLOps ( MVT  VecVT,
MVT  ContainerVT,
SDLoc  DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ getDefaultVLOps() [2/2]

static std::pair<SDValue, SDValue> getDefaultVLOps ( uint64_t  NumElts,
MVT  ContainerVT,
SDLoc  DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ getExactInteger()

static std::optional<uint64_t> getExactInteger ( const APFloat APF,
uint32_t  BitWidth 
)
static

◆ getIntrinsicForMaskedAtomicRMWBinOp()

static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp ( unsigned  XLen,
AtomicRMWInst::BinOp  BinOp 
)
static

◆ getLMUL1VT()

static MVT getLMUL1VT ( MVT  VT)
static

◆ getMaskTypeFor()

static MVT getMaskTypeFor ( MVT  VecVT)
static

Return the type of the mask type suitable for masking the provided vector type.

This is simply an i1 element type vector of the same (possibly scalable) length.

Definition at line 1884 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::MVT::i1, and llvm::MVT::isVector().

Referenced by getAllOnesMask(), and llvm::RISCVTargetLowering::PerformDAGCombine().

◆ getPrefTypeAlign()

static Align getPrefTypeAlign ( EVT  VT,
SelectionDAG DAG 
)
static

◆ getRISCVWOpcode()

static RISCVISD::NodeType getRISCVWOpcode ( unsigned  Opcode)
static

◆ getRVVFPReductionOpAndOperands()

static std::tuple<unsigned, SDValue, SDValue> getRVVFPReductionOpAndOperands ( SDValue  Op,
SelectionDAG DAG,
EVT  EltVT 
)
static

◆ getRVVReductionOp()

static unsigned getRVVReductionOp ( unsigned  ISDOpcode)
static

◆ getRVVVPReductionOp()

static unsigned getRVVVPReductionOp ( unsigned  ISDOpcode)
static

◆ getTargetNode() [1/4]

static SDValue getTargetNode ( BlockAddressSDNode N,
SDLoc  DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 4210 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getTargetBlockAddress(), and N.

◆ getTargetNode() [2/4]

static SDValue getTargetNode ( ConstantPoolSDNode N,
SDLoc  DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 4216 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getTargetConstantPool(), and N.

◆ getTargetNode() [3/4]

static SDValue getTargetNode ( GlobalAddressSDNode N,
SDLoc  DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 4205 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getTargetGlobalAddress(), and N.

◆ getTargetNode() [4/4]

static SDValue getTargetNode ( JumpTableSDNode N,
SDLoc  DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 4222 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getTargetJumpTable(), and N.

◆ getVLOp()

static SDValue getVLOp ( uint64_t  NumElts,
SDLoc  DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ getVLOperand()

static SDValue getVLOperand ( SDValue  Op)
static

◆ isElementRotate()

static int isElementRotate ( int LoSrc,
int HiSrc,
ArrayRef< int Mask 
)
static

Match shuffles that concatenate two vectors, rotate the concatenation, and then extract the original number of elements from the rotated result.

This is equivalent to vector.splice or X86's PALIGNR instruction. The returned rotation amount is for a rotate right, where elements move from higher elements to lower elements. LoSrc indicates the first source vector of the rotate or -1 for undef. HiSrc indicates the second vector of the rotate or -1 for undef. At least one of LoSrc and HiSrc will be 0 or 1 if a rotation is found.

NOTE: We talk about rotate to the right which matches how bit shift and rotate instructions are described where LSBs are on the right, but LLVM IR and the table below write vectors with the lowest elements on the left.

Definition at line 2857 of file RISCVISelLowering.cpp.

References assert(), i, M, and llvm::BitmaskEnumDetail::Mask().

Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal(), and lowerVECTOR_SHUFFLE().

◆ isInterleaveShuffle()

static bool isInterleaveShuffle ( ArrayRef< int Mask,
MVT  VT,
bool &  SwapSources,
const RISCVSubtarget Subtarget 
)
static

◆ isSelectPseudo()

static bool isSelectPseudo ( MachineInstr MI)
static

Definition at line 10633 of file RISCVISelLowering.cpp.

References MI.

Referenced by emitSelectPseudo().

◆ isSimpleVIDSequence()

static std::optional<VIDSequence> isSimpleVIDSequence ( SDValue  Op)
static

◆ lowerBUILD_VECTOR()

static SDValue lowerBUILD_VECTOR ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

Definition at line 2378 of file RISCVISelLowering.cpp.

References llvm::abs(), llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::tgtok::Bits, llvm::MVT::bitsLE(), llvm::MVT::changeVectorElementType(), llvm::MVT::changeVectorElementTypeToInteger(), convertFromScalableVector(), llvm::count_if(), llvm::divideCeil(), DL, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::RISCVSubtarget::getELEN(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplatBuildVector(), llvm::getSplatValue(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::insert(), llvm::ISD::INSERT_VECTOR_ELT, llvm::RISCVSubtarget::is64Bit(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), llvm::isPowerOf2_32(), llvm::isPowerOf2_64(), isSimpleVIDSequence(), llvm::SDValue::isUndef(), llvm::Log2_32(), llvm::Log2_64(), llvm::BitmaskEnumDetail::Mask(), matchSplatAsGather(), llvm::max(), llvm::min(), llvm::ISD::MUL, llvm::ISD::SETNE, llvm::ISD::SHL, llvm::SelectionDAG::shouldOptForSize(), llvm::ISD::SINT_TO_FP, llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::size(), llvm::ISD::SRL, llvm::ISD::SUB, llvm::transform(), llvm::MVT::v1i8, llvm::MVT::v8i1, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VID_VL, llvm::RISCVISD::VMCLR_VL, llvm::RISCVISD::VMSET_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::ISD::VSELECT.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

◆ lowerConstant()

static SDValue lowerConstant ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerCTLZ_CTTZ_ZERO_UNDEF()

static SDValue lowerCTLZ_CTTZ_ZERO_UNDEF ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ lowerFP_TO_INT_SAT()

static SDValue lowerFP_TO_INT_SAT ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerFTRUNC_FCEIL_FFLOOR_FROUND()

static SDValue lowerFTRUNC_FCEIL_FFLOOR_FROUND ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerScalarSplat()

static SDValue lowerScalarSplat ( SDValue  Passthru,
SDValue  Scalar,
SDValue  VL,
MVT  VT,
SDLoc  DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerVECTOR_SHUFFLE()

static SDValue lowerVECTOR_SHUFFLE ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

Definition at line 3075 of file RISCVISelLowering.cpp.

References llvm::RISCVISD::ADD_VL, llvm::all_of(), assert(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::begin(), llvm::MVT::bitsGT(), llvm::MVT::changeTypeToInteger(), llvm::MVT::changeVectorElementType(), llvm::ISD::CONCAT_VECTORS, convertFromScalableVector(), convertToScalableVector(), DL, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::TypeSize::Fixed(), llvm::SelectionDAG::getAllOnesConstant(), getAllOnesMask(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtLoad(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getFreeze(), llvm::MVT::getHalfNumVectorElementsVT(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getScalarType(), llvm::SDValue::getSimpleValueType(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getSplatValue(), llvm::MVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i1, llvm::MVT::i16, int, llvm::ISD::INTRINSIC_W_CHAIN, isElementRotate(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), isInterleaveShuffle(), llvm::ISD::isNormalLoad(), llvm::ShuffleVectorSDNode::isSplat(), llvm::SelectionDAG::isSplatValue(), llvm::SDValue::isUndef(), lowerScalarSplat(), lowerVECTOR_SHUFFLEAsVNSRL(), lowerVECTOR_SHUFFLEAsVSlidedown(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::BitmaskEnumDetail::Mask(), llvm::MVT::Other, llvm::ISD::SEXTLOAD, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::size(), std::swap(), llvm::NVPTX::PTXLdStInstCode::V2, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_V_X_VL, llvm::RISCVISD::VRGATHER_VV_VL, llvm::RISCVISD::VRGATHER_VX_VL, llvm::RISCVISD::VRGATHEREI16_VV_VL, llvm::ISD::VSELECT, llvm::RISCVISD::VSLIDEDOWN_VL, llvm::RISCVISD::VSLIDEUP_VL, llvm::RISCVISD::VWADDU_VL, and llvm::RISCVISD::VWMULU_VL.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

◆ lowerVECTOR_SHUFFLEAsVNSRL()

static SDValue lowerVECTOR_SHUFFLEAsVNSRL ( const SDLoc DL,
MVT  VT,
MVT  ContainerVT,
SDValue  V1,
SDValue  V2,
SDValue  TrueMask,
SDValue  VL,
ArrayRef< int Mask,
const RISCVSubtarget Subtarget,
SelectionDAG DAG 
)
static

◆ lowerVECTOR_SHUFFLEAsVSlidedown()

static SDValue lowerVECTOR_SHUFFLEAsVSlidedown ( const SDLoc DL,
MVT  VT,
SDValue  V1,
SDValue  V2,
ArrayRef< int Mask,
const RISCVSubtarget Subtarget,
SelectionDAG DAG 
)
static

◆ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()

static SDValue lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerVectorIntrinsicScalars()

static SDValue lowerVectorIntrinsicScalars ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

Definition at line 5239 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLT(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::RISCVTargetLowering::computeVLMAX(), DL, llvm::RISCVVType::encodeSEW(), llvm::ISD::EXTRACT_ELEMENT, getAllOnesMask(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::LinearPolySize< LeafTy >::getKnownMinValue(), llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealMaxVLen(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), getVLOperand(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::hasScalarOperand(), llvm::RISCVSubtarget::hasVInstructions(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::MVT::isScalarInteger(), llvm::SDValue::isUndef(), llvm::XCoreISD::LMUL, llvm::BitmaskEnumDetail::Mask(), Operands, llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::ScalarOperand, SEW, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, splatSplitI64WithVL(), llvm::RISCVII::TAIL_AGNOSTIC, llvm::ISD::TRUNCATE, llvm::RISCVISD::VP_MERGE_VL, llvm::RISCVISD::VSELECT_VL, llvm::RISCVISD::VSLIDE1DOWN_VL, and llvm::RISCVISD::VSLIDE1UP_VL.

◆ matchRoundingOp()

static RISCVFPRndMode::RoundingMode matchRoundingOp ( unsigned  Opc)
static

◆ matchSplatAsGather()

static SDValue matchSplatAsGather ( SDValue  SplatVal,
MVT  VT,
const SDLoc DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ negateFMAOpcode()

static unsigned negateFMAOpcode ( unsigned  Opcode,
bool  NegMul,
bool  NegAcc 
)
static

◆ performADDCombine()

static SDValue performADDCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performANDCombine()

static SDValue performANDCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const RISCVSubtarget Subtarget 
)
static

◆ performBITREVERSECombine()

static SDValue performBITREVERSECombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performFP_TO_INT_SATCombine()

static SDValue performFP_TO_INT_SATCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const RISCVSubtarget Subtarget 
)
static

◆ performFP_TO_INTCombine()

static SDValue performFP_TO_INTCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const RISCVSubtarget Subtarget 
)
static

◆ performORCombine()

static SDValue performORCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const RISCVSubtarget Subtarget 
)
static

◆ performSETCCCombine()

static SDValue performSETCCCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performSIGN_EXTEND_INREGCombine()

static SDValue performSIGN_EXTEND_INREGCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performSRACombine()

static SDValue performSRACombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performSUBCombine()

static SDValue performSUBCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performTRUNCATECombine()

static SDValue performTRUNCATECombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performXORCombine()

static SDValue performXORCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ preAssignMask()

template<typename ArgTy >
static std::optional<unsigned> preAssignMask ( const ArgTy &  Args)
static

◆ splatPartsI64WithVL()

static SDValue splatPartsI64WithVL ( const SDLoc DL,
MVT  VT,
SDValue  Passthru,
SDValue  Lo,
SDValue  Hi,
SDValue  VL,
SelectionDAG DAG 
)
static

◆ splatSplitI64WithVL()

static SDValue splatSplitI64WithVL ( const SDLoc DL,
MVT  VT,
SDValue  Passthru,
SDValue  Scalar,
SDValue  VL,
SelectionDAG DAG 
)
static

◆ STATISTIC()

STATISTIC ( NumTailCalls  ,
"Number of tail calls  
)

◆ transformAddImmMulImm()

static SDValue transformAddImmMulImm ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ transformAddShlImm()

static SDValue transformAddShlImm ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ translateSetCCForBranch()

static void translateSetCCForBranch ( const SDLoc DL,
SDValue LHS,
SDValue RHS,
ISD::CondCode CC,
SelectionDAG DAG 
)
static

◆ tryDemorganOfBooleanCondition()

static SDValue tryDemorganOfBooleanCondition ( SDValue  Cond,
SelectionDAG DAG 
)
static

◆ unpackF64OnRV32DSoftABI()

static SDValue unpackF64OnRV32DSoftABI ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const SDLoc DL 
)
static

◆ unpackFromMemLoc()

static SDValue unpackFromMemLoc ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const SDLoc DL 
)
static

◆ unpackFromRegLoc()

static SDValue unpackFromRegLoc ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const SDLoc DL,
const ISD::InputArg In,
const RISCVTargetLowering TLI 
)
static

◆ useRVVForFixedLengthVectorVT()

static bool useRVVForFixedLengthVectorVT ( MVT  VT,
const RISCVSubtarget Subtarget 
)
static

Variable Documentation

◆ AllowSplatInVW_W

cl::opt<bool> AllowSplatInVW_W(DEBUG_TYPE "-form-vw-w-with-splat", cl::Hidden, cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants"), cl::init(false))
static

◆ ArgFPR16s

const MCPhysReg ArgFPR16s[]
static
Initial value:
= {
RISCV::F10_H, RISCV::F11_H, RISCV::F12_H, RISCV::F13_H,
RISCV::F14_H, RISCV::F15_H, RISCV::F16_H, RISCV::F17_H
}

Definition at line 11220 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV().

◆ ArgFPR32s

const MCPhysReg ArgFPR32s[]
static
Initial value:
= {
RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F,
RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F
}

Definition at line 11224 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV().

◆ ArgFPR64s

const MCPhysReg ArgFPR64s[]
static
Initial value:
= {
RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D,
RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D
}

Definition at line 11228 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV().

◆ ArgGPRs

const MCPhysReg ArgGPRs[]
static
Initial value:
= {
RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13,
RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
}

Definition at line 11216 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV(), CC_RISCVAssign2XLen(), llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerFormalArguments().

◆ ArgVRM2s

const MCPhysReg ArgVRM2s[]
static
Initial value:
= {RISCV::V8M2, RISCV::V10M2, RISCV::V12M2,
RISCV::V14M2, RISCV::V16M2, RISCV::V18M2,
RISCV::V20M2, RISCV::V22M2}

Definition at line 11237 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

◆ ArgVRM4s

const MCPhysReg ArgVRM4s[]
static
Initial value:
= {RISCV::V8M4, RISCV::V12M4, RISCV::V16M4,
RISCV::V20M4}

Definition at line 11240 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

◆ ArgVRM8s

const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8}
static

Definition at line 11242 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

◆ ArgVRs

const MCPhysReg ArgVRs[]
static
Initial value:
= {
RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13,
RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19,
RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23}

Definition at line 11233 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

◆ ExtensionMaxWebSize

cl::opt<unsigned> ExtensionMaxWebSize(DEBUG_TYPE "-ext-max-web-size", cl::Hidden, cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion"), cl::init(18))
static
NODE
#define NODE(NodeKind)
Definition: ItaniumDemangle.h:2374