RISCVISelLowering.cpp File Reference

#include "RISCVISelLowering.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVRegisterInfo.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/DiagnosticPrinter.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <optional>
#include "RISCVGenAsmMatcher.inc"
#include "RISCVGenSearchableTables.inc"

Include dependency graph for RISCVISelLowering.cpp:

Go to the source code of this file.

Classes
struct	VIDSequence

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::RISCVVIntrinsicsTable

Macros
#define	DEBUG_TYPE   "riscv-lower"
#define	NODE_NAME_CASE(NODE)
#define	GET_REGISTER_MATCHER
#define	GET_RISCVVIntrinsicsTable_IMPL

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")
static void	translateSetCCForBranch (const SDLoc &DL, SDValue &LHS, SDValue &RHS, ISD::CondCode &CC, SelectionDAG &DAG)
static SDValue	getVLOperand (SDValue Op)
static bool	useRVVForFixedLengthVectorVT (MVT VT, const RISCVSubtarget &Subtarget)
static MVT	getContainerForFixedLengthVector (const TargetLowering &TLI, MVT VT, const RISCVSubtarget &Subtarget)
static MVT	getContainerForFixedLengthVector (SelectionDAG &DAG, MVT VT, const RISCVSubtarget &Subtarget)
static SDValue	convertToScalableVector (EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	convertFromScalableVector (EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static MVT	getMaskTypeFor (MVT VecVT)
	Return the type of the mask type suitable for masking the provided vector type.
static SDValue	getAllOnesMask (MVT VecVT, SDValue VL, SDLoc DL, SelectionDAG &DAG)
	Creates an all ones mask suitable for masking a vector of type VecTy with vector length VL.
static SDValue	getVLOp (uint64_t NumElts, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static std::pair< SDValue, SDValue >	getDefaultVLOps (uint64_t NumElts, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static std::pair< SDValue, SDValue >	getDefaultVLOps (MVT VecVT, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static std::pair< SDValue, SDValue >	getDefaultScalableVLOps (MVT VecVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerFP_TO_INT_SAT (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static RISCVFPRndMode::RoundingMode	matchRoundingOp (unsigned Opc)
static SDValue	lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerFTRUNC_FCEIL_FFLOOR_FROUND (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static std::optional< uint64_t >	getExactInteger (const APFloat &APF, uint32_t BitWidth)
static std::optional< VIDSequence >	isSimpleVIDSequence (SDValue Op)
static SDValue	matchSplatAsGather (SDValue SplatVal, MVT VT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerBUILD_VECTOR (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	splatPartsI64WithVL (const SDLoc &DL, MVT VT, SDValue Passthru, SDValue Lo, SDValue Hi, SDValue VL, SelectionDAG &DAG)
static SDValue	splatSplitI64WithVL (const SDLoc &DL, MVT VT, SDValue Passthru, SDValue Scalar, SDValue VL, SelectionDAG &DAG)
static SDValue	lowerScalarSplat (SDValue Passthru, SDValue Scalar, SDValue VL, MVT VT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static MVT	getLMUL1VT (MVT VT)
static SDValue	lowerScalarInsert (SDValue Scalar, SDValue VL, MVT VT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static bool	isDeinterleaveShuffle (MVT VT, MVT ContainerVT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const RISCVSubtarget &Subtarget)
static bool	isInterleaveShuffle (ArrayRef< int > Mask, MVT VT, int &EvenSrc, int &OddSrc, const RISCVSubtarget &Subtarget)
	Is this shuffle interleaving contiguous elements from one vector into the even elements and contiguous elements from another vector into the odd elements.
static int	isElementRotate (int &LoSrc, int &HiSrc, ArrayRef< int > Mask)
	Match shuffles that concatenate two vectors, rotate the concatenation, and then extract the original number of elements from the rotated result.
static SDValue	getDeinterleaveViaVNSRL (const SDLoc &DL, MVT VT, SDValue Src, bool EvenElts, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
static SDValue	getVSlidedown (SelectionDAG &DAG, const RISCVSubtarget &Subtarget, SDLoc DL, EVT VT, SDValue Merge, SDValue Op, SDValue Offset, SDValue Mask, SDValue VL, unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED)
static SDValue	getVSlideup (SelectionDAG &DAG, const RISCVSubtarget &Subtarget, SDLoc DL, EVT VT, SDValue Merge, SDValue Op, SDValue Offset, SDValue Mask, SDValue VL, unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED)
static SDValue	lowerVECTOR_SHUFFLEAsVSlidedown (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
static SDValue	lowerVECTOR_SHUFFLEAsVSlideup (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
static SDValue	getWideningInterleave (SDValue EvenV, SDValue OddV, SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerConstant (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	LowerATOMIC_FENCE (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	getTargetNode (GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (BlockAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (ConstantPoolSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (JumpTableSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	lowerVectorIntrinsicScalars (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static unsigned	getRVVReductionOp (unsigned ISDOpcode)
static bool	hasNonZeroAVL (SDValue AVL)
static SDValue	lowerReductionSeq (unsigned RVVOpcode, MVT ResVT, SDValue StartValue, SDValue Vec, SDValue Mask, SDValue VL, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
	Helper to lower a reduction sequence of the form: scalar = reduce_op vec, scalar_start.
static std::tuple< unsigned, SDValue, SDValue >	getRVVFPReductionOpAndOperands (SDValue Op, SelectionDAG &DAG, EVT EltVT)
static unsigned	getRVVVPReductionOp (unsigned ISDOpcode)
static SDValue	widenVectorOpsToi8 (SDValue N, SDLoc &DL, SelectionDAG &DAG)
static RISCVISD::NodeType	getRISCVWOpcode (unsigned Opcode)
static SDValue	customLegalizeToWOp (SDNode *N, SelectionDAG &DAG, unsigned ExtOpc=ISD::ANY_EXTEND)
static SDValue	customLegalizeToWOpWithSExt (SDNode *N, SelectionDAG &DAG)
static SDValue	combineBinOpToReduce (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	transformAddShlImm (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	combineSelectAndUse (SDNode *N, SDValue Slct, SDValue OtherOp, SelectionDAG &DAG, bool AllOnes, const RISCVSubtarget &Subtarget)
static SDValue	combineSelectAndUseCommutative (SDNode *N, SelectionDAG &DAG, bool AllOnes, const RISCVSubtarget &Subtarget)
static SDValue	transformAddImmMulImm (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	performADDCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	combineSubOfBoolean (SDNode *N, SelectionDAG &DAG)
static SDValue	performSUBCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	combineDeMorganOfBoolean (SDNode *N, SelectionDAG &DAG)
static SDValue	performTRUNCATECombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static std::optional< std::tuple< ISD::CondCode, SDValue, SDValue, SDValue > >	verifyCompareConds (SDNode *N, SelectionDAG &DAG)
static ISD::NodeType	getSelectionCode (bool IsUnsigned, bool IsAnd, bool IsGreaterOp)
static SDValue	combineCmpOp (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	performANDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static SDValue	performORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static SDValue	performXORCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	performSETCCCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	performSIGN_EXTEND_INREGCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	combineBinOp_VLToVWBinOp_VL (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	Combine a binary operation to its equivalent VW or VW_W form.
static SDValue	tryMemPairCombine (SelectionDAG &DAG, LSBaseSDNode *LSNode1, LSBaseSDNode *LSNode2, SDValue BasePtr, uint64_t Imm)
static SDValue	performMemPairCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performFP_TO_INTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static SDValue	performFP_TO_INT_SATCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static SDValue	performBITREVERSECombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static unsigned	negateFMAOpcode (unsigned Opcode, bool NegMul, bool NegAcc)
static SDValue	performSRACombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	tryDemorganOfBooleanCondition (SDValue Cond, SelectionDAG &DAG)
static bool	combine_CC (SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	tryFoldSelectIntoOp (SDNode *N, SelectionDAG &DAG, SDValue TrueVal, SDValue FalseVal, bool Swapped)
static SDValue	performSELECTCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static uint64_t	computeGREVOrGORC (uint64_t x, unsigned ShAmt, bool IsGORC)
static MachineBasicBlock *	emitReadCycleWidePseudo (MachineInstr &MI, MachineBasicBlock *BB)
static MachineBasicBlock *	emitSplitF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB, const RISCVSubtarget &Subtarget)
static MachineBasicBlock *	emitBuildPairF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB, const RISCVSubtarget &Subtarget)
static bool	isSelectPseudo (MachineInstr &MI)
static MachineBasicBlock *	emitQuietFCMP (MachineInstr &MI, MachineBasicBlock *BB, unsigned RelOpcode, unsigned EqOpcode, const RISCVSubtarget &Subtarget)
static MachineBasicBlock *	EmitLoweredCascadedSelect (MachineInstr &First, MachineInstr &Second, MachineBasicBlock *ThisMBB, const RISCVSubtarget &Subtarget)
static MachineBasicBlock *	emitSelectPseudo (MachineInstr &MI, MachineBasicBlock *BB, const RISCVSubtarget &Subtarget)
static MachineBasicBlock *	emitVFCVT_RM_MASK (MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode)
static MachineBasicBlock *	emitVFROUND_NOEXCEPT_MASK (MachineInstr &MI, MachineBasicBlock *BB, unsigned CVTXOpc, unsigned CVTFOpc)
static MachineBasicBlock *	emitFROUND (MachineInstr &MI, MachineBasicBlock *MBB, const RISCVSubtarget &Subtarget)
static bool	CC_RISCVAssign2XLen (unsigned XLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
static unsigned	allocateRVVReg (MVT ValVT, unsigned ValNo, std::optional< unsigned > FirstMaskArgument, CCState &State, const RISCVTargetLowering &TLI)
static bool	CC_RISCV (const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
template<typename ArgTy >
static std::optional< unsigned >	preAssignMask (const ArgTy &Args)
static SDValue	convertLocVTToValVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget)
static SDValue	unpackFromRegLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const ISD::InputArg &In, const RISCVTargetLowering &TLI)
static SDValue	convertValVTToLocVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget)
static SDValue	unpackFromMemLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static SDValue	unpackF64OnRV32DSoftABI (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static bool	CC_RISCV_FastCC (const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
static bool	CC_RISCV_GHC (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static Align	getPrefTypeAlign (EVT VT, SelectionDAG &DAG)
static Intrinsic::ID	getIntrinsicForMaskedAtomicRMWBinOp (unsigned XLen, AtomicRMWInst::BinOp BinOp)
static Value *	useTpOffset (IRBuilderBase &IRB, unsigned Offset)

Variables
static cl::opt< unsigned >	ExtensionMaxWebSize (DEBUG_TYPE "-ext-max-web-size", cl::Hidden, cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion"), cl::init(18))
static cl::opt< bool >	AllowSplatInVW_W (DEBUG_TYPE "-form-vw-w-with-splat", cl::Hidden, cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants"), cl::init(false))
static cl::opt< unsigned >	NumRepeatedDivisors (DEBUG_TYPE "-fp-repeated-divisors", cl::Hidden, cl::desc("Set the minimum number of repetitions of a divisor to allow " "transformation to multiplications by the reciprocal"), cl::init(2))
static cl::opt< int >	FPImmCost (DEBUG_TYPE "-fpimm-cost", cl::Hidden, cl::desc("Give the maximum number of instructions that we will " "use for creating a floating-point immediate value"), cl::init(2))
static const MCPhysReg	ArgGPRs []
static const MCPhysReg	ArgFPR16s []
static const MCPhysReg	ArgFPR32s []
static const MCPhysReg	ArgFPR64s []
static const MCPhysReg	ArgVRs []
static const MCPhysReg	ArgVRM2s []
static const MCPhysReg	ArgVRM4s []
static const MCPhysReg	ArgVRM8s [] = {RISCV::V8M8, RISCV::V16M8}

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "riscv-lower"

Definition at line 47 of file RISCVISelLowering.cpp.

GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 15008 of file RISCVISelLowering.cpp.

GET_RISCVVIntrinsicsTable_IMPL

#define GET_RISCVVIntrinsicsTable_IMPL

Definition at line 15029 of file RISCVISelLowering.cpp.

NODE_NAME_CASE

#define NODE_NAME_CASE

(

NODE

)

Value:

  case RISCVISD::NODE:                                                         \
    return "RISCVISD::" #NODE;

Function Documentation

allocateRVVReg()

static unsigned allocateRVVReg ( MVT  ValVT, unsigned  ValNo, std::optional< unsigned >  FirstMaskArgument, CCState &  State, const RISCVTargetLowering &  TLI  )

static

Definition at line 12630 of file RISCVISelLowering.cpp.

References llvm::CCState::AllocateReg(), ArgVRM2s, ArgVRM4s, ArgVRM8s, ArgVRs, llvm::TargetLoweringBase::getRegClassFor(), and llvm_unreachable.

Referenced by CC_RISCV(), and CC_RISCV_FastCC().

CC_RISCV()

static bool CC_RISCV ( const DataLayout &  DL, RISCVABI::ABI  ABI, unsigned  ValNo, MVT  ValVT, MVT  LocVT, CCValAssign::LocInfo  LocInfo, ISD::ArgFlagsTy  ArgFlags, CCState &  State, bool  IsFixed, bool  IsRet, Type *  OrigTy, const RISCVTargetLowering &  TLI, std::optional< unsigned >  FirstMaskArgument  )

static

Definition at line 12652 of file RISCVISelLowering.cpp.

References llvm::RISCVABI::ABI_ILP32, llvm::RISCVABI::ABI_ILP32D, llvm::RISCVABI::ABI_ILP32F, llvm::RISCVABI::ABI_LP64, llvm::RISCVABI::ABI_LP64D, llvm::RISCVABI::ABI_LP64F, llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), allocateRVVReg(), llvm::CCState::AllocateStack(), ArgFPR16s, ArgFPR32s, ArgFPR64s, ArgGPRs, assert(), llvm::CCValAssign::BCvt, CC_RISCVAssign2XLen(), llvm::SmallVectorImpl< T >::clear(), DL, llvm::SmallVectorBase< Size_T >::empty(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::CCValAssign::Full, llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), llvm::CCState::getFirstUnallocated(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getPending(), llvm::CCState::getPendingArgFlags(), llvm::CCState::getPendingLocs(), llvm::CCValAssign::getReg(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getStoreSize(), llvm::RISCVTargetLowering::getSubtarget(), llvm::RISCVSubtarget::hasVInstructions(), llvm::MVT::i32, llvm::MVT::i64, llvm::CCValAssign::Indirect, llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::ISD::ArgFlagsTy::isNest(), llvm::MVT::isScalableVector(), llvm::MVT::isScalarInteger(), llvm::ISD::ArgFlagsTy::isSplit(), llvm::ISD::ArgFlagsTy::isSplitEnd(), llvm::MVT::isVector(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorBase< Size_T >::size(), and llvm::MaybeAlign::valueOrOne().

Referenced by llvm::RISCVTargetLowering::CanLowerReturn(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerFormalArguments(), and llvm::RISCVTargetLowering::LowerReturn().

CC_RISCV_FastCC()

static bool CC_RISCV_FastCC ( const DataLayout &  DL, RISCVABI::ABI  ABI, unsigned  ValNo, MVT  ValVT, MVT  LocVT, CCValAssign::LocInfo  LocInfo, ISD::ArgFlagsTy  ArgFlags, CCState &  State, bool  IsFixed, bool  IsRet, Type *  OrigTy, const RISCVTargetLowering &  TLI, std::optional< unsigned >  FirstMaskArgument  )

static

Definition at line 13105 of file RISCVISelLowering.cpp.

References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), allocateRVVReg(), llvm::CCState::AllocateStack(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), llvm::CCValAssign::getMem(), llvm::CCValAssign::getReg(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getStoreSize(), llvm::RISCVTargetLowering::getSubtarget(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::CCValAssign::Indirect, llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), and llvm::MaybeAlign::valueOrOne().

Referenced by llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerFormalArguments().

CC_RISCV_GHC()

static bool CC_RISCV_GHC ( unsigned  ValNo, MVT  ValVT, MVT  LocVT, CCValAssign::LocInfo  LocInfo, ISD::ArgFlagsTy  ArgFlags, CCState &  State  )

static

Definition at line 13207 of file RISCVISelLowering.cpp.

References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::MVT::f32, llvm::MVT::f64, llvm::CCValAssign::getReg(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::ArgFlagsTy::isNest(), and llvm::report_fatal_error().

Referenced by llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerFormalArguments().

CC_RISCVAssign2XLen()

static bool CC_RISCVAssign2XLen ( unsigned  XLen, CCState &  State, CCValAssign  VA1, ISD::ArgFlagsTy  ArgFlags1, unsigned  ValNo2, MVT  ValVT2, MVT  LocVT2, ISD::ArgFlagsTy  ArgFlags2  )

static

Definition at line 12593 of file RISCVISelLowering.cpp.

References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), ArgGPRs, llvm::CCValAssign::Full, llvm::CCValAssign::getLocVT(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getReg(), llvm::CCValAssign::getValNo(), and llvm::CCValAssign::getValVT().

Referenced by CC_RISCV().

combine_CC()

static bool combine_CC ( SDValue &  LHS, SDValue &  RHS, SDValue &  CC, const SDLoc &  DL, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 10578 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, CC, llvm::ISD::Constant, DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::RISCVSubtarget::getXLenVT(), llvm::Value::hasOneUse(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::isPowerOf2_64(), LHS, llvm::Log2_64(), llvm::SelectionDAG::MaskedValueIsZero(), RHS, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, translateSetCCForBranch(), tryDemorganOfBooleanCondition(), and llvm::ISD::XOR.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

combineBinOp_VLToVWBinOp_VL()

static SDValue combineBinOp_VLToVWBinOp_VL ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Combine a binary operation to its equivalent VW or VW_W form.

The supported combines are: add_vl -> vwadd(u) | vwadd(u)_w sub_vl -> vwsub(u) | vwsub(u)_w mul_vl -> vwmul(u) | vwmul_su vwadd_w(u) -> vwadd(u) vwub_w(u) -> vwadd(u)

Definition at line 9967 of file RISCVISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorBase< Size_T >::empty(), ExtensionMaxWebSize, LHS, N, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SmallVectorImpl< T >::reserve(), RHS, llvm::SmallVectorBase< Size_T >::size(), and std::swap().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

combineBinOpToReduce()

static SDValue combineBinOpToReduce ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 8663 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::RISCVSubtarget::getXLenVT(), hasNonZeroAVL(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_SUBVECTOR, llvm::isNeutralConstant(), llvm::isNullConstant(), llvm::SDNode::isUndef(), llvm_unreachable, lowerScalarInsert(), N, llvm::ISD::OR, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::RISCVISD::VECREDUCE_ADD_VL, llvm::RISCVISD::VECREDUCE_AND_VL, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::RISCVISD::VECREDUCE_OR_VL, llvm::RISCVISD::VECREDUCE_SMAX_VL, llvm::RISCVISD::VECREDUCE_SMIN_VL, llvm::RISCVISD::VECREDUCE_UMAX_VL, llvm::RISCVISD::VECREDUCE_UMIN_VL, llvm::RISCVISD::VECREDUCE_XOR_VL, llvm::RISCVISD::VFMV_S_F_VL, llvm::RISCVISD::VMV_S_X_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::ISD::XOR.

Referenced by performADDCombine(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performORCombine(), and performXORCombine().

combineCmpOp()

static SDValue combineCmpOp ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 9275 of file RISCVISelLowering.cpp.

References A, llvm::ISD::AND, assert(), B, llvm::CallingConv::C, DL, llvm::SelectionDAG::getNode(), getSelectionCode(), llvm::SelectionDAG::getSetCC(), llvm::ISD::isSignedIntSetCC(), llvm::ISD::isUnsignedIntSetCC(), N, llvm::ISD::OR, and verifyCompareConds().

Referenced by performANDCombine(), and performORCombine().

combineDeMorganOfBoolean()

static SDValue combineDeMorganOfBoolean ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 9020 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::ISD::OR, and llvm::ISD::XOR.

Referenced by performANDCombine(), and performORCombine().

combineSelectAndUse()

static SDValue combineSelectAndUse ( SDNode *  N, SDValue  Slct, SDValue  OtherOp, SelectionDAG &  DAG, bool  AllOnes, const RISCVSubtarget &  Subtarget  )

static

Definition at line 8822 of file RISCVISelLowering.cpp.

References llvm::AllOnes, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::isNullConstant(), llvm::EVT::isVector(), isZeroOrAllOnes(), N, llvm::ISD::SELECT, llvm::RISCVISD::SELECT_CC, and std::swap().

combineSelectAndUseCommutative()

static SDValue combineSelectAndUseCommutative ( SDNode *  N, SelectionDAG &  DAG, bool  AllOnes, const RISCVSubtarget &  Subtarget  )

static

Definition at line 8872 of file RISCVISelLowering.cpp.

References llvm::AllOnes, combineSelectAndUse(), and N.

combineSubOfBoolean()

static SDValue combineSubOfBoolean ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 8965 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::EVT::isInteger(), llvm::isOneConstant(), llvm::APInt::isSignedIntN(), N, llvm::ISD::SETCC, and llvm::ISD::XOR.

Referenced by performSUBCombine().

computeGREVOrGORC()

static uint64_t computeGREVOrGORC ( uint64_t  x, unsigned  ShAmt, bool  IsGORC  )

static

Definition at line 11444 of file RISCVISelLowering.cpp.

Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode().

convertFromScalableVector()

static SDValue convertFromScalableVector ( EVT  VT, SDValue  V, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 2008 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getXLenVT(), and llvm::EVT::isFixedLengthVector().

convertLocVTToValVT()

static SDValue convertLocVTToValVT ( SelectionDAG &  DAG, SDValue  Val, const CCValAssign &  VA, const SDLoc &  DL, const RISCVSubtarget &  Subtarget  )

static

Definition at line 12948 of file RISCVISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertFromScalableVector(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::RISCVISD::FMV_H_X, llvm::RISCVISD::FMV_W_X_RV64, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::i64, llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::MVT::isScalableVector(), and llvm_unreachable.

convertToScalableVector()

static SDValue convertToScalableVector ( EVT  VT, SDValue  V, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 1996 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INSERT_SUBVECTOR, and llvm::EVT::isScalableVector().

convertValVTToLocVT()

static SDValue convertValVTToLocVT ( SelectionDAG &  DAG, SDValue  Val, const CCValAssign &  VA, const SDLoc &  DL, const RISCVSubtarget &  Subtarget  )

static

Definition at line 13005 of file RISCVISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertToScalableVector(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::RISCVISD::FMV_X_ANYEXTH, llvm::RISCVISD::FMV_X_ANYEXTW_RV64, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::i64, llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::EVT::isScalableVector(), and llvm_unreachable.

customLegalizeToWOp()

static SDValue customLegalizeToWOp ( SDNode *  N, SelectionDAG &  DAG, unsigned  ExtOpc = ISD::ANY_EXTEND  )

static

Definition at line 8131 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), getRISCVWOpcode(), llvm::MVT::i64, N, and llvm::ISD::TRUNCATE.

customLegalizeToWOpWithSExt()

static SDValue customLegalizeToWOpWithSExt ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 8144 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), llvm::MVT::i32, llvm::MVT::i64, N, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::TRUNCATE.

Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().

emitBuildPairF64Pseudo()

static MachineBasicBlock * emitBuildPairF64Pseudo ( MachineInstr &  MI, MachineBasicBlock *  BB, const RISCVSubtarget &  Subtarget  )

static

Definition at line 11792 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), llvm::HexagonInstrInfo::loadRegFromStackSlot(), MI, llvm::MachineMemOperand::MOStore, and TII.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

emitFROUND()

static MachineBasicBlock * emitFROUND ( MachineInstr &  MI, MachineBasicBlock *  MBB, const RISCVSubtarget &  Subtarget  )

static

Definition at line 12198 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, llvm::RISCVSubtarget::is64Bit(), llvm_unreachable, MBB, MI, MRI, llvm::MachineInstr::NoFPExcept, llvm::MachineInstr::setFlag(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

EmitLoweredCascadedSelect()

static MachineBasicBlock * EmitLoweredCascadedSelect ( MachineInstr &  First, MachineInstr &  Second, MachineBasicBlock *  ThisMBB, const RISCVSubtarget &  Subtarget  )

static

Definition at line 11878 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineOperand::getImm(), llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

Referenced by emitSelectPseudo().

emitQuietFCMP()

static MachineBasicBlock * emitQuietFCMP ( MachineInstr &  MI, MachineBasicBlock *  BB, unsigned  RelOpcode, unsigned  EqOpcode, const RISCVSubtarget &  Subtarget  )

static

Definition at line 11841 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::RegState::Kill, MI, MRI, llvm::MachineInstr::NoFPExcept, llvm::MachineInstr::setFlag(), and TII.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

emitReadCycleWidePseudo()

static MachineBasicBlock * emitReadCycleWidePseudo ( MachineInstr &  MI, MachineBasicBlock *  BB  )

static

Definition at line 11695 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getBasicBlock(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::insert(), MI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

emitSelectPseudo()

static MachineBasicBlock * emitSelectPseudo ( MachineInstr &  MI, MachineBasicBlock *  BB, const RISCVSubtarget &  Subtarget  )

static

Definition at line 11980 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::any_of(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), CC, llvm::MachineInstr::collectDebugValues(), llvm::SmallSet< T, N, C >::count(), DL, E, EmitLoweredCascadedSelect(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), I, llvm::SmallSet< T, N, C >::insert(), llvm::MachineBasicBlock::instr_end(), isSelectPseudo(), LHS, MI, llvm::next_nodbg(), llvm::MachineFunctionProperties::NoPHIs, llvm::MachineBasicBlock::push_back(), RHS, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

emitSplitF64Pseudo()

static MachineBasicBlock * emitSplitF64Pseudo ( MachineInstr &  MI, MachineBasicBlock *  BB, const RISCVSubtarget &  Subtarget  )

static

Definition at line 11757 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), assert(), llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), MI, llvm::MachineMemOperand::MOLoad, llvm::HexagonInstrInfo::storeRegToStackSlot(), and TII.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

emitVFCVT_RM_MASK()

static MachineBasicBlock * emitVFCVT_RM_MASK ( MachineInstr &  MI, MachineBasicBlock *  BB, unsigned  Opcode  )

static

Definition at line 12116 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::RegState::Kill, MI, MRI, llvm::MachineInstr::NoFPExcept, llvm::MachineInstr::setFlag(), and TII.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

emitVFROUND_NOEXCEPT_MASK()

static MachineBasicBlock * emitVFROUND_NOEXCEPT_MASK ( MachineInstr &  MI, MachineBasicBlock *  BB, unsigned  CVTXOpc, unsigned  CVTFOpc  )

static

Definition at line 12150 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::RegState::Kill, MI, MRI, TII, and TRI.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

getAllOnesMask()

static SDValue getAllOnesMask ( MVT  VecVT, SDValue  VL, SDLoc  DL, SelectionDAG &  DAG  )

static

Creates an all ones mask suitable for masking a vector of type VecTy with vector length VL.

Definition at line 2030 of file RISCVISelLowering.cpp.

References DL, getMaskTypeFor(), llvm::SelectionDAG::getNode(), and llvm::RISCVISD::VMSET_VL.

Referenced by getDefaultVLOps(), and lowerVectorIntrinsicScalars().

getContainerForFixedLengthVector() [1/2]

static MVT getContainerForFixedLengthVector ( const TargetLowering &  TLI, MVT  VT, const RISCVSubtarget &  Subtarget  )

static

Definition at line 1951 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::RISCVSubtarget::getELEN(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalableVectorVT(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::MVT::isFixedLengthVector(), llvm::isPowerOf2_32(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::RISCV::RVVBitsPerBlock, llvm::MVT::SimpleTy, and useRVVForFixedLengthVectorVT().

getContainerForFixedLengthVector() [2/2]

static MVT getContainerForFixedLengthVector ( SelectionDAG &  DAG, MVT  VT, const RISCVSubtarget &  Subtarget  )

static

Definition at line 1985 of file RISCVISelLowering.cpp.

References getContainerForFixedLengthVector(), and llvm::SelectionDAG::getTargetLoweringInfo().

getDefaultScalableVLOps()

static std::pair< SDValue, SDValue > getDefaultScalableVLOps ( MVT  VecVT, SDLoc  DL, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 2069 of file RISCVISelLowering.cpp.

References assert(), DL, getDefaultVLOps(), and llvm::MVT::isScalableVector().

getDefaultVLOps() [1/2]

static std::pair< SDValue, SDValue > getDefaultVLOps ( MVT  VecVT, MVT  ContainerVT, SDLoc  DL, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 2055 of file RISCVISelLowering.cpp.

References assert(), DL, getAllOnesMask(), getDefaultVLOps(), llvm::SelectionDAG::getRegister(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), and llvm::MVT::isScalableVector().

getDefaultVLOps() [2/2]

static std::pair< SDValue, SDValue > getDefaultVLOps ( uint64_t  NumElts, MVT  ContainerVT, SDLoc  DL, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 2042 of file RISCVISelLowering.cpp.

References assert(), DL, getAllOnesMask(), getVLOp(), and llvm::MVT::isScalableVector().

Referenced by getDefaultScalableVLOps(), getDefaultVLOps(), getDeinterleaveViaVNSRL(), getWideningInterleave(), lowerBUILD_VECTOR(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), matchSplatAsGather(), performFP_TO_INTCombine(), and llvm::RISCVTargetLowering::ReplaceNodeResults().

getDeinterleaveViaVNSRL()

static SDValue getDeinterleaveViaVNSRL ( const SDLoc &  DL, MVT  VT, SDValue  Src, bool  EvenElts, const RISCVSubtarget &  Subtarget, SelectionDAG &  DAG  )

static

Definition at line 3170 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::changeVectorElementTypeToInteger(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::RISCVISD::VMV_V_X_VL, and llvm::RISCVISD::VNSRL_VL.

Referenced by lowerVECTOR_SHUFFLE().

getExactInteger()

static std::optional< uint64_t > getExactInteger ( const APFloat &  APF, uint32_t  BitWidth  )

static

Definition at line 2358 of file RISCVISelLowering.cpp.

References llvm::BitWidth, llvm::APFloat::convertToInteger(), llvm::APInt::extractBitsAsZExtValue(), llvm::APFloat::isNegative(), llvm::APFloatBase::opInvalidOp, and llvm::TowardZero.

Referenced by isSimpleVIDSequence().

getIntrinsicForMaskedAtomicRMWBinOp()

static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp ( unsigned  XLen, AtomicRMWInst::BinOp  BinOp  )

static

Definition at line 14474 of file RISCVISelLowering.cpp.

References llvm::AtomicRMWInst::Add, llvm_unreachable, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, and llvm::AtomicRMWInst::Xchg.

getLMUL1VT()

static MVT getLMUL1VT ( MVT  VT )

static

Definition at line 2949 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::getScalableVectorVT(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), and llvm::RISCV::RVVBitsPerBlock.

Referenced by lowerReductionSeq(), and lowerScalarInsert().

getMaskTypeFor()

static MVT getMaskTypeFor ( MVT  VecVT )

static

Return the type of the mask type suitable for masking the provided vector type.

This is simply an i1 element type vector of the same (possibly scalable) length.

Definition at line 2022 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::MVT::i1, and llvm::MVT::isVector().

Referenced by getAllOnesMask(), and llvm::RISCVTargetLowering::PerformDAGCombine().

getPrefTypeAlign()

static Align getPrefTypeAlign ( EVT  VT, SelectionDAG &  DAG  )

static

Definition at line 13477 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), and llvm::EVT::getTypeForEVT().

getRISCVWOpcode()

static RISCVISD::NodeType getRISCVWOpcode ( unsigned  Opcode )

static

Definition at line 8103 of file RISCVISelLowering.cpp.

References llvm::RISCVISD::DIVUW, llvm::RISCVISD::DIVW, llvm_unreachable, llvm::RISCVISD::REMUW, llvm::RISCVISD::ROLW, llvm::RISCVISD::RORW, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::RISCVISD::SLLW, llvm::ISD::SRA, llvm::RISCVISD::SRAW, llvm::ISD::SRL, llvm::RISCVISD::SRLW, llvm::ISD::UDIV, and llvm::ISD::UREM.

Referenced by customLegalizeToWOp().

getRVVFPReductionOpAndOperands()

static std::tuple< unsigned, SDValue, SDValue > getRVVFPReductionOpAndOperands ( SDValue  Op, SelectionDAG &  DAG, EVT  EltVT  )

static

Definition at line 6388 of file RISCVISelLowering.cpp.

References DL, Flags, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getNeutralElement(), llvm::ISD::getVecReduceBaseOpcode(), llvm_unreachable, llvm::ISD::VECREDUCE_FADD, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::ISD::VECREDUCE_FMAX, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::ISD::VECREDUCE_FMIN, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::ISD::VECREDUCE_SEQ_FADD, and llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL.

getRVVReductionOp()

static unsigned getRVVReductionOp ( unsigned  ISDOpcode )

static

Definition at line 6199 of file RISCVISelLowering.cpp.

References llvm_unreachable, llvm::ISD::VECREDUCE_ADD, llvm::RISCVISD::VECREDUCE_ADD_VL, llvm::ISD::VECREDUCE_AND, llvm::RISCVISD::VECREDUCE_AND_VL, llvm::ISD::VECREDUCE_OR, llvm::RISCVISD::VECREDUCE_OR_VL, llvm::ISD::VECREDUCE_SMAX, llvm::RISCVISD::VECREDUCE_SMAX_VL, llvm::ISD::VECREDUCE_SMIN, llvm::RISCVISD::VECREDUCE_SMIN_VL, llvm::ISD::VECREDUCE_UMAX, llvm::RISCVISD::VECREDUCE_UMAX_VL, llvm::ISD::VECREDUCE_UMIN, llvm::RISCVISD::VECREDUCE_UMIN_VL, llvm::ISD::VECREDUCE_XOR, and llvm::RISCVISD::VECREDUCE_XOR_VL.

getRVVVPReductionOp()

static unsigned getRVVVPReductionOp ( unsigned  ISDOpcode )

static

Definition at line 6436 of file RISCVISelLowering.cpp.

References llvm_unreachable, llvm::RISCVISD::VECREDUCE_ADD_VL, llvm::RISCVISD::VECREDUCE_AND_VL, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::RISCVISD::VECREDUCE_OR_VL, llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL, llvm::RISCVISD::VECREDUCE_SMAX_VL, llvm::RISCVISD::VECREDUCE_SMIN_VL, llvm::RISCVISD::VECREDUCE_UMAX_VL, llvm::RISCVISD::VECREDUCE_UMIN_VL, and llvm::RISCVISD::VECREDUCE_XOR_VL.

getSelectionCode()

static ISD::NodeType getSelectionCode ( bool  IsUnsigned, bool  IsAnd, bool  IsGreaterOp  )

static

Definition at line 9262 of file RISCVISelLowering.cpp.

References llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMAX, and llvm::ISD::UMIN.

Referenced by combineCmpOp().

getTargetNode() [1/4]

static SDValue getTargetNode ( BlockAddressSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 4624 of file RISCVISelLowering.cpp.

References Flags, llvm::SelectionDAG::getTargetBlockAddress(), and N.

getTargetNode() [2/4]

static SDValue getTargetNode ( ConstantPoolSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 4630 of file RISCVISelLowering.cpp.

References Flags, llvm::SelectionDAG::getTargetConstantPool(), and N.

getTargetNode() [3/4]

static SDValue getTargetNode ( GlobalAddressSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 4619 of file RISCVISelLowering.cpp.

References DL, Flags, llvm::SelectionDAG::getTargetGlobalAddress(), and N.

getTargetNode() [4/4]

static SDValue getTargetNode ( JumpTableSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 4636 of file RISCVISelLowering.cpp.

References Flags, llvm::SelectionDAG::getTargetJumpTable(), and N.

getVLOp()

static SDValue getVLOp ( uint64_t  NumElts, SDLoc  DL, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 2036 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), and llvm::RISCVSubtarget::getXLenVT().

Referenced by llvm::RISCVTargetLowering::computeVLMax(), and getDefaultVLOps().

getVLOperand()

static SDValue getVLOperand ( SDValue  Op )

static

Definition at line 1866 of file RISCVISelLowering.cpp.

References assert(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::VLOperand.

Referenced by lowerVectorIntrinsicScalars().

getVSlidedown()

static SDValue getVSlidedown ( SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget, SDLoc  DL, EVT  VT, SDValue  Merge, SDValue  Op, SDValue  Offset, SDValue  Mask, SDValue  VL, unsigned  Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED  )

static

Definition at line 3218 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVII::MASK_AGNOSTIC, Merge, llvm::Offset, llvm::RISCVII::TAIL_AGNOSTIC, and llvm::RISCVISD::VSLIDEDOWN_VL.

Referenced by lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlidedown(), and llvm::RISCVTargetLowering::ReplaceNodeResults().

getVSlideup()

static SDValue getVSlideup ( SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget, SDLoc  DL, EVT  VT, SDValue  Merge, SDValue  Op, SDValue  Offset, SDValue  Mask, SDValue  VL, unsigned  Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED  )

static

Definition at line 3230 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVII::MASK_AGNOSTIC, Merge, llvm::Offset, llvm::RISCVII::TAIL_AGNOSTIC, and llvm::RISCVISD::VSLIDEUP_VL.

Referenced by lowerVECTOR_SHUFFLE(), and lowerVECTOR_SHUFFLEAsVSlideup().

getWideningInterleave()

static SDValue getWideningInterleave ( SDValue  EvenV, SDValue  OddV, SDLoc &  DL, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 3368 of file RISCVISelLowering.cpp.

References llvm::RISCVISD::ADD_VL, assert(), llvm::MVT::changeTypeToInteger(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::RISCVSubtarget::getELEN(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::multiplyCoefficientBy(), llvm::RISCVISD::VWADDU_VL, and llvm::RISCVISD::VWMULU_VL.

Referenced by lowerVECTOR_SHUFFLE().

hasNonZeroAVL()

static bool hasNonZeroAVL ( SDValue  AVL )

static

Definition at line 6305 of file RISCVISelLowering.cpp.

Referenced by combineBinOpToReduce(), and lowerReductionSeq().

isDeinterleaveShuffle()

static bool isDeinterleaveShuffle ( MVT  VT, MVT  ContainerVT, SDValue  V1, SDValue  V2, ArrayRef< int >  Mask, const RISCVSubtarget &  Subtarget  )

static

Definition at line 3024 of file RISCVISelLowering.cpp.

References llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getConstantOperandVal(), llvm::RISCVSubtarget::getELEN(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), and llvm::MVT::getScalarSizeInBits().

Referenced by lowerVECTOR_SHUFFLE().

isElementRotate()

static int isElementRotate ( int &  LoSrc, int &  HiSrc, ArrayRef< int >  Mask  )

static

Match shuffles that concatenate two vectors, rotate the concatenation, and then extract the original number of elements from the rotated result.

This is equivalent to vector.splice or X86's PALIGNR instruction. The returned rotation amount is for a rotate right, where elements move from higher elements to lower elements. LoSrc indicates the first source vector of the rotate or -1 for undef. HiSrc indicates the second vector of the rotate or -1 for undef. At least one of LoSrc and HiSrc will be 0 or 1 if a rotation is found.

NOTE: We talk about rotate to the right which matches how bit shift and rotate instructions are described where LSBs are on the right, but LLVM IR and the table below write vectors with the lowest elements on the left.

Definition at line 3104 of file RISCVISelLowering.cpp.

References assert(), and Size.

Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal(), and lowerVECTOR_SHUFFLE().

isInterleaveShuffle()

static bool isInterleaveShuffle ( ArrayRef< int >  Mask, MVT  VT, int &  EvenSrc, int &  OddSrc, const RISCVSubtarget &  Subtarget  )

static

Is this shuffle interleaving contiguous elements from one vector into the even elements and contiguous elements from another vector into the odd elements.

Src1 will contain the element that should be in the first even element. Src2 will contain the element that should be in the first odd element. These can be the first element in a source or the element half way through the source.

Definition at line 3069 of file RISCVISelLowering.cpp.

References assert(), llvm::RISCVSubtarget::getELEN(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::ShuffleVectorInst::isInterleaveMask(), and Size.

Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal(), and lowerVECTOR_SHUFFLE().

isSelectPseudo()

static bool isSelectPseudo ( MachineInstr &  MI )

static

Definition at line 11829 of file RISCVISelLowering.cpp.

References MI.

Referenced by emitSelectPseudo().

isSimpleVIDSequence()

static std::optional< VIDSequence > isSimpleVIDSequence ( SDValue  Op )

static

Definition at line 2386 of file RISCVISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, getExactInteger(), Idx, and llvm::SignExtend64().

Referenced by lowerBUILD_VECTOR().

LowerATOMIC_FENCE()

static SDValue LowerATOMIC_FENCE ( SDValue  Op, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 3927 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::ISD::MEMBARRIER, llvm::MVT::Other, llvm::SequentiallyConsistent, llvm::SyncScope::SingleThread, and llvm::SyncScope::System.

lowerBUILD_VECTOR()

static SDValue lowerBUILD_VECTOR ( SDValue  Op, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 2525 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::MVT::bitsLE(), llvm::MVT::changeVectorElementType(), llvm::MVT::changeVectorElementTypeToInteger(), convertFromScalableVector(), llvm::count_if(), llvm::divideCeil(), DL, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::RISCVSubtarget::getELEN(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplatBuildVector(), llvm::getSplatValue(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::ISD::INSERT_VECTOR_ELT, llvm::RISCVSubtarget::is64Bit(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), llvm::isPowerOf2_32(), llvm::isPowerOf2_64(), isSimpleVIDSequence(), llvm::Log2_32(), llvm::Log2_64(), matchSplatAsGather(), llvm::ISD::MUL, llvm::ISD::SETNE, llvm::ISD::SHL, llvm::SelectionDAG::shouldOptForSize(), llvm::ISD::SINT_TO_FP, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::size(), llvm::ISD::SRL, llvm::ISD::SUB, llvm::transform(), llvm::MVT::v1i8, llvm::MVT::v8i1, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VID_VL, llvm::RISCVISD::VMCLR_VL, llvm::RISCVISD::VMSET_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::ISD::VSELECT.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerConstant()

static SDValue lowerConstant ( SDValue  Op, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 3901 of file RISCVISelLowering.cpp.

References assert(), llvm::RISCVMatInt::generateInstSeq(), llvm::RISCVSubtarget::getMaxBuildIntsCost(), llvm::MVT::i64, llvm::SmallVectorBase< Size_T >::size(), and llvm::RISCVSubtarget::useConstantPoolForLargeInts().

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerFP_TO_INT_SAT()

static SDValue lowerFP_TO_INT_SAT ( SDValue  Op, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 2096 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::RISCVISD::FCVT_W_RV64, llvm::RISCVISD::FCVT_WU_RV64, llvm::RISCVISD::FCVT_X, llvm::RISCVISD::FCVT_XU, llvm::ISD::FP_EXTEND, llvm::RISCVISD::FP_EXTEND_VL, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), llvm::RISCVFPRndMode::RTZ, llvm::RISCVISD::SETCC_VL, llvm::ISD::SETUO, llvm::RISCVISD::VFCVT_RTZ_X_F_VL, llvm::RISCVISD::VFCVT_RTZ_XU_F_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::RISCVISD::VSELECT_VL.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerFTRUNC_FCEIL_FFLOOR_FROUND()

static SDValue lowerFTRUNC_FCEIL_FFLOOR_FROUND ( SDValue  Op, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 2325 of file RISCVISelLowering.cpp.

References llvm::APFloat::convertFromAPInt(), DL, llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::RISCVISD::FROUND, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isVector(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), and llvm::SelectionDAG::shouldOptForSize().

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerReductionSeq()

static SDValue lowerReductionSeq ( unsigned  RVVOpcode, MVT  ResVT, SDValue  StartValue, SDValue  Vec, SDValue  Mask, SDValue  VL, SDLoc  DL, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Helper to lower a reduction sequence of the form: scalar = reduce_op vec, scalar_start.

Definition at line 6314 of file RISCVISelLowering.cpp.

References llvm::MVT::bitsLE(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), getLMUL1VT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), hasNonZeroAVL(), llvm::ISD::INSERT_SUBVECTOR, lowerScalarInsert(), Reduction, and llvm::RISCVII::TAIL_AGNOSTIC.

lowerScalarInsert()

static SDValue lowerScalarInsert ( SDValue  Scalar, SDValue  VL, MVT  VT, SDLoc  DL, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 2961 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::MVT::bitsLE(), DL, llvm::SelectionDAG::getConstant(), getLMUL1VT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INSERT_SUBVECTOR, llvm::MVT::isFloatingPoint(), llvm::isNullConstant(), lowerScalarSplat(), llvm::ISD::SIGN_EXTEND, llvm::RISCVISD::VFMV_S_F_VL, llvm::RISCVISD::VMV_S_X_VL, and llvm::RISCVISD::VMV_V_X_VL.

Referenced by combineBinOpToReduce(), and lowerReductionSeq().

lowerScalarSplat()

static SDValue lowerScalarSplat ( SDValue  Passthru, SDValue  Scalar, SDValue  VL, MVT  VT, SDLoc  DL, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 2905 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::isFloatingPoint(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::SDValue::isUndef(), llvm::ISD::SIGN_EXTEND, splatSplitI64WithVL(), llvm::RISCVISD::VFMV_S_F_VL, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_S_X_VL, and llvm::RISCVISD::VMV_V_X_VL.

Referenced by lowerScalarInsert(), and lowerVECTOR_SHUFFLE().

lowerVECTOR_SHUFFLE()

static SDValue lowerVECTOR_SHUFFLE ( SDValue  Op, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 3437 of file RISCVISelLowering.cpp.

References llvm::all_of(), assert(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::begin(), llvm::MVT::bitsGT(), llvm::MVT::changeTypeToInteger(), llvm::MVT::changeVectorElementType(), llvm::ISD::CONCAT_VECTORS, convertFromScalableVector(), convertToScalableVector(), DL, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::TypeSize::Fixed(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), getDeinterleaveViaVNSRL(), llvm::SelectionDAG::getExtLoad(), llvm::SDNode::getFlags(), llvm::MVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getScalarType(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getSplatValue(), llvm::MVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), getVSlidedown(), getVSlideup(), llvm::SelectionDAG::getVTList(), getWideningInterleave(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i1, llvm::MVT::i16, llvm::ISD::INTRINSIC_W_CHAIN, isDeinterleaveShuffle(), isElementRotate(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), isInterleaveShuffle(), llvm::ISD::isNormalLoad(), llvm::ShuffleVectorSDNode::isSplat(), llvm::SelectionDAG::isSplatValue(), llvm::SDValue::isUndef(), lowerScalarSplat(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::Offset, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SEXTLOAD, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::size(), llvm::SmallVectorBase< Size_T >::size(), Size, std::swap(), llvm::RISCVII::TAIL_AGNOSTIC, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_V_X_VL, llvm::RISCVISD::VRGATHER_VV_VL, llvm::RISCVISD::VRGATHER_VX_VL, llvm::RISCVISD::VRGATHEREI16_VV_VL, and llvm::ISD::VSELECT.

Referenced by llvm::RISCVTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

lowerVECTOR_SHUFFLEAsVSlidedown()

static SDValue lowerVECTOR_SHUFFLEAsVSlidedown ( const SDLoc &  DL, MVT  VT, SDValue  V1, SDValue  V2, ArrayRef< int >  Mask, const RISCVSubtarget &  Subtarget, SelectionDAG &  DAG  )

static

Definition at line 3253 of file RISCVISelLowering.cpp.

References convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), getVSlidedown(), llvm::RISCVSubtarget::getXLenVT(), llvm::Offset, and llvm::SmallVectorBase< Size_T >::size().

Referenced by lowerVECTOR_SHUFFLE().

lowerVECTOR_SHUFFLEAsVSlideup()

static SDValue lowerVECTOR_SHUFFLEAsVSlideup ( const SDLoc &  DL, MVT  VT, SDValue  V1, SDValue  V2, ArrayRef< int >  Mask, const RISCVSubtarget &  Subtarget, SelectionDAG &  DAG  )

static

Definition at line 3330 of file RISCVISelLowering.cpp.

References convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getVectorNumElements(), getVSlideup(), llvm::RISCVSubtarget::getXLenVT(), llvm::ShuffleVectorInst::isInsertSubvectorMask(), llvm::RISCVII::MASK_AGNOSTIC, llvm::RISCVII::TAIL_AGNOSTIC, and llvm::RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED.

Referenced by lowerVECTOR_SHUFFLE().

lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()

static SDValue lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND ( SDValue  Op, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 2224 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::APFloat::convertFromAPInt(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::RISCVISD::FABS_VL, llvm::ISD::FCEIL, llvm::RISCVISD::FCOPYSIGN_VL, llvm::ISD::FFLOOR, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FTRUNC, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstantFP(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i1, llvm::RISCVFPRndMode::Invalid, llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), llvm_unreachable, matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), llvm::RISCVISD::SETCC_VL, llvm::ISD::SETOLT, llvm::RISCVISD::SINT_TO_FP_VL, llvm::RISCVISD::VFCVT_RM_X_F_VL, llvm::RISCVISD::VFCVT_RTZ_X_F_VL, llvm::RISCVISD::VFCVT_X_F_VL, llvm::RISCVISD::VFMV_V_F_VL, and llvm::RISCVISD::VFROUND_NOEXCEPT_VL.

Referenced by lowerFTRUNC_FCEIL_FFLOOR_FROUND(), and llvm::RISCVTargetLowering::LowerOperation().

lowerVectorIntrinsicScalars()

static SDValue lowerVectorIntrinsicScalars ( SDValue  Op, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 5715 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLT(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::RISCVTargetLowering::computeVLMAX(), DL, llvm::RISCVVType::encodeSEW(), llvm::ISD::EXTRACT_ELEMENT, getAllOnesMask(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealMaxVLen(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), getVLOperand(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::hasScalarOperand(), llvm::RISCVSubtarget::hasVInstructions(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::MVT::isScalarInteger(), llvm::SDValue::isUndef(), Operands, llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::ScalarOperand, SEW, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, splatSplitI64WithVL(), llvm::RISCVII::TAIL_AGNOSTIC, llvm::ISD::TRUNCATE, llvm::RISCVISD::VP_MERGE_VL, llvm::RISCVISD::VSELECT_VL, llvm::RISCVISD::VSLIDE1DOWN_VL, and llvm::RISCVISD::VSLIDE1UP_VL.

matchRoundingOp()

static RISCVFPRndMode::RoundingMode matchRoundingOp ( unsigned  Opc )

static

Definition at line 2195 of file RISCVISelLowering.cpp.

References llvm::RISCVFPRndMode::DYN, llvm::ISD::FCEIL, llvm::ISD::FFLOOR, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FTRUNC, llvm::RISCVFPRndMode::Invalid, llvm::RISCVFPRndMode::RDN, llvm::RISCVFPRndMode::RMM, llvm::RISCVFPRndMode::RNE, llvm::RISCVFPRndMode::RTZ, and llvm::RISCVFPRndMode::RUP.

Referenced by lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), performFP_TO_INT_SATCombine(), and performFP_TO_INTCombine().

matchSplatAsGather()

static SDValue matchSplatAsGather ( SDValue  SplatVal, MVT  VT, const SDLoc &  DL, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 2492 of file RISCVISelLowering.cpp.

References convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i1, Idx, llvm::MVT::isFixedLengthVector(), and llvm::RISCVISD::VRGATHER_VX_VL.

Referenced by lowerBUILD_VECTOR(), and llvm::RISCVTargetLowering::PerformDAGCombine().

negateFMAOpcode()

static unsigned negateFMAOpcode ( unsigned  Opcode, bool  NegMul, bool  NegAcc  )

static

Definition at line 10375 of file RISCVISelLowering.cpp.

References assert(), llvm_unreachable, llvm::RISCVISD::VFMADD_VL, llvm::RISCVISD::VFMSUB_VL, llvm::RISCVISD::VFNMADD_VL, and llvm::RISCVISD::VFNMSUB_VL.

Referenced by combineFMA(), combineFMADDSUB(), llvm::X86TargetLowering::getNegatedExpression(), and llvm::RISCVTargetLowering::PerformDAGCombine().

performADDCombine()

static SDValue performADDCombine ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 8951 of file RISCVISelLowering.cpp.

References combineBinOpToReduce(), combineSelectAndUseCommutative(), N, transformAddImmMulImm(), and transformAddShlImm().

performANDCombine()

static SDValue performANDCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const RISCVSubtarget &  Subtarget  )

static

Definition at line 9309 of file RISCVISelLowering.cpp.

References llvm::And, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, combineBinOpToReduce(), combineCmpOp(), combineDeMorganOfBoolean(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, llvm::RISCVSubtarget::is64Bit(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::isOneConstant(), N, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

performBITREVERSECombine()

static SDValue performBITREVERSECombine ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 10355 of file RISCVISelLowering.cpp.

References assert(), llvm::RISCVISD::BREV8, llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::EVT::isScalarInteger(), and N.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performFP_TO_INT_SATCombine()

static SDValue performFP_TO_INT_SATCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const RISCVSubtarget &  Subtarget  )

static

Definition at line 10296 of file RISCVISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::MVT::f16, llvm::RISCVISD::FCVT_W_RV64, llvm::RISCVISD::FCVT_WU_RV64, llvm::RISCVISD::FCVT_X, llvm::RISCVISD::FCVT_XU, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::MVT::i32, llvm::MVT::i64, llvm::RISCVFPRndMode::Invalid, llvm::TargetLoweringBase::isTypeLegal(), matchRoundingOp(), N, and llvm::ISD::SETUO.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performFP_TO_INTCombine()

static SDValue performFP_TO_INTCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const RISCVSubtarget &  Subtarget  )

static

Definition at line 10203 of file RISCVISelLowering.cpp.

References convertFromScalableVector(), convertToScalableVector(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::MVT::f16, llvm::RISCVISD::FCVT_W_RV64, llvm::RISCVISD::FCVT_WU_RV64, llvm::RISCVISD::FCVT_X, llvm::RISCVISD::FCVT_XU, llvm::ISD::FP_TO_SINT, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i32, llvm::RISCVFPRndMode::Invalid, llvm::EVT::isFixedLengthVector(), llvm::MVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), matchRoundingOp(), N, llvm::RISCVFPRndMode::RTZ, llvm::ISD::TRUNCATE, llvm::RISCVISD::VFCVT_RM_X_F_VL, llvm::RISCVISD::VFCVT_RM_XU_F_VL, llvm::RISCVISD::VFCVT_RTZ_X_F_VL, and llvm::RISCVISD::VFCVT_RTZ_XU_F_VL.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performMemPairCombine()

static SDValue performMemPairCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 10117 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::DAG, getExtensionType(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemoryVT(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MachineFunction::getSubtarget(), llvm::Use::getUser(), llvm::MVT::i32, llvm::MVT::i64, llvm::LSBaseSDNode::isIndexed(), llvm::MemSDNode::isSimple(), llvm::ISD::LOAD, N, Ptr, tryMemPairCombine(), llvm::SDNode::use_begin(), and llvm::SDNode::use_end().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performORCombine()

static SDValue performORCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const RISCVSubtarget &  Subtarget  )

static

Definition at line 9348 of file RISCVISelLowering.cpp.

References combineBinOpToReduce(), combineCmpOp(), combineDeMorganOfBoolean(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), and N.

performSELECTCombine()

static SDValue performSELECTCombine ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 10711 of file RISCVISelLowering.cpp.

References llvm::RISCVSubtarget::getXLenVT(), N, and tryFoldSelectIntoOp().

performSETCCCombine()

static SDValue performSETCCCombine ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 9394 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, Cond, llvm::APInt::getActiveBits(), llvm::SelectionDAG::getBoolConstant(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, llvm::RISCVSubtarget::is64Bit(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::ISD::SETNE, llvm::APInt::sext(), llvm::ISD::SIGN_EXTEND_INREG, and llvm::APInt::trunc().

performSIGN_EXTEND_INREGCombine()

static SDValue performSIGN_EXTEND_INREGCombine ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 9441 of file RISCVISelLowering.cpp.

References llvm::RISCVISD::FMV_X_ANYEXTH, llvm::RISCVISD::FMV_X_SIGNEXTH, llvm::SelectionDAG::getNode(), llvm::MVT::i16, and N.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performSRACombine()

static SDValue performSRACombine ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 10407 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::APInt::countr_zero(), DL, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, llvm::RISCVSubtarget::is64Bit(), llvm::APInt::lshr(), N, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SUB, and llvm::SDNode::uses().

performSUBCombine()

static SDValue performSUBCombine ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 9005 of file RISCVISelLowering.cpp.

References combineSelectAndUse(), combineSubOfBoolean(), and N.

performTRUNCATECombine()

static SDValue performTRUNCATECombine ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 9064 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i64, llvm::RISCVSubtarget::is64Bit(), N, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performXORCombine()

static SDValue performXORCombine ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 9367 of file RISCVISelLowering.cpp.

References combineBinOpToReduce(), combineSelectAndUseCommutative(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::i64, llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::TargetLoweringBase::isOperationLegal(), N, llvm::RISCVISD::ROLW, llvm::ISD::ROTL, and llvm::RISCVISD::SLLW.

preAssignMask()

template<typename ArgTy >

static std::optional< unsigned > preAssignMask ( const ArgTy &  Args )

static

Definition at line 12879 of file RISCVISelLowering.cpp.

References llvm::enumerate(), llvm::MVT::getVectorElementType(), llvm::MVT::i1, and llvm::MVT::isVector().

Referenced by llvm::RISCVTargetLowering::CanLowerReturn().

splatPartsI64WithVL()

static SDValue splatPartsI64WithVL ( const SDLoc &  DL, MVT  VT, SDValue  Passthru, SDValue  Lo, SDValue  Hi, SDValue  VL, SelectionDAG &  DAG  )

static

Definition at line 2856 of file RISCVISelLowering.cpp.

References llvm::ISD::BITCAST, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::Hi, llvm::MVT::i32, llvm::Lo, llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, and llvm::RISCVISD::VMV_V_X_VL.

Referenced by splatSplitI64WithVL().

splatSplitI64WithVL()

static SDValue splatSplitI64WithVL ( const SDLoc &  DL, MVT  VT, SDValue  Passthru, SDValue  Scalar, SDValue  VL, SelectionDAG &  DAG  )

static

Definition at line 2891 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::Lo, and splatPartsI64WithVL().

Referenced by lowerScalarSplat(), and lowerVectorIntrinsicScalars().

STATISTIC()

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"
	)

transformAddImmMulImm()

static SDValue transformAddImmMulImm ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 8902 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::EVT::isVector(), llvm::ISD::MUL, and N.

Referenced by performADDCombine().

transformAddShlImm()

static SDValue transformAddShlImm ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 8766 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::EVT::isVector(), N, NL, and llvm::ISD::SHL.

Referenced by performADDCombine().

translateSetCCForBranch()

static void translateSetCCForBranch ( const SDLoc &  DL, SDValue &  LHS, SDValue &  RHS, ISD::CondCode &  CC, SelectionDAG &  DAG  )

static

Definition at line 1663 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, llvm::bit_width(), llvm::CallingConv::C, CC, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::getSetCCSwappedOperands(), llvm::Value::hasOneUse(), llvm::isMask_64(), llvm::isNullConstant(), llvm::isPowerOf2_64(), LHS, llvm::Log2_64(), RHS, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SHL, and std::swap().

Referenced by combine_CC().

tryDemorganOfBooleanCondition()

static SDValue tryDemorganOfBooleanCondition ( SDValue  Cond, SelectionDAG &  DAG  )

static

Definition at line 10519 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, Cond, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::EVT::isScalarInteger(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETLT, std::swap(), llvm::Xor, and llvm::ISD::XOR.

Referenced by combine_CC().

tryFoldSelectIntoOp()

static SDValue tryFoldSelectIntoOp ( SDNode *  N, SelectionDAG &  DAG, SDValue  TrueVal, SDValue  FalseVal, bool  Swapped  )

static

Definition at line 10673 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), N, llvm::ISD::OR, llvm::ISD::SUB, std::swap(), and llvm::ISD::XOR.

Referenced by performSELECTCombine().

tryMemPairCombine()

static SDValue tryMemPairCombine ( SelectionDAG &  DAG, LSBaseSDNode *  LSNode1, LSBaseSDNode *  LSNode2, SDValue  BasePtr, uint64_t  Imm  )

static

Definition at line 10059 of file RISCVISelLowering.cpp.

References llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MachineMemOperand::getPointerInfo(), llvm::MachineFunction::getSubtarget(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDNode::hasPredecessorHelper(), llvm::MVT::i128, llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::LOAD, llvm::MVT::Other, llvm::SelectionDAG::ReplaceAllUsesWith(), llvm::RISCVISD::TH_LDD, llvm::RISCVISD::TH_LWD, llvm::RISCVISD::TH_LWUD, llvm::RISCVISD::TH_SDD, llvm::RISCVISD::TH_SWD, and llvm::ISD::ZEXTLOAD.

Referenced by performMemPairCombine().

unpackF64OnRV32DSoftABI()

static SDValue unpackF64OnRV32DSoftABI ( SelectionDAG &  DAG, SDValue  Chain, const CCValAssign &  VA, const SDLoc &  DL  )

static

Definition at line 13065 of file RISCVISelLowering.cpp.

References assert(), llvm::RISCVISD::BuildPairF64, llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::MVT::f64, llvm::SelectionDAG::getCopyFromReg(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getRegInfo(), llvm::CCValAssign::getValVT(), llvm::Hi, llvm::MVT::i32, llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), and llvm::Lo.

Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().

unpackFromMemLoc()

static SDValue unpackFromMemLoc ( SelectionDAG &  DAG, SDValue  Chain, const CCValAssign &  VA, const SDLoc &  DL  )

static

Definition at line 13031 of file RISCVISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::CCValAssign::Full, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MVT::getIntegerVT(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::DataLayout::getPointerSizeInBits(), llvm::EVT::getStoreSize(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, llvm::EVT::isScalableVector(), llvm_unreachable, and llvm::ISD::NON_EXTLOAD.

unpackFromRegLoc()

static SDValue unpackFromRegLoc ( SelectionDAG &  DAG, SDValue  Chain, const CCValAssign &  VA, const SDLoc &  DL, const ISD::InputArg &  In, const RISCVTargetLowering &  TLI  )

static

Definition at line 12972 of file RISCVISelLowering.cpp.

References llvm::RISCVMachineFunctionInfo::addSExt32Register(), llvm::BitWidth, convertLocVTToValVT(), DL, llvm::Function::getArg(), llvm::SelectionDAG::getCopyFromReg(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::Type::getIntegerBitWidth(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MachineFunction::getRegInfo(), llvm::EVT::getSimpleVT(), llvm::RISCVTargetLowering::getSubtarget(), llvm::Value::getType(), llvm::CCValAssign::Indirect, and llvm::Type::isIntegerTy().

useRVVForFixedLengthVectorVT()

static bool useRVVForFixedLengthVectorVT ( MVT  VT, const RISCVSubtarget &  Subtarget  )

static

Definition at line 1879 of file RISCVISelLowering.cpp.

References assert(), llvm::divideCeil(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::RISCVSubtarget::getELEN(), llvm::MVT::getFixedSizeInBits(), llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::hasVInstructionsF16(), llvm::RISCVSubtarget::hasVInstructionsF32(), llvm::RISCVSubtarget::hasVInstructionsF64(), llvm::RISCVSubtarget::hasVInstructionsI64(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::MVT::isFixedLengthVector(), llvm::MVT::isPow2VectorType(), llvm::MVT::SimpleTy, and llvm::RISCVSubtarget::useRVVForFixedLengthVectors().

Referenced by getContainerForFixedLengthVector().

useTpOffset()

static Value * useTpOffset ( IRBuilderBase &  IRB, unsigned  Offset  )

static

Definition at line 14989 of file RISCVISelLowering.cpp.

References llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateConstGEP1_32(), llvm::IRBuilderBase::CreatePointerCast(), llvm::Intrinsic::getDeclaration(), llvm::IRBuilderBase::GetInsertBlock(), llvm::IRBuilderBase::getInt8PtrTy(), llvm::IRBuilderBase::getInt8Ty(), llvm::GlobalValue::getParent(), llvm::BasicBlock::getParent(), llvm::Type::getPointerTo(), and llvm::Offset.

Referenced by llvm::RISCVTargetLowering::getIRStackGuard().

verifyCompareConds()

static std::optional< std::tuple< ISD::CondCode, SDValue, SDValue, SDValue > > verifyCompareConds ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 9196 of file RISCVISelLowering.cpp.

References A, assert(), B, llvm::CallingConv::C, llvm::dbgs(), llvm::SDValue::getOpcode(), llvm::ISD::getSetCCSwappedOperands(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), LLVM_DEBUG, N, and llvm::ISD::SETCC.

Referenced by combineCmpOp().

widenVectorOpsToi8()

static SDValue widenVectorOpsToi8 ( SDValue  N, SDLoc &  DL, SelectionDAG &  DAG  )

static

Definition at line 6776 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::changeVectorElementType(), DL, llvm::SmallVectorTemplateCommon< T, typename >::front(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), I, llvm::MVT::i8, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Variable Documentation

AllowSplatInVW_W

cl::opt< bool > AllowSplatInVW_W(DEBUG_TYPE "-form-vw-w-with-splat", cl::Hidden, cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants"), cl::init(false)) ( DEBUG_TYPE "-form-vw-w-with-splat"  , cl::Hidden  , cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants")  , cl::init(false)    )

static

ArgFPR16s

const MCPhysReg ArgFPR16s[]

static

Initial value:

= {
  RISCV::F10_H, RISCV::F11_H, RISCV::F12_H, RISCV::F13_H,
  RISCV::F14_H, RISCV::F15_H, RISCV::F16_H, RISCV::F17_H
}

Definition at line 12567 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV().

ArgFPR32s

const MCPhysReg ArgFPR32s[]

static

Initial value:

= {
  RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F,
  RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F
}

Definition at line 12571 of file RISCVISelLowering.cpp.

ArgFPR64s

const MCPhysReg ArgFPR64s[]

static

Initial value:

= {
  RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D,
  RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D
}

Definition at line 12575 of file RISCVISelLowering.cpp.

ArgGPRs

const MCPhysReg ArgGPRs[]

static

Initial value:

= {
  RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13,
  RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
}

Definition at line 12563 of file RISCVISelLowering.cpp.

ArgVRM2s

const MCPhysReg ArgVRM2s[]

static

Initial value:

= {RISCV::V8M2,  RISCV::V10M2, RISCV::V12M2,
                                     RISCV::V14M2, RISCV::V16M2, RISCV::V18M2,
                                     RISCV::V20M2, RISCV::V22M2}

Definition at line 12584 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

ArgVRM4s

const MCPhysReg ArgVRM4s[]

static

Initial value:

= {RISCV::V8M4, RISCV::V12M4, RISCV::V16M4,
                                     RISCV::V20M4}

Definition at line 12587 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

ArgVRM8s

const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8}

static

Definition at line 12589 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

ArgVRs

const MCPhysReg ArgVRs[]

static

Initial value:

= {
    RISCV::V8,  RISCV::V9,  RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13,
    RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19,
    RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23}

Definition at line 12580 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

ExtensionMaxWebSize

cl::opt< unsigned > ExtensionMaxWebSize(DEBUG_TYPE "-ext-max-web-size", cl::Hidden, cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion"), cl::init(18)) ( DEBUG_TYPE "-ext-max-web-size"  , cl::Hidden  , cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion")  , cl::init(18)    )

static

Referenced by combineBinOp_VLToVWBinOp_VL().

FPImmCost

cl::opt< int > FPImmCost(DEBUG_TYPE "-fpimm-cost", cl::Hidden, cl::desc("Give the maximum number of instructions that we will " "use for creating a floating-point immediate value"), cl::init(2)) ( DEBUG_TYPE "-fpimm-cost"  , cl::Hidden  , cl::desc("Give the maximum number of instructions that we will " "use for creating a floating-point immediate value")  , cl::init(2)    )

static

Referenced by llvm::RISCVTargetLowering::isFPImmLegal().

NumRepeatedDivisors

cl::opt< unsigned > NumRepeatedDivisors(DEBUG_TYPE "-fp-repeated-divisors", cl::Hidden, cl::desc("Set the minimum number of repetitions of a divisor to allow " "transformation to multiplications by the reciprocal"), cl::init(2)) ( DEBUG_TYPE "-fp-repeated-divisors"  , cl::Hidden  , cl::desc("Set the minimum number of repetitions of a divisor to allow " "transformation to multiplications by the reciprocal")  , cl::init(2)    )

static