LLVM  16.0.0git
Classes | Namespaces | Macros | Functions | Variables
RISCVISelLowering.cpp File Reference
#include "RISCVISelLowering.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVRegisterInfo.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/DiagnosticPrinter.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <optional>
#include "RISCVGenAsmMatcher.inc"
#include "RISCVGenSearchableTables.inc"
Include dependency graph for RISCVISelLowering.cpp:

Go to the source code of this file.

Classes

struct  VIDSequence
 

Namespaces

 llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
 llvm::RISCVVIntrinsicsTable
 

Macros

#define DEBUG_TYPE   "riscv-lower"
 
#define NODE_NAME_CASE(NODE)
 
#define GET_REGISTER_MATCHER
 
#define GET_RISCVVIntrinsicsTable_IMPL
 

Functions

 STATISTIC (NumTailCalls, "Number of tail calls")
 
static void translateSetCCForBranch (const SDLoc &DL, SDValue &LHS, SDValue &RHS, ISD::CondCode &CC, SelectionDAG &DAG)
 
static SDValue getVLOperand (SDValue Op)
 
static bool useRVVForFixedLengthVectorVT (MVT VT, const RISCVSubtarget &Subtarget)
 
static MVT getContainerForFixedLengthVector (const TargetLowering &TLI, MVT VT, const RISCVSubtarget &Subtarget)
 
static MVT getContainerForFixedLengthVector (SelectionDAG &DAG, MVT VT, const RISCVSubtarget &Subtarget)
 
static SDValue convertToScalableVector (EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue convertFromScalableVector (EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static MVT getMaskTypeFor (MVT VecVT)
 Return the type of the mask type suitable for masking the provided vector type. More...
 
static SDValue getAllOnesMask (MVT VecVT, SDValue VL, SDLoc DL, SelectionDAG &DAG)
 Creates an all ones mask suitable for masking a vector of type VecTy with vector length VL. More...
 
static SDValue getVLOp (uint64_t NumElts, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static std::pair< SDValue, SDValue > getDefaultVLOps (uint64_t NumElts, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static std::pair< SDValue, SDValue > getDefaultVLOps (MVT VecVT, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static std::pair< SDValue, SDValue > getDefaultScalableVLOps (MVT VecVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerFP_TO_INT_SAT (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static RISCVFPRndMode::RoundingMode matchRoundingOp (unsigned Opc)
 
static SDValue lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerFTRUNC_FCEIL_FFLOOR_FROUND (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static std::optional< uint64_t > getExactInteger (const APFloat &APF, uint32_t BitWidth)
 
static std::optional< VIDSequence > isSimpleVIDSequence (SDValue Op)
 
static SDValue matchSplatAsGather (SDValue SplatVal, MVT VT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerBUILD_VECTOR (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue splatPartsI64WithVL (const SDLoc &DL, MVT VT, SDValue Passthru, SDValue Lo, SDValue Hi, SDValue VL, SelectionDAG &DAG)
 
static SDValue splatSplitI64WithVL (const SDLoc &DL, MVT VT, SDValue Passthru, SDValue Scalar, SDValue VL, SelectionDAG &DAG)
 
static SDValue lowerScalarSplat (SDValue Passthru, SDValue Scalar, SDValue VL, MVT VT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static bool isInterleaveShuffle (ArrayRef< int > Mask, MVT VT, bool &SwapSources, const RISCVSubtarget &Subtarget)
 
static int isElementRotate (int &LoSrc, int &HiSrc, ArrayRef< int > Mask)
 Match shuffles that concatenate two vectors, rotate the concatenation, and then extract the original number of elements from the rotated result. More...
 
static SDValue lowerVECTOR_SHUFFLEAsVNSRL (const SDLoc &DL, MVT VT, MVT ContainerVT, SDValue V1, SDValue V2, SDValue TrueMask, SDValue VL, ArrayRef< int > Mask, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
 
static SDValue lowerVECTOR_SHUFFLEAsVSlidedown (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
 
static SDValue lowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerCTLZ_CTTZ_ZERO_UNDEF (SDValue Op, SelectionDAG &DAG)
 
static SDValue lowerConstant (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue getTargetNode (GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (BlockAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (ConstantPoolSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (JumpTableSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue lowerVectorIntrinsicScalars (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static MVT getLMUL1VT (MVT VT)
 
static unsigned getRVVReductionOp (unsigned ISDOpcode)
 
static std::tuple< unsigned, SDValue, SDValue > getRVVFPReductionOpAndOperands (SDValue Op, SelectionDAG &DAG, EVT EltVT)
 
static unsigned getRVVVPReductionOp (unsigned ISDOpcode)
 
static RISCVISD::NodeType getRISCVWOpcode (unsigned Opcode)
 
static SDValue customLegalizeToWOp (SDNode *N, SelectionDAG &DAG, unsigned ExtOpc=ISD::ANY_EXTEND)
 
static SDValue customLegalizeToWOpWithSExt (SDNode *N, SelectionDAG &DAG)
 
static SDValue combineBinOpToReduce (SDNode *N, SelectionDAG &DAG)
 
static SDValue transformAddShlImm (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue combineSelectAndUse (SDNode *N, SDValue Slct, SDValue OtherOp, SelectionDAG &DAG, bool AllOnes, const RISCVSubtarget &Subtarget)
 
static SDValue combineSelectAndUseCommutative (SDNode *N, SelectionDAG &DAG, bool AllOnes, const RISCVSubtarget &Subtarget)
 
static SDValue transformAddImmMulImm (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue performADDCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue combineSubOfBoolean (SDNode *N, SelectionDAG &DAG)
 
static SDValue performSUBCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue combineDeMorganOfBoolean (SDNode *N, SelectionDAG &DAG)
 
static SDValue performTRUNCATECombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue performANDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static SDValue performORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static SDValue performXORCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue performSETCCCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue performSIGN_EXTEND_INREGCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue combineBinOp_VLToVWBinOp_VL (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 Combine a binary operation to its equivalent VW or VW_W form. More...
 
static SDValue performFP_TO_INTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static SDValue performFP_TO_INT_SATCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static SDValue performBITREVERSECombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static unsigned negateFMAOpcode (unsigned Opcode, bool NegMul, bool NegAcc)
 
static SDValue performSRACombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue tryDemorganOfBooleanCondition (SDValue Cond, SelectionDAG &DAG)
 
static bool combine_CC (SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static uint64_t computeGREVOrGORC (uint64_t x, unsigned ShAmt, bool IsGORC)
 
static MachineBasicBlock * emitReadCycleWidePseudo (MachineInstr &MI, MachineBasicBlock *BB)
 
static MachineBasicBlock * emitSplitF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB)
 
static MachineBasicBlock * emitBuildPairF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB)
 
static bool isSelectPseudo (MachineInstr &MI)
 
static MachineBasicBlock * emitQuietFCMP (MachineInstr &MI, MachineBasicBlock *BB, unsigned RelOpcode, unsigned EqOpcode, const RISCVSubtarget &Subtarget)
 
static MachineBasicBlock * EmitLoweredCascadedSelect (MachineInstr &First, MachineInstr &Second, MachineBasicBlock *ThisMBB, const RISCVSubtarget &Subtarget)
 
static MachineBasicBlock * emitSelectPseudo (MachineInstr &MI, MachineBasicBlock *BB, const RISCVSubtarget &Subtarget)
 
static MachineBasicBlock * emitVFCVT_RM_MASK (MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode)
 
static MachineBasicBlock * emitVFROUND_NOEXCEPT_MASK (MachineInstr &MI, MachineBasicBlock *BB, unsigned CVTXOpc, unsigned CVTFOpc)
 
static MachineBasicBlock * emitFROUND (MachineInstr &MI, MachineBasicBlock *MBB, const RISCVSubtarget &Subtarget)
 
static bool CC_RISCVAssign2XLen (unsigned XLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
 
static unsigned allocateRVVReg (MVT ValVT, unsigned ValNo, std::optional< unsigned > FirstMaskArgument, CCState &State, const RISCVTargetLowering &TLI)
 
static bool CC_RISCV (const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
 
template<typename ArgTy >
static std::optional< unsigned > preAssignMask (const ArgTy &Args)
 
static SDValue convertLocVTToValVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget)
 
static SDValue unpackFromRegLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const ISD::InputArg &In, const RISCVTargetLowering &TLI)
 
static SDValue convertValVTToLocVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget)
 
static SDValue unpackFromMemLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
 
static SDValue unpackF64OnRV32DSoftABI (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
 
static bool CC_RISCV_FastCC (const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
 
static bool CC_RISCV_GHC (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
 
static Align getPrefTypeAlign (EVT VT, SelectionDAG &DAG)
 
static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp (unsigned XLen, AtomicRMWInst::BinOp BinOp)
 

Variables

static cl::opt< unsigned > ExtensionMaxWebSize (DEBUG_TYPE "-ext-max-web-size", cl::Hidden, cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion"), cl::init(18))
 
static cl::opt< bool > AllowSplatInVW_W (DEBUG_TYPE "-form-vw-w-with-splat", cl::Hidden, cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants"), cl::init(false))
 
static const MCPhysReg ArgGPRs []
 
static const MCPhysReg ArgFPR16s []
 
static const MCPhysReg ArgFPR32s []
 
static const MCPhysReg ArgFPR64s []
 
static const MCPhysReg ArgVRs []
 
static const MCPhysReg ArgVRM2s []
 
static const MCPhysReg ArgVRM4s []
 
static const MCPhysReg ArgVRM8s [] = {RISCV::V8M8, RISCV::V16M8}
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "riscv-lower"

Definition at line 46 of file RISCVISelLowering.cpp.

◆ GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 13517 of file RISCVISelLowering.cpp.

◆ GET_RISCVVIntrinsicsTable_IMPL

#define GET_RISCVVIntrinsicsTable_IMPL

Definition at line 13538 of file RISCVISelLowering.cpp.

◆ NODE_NAME_CASE

#define NODE_NAME_CASE (   NODE)
Value:
case RISCVISD::NODE: \
return "RISCVISD::" #NODE;

Function Documentation

◆ allocateRVVReg()

static unsigned allocateRVVReg ( MVT  ValVT,
unsigned  ValNo,
std::optional< unsigned >  FirstMaskArgument,
CCState &  State,
const RISCVTargetLowering &  TLI 
)
static

Definition at line 11283 of file RISCVISelLowering.cpp.

References llvm::CCState::AllocateReg(), ArgVRM2s, ArgVRM4s, ArgVRM8s, ArgVRs, llvm::TargetLoweringBase::getRegClassFor(), and llvm_unreachable.

Referenced by CC_RISCV(), and CC_RISCV_FastCC().

◆ CC_RISCV()

static bool CC_RISCV ( const DataLayout &  DL,
RISCVABI::ABI  ABI,
unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState &  State,
bool  IsFixed,
bool  IsRet,
Type *  OrigTy,
const RISCVTargetLowering &  TLI,
std::optional< unsigned >  FirstMaskArgument 
)
static

Definition at line 11305 of file RISCVISelLowering.cpp.

References ABI, llvm::RISCVABI::ABI_ILP32, llvm::RISCVABI::ABI_ILP32D, llvm::RISCVABI::ABI_ILP32F, llvm::RISCVABI::ABI_LP64, llvm::RISCVABI::ABI_LP64D, llvm::RISCVABI::ABI_LP64F, llvm::CCState::addLoc(), Align, llvm::CCState::AllocateReg(), allocateRVVReg(), llvm::CCState::AllocateStack(), ArgFPR16s, ArgFPR32s, ArgFPR64s, ArgGPRs, assert(), llvm::CCValAssign::BCvt, CC_RISCVAssign2XLen(), llvm::SmallVectorImpl< T >::clear(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::CCValAssign::Full, llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), llvm::CCState::getFirstUnallocated(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getPending(), llvm::CCState::getPendingArgFlags(), llvm::CCState::getPendingLocs(), llvm::CCValAssign::getReg(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getStoreSize(), llvm::RISCVTargetLowering::getSubtarget(), llvm::RISCVSubtarget::hasVInstructions(), llvm::MVT::i32, llvm::MVT::i64, llvm::CCValAssign::Indirect, llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::ISD::ArgFlagsTy::isNest(), llvm::MVT::isScalableVector(), llvm::MVT::isScalarInteger(), llvm::ISD::ArgFlagsTy::isSplit(), llvm::ISD::ArgFlagsTy::isSplitEnd(), llvm::MVT::isVector(), llvm_unreachable, size, and llvm::MaybeAlign::valueOrOne().

Referenced by llvm::RISCVTargetLowering::CanLowerReturn(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerFormalArguments(), and llvm::RISCVTargetLowering::LowerReturn().

◆ CC_RISCV_FastCC()

static bool CC_RISCV_FastCC ( const DataLayout &  DL,
RISCVABI::ABI  ABI,
unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState &  State,
bool  IsFixed,
bool  IsRet,
Type *  OrigTy,
const RISCVTargetLowering &  TLI,
std::optional< unsigned >  FirstMaskArgument 
)
static

Definition at line 11757 of file RISCVISelLowering.cpp.

References llvm::CCState::addLoc(), Align, llvm::CCState::AllocateReg(), allocateRVVReg(), llvm::CCState::AllocateStack(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), llvm::CCValAssign::getMem(), llvm::CCValAssign::getReg(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getStoreSize(), llvm::RISCVTargetLowering::getSubtarget(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::CCValAssign::Indirect, llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), and llvm::MaybeAlign::valueOrOne().

Referenced by llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerFormalArguments().

◆ CC_RISCV_GHC()

static bool CC_RISCV_GHC ( unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState &  State 
)
static

Definition at line 11859 of file RISCVISelLowering.cpp.

References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::MVT::f32, llvm::MVT::f64, llvm::CCValAssign::getReg(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::ArgFlagsTy::isNest(), and llvm::report_fatal_error().

Referenced by llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerFormalArguments().

◆ CC_RISCVAssign2XLen()

static bool CC_RISCVAssign2XLen ( unsigned  XLen,
CCState &  State,
CCValAssign  VA1,
ISD::ArgFlagsTy  ArgFlags1,
unsigned  ValNo2,
MVT  ValVT2,
MVT  LocVT2,
ISD::ArgFlagsTy  ArgFlags2 
)
static

Definition at line 11246 of file RISCVISelLowering.cpp.

References llvm::CCState::addLoc(), Align, llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), ArgGPRs, llvm::CCValAssign::Full, llvm::CCValAssign::getLocVT(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getReg(), llvm::CCValAssign::getValNo(), llvm::CCValAssign::getValVT(), and llvm::max().

Referenced by CC_RISCV().

◆ combine_CC()

static bool combine_CC ( SDValue &  LHS,
SDValue &  RHS,
SDValue &  CC,
const SDLoc &  DL,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 9453 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, CC, llvm::ISD::Constant, DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::RISCVSubtarget::getXLenVT(), llvm::Value::hasOneUse(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::isPowerOf2_64(), LHS, llvm::Log2_64(), llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), RHS, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SHL, llvm::ISD::SRL, translateSetCCForBranch(), tryDemorganOfBooleanCondition(), and llvm::ISD::XOR.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ combineBinOp_VLToVWBinOp_VL()

static SDValue combineBinOp_VLToVWBinOp_VL ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI 
)
static

Combine a binary operation to its equivalent VW or VW_W form.

The supported combines are: add_vl -> vwadd(u) | vwadd(u)_w sub_vl -> vwsub(u) | vwsub(u)_w mul_vl -> vwmul(u) | vwmul_su vwadd_w(u) -> vwadd(u) vwub_w(u) -> vwadd(u)

Definition at line 9034 of file RISCVISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SmallVectorImpl< T >::emplace_back(), ExtensionMaxWebSize, isCommutative(), LHS, N, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SmallVectorImpl< T >::reserve(), RHS, and std::swap().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ combineBinOpToReduce()

static SDValue combineBinOpToReduce ( SDNode *  N,
SelectionDAG &  DAG 
)
static

Definition at line 7963 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::EVT::isInteger(), llvm::isNeutralConstant(), llvm::isNullConstant(), llvm::isOneConstant(), llvm_unreachable, N, llvm::ISD::OR, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::RISCVISD::VECREDUCE_ADD_VL, llvm::RISCVISD::VECREDUCE_AND_VL, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::RISCVISD::VECREDUCE_OR_VL, llvm::RISCVISD::VECREDUCE_SMAX_VL, llvm::RISCVISD::VECREDUCE_SMIN_VL, llvm::RISCVISD::VECREDUCE_UMAX_VL, llvm::RISCVISD::VECREDUCE_UMIN_VL, llvm::RISCVISD::VECREDUCE_XOR_VL, llvm::RISCVISD::VFMV_S_F_VL, llvm::RISCVISD::VMV_S_X_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::ISD::XOR.

Referenced by performADDCombine(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performORCombine(), and performXORCombine().

◆ combineDeMorganOfBoolean()

static SDValue combineDeMorganOfBoolean ( SDNode *  N,
SelectionDAG &  DAG 
)
static

Definition at line 8315 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::ISD::OR, and llvm::ISD::XOR.

Referenced by performANDCombine(), and performORCombine().

◆ combineSelectAndUse()

static SDValue combineSelectAndUse ( SDNode *  N,
SDValue  Slct,
SDValue  OtherOp,
SelectionDAG &  DAG,
bool  AllOnes,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 8117 of file RISCVISelLowering.cpp.

References llvm::tgtok::FalseVal, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::hasShortForwardBranchOpt(), llvm::isAllOnesConstant(), llvm::isNullConstant(), llvm::EVT::isVector(), isZeroOrAllOnes(), N, llvm::ISD::SELECT, llvm::RISCVISD::SELECT_CC, std::swap(), and llvm::tgtok::TrueVal.

Referenced by combineSelectAndUseCommutative(), and performSUBCombine().

◆ combineSelectAndUseCommutative()

static SDValue combineSelectAndUseCommutative ( SDNode *  N,
SelectionDAG &  DAG,
bool  AllOnes,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 8167 of file RISCVISelLowering.cpp.

References combineSelectAndUse(), and N.

Referenced by performADDCombine(), performANDCombine(), performORCombine(), and performXORCombine().

◆ combineSubOfBoolean()

static SDValue combineSubOfBoolean ( SDNode *  N,
SelectionDAG &  DAG 
)
static

Definition at line 8260 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::EVT::isInteger(), llvm::ISD::isIntEqualitySetCC(), llvm::isOneConstant(), llvm::APInt::isSignedIntN(), N, llvm::ISD::SETCC, and llvm::ISD::XOR.

Referenced by performSUBCombine().

◆ computeGREVOrGORC()

static uint64_t computeGREVOrGORC ( uint64_t  x,
unsigned  ShAmt,
bool  IsGORC 
)
static

Definition at line 10257 of file RISCVISelLowering.cpp.

References llvm::BitmaskEnumDetail::Mask(), Shift, and x.

Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode().

◆ convertFromScalableVector()

static SDValue convertFromScalableVector ( EVT  VT,
SDValue  V,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 1870 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::RISCVSubtarget::getXLenVT(), llvm::EVT::isFixedLengthVector(), and llvm::EVT::isScalableVector().

Referenced by convertLocVTToValVT(), lowerBUILD_VECTOR(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVNSRL(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), and matchSplatAsGather().

◆ convertLocVTToValVT()

static SDValue convertLocVTToValVT ( SelectionDAG &  DAG,
SDValue  Val,
const CCValAssign &  VA,
const SDLoc &  DL,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 11600 of file RISCVISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertFromScalableVector(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::RISCVISD::FMV_H_X, llvm::RISCVISD::FMV_W_X_RV64, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::i64, llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::MVT::isScalableVector(), and llvm_unreachable.

Referenced by llvm::RISCVTargetLowering::LowerCall(), and unpackFromRegLoc().

◆ convertToScalableVector()

static SDValue convertToScalableVector ( EVT  VT,
SDValue  V,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 1858 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INSERT_SUBVECTOR, llvm::EVT::isFixedLengthVector(), and llvm::EVT::isScalableVector().

Referenced by convertValVTToLocVT(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVNSRL(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), matchSplatAsGather(), and llvm::RISCVTargetLowering::ReplaceNodeResults().

◆ convertValVTToLocVT()

static SDValue convertValVTToLocVT ( SelectionDAG &  DAG,
SDValue  Val,
const CCValAssign &  VA,
const SDLoc &  DL,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 11657 of file RISCVISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertToScalableVector(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::RISCVISD::FMV_X_ANYEXTH, llvm::RISCVISD::FMV_X_ANYEXTW_RV64, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::i64, llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::EVT::isScalableVector(), and llvm_unreachable.

Referenced by llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerReturn().

◆ customLegalizeToWOp()

static SDValue customLegalizeToWOp ( SDNode *  N,
SelectionDAG &  DAG,
unsigned  ExtOpc = ISD::ANY_EXTEND 
)
static

Definition at line 7438 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), getRISCVWOpcode(), llvm::MVT::i64, N, and llvm::ISD::TRUNCATE.

Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().

◆ customLegalizeToWOpWithSExt()

static SDValue customLegalizeToWOpWithSExt ( SDNode *  N,
SelectionDAG &  DAG 
)
static

Definition at line 7451 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), llvm::MVT::i32, llvm::MVT::i64, N, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::TRUNCATE.

Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().

◆ emitBuildPairF64Pseudo()

static MachineBasicBlock* emitBuildPairF64Pseudo ( MachineInstr &  MI,
MachineBasicBlock *  BB 
)
static

Definition at line 10598 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), Align, assert(), BB, llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), llvm::HexagonInstrInfo::loadRegFromStackSlot(), MI, llvm::MachineMemOperand::MOStore, and TII.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

◆ emitFROUND()

static MachineBasicBlock* emitFROUND ( MachineInstr &  MI,
MachineBasicBlock *  MBB,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 11000 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), BB, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::MachineBasicBlock::end(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, llvm::RISCVSubtarget::is64Bit(), llvm_unreachable, MBB, MI, MRI, PHI, llvm::MachineInstr::setFlag(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

◆ EmitLoweredCascadedSelect()

static MachineBasicBlock* EmitLoweredCascadedSelect ( MachineInstr &  First,
MachineInstr &  Second,
MachineBasicBlock *  ThisMBB,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 10682 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, First, llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineOperand::getImm(), llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), PHI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

Referenced by emitSelectPseudo().

◆ emitQuietFCMP()

static MachineBasicBlock* emitQuietFCMP ( MachineInstr &  MI,
MachineBasicBlock *  BB,
unsigned  RelOpcode,
unsigned  EqOpcode,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 10645 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addReg(), BB, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::getKillRegState(), llvm::RegState::Kill, MI, MRI, llvm::MachineInstr::setFlag(), and TII.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

◆ emitReadCycleWidePseudo()

static MachineBasicBlock* emitReadCycleWidePseudo ( MachineInstr &  MI,
MachineBasicBlock *  BB 
)
static

Definition at line 10503 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), BB, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::insert(), llvm::AArch64SysReg::lookupSysRegByName(), MI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

◆ emitSelectPseudo()

static MachineBasicBlock* emitSelectPseudo ( MachineInstr &  MI,
MachineBasicBlock *  BB,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 10784 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::any_of(), BB, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), CC, llvm::MachineInstr::collectDebugValues(), llvm::SmallSet< T, N, C >::count(), DL, E, EmitLoweredCascadedSelect(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), I, llvm::SmallSet< T, N, C >::insert(), isSelectPseudo(), LHS, MI, llvm::next_nodbg(), llvm::MachineFunctionProperties::NoPHIs, PHI, llvm::MachineBasicBlock::push_back(), RHS, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

◆ emitSplitF64Pseudo()

static MachineBasicBlock* emitSplitF64Pseudo ( MachineInstr &  MI,
MachineBasicBlock *  BB 
)
static

Definition at line 10565 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), Align, assert(), BB, llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), MI, llvm::MachineMemOperand::MOLoad, llvm::HexagonInstrInfo::storeRegToStackSlot(), and TII.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

◆ emitVFCVT_RM_MASK()

static MachineBasicBlock* emitVFCVT_RM_MASK ( MachineInstr &  MI,
MachineBasicBlock *  BB,
unsigned  Opcode 
)
static

Definition at line 10918 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), BB, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::RegState::Kill, MI, MRI, llvm::MachineInstr::setFlag(), and TII.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

◆ emitVFROUND_NOEXCEPT_MASK()

static MachineBasicBlock* emitVFROUND_NOEXCEPT_MASK ( MachineInstr &  MI,
MachineBasicBlock *  BB,
unsigned  CVTXOpc,
unsigned  CVTFOpc 
)
static

Definition at line 10952 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), BB, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::RegState::Kill, MI, MRI, TII, and TRI.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

◆ getAllOnesMask()

static SDValue getAllOnesMask ( MVT  VecVT,
SDValue  VL,
SDLoc  DL,
SelectionDAG &  DAG 
)
static

Creates an all ones mask suitable for masking a vector of type VecTy with vector length VL.

Definition at line 1892 of file RISCVISelLowering.cpp.

References DL, getMaskTypeFor(), llvm::SelectionDAG::getNode(), and llvm::RISCVISD::VMSET_VL.

Referenced by getDefaultVLOps(), lowerVECTOR_SHUFFLE(), and lowerVectorIntrinsicScalars().

◆ getContainerForFixedLengthVector() [1/2]

static MVT getContainerForFixedLengthVector ( const TargetLowering &  TLI,
MVT  VT,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 1813 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::RISCVSubtarget::getELEN(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalableVectorVT(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::MVT::isFixedLengthVector(), llvm::isPowerOf2_32(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::max(), llvm::RISCV::RVVBitsPerBlock, and llvm::MVT::SimpleTy.

Referenced by llvm::RISCVTargetLowering::getContainerForFixedLengthVector().

◆ getContainerForFixedLengthVector() [2/2]

static MVT getContainerForFixedLengthVector ( SelectionDAG &  DAG,
MVT  VT,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 1847 of file RISCVISelLowering.cpp.

References llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), and llvm::SelectionDAG::getTargetLoweringInfo().

◆ getDefaultScalableVLOps()

static std::pair<SDValue, SDValue> getDefaultScalableVLOps ( MVT  VecVT,
SDLoc  DL,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 1930 of file RISCVISelLowering.cpp.

References assert(), DL, getDefaultVLOps(), and llvm::MVT::isScalableVector().

◆ getDefaultVLOps() [1/2]

static std::pair<SDValue, SDValue> getDefaultVLOps ( MVT  VecVT,
MVT  ContainerVT,
SDLoc  DL,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 1916 of file RISCVISelLowering.cpp.

References assert(), DL, getAllOnesMask(), getDefaultVLOps(), llvm::SelectionDAG::getRegister(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isScalableVector(), and llvm::BitmaskEnumDetail::Mask().

◆ getDefaultVLOps() [2/2]

static std::pair<SDValue, SDValue> getDefaultVLOps ( uint64_t  NumElts,
MVT  ContainerVT,
SDLoc  DL,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 1904 of file RISCVISelLowering.cpp.

References assert(), DL, getAllOnesMask(), getVLOp(), llvm::MVT::isScalableVector(), and llvm::BitmaskEnumDetail::Mask().

Referenced by getDefaultScalableVLOps(), getDefaultVLOps(), lowerBUILD_VECTOR(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), matchSplatAsGather(), and llvm::RISCVTargetLowering::ReplaceNodeResults().

◆ getExactInteger()

static std::optional<uint64_t> getExactInteger ( const APFloat &  APF,
uint32_t  BitWidth 
)
static

Definition at line 2211 of file RISCVISelLowering.cpp.

References llvm::BitWidth, llvm::APFloat::convertToInteger(), llvm::APInt::extractBitsAsZExtValue(), llvm::APFloat::isNegative(), llvm::APFloatBase::opInvalidOp, and llvm::TowardZero.

Referenced by isSimpleVIDSequence().

◆ getIntrinsicForMaskedAtomicRMWBinOp()

static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp ( unsigned  XLen,
AtomicRMWInst::BinOp  BinOp 
)
static

Definition at line 13099 of file RISCVISelLowering.cpp.

References llvm::AtomicRMWInst::Add, llvm_unreachable, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, and llvm::AtomicRMWInst::Xchg.

Referenced by llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic().

◆ getLMUL1VT()

static MVT getLMUL1VT ( MVT  VT)
static

Definition at line 5685 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::getScalableVectorVT(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), and llvm::RISCV::RVVBitsPerBlock.

◆ getMaskTypeFor()

static MVT getMaskTypeFor ( MVT  VecVT)
static

Return the type of the mask type suitable for masking the provided vector type.

This is simply an i1 element type vector of the same (possibly scalable) length.

Definition at line 1884 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::MVT::i1, and llvm::MVT::isVector().

Referenced by getAllOnesMask(), and llvm::RISCVTargetLowering::PerformDAGCombine().

◆ getPrefTypeAlign()

static Align getPrefTypeAlign ( EVT  VT,
SelectionDAG &  DAG 
)
static

Definition at line 12137 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), and llvm::EVT::getTypeForEVT().

Referenced by llvm::RISCVTargetLowering::LowerCall().

◆ getRISCVWOpcode()

static RISCVISD::NodeType getRISCVWOpcode ( unsigned  Opcode)
static

Definition at line 7410 of file RISCVISelLowering.cpp.

References llvm::RISCVISD::DIVUW, llvm::RISCVISD::DIVW, llvm_unreachable, llvm::RISCVISD::REMUW, llvm::RISCVISD::ROLW, llvm::RISCVISD::RORW, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::RISCVISD::SLLW, llvm::ISD::SRA, llvm::RISCVISD::SRAW, llvm::ISD::SRL, llvm::RISCVISD::SRLW, llvm::ISD::UDIV, and llvm::ISD::UREM.

Referenced by customLegalizeToWOp().

◆ getRVVFPReductionOpAndOperands()

static std::tuple<unsigned, SDValue, SDValue> getRVVFPReductionOpAndOperands ( SDValue  Op,
SelectionDAG &  DAG,
EVT  EltVT 
)
static

Definition at line 5852 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getNeutralElement(), llvm::ISD::getVecReduceBaseOpcode(), llvm_unreachable, llvm::ISD::VECREDUCE_FADD, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::ISD::VECREDUCE_FMAX, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::ISD::VECREDUCE_FMIN, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::ISD::VECREDUCE_SEQ_FADD, and llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL.

◆ getRVVReductionOp()

static unsigned getRVVReductionOp ( unsigned  ISDOpcode)
static

Definition at line 5693 of file RISCVISelLowering.cpp.

References llvm_unreachable, llvm::ISD::VECREDUCE_ADD, llvm::RISCVISD::VECREDUCE_ADD_VL, llvm::ISD::VECREDUCE_AND, llvm::RISCVISD::VECREDUCE_AND_VL, llvm::ISD::VECREDUCE_OR, llvm::RISCVISD::VECREDUCE_OR_VL, llvm::ISD::VECREDUCE_SMAX, llvm::RISCVISD::VECREDUCE_SMAX_VL, llvm::ISD::VECREDUCE_SMIN, llvm::RISCVISD::VECREDUCE_SMIN_VL, llvm::ISD::VECREDUCE_UMAX, llvm::RISCVISD::VECREDUCE_UMAX_VL, llvm::ISD::VECREDUCE_UMIN, llvm::RISCVISD::VECREDUCE_UMIN_VL, llvm::ISD::VECREDUCE_XOR, and llvm::RISCVISD::VECREDUCE_XOR_VL.

◆ getRVVVPReductionOp()

static unsigned getRVVVPReductionOp ( unsigned  ISDOpcode)
static

Definition at line 5909 of file RISCVISelLowering.cpp.

References llvm_unreachable, llvm::RISCVISD::VECREDUCE_ADD_VL, llvm::RISCVISD::VECREDUCE_AND_VL, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::RISCVISD::VECREDUCE_OR_VL, llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL, llvm::RISCVISD::VECREDUCE_SMAX_VL, llvm::RISCVISD::VECREDUCE_SMIN_VL, llvm::RISCVISD::VECREDUCE_UMAX_VL, llvm::RISCVISD::VECREDUCE_UMIN_VL, and llvm::RISCVISD::VECREDUCE_XOR_VL.

◆ getTargetNode() [1/4]

static SDValue getTargetNode ( BlockAddressSDNode *  N,
SDLoc  DL,
EVT  Ty,
SelectionDAG &  DAG,
unsigned  Flags 
)
static

Definition at line 4210 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getTargetBlockAddress(), and N.

◆ getTargetNode() [2/4]

static SDValue getTargetNode ( ConstantPoolSDNode *  N,
SDLoc  DL,
EVT  Ty,
SelectionDAG &  DAG,
unsigned  Flags 
)
static

Definition at line 4216 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getTargetConstantPool(), and N.

◆ getTargetNode() [3/4]

static SDValue getTargetNode ( GlobalAddressSDNode *  N,
SDLoc  DL,
EVT  Ty,
SelectionDAG &  DAG,
unsigned  Flags 
)
static

Definition at line 4205 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getTargetGlobalAddress(), and N.

◆ getTargetNode() [4/4]

static SDValue getTargetNode ( JumpTableSDNode *  N,
SDLoc  DL,
EVT  Ty,
SelectionDAG &  DAG,
unsigned  Flags 
)
static

Definition at line 4222 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getTargetJumpTable(), and N.

◆ getVLOp()

static SDValue getVLOp ( uint64_t  NumElts,
SDLoc  DL,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 1898 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), and llvm::RISCVSubtarget::getXLenVT().

Referenced by getDefaultVLOps().

◆ getVLOperand()

static SDValue getVLOperand ( SDValue  Op)
static

Definition at line 1728 of file RISCVISelLowering.cpp.

References assert(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::VLOperand.

Referenced by lowerVectorIntrinsicScalars().

◆ isElementRotate()

static int isElementRotate ( int &  LoSrc,
int &  HiSrc,
ArrayRef< int >  Mask 
)
static

Match shuffles that concatenate two vectors, rotate the concatenation, and then extract the original number of elements from the rotated result.

This is equivalent to vector.splice or X86's PALIGNR instruction. The returned rotation amount is for a rotate right, where elements move from higher elements to lower elements. LoSrc indicates the first source vector of the rotate or -1 for undef. HiSrc indicates the second vector of the rotate or -1 for undef. At least one of LoSrc and HiSrc will be 0 or 1 if a rotation is found.

NOTE: We talk about rotate to the right which matches how bit shift and rotate instructions are described where LSBs are on the right, but LLVM IR and the table below write vectors with the lowest elements on the left.

Definition at line 2857 of file RISCVISelLowering.cpp.

References assert(), i, M, and llvm::BitmaskEnumDetail::Mask().

Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal(), and lowerVECTOR_SHUFFLE().

◆ isInterleaveShuffle()

static bool isInterleaveShuffle ( ArrayRef< int >  Mask,
MVT  VT,
bool &  SwapSources,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 2803 of file RISCVISelLowering.cpp.

References assert(), llvm::RISCVSubtarget::getELEN(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorNumElements(), i, and llvm::BitmaskEnumDetail::Mask().

Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal(), and lowerVECTOR_SHUFFLE().

◆ isSelectPseudo()

static bool isSelectPseudo ( MachineInstr &  MI)
static

Definition at line 10633 of file RISCVISelLowering.cpp.

References MI.

Referenced by emitSelectPseudo().

◆ isSimpleVIDSequence()

static std::optional<VIDSequence> isSimpleVIDSequence ( SDValue  Op)
static

Definition at line 2239 of file RISCVISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, getExactInteger(), and llvm::SignExtend64().

Referenced by lowerBUILD_VECTOR().

◆ lowerBUILD_VECTOR()

static SDValue lowerBUILD_VECTOR ( SDValue  Op,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 2378 of file RISCVISelLowering.cpp.

References llvm::abs(), llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::tgtok::Bits, llvm::MVT::bitsLE(), llvm::MVT::changeVectorElementType(), llvm::MVT::changeVectorElementTypeToInteger(), convertFromScalableVector(), llvm::count_if(), llvm::divideCeil(), DL, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::RISCVSubtarget::getELEN(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplatBuildVector(), llvm::getSplatValue(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::insert(), llvm::ISD::INSERT_VECTOR_ELT, llvm::RISCVSubtarget::is64Bit(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), llvm::isPowerOf2_32(), llvm::isPowerOf2_64(), isSimpleVIDSequence(), llvm::SDValue::isUndef(), llvm::Log2_32(), llvm::Log2_64(), llvm::BitmaskEnumDetail::Mask(), matchSplatAsGather(), llvm::max(), llvm::min(), llvm::ISD::MUL, llvm::ISD::SETNE, llvm::ISD::SHL, llvm::SelectionDAG::shouldOptForSize(), llvm::ISD::SINT_TO_FP, llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::size(), llvm::ISD::SRL, llvm::ISD::SUB, llvm::transform(), llvm::MVT::v1i8, llvm::MVT::v8i1, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VID_VL, llvm::RISCVISD::VMCLR_VL, llvm::RISCVISD::VMSET_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::ISD::VSELECT.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

◆ lowerConstant()

static SDValue lowerConstant ( SDValue  Op,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 3548 of file RISCVISelLowering.cpp.

References assert(), llvm::RISCVMatInt::generateInstSeq(), llvm::RISCVSubtarget::getMaxBuildIntsCost(), llvm::MVT::i64, llvm::RISCVMatInt::Imm, and llvm::RISCVSubtarget::useConstantPoolForLargeInts().

Referenced by llvm::RISCVTargetLowering::LowerOperation().

◆ lowerCTLZ_CTTZ_ZERO_UNDEF()

static SDValue lowerCTLZ_CTTZ_ZERO_UNDEF ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 3440 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::LegacyLegalizeActions::Bitcast, llvm::MVT::changeVectorElementTypeToInteger(), llvm::ISD::CTTZ_ZERO_UNDEF, DL, llvm::MVT::f32, llvm::MVT::f64, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::TargetLoweringBase::isTypeLegal(), Shift, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::TRUNCATE, and llvm::ISD::UINT_TO_FP.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

◆ lowerFP_TO_INT_SAT()

static SDValue lowerFP_TO_INT_SAT ( SDValue  Op,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 1949 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::RISCVISD::FCVT_W_RV64, llvm::RISCVISD::FCVT_WU_RV64, llvm::RISCVISD::FCVT_X, llvm::RISCVISD::FCVT_XU, llvm::ISD::FP_EXTEND, llvm::RISCVISD::FP_EXTEND_VL, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::RISCVSubtarget::hasStdExtZfh(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), llvm::BitmaskEnumDetail::Mask(), llvm::RISCVFPRndMode::RTZ, llvm::RISCVISD::SETCC_VL, llvm::ISD::SETUO, llvm::RISCVISD::VFCVT_RTZ_X_F_VL, llvm::RISCVISD::VFCVT_RTZ_XU_F_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::RISCVISD::VSELECT_VL.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

◆ lowerFTRUNC_FCEIL_FFLOOR_FROUND()

static SDValue lowerFTRUNC_FCEIL_FFLOOR_FROUND ( SDValue  Op,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 2178 of file RISCVISelLowering.cpp.

References llvm::lltok::APFloat, llvm::APFloat::convertFromAPInt(), DL, llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::RISCVISD::FROUND, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isVector(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), and llvm::SelectionDAG::shouldOptForSize().

Referenced by llvm::RISCVTargetLowering::LowerOperation().

◆ lowerScalarSplat()

static SDValue lowerScalarSplat ( SDValue  Passthru,
SDValue  Scalar,
SDValue  VL,
MVT  VT,
SDLoc  DL,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 2759 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::isFloatingPoint(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::SDValue::isUndef(), llvm::ISD::SIGN_EXTEND, splatSplitI64WithVL(), llvm::RISCVISD::VFMV_S_F_VL, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_S_X_VL, and llvm::RISCVISD::VMV_V_X_VL.

Referenced by lowerVECTOR_SHUFFLE().

◆ lowerVECTOR_SHUFFLE()

static SDValue lowerVECTOR_SHUFFLE ( SDValue  Op,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 3075 of file RISCVISelLowering.cpp.

References llvm::RISCVISD::ADD_VL, llvm::all_of(), assert(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::begin(), llvm::MVT::bitsGT(), llvm::MVT::changeTypeToInteger(), llvm::MVT::changeVectorElementType(), llvm::ISD::CONCAT_VECTORS, convertFromScalableVector(), convertToScalableVector(), DL, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::TypeSize::Fixed(), llvm::SelectionDAG::getAllOnesConstant(), getAllOnesMask(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtLoad(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getFreeze(), llvm::MVT::getHalfNumVectorElementsVT(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getScalarType(), llvm::SDValue::getSimpleValueType(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getSplatValue(), llvm::MVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i1, llvm::MVT::i16, int, llvm::ISD::INTRINSIC_W_CHAIN, isElementRotate(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), isInterleaveShuffle(), llvm::ISD::isNormalLoad(), llvm::ShuffleVectorSDNode::isSplat(), llvm::SelectionDAG::isSplatValue(), llvm::SDValue::isUndef(), lowerScalarSplat(), lowerVECTOR_SHUFFLEAsVNSRL(), lowerVECTOR_SHUFFLEAsVSlidedown(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::BitmaskEnumDetail::Mask(), llvm::MVT::Other, llvm::ISD::SEXTLOAD, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::size(), std::swap(), llvm::NVPTX::PTXLdStInstCode::V2, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_V_X_VL, llvm::RISCVISD::VRGATHER_VV_VL, llvm::RISCVISD::VRGATHER_VX_VL, llvm::RISCVISD::VRGATHEREI16_VV_VL, llvm::ISD::VSELECT, llvm::RISCVISD::VSLIDEDOWN_VL, llvm::RISCVISD::VSLIDEUP_VL, llvm::RISCVISD::VWADDU_VL, and llvm::RISCVISD::VWMULU_VL.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

◆ lowerVECTOR_SHUFFLEAsVNSRL()

static SDValue lowerVECTOR_SHUFFLEAsVNSRL ( const SDLoc &  DL,
MVT  VT,
MVT  ContainerVT,
SDValue  V1,
SDValue  V2,
SDValue  TrueMask,
SDValue  VL,
ArrayRef< int >  Mask,
const RISCVSubtarget &  Subtarget,
SelectionDAG &  DAG 
)
static

Definition at line 2923 of file RISCVISelLowering.cpp.

References convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::RISCVSubtarget::getELEN(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), i, llvm::BitmaskEnumDetail::Mask(), Shift, llvm::NVPTX::PTXLdStInstCode::V2, llvm::RISCVISD::VMV_V_X_VL, and llvm::RISCVISD::VNSRL_VL.

Referenced by lowerVECTOR_SHUFFLE().

◆ lowerVECTOR_SHUFFLEAsVSlidedown()

static SDValue lowerVECTOR_SHUFFLEAsVSlidedown ( const SDLoc &  DL,
MVT  VT,
SDValue  V1,
SDValue  V2,
ArrayRef< int >  Mask,
const RISCVSubtarget &  Subtarget,
SelectionDAG &  DAG 
)
static

Definition at line 3010 of file RISCVISelLowering.cpp.

References convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), i, llvm::BitmaskEnumDetail::Mask(), llvm::NVPTX::PTXLdStInstCode::V2, and llvm::RISCVISD::VSLIDEDOWN_VL.

Referenced by lowerVECTOR_SHUFFLE().

◆ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()

static SDValue lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND ( SDValue  Op,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 2077 of file RISCVISelLowering.cpp.

References llvm::lltok::APFloat, assert(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::APFloat::convertFromAPInt(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::RISCVISD::FABS_VL, llvm::ISD::FCEIL, llvm::RISCVISD::FCOPYSIGN_VL, llvm::ISD::FFLOOR, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FTRUNC, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstantFP(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i1, llvm::RISCVFPRndMode::Invalid, llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), llvm_unreachable, llvm::BitmaskEnumDetail::Mask(), matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), llvm::RISCVISD::SETCC_VL, llvm::ISD::SETOLT, llvm::RISCVISD::SINT_TO_FP_VL, llvm::RISCVISD::VFCVT_RM_X_F_VL, llvm::RISCVISD::VFCVT_RTZ_X_F_VL, llvm::RISCVISD::VFCVT_X_F_VL, llvm::RISCVISD::VFMV_V_F_VL, and llvm::RISCVISD::VFROUND_NOEXCEPT_VL.

Referenced by lowerFTRUNC_FCEIL_FFLOOR_FROUND(), and llvm::RISCVTargetLowering::LowerOperation().

◆ lowerVectorIntrinsicScalars()

static SDValue lowerVectorIntrinsicScalars ( SDValue  Op,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 5239 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLT(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::RISCVTargetLowering::computeVLMAX(), DL, llvm::RISCVVType::encodeSEW(), llvm::ISD::EXTRACT_ELEMENT, getAllOnesMask(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::LinearPolySize< LeafTy >::getKnownMinValue(), llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealMaxVLen(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), getVLOperand(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::hasScalarOperand(), llvm::RISCVSubtarget::hasVInstructions(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::MVT::isScalarInteger(), llvm::SDValue::isUndef(), llvm::XCoreISD::LMUL, llvm::BitmaskEnumDetail::Mask(), Operands, llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::ScalarOperand, SEW, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, splatSplitI64WithVL(), llvm::RISCVII::TAIL_AGNOSTIC, llvm::ISD::TRUNCATE, llvm::RISCVISD::VP_MERGE_VL, llvm::RISCVISD::VSELECT_VL, llvm::RISCVISD::VSLIDE1DOWN_VL, and llvm::RISCVISD::VSLIDE1UP_VL.

◆ matchRoundingOp()

static RISCVFPRndMode::RoundingMode matchRoundingOp ( unsigned  Opc)
static

Definition at line 2048 of file RISCVISelLowering.cpp.

References llvm::RISCVFPRndMode::DYN, llvm::ISD::FCEIL, llvm::ISD::FFLOOR, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FTRUNC, llvm::RISCVFPRndMode::Invalid, llvm::RISCVFPRndMode::RDN, llvm::RISCVFPRndMode::RMM, llvm::RISCVFPRndMode::RNE, llvm::RISCVFPRndMode::RTZ, and llvm::RISCVFPRndMode::RUP.

Referenced by lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), performFP_TO_INT_SATCombine(), and performFP_TO_INTCombine().

◆ matchSplatAsGather()

static SDValue matchSplatAsGather ( SDValue  SplatVal,
MVT  VT,
const SDLoc &  DL,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 2345 of file RISCVISelLowering.cpp.

References convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i1, llvm::MVT::isFixedLengthVector(), llvm::BitmaskEnumDetail::Mask(), and llvm::RISCVISD::VRGATHER_VX_VL.

Referenced by lowerBUILD_VECTOR(), and llvm::RISCVTargetLowering::PerformDAGCombine().

◆ negateFMAOpcode()

static unsigned negateFMAOpcode ( unsigned  Opcode,
bool  NegMul,
bool  NegAcc 
)
static

Definition at line 9250 of file RISCVISelLowering.cpp.

References assert(), llvm_unreachable, llvm::RISCVISD::VFMADD_VL, llvm::RISCVISD::VFMSUB_VL, llvm::RISCVISD::VFNMADD_VL, and llvm::RISCVISD::VFNMSUB_VL.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ performADDCombine()

static SDValue performADDCombine ( SDNode *  N,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 8246 of file RISCVISelLowering.cpp.

References combineBinOpToReduce(), combineSelectAndUseCommutative(), N, transformAddImmMulImm(), and transformAddShlImm().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ performANDCombine()

static SDValue performANDCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 8382 of file RISCVISelLowering.cpp.

References llvm::And, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, combineBinOpToReduce(), combineDeMorganOfBoolean(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::hasStdExtZbs(), llvm::MVT::i32, llvm::MVT::i64, llvm::RISCVSubtarget::is64Bit(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::isOneConstant(), N, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ performBITREVERSECombine()

static SDValue performBITREVERSECombine ( SDNode *  N,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 9230 of file RISCVISelLowering.cpp.

References assert(), llvm::RISCVISD::BREV8, llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::hasStdExtZbkb(), llvm::isPowerOf2_32(), llvm::EVT::isScalarInteger(), and N.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ performFP_TO_INT_SATCombine()

static SDValue performFP_TO_INT_SATCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 9171 of file RISCVISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::MVT::f16, llvm::RISCVISD::FCVT_W_RV64, llvm::RISCVISD::FCVT_WU_RV64, llvm::RISCVISD::FCVT_X, llvm::RISCVISD::FCVT_XU, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::RISCVSubtarget::hasStdExtZfh(), llvm::MVT::i32, llvm::MVT::i64, llvm::RISCVFPRndMode::Invalid, llvm::TargetLoweringBase::isTypeLegal(), matchRoundingOp(), N, and llvm::ISD::SETUO.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ performFP_TO_INTCombine()

static SDValue performFP_TO_INTCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 9124 of file RISCVISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::MVT::f16, llvm::RISCVISD::FCVT_W_RV64, llvm::RISCVISD::FCVT_WU_RV64, llvm::RISCVISD::FCVT_X, llvm::RISCVISD::FCVT_XU, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasStdExtZfh(), llvm::MVT::i32, llvm::RISCVFPRndMode::Invalid, llvm::TargetLoweringBase::isTypeLegal(), matchRoundingOp(), N, and llvm::ISD::TRUNCATE.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ performORCombine()

static SDValue performORCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 8418 of file RISCVISelLowering.cpp.

References combineBinOpToReduce(), combineDeMorganOfBoolean(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), and N.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ performSETCCCombine()

static SDValue performSETCCCombine ( SDNode *  N,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 8461 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, C1, Cond, llvm::SelectionDAG::getBoolConstant(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, llvm::RISCVSubtarget::is64Bit(), llvm::ISD::isIntEqualitySetCC(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::ISD::SETNE, and llvm::ISD::SIGN_EXTEND_INREG.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ performSIGN_EXTEND_INREGCombine()

static SDValue performSIGN_EXTEND_INREGCombine ( SDNode *  N,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 8508 of file RISCVISelLowering.cpp.

References llvm::RISCVISD::FMV_X_ANYEXTH, llvm::RISCVISD::FMV_X_SIGNEXTH, llvm::SelectionDAG::getNode(), llvm::MVT::i16, and N.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ performSRACombine()

static SDValue performSRACombine ( SDNode *  N,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 9282 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::APInt::countTrailingZeros(), DL, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, llvm::tgtok::In, llvm::RISCVSubtarget::is64Bit(), llvm::APInt::lshr(), N, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SUB, and llvm::SDNode::uses().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ performSUBCombine()

static SDValue performSUBCombine ( SDNode *  N,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 8300 of file RISCVISelLowering.cpp.

References combineSelectAndUse(), combineSubOfBoolean(), and N.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ performTRUNCATECombine()

static SDValue performTRUNCATECombine ( SDNode *  N,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 8359 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::hasStdExtZbs(), llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i64, llvm::RISCVSubtarget::is64Bit(), N, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ performXORCombine()

static SDValue performXORCombine ( SDNode *  N,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 8434 of file RISCVISelLowering.cpp.

References combineBinOpToReduce(), combineSelectAndUseCommutative(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::i64, llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::TargetLoweringBase::isOperationLegal(), N, llvm::RISCVISD::ROLW, llvm::ISD::ROTL, and llvm::RISCVISD::SLLW.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ preAssignMask()

template<typename ArgTy >
static std::optional<unsigned> preAssignMask ( const ArgTy &  Args)
static

Definition at line 11531 of file RISCVISelLowering.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Key::Args, llvm::enumerate(), llvm::MVT::getVectorElementType(), llvm::MVT::i1, and llvm::MVT::isVector().

Referenced by llvm::RISCVTargetLowering::CanLowerReturn().

◆ splatPartsI64WithVL()

static SDValue splatPartsI64WithVL ( const SDLoc &  DL,
MVT  VT,
SDValue  Passthru,
SDValue  Lo,
SDValue  Hi,
SDValue  VL,
SelectionDAG &  DAG 
)
static

Definition at line 2710 of file RISCVISelLowering.cpp.

References llvm::ISD::BITCAST, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::MVT::i32, llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, and llvm::RISCVISD::VMV_V_X_VL.

Referenced by splatSplitI64WithVL().

◆ splatSplitI64WithVL()

static SDValue splatSplitI64WithVL ( const SDLoc &  DL,
MVT  VT,
SDValue  Passthru,
SDValue  Scalar,
SDValue  VL,
SelectionDAG &  DAG 
)
static

Definition at line 2745 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::MVT::i64, and splatPartsI64WithVL().

Referenced by lowerScalarSplat(), and lowerVectorIntrinsicScalars().

◆ STATISTIC()

STATISTIC ( NumTailCalls  ,
"Number of tail calls"   
)

◆ transformAddImmMulImm()

static SDValue transformAddImmMulImm ( SDNode *  N,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 8197 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, C1, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::EVT::isVector(), llvm::ISD::MUL, and N.

Referenced by performADDCombine().

◆ transformAddShlImm()

static SDValue transformAddShlImm ( SDNode *  N,
SelectionDAG &  DAG,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 8061 of file RISCVISelLowering.cpp.

References llvm::abs(), llvm::ISD::ADD, llvm::tgtok::Bits, C1, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::RISCVSubtarget::hasStdExtZba(), llvm::EVT::isVector(), llvm::min(), N, NL, and llvm::ISD::SHL.

Referenced by performADDCombine().

◆ translateSetCCForBranch()

static void translateSetCCForBranch ( const SDLoc &  DL,
SDValue &  LHS,
SDValue &  RHS,
ISD::CondCode &  CC,
SelectionDAG &  DAG 
)
static

Definition at line 1535 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, CC, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::getSetCCSwappedOperands(), llvm::Value::hasOneUse(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isPowerOf2_64(), LHS, llvm::Log2_64(), llvm::BitmaskEnumDetail::Mask(), RHS, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SHL, and std::swap().

Referenced by combine_CC().

◆ tryDemorganOfBooleanCondition()

static SDValue tryDemorganOfBooleanCondition ( SDValue  Cond,
SelectionDAG &  DAG 
)
static

Definition at line 9394 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, Cond, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::EVT::isScalarInteger(), llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETLT, std::swap(), llvm::Xor, and llvm::ISD::XOR.

Referenced by combine_CC().

◆ unpackF64OnRV32DSoftABI()

static SDValue unpackF64OnRV32DSoftABI ( SelectionDAG &  DAG,
SDValue  Chain,
const CCValAssign &  VA,
const SDLoc &  DL 
)
static

Definition at line 11717 of file RISCVISelLowering.cpp.

References llvm::MachineRegisterInfo::addLiveIn(), assert(), llvm::RISCVISD::BuildPairF64, llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::MVT::f64, llvm::SelectionDAG::getCopyFromReg(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getRegInfo(), llvm::CCValAssign::getValVT(), llvm::MVT::i32, llvm::CCValAssign::isMemLoc(), and llvm::CCValAssign::isRegLoc().

Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().

◆ unpackFromMemLoc()

static SDValue unpackFromMemLoc ( SelectionDAG &  DAG,
SDValue  Chain,
const CCValAssign &  VA,
const SDLoc &  DL 
)
static

Definition at line 11683 of file RISCVISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::CCValAssign::Full, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MVT::getIntegerVT(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::DataLayout::getPointerSizeInBits(), llvm::EVT::getStoreSize(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, llvm::EVT::isScalableVector(), llvm_unreachable, and llvm::ISD::NON_EXTLOAD.

Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().

◆ unpackFromRegLoc()

static SDValue unpackFromRegLoc ( SelectionDAG &  DAG,
SDValue  Chain,
const CCValAssign &  VA,
const SDLoc &  DL,
const ISD::InputArg &  In,
const RISCVTargetLowering &  TLI 
)
static

Definition at line 11624 of file RISCVISelLowering.cpp.

References llvm::MachineRegisterInfo::addLiveIn(), llvm::RISCVMachineFunctionInfo::addSExt32Register(), llvm::BitWidth, convertLocVTToValVT(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::Function::getArg(), llvm::SelectionDAG::getCopyFromReg(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::Type::getIntegerBitWidth(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MachineFunction::getRegInfo(), llvm::EVT::getSimpleVT(), llvm::RISCVTargetLowering::getSubtarget(), llvm::Value::getType(), llvm::tgtok::In, llvm::CCValAssign::Indirect, and llvm::Type::isIntegerTy().

Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().

◆ useRVVForFixedLengthVectorVT()

static bool useRVVForFixedLengthVectorVT ( MVT  VT,
const RISCVSubtarget &  Subtarget 
)
static

Definition at line 1741 of file RISCVISelLowering.cpp.

References assert(), llvm::divideCeil(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::RISCVSubtarget::getELEN(), llvm::MVT::getFixedSizeInBits(), llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::hasVInstructionsF16(), llvm::RISCVSubtarget::hasVInstructionsF32(), llvm::RISCVSubtarget::hasVInstructionsF64(), llvm::RISCVSubtarget::hasVInstructionsI64(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::MVT::isFixedLengthVector(), llvm::MVT::isPow2VectorType(), llvm::MVT::SimpleTy, and llvm::RISCVSubtarget::useRVVForFixedLengthVectors().

Variable Documentation

◆ AllowSplatInVW_W

cl::opt<bool> AllowSplatInVW_W(DEBUG_TYPE "-form-vw-w-with-splat", cl::Hidden, cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants"), cl::init(false))
static

◆ ArgFPR16s

const MCPhysReg ArgFPR16s[]
static
Initial value:
= {
RISCV::F10_H, RISCV::F11_H, RISCV::F12_H, RISCV::F13_H,
RISCV::F14_H, RISCV::F15_H, RISCV::F16_H, RISCV::F17_H
}

Definition at line 11220 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV().

◆ ArgFPR32s

const MCPhysReg ArgFPR32s[]
static
Initial value:
= {
RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F,
RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F
}

Definition at line 11224 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV().

◆ ArgFPR64s

const MCPhysReg ArgFPR64s[]
static
Initial value:
= {
RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D,
RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D
}

Definition at line 11228 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV().

◆ ArgGPRs

const MCPhysReg ArgGPRs[]
static
Initial value:
= {
RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13,
RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
}

Definition at line 11216 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV(), CC_RISCVAssign2XLen(), llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerFormalArguments().

◆ ArgVRM2s

const MCPhysReg ArgVRM2s[]
static
Initial value:
= {RISCV::V8M2, RISCV::V10M2, RISCV::V12M2,
RISCV::V14M2, RISCV::V16M2, RISCV::V18M2,
RISCV::V20M2, RISCV::V22M2}

Definition at line 11237 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

◆ ArgVRM4s

const MCPhysReg ArgVRM4s[]
static
Initial value:
= {RISCV::V8M4, RISCV::V12M4, RISCV::V16M4,
RISCV::V20M4}

Definition at line 11240 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

◆ ArgVRM8s

const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8}
static

Definition at line 11242 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

◆ ArgVRs

const MCPhysReg ArgVRs[]
static
Initial value:
= {
RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13,
RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19,
RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23}

Definition at line 11233 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

◆ ExtensionMaxWebSize

cl::opt<unsigned> ExtensionMaxWebSize(DEBUG_TYPE "-ext-max-web-size", cl::Hidden, cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion"), cl::init(18))
static

Referenced by combineBinOp_VLToVWBinOp_VL().

NODE
#define NODE(NodeKind)
Definition: ItaniumDemangle.h:2374
Generated on Thu Dec 8 2022 15:35:15 for LLVM by   doxygen 1.8.17