LLVM 19.0.0git
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RISCVISelLowering.cpp File Reference
#include "RISCVISelLowering.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVRegisterInfo.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/DiagnosticPrinter.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/InstructionCost.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <optional>
#include "RISCVGenAsmMatcher.inc"
#include "RISCVGenSearchableTables.inc"

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Classes

struct  VIDSequence
 

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
namespace  llvm::RISCVVIntrinsicsTable
 

Macros

#define DEBUG_TYPE   "riscv-lower"
 
#define OP_CASE(NODE)
 
#define VP_CASE(NODE)
 
#define NODE_NAME_CASE(NODE)
 
#define GET_REGISTER_MATCHER
 
#define GET_RISCVVIntrinsicsTable_IMPL
 

Functions

 STATISTIC (NumTailCalls, "Number of tail calls")
 
static void translateSetCCForBranch (const SDLoc &DL, SDValue &LHS, SDValue &RHS, ISD::CondCode &CC, SelectionDAG &DAG)
 
static SDValue getVLOperand (SDValue Op)
 
static bool useRVVForFixedLengthVectorVT (MVT VT, const RISCVSubtarget &Subtarget)
 
static MVT getContainerForFixedLengthVector (const TargetLowering &TLI, MVT VT, const RISCVSubtarget &Subtarget)
 
static MVT getContainerForFixedLengthVector (SelectionDAG &DAG, MVT VT, const RISCVSubtarget &Subtarget)
 
static SDValue convertToScalableVector (EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue convertFromScalableVector (EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static MVT getMaskTypeFor (MVT VecVT)
 Return the type of the mask type suitable for masking the provided vector type.
 
static SDValue getAllOnesMask (MVT VecVT, SDValue VL, const SDLoc &DL, SelectionDAG &DAG)
 Creates an all ones mask suitable for masking a vector of type VecTy with vector length VL.
 
static SDValue getVLOp (uint64_t NumElts, MVT ContainerVT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static std::pair< SDValue, SDValuegetDefaultScalableVLOps (MVT VecVT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static std::pair< SDValue, SDValuegetDefaultVLOps (uint64_t NumElts, MVT ContainerVT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static std::pair< SDValue, SDValuegetDefaultVLOps (MVT VecVT, MVT ContainerVT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerFP_TO_INT_SAT (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static RISCVFPRndMode::RoundingMode matchRoundingOp (unsigned Opc)
 
static SDValue lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerFTRUNC_FCEIL_FFLOOR_FROUND (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerVectorXRINT (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue getVSlidedown (SelectionDAG &DAG, const RISCVSubtarget &Subtarget, const SDLoc &DL, EVT VT, SDValue Merge, SDValue Op, SDValue Offset, SDValue Mask, SDValue VL, unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED)
 
static SDValue getVSlideup (SelectionDAG &DAG, const RISCVSubtarget &Subtarget, const SDLoc &DL, EVT VT, SDValue Merge, SDValue Op, SDValue Offset, SDValue Mask, SDValue VL, unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED)
 
static MVT getLMUL1VT (MVT VT)
 
static std::optional< uint64_tgetExactInteger (const APFloat &APF, uint32_t BitWidth)
 
static std::optional< VIDSequenceisSimpleVIDSequence (SDValue Op, unsigned EltSizeInBits)
 
static SDValue matchSplatAsGather (SDValue SplatVal, MVT VT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerBuildVectorViaDominantValues (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 Try and optimize BUILD_VECTORs with "dominant values" - these are values which constitute a large proportion of the elements.
 
static SDValue lowerBuildVectorOfConstants (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerBUILD_VECTOR (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue splatPartsI64WithVL (const SDLoc &DL, MVT VT, SDValue Passthru, SDValue Lo, SDValue Hi, SDValue VL, SelectionDAG &DAG)
 
static SDValue splatSplitI64WithVL (const SDLoc &DL, MVT VT, SDValue Passthru, SDValue Scalar, SDValue VL, SelectionDAG &DAG)
 
static SDValue lowerScalarSplat (SDValue Passthru, SDValue Scalar, SDValue VL, MVT VT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerScalarInsert (SDValue Scalar, SDValue VL, MVT VT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static bool isDeinterleaveShuffle (MVT VT, MVT ContainerVT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const RISCVSubtarget &Subtarget)
 
static bool isInterleaveShuffle (ArrayRef< int > Mask, MVT VT, int &EvenSrc, int &OddSrc, const RISCVSubtarget &Subtarget)
 Is this shuffle interleaving contiguous elements from one vector into the even elements and contiguous elements from another vector into the odd elements.
 
static int isElementRotate (int &LoSrc, int &HiSrc, ArrayRef< int > Mask)
 Match shuffles that concatenate two vectors, rotate the concatenation, and then extract the original number of elements from the rotated result.
 
static SDValue getDeinterleaveViaVNSRL (const SDLoc &DL, MVT VT, SDValue Src, bool EvenElts, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
 
static SDValue lowerVECTOR_SHUFFLEAsVSlidedown (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
 
static SDValue lowerVECTOR_SHUFFLEAsVSlideup (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
 
static SDValue lowerVECTOR_SHUFFLEAsVSlide1 (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
 Match v(f)slide1up/down idioms.
 
static SDValue getWideningInterleave (SDValue EvenV, SDValue OddV, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerBitreverseShuffle (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static bool isLegalBitRotate (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const RISCVSubtarget &Subtarget, MVT &RotateVT, unsigned &RotateAmt)
 
static SDValue lowerVECTOR_SHUFFLEAsRotate (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerShuffleViaVRegSplitting (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerConstant (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue LowerATOMIC_FENCE (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerSADDSAT_SSUBSAT (SDValue Op, SelectionDAG &DAG)
 
static SDValue lowerUADDSAT_USUBSAT (SDValue Op, SelectionDAG &DAG)
 
static SDValue lowerSADDO_SSUBO (SDValue Op, SelectionDAG &DAG)
 
static SDValue lowerSMULO (SDValue Op, SelectionDAG &DAG)
 
static SDValue lowerFMAXIMUM_FMINIMUM (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static unsigned getRISCVVLOp (SDValue Op)
 Get a RISC-V target specified VL op for a given SDNode.
 
static bool hasMergeOp (unsigned Opcode)
 Return true if a RISC-V target specified op has a merge operand.
 
static bool hasMaskOp (unsigned Opcode)
 Return true if a RISC-V target specified op has a mask operand.
 
static SDValue SplitVectorOp (SDValue Op, SelectionDAG &DAG)
 
static SDValue SplitVPOp (SDValue Op, SelectionDAG &DAG)
 
static SDValue SplitVectorReductionOp (SDValue Op, SelectionDAG &DAG)
 
static SDValue SplitStrictFPVectorOp (SDValue Op, SelectionDAG &DAG)
 
static SDValue getTargetNode (GlobalAddressSDNode *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (BlockAddressSDNode *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (ConstantPoolSDNode *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (JumpTableSDNode *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static std::optional< boolmatchSetCC (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue Val)
 
static SDValue combineSelectToBinOp (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue foldBinOpIntoSelectIfProfitable (SDNode *BO, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static std::optional< MVTgetSmallestVTForIndex (MVT VecVT, unsigned MaxIdx, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerVectorIntrinsicScalars (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerGetVectorLength (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerCttzElts (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static void promoteVCIXScalar (const SDValue &Op, SmallVectorImpl< SDValue > &Operands, SelectionDAG &DAG)
 
static void processVCIXOperands (SDValue &OrigOp, SmallVectorImpl< SDValue > &Operands, SelectionDAG &DAG)
 
static bool isValidEGW (int EGS, EVT VT, const RISCVSubtarget &Subtarget)
 
static SDValue getVCIXISDNodeWCHAIN (SDValue &Op, SelectionDAG &DAG, unsigned Type)
 
static SDValue getVCIXISDNodeVOID (SDValue &Op, SelectionDAG &DAG, unsigned Type)
 
static unsigned getRVVReductionOp (unsigned ISDOpcode)
 
static bool isNonZeroAVL (SDValue AVL)
 
static SDValue lowerReductionSeq (unsigned RVVOpcode, MVT ResVT, SDValue StartValue, SDValue Vec, SDValue Mask, SDValue VL, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 Helper to lower a reduction sequence of the form: scalar = reduce_op vec, scalar_start.
 
static std::tuple< unsigned, SDValue, SDValuegetRVVFPReductionOpAndOperands (SDValue Op, SelectionDAG &DAG, EVT EltVT, const RISCVSubtarget &Subtarget)
 
static SDValue widenVectorOpsToi8 (SDValue N, const SDLoc &DL, SelectionDAG &DAG)
 
static RISCVISD::NodeType getRISCVWOpcode (unsigned Opcode)
 
static SDValue customLegalizeToWOp (SDNode *N, SelectionDAG &DAG, unsigned ExtOpc=ISD::ANY_EXTEND)
 
static SDValue customLegalizeToWOpWithSExt (SDNode *N, SelectionDAG &DAG)
 
static unsigned getVecReduceOpcode (unsigned Opc)
 Given a binary operator, return the associative generic ISD::VECREDUCE_OP which corresponds to it.
 
static SDValue combineBinOpOfExtractToReduceTree (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 Perform two related transforms whose purpose is to incrementally recognize an explode_vector followed by scalar reduction as a vector reduction node.
 
static SDValue combineBinOpToReduce (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue transformAddShlImm (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue combineSelectAndUse (SDNode *N, SDValue Slct, SDValue OtherOp, SelectionDAG &DAG, bool AllOnes, const RISCVSubtarget &Subtarget)
 
static SDValue combineSelectAndUseCommutative (SDNode *N, SelectionDAG &DAG, bool AllOnes, const RISCVSubtarget &Subtarget)
 
static SDValue transformAddImmMulImm (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue combineBinOpOfZExt (SDNode *N, SelectionDAG &DAG)
 
static SDValue combineAddOfBooleanXor (SDNode *N, SelectionDAG &DAG)
 
static SDValue performADDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static SDValue combineSubOfBoolean (SDNode *N, SelectionDAG &DAG)
 
static SDValue performSUBCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue combineDeMorganOfBoolean (SDNode *N, SelectionDAG &DAG)
 
static SDValue performTRUNCATECombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue performANDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static SDValue combineOrOfCZERO (SDNode *N, SDValue N0, SDValue N1, SelectionDAG &DAG)
 
static SDValue performORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static SDValue performXORCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue expandMul (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static SDValue performMULCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static bool narrowIndex (SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &DAG)
 According to the property that indexed load/store instructions zero-extend their indices, try to narrow the type of index operand.
 
static SDValue performSETCCCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue performSIGN_EXTEND_INREGCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue combineBinOp_VLToVWBinOp_VL (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 Combine a binary operation to its equivalent VW or VW_W form.
 
static SDValue combineVWADDSUBWSelect (SDNode *N, SelectionDAG &DAG)
 
static SDValue performVWADDSUBW_VLCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static SDValue tryMemPairCombine (SelectionDAG &DAG, LSBaseSDNode *LSNode1, LSBaseSDNode *LSNode2, SDValue BasePtr, uint64_t Imm)
 
static SDValue performMemPairCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue performFP_TO_INTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static SDValue performFP_TO_INT_SATCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static SDValue performBITREVERSECombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static unsigned negateFMAOpcode (unsigned Opcode, bool NegMul, bool NegAcc)
 
static SDValue combineVFMADD_VLWithVFNEG_VL (SDNode *N, SelectionDAG &DAG)
 
static SDValue performVFMADD_VLCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue performSRACombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue tryDemorganOfBooleanCondition (SDValue Cond, SelectionDAG &DAG)
 
static bool combine_CC (SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue tryFoldSelectIntoOp (SDNode *N, SelectionDAG &DAG, SDValue TrueVal, SDValue FalseVal, bool Swapped)
 
static SDValue foldSelectOfCTTZOrCTLZ (SDNode *N, SelectionDAG &DAG)
 
static SDValue useInversedSetcc (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue performSELECTCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue performBUILD_VECTORCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget, const RISCVTargetLowering &TLI)
 If we have a build_vector where each lane is binop X, C, where C is a constant (but not necessarily the same constant on all lanes), form binop (build_vector x1, x2, ...), (build_vector c1, c2, c3, ..).
 
static SDValue performINSERT_VECTOR_ELTCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget, const RISCVTargetLowering &TLI)
 
static SDValue performCONCAT_VECTORSCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget, const RISCVTargetLowering &TLI)
 
static SDValue combineToVWMACC (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static bool legalizeScatterGatherIndexType (SDLoc DL, SDValue &Index, ISD::MemIndexType &IndexType, RISCVTargetLowering::DAGCombinerInfo &DCI)
 
static bool matchIndexAsShuffle (EVT VT, SDValue Index, SDValue Mask, SmallVector< int > &ShuffleMask)
 Match the index vector of a scatter or gather node as the shuffle mask which performs the rearrangement if possible.
 
static bool matchIndexAsWiderOp (EVT VT, SDValue Index, SDValue Mask, Align BaseAlign, const RISCVSubtarget &ST)
 Match the index of a gather or scatter operation as an operation with twice the element width and half the number of elements.
 
static uint64_t computeGREVOrGORC (uint64_t x, unsigned ShAmt, bool IsGORC)
 
static MachineBasicBlockemitReadCounterWidePseudo (MachineInstr &MI, MachineBasicBlock *BB)
 
static MachineBasicBlockemitSplitF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB, const RISCVSubtarget &Subtarget)
 
static MachineBasicBlockemitBuildPairF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB, const RISCVSubtarget &Subtarget)
 
static bool isSelectPseudo (MachineInstr &MI)
 
static MachineBasicBlockemitQuietFCMP (MachineInstr &MI, MachineBasicBlock *BB, unsigned RelOpcode, unsigned EqOpcode, const RISCVSubtarget &Subtarget)
 
static MachineBasicBlockEmitLoweredCascadedSelect (MachineInstr &First, MachineInstr &Second, MachineBasicBlock *ThisMBB, const RISCVSubtarget &Subtarget)
 
static MachineBasicBlockemitSelectPseudo (MachineInstr &MI, MachineBasicBlock *BB, const RISCVSubtarget &Subtarget)
 
static const RISCV::RISCVMaskedPseudoInfolookupMaskedIntrinsic (uint16_t MCOpcode, RISCVII::VLMUL LMul, unsigned SEW)
 
static MachineBasicBlockemitVFROUND_NOEXCEPT_MASK (MachineInstr &MI, MachineBasicBlock *BB, unsigned CVTXOpc)
 
static MachineBasicBlockemitFROUND (MachineInstr &MI, MachineBasicBlock *MBB, const RISCVSubtarget &Subtarget)
 
static ArrayRef< MCPhysReggetFastCCArgGPRs (const RISCVABI::ABI ABI)
 
static bool CC_RISCVAssign2XLen (unsigned XLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2, bool EABI)
 
template<typename ArgTy >
static std::optional< unsignedpreAssignMask (const ArgTy &Args)
 
static SDValue convertLocVTToValVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget)
 
static SDValue unpackFromRegLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const ISD::InputArg &In, const RISCVTargetLowering &TLI)
 
static SDValue convertValVTToLocVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget)
 
static SDValue unpackFromMemLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
 
static SDValue unpackF64OnRV32DSoftABI (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const CCValAssign &HiVA, const SDLoc &DL)
 
static Align getPrefTypeAlign (EVT VT, SelectionDAG &DAG)
 
static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp (unsigned XLen, AtomicRMWInst::BinOp BinOp)
 
static ValueuseTpOffset (IRBuilderBase &IRB, unsigned Offset)
 

Variables

static cl::opt< unsignedExtensionMaxWebSize (DEBUG_TYPE "-ext-max-web-size", cl::Hidden, cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion"), cl::init(18))
 
static cl::opt< boolAllowSplatInVW_W (DEBUG_TYPE "-form-vw-w-with-splat", cl::Hidden, cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants"), cl::init(false))
 
static cl::opt< unsignedNumRepeatedDivisors (DEBUG_TYPE "-fp-repeated-divisors", cl::Hidden, cl::desc("Set the minimum number of repetitions of a divisor to allow " "transformation to multiplications by the reciprocal"), cl::init(2))
 
static cl::opt< int > FPImmCost (DEBUG_TYPE "-fpimm-cost", cl::Hidden, cl::desc("Give the maximum number of instructions that we will " "use for creating a floating-point immediate value"), cl::init(2))
 
static cl::opt< boolRV64LegalI32 ("riscv-experimental-rv64-legal-i32", cl::ReallyHidden, cl::desc("Make i32 a legal type for SelectionDAG on RV64."))
 
static const MCPhysReg ArgFPR16s []
 
static const MCPhysReg ArgFPR32s []
 
static const MCPhysReg ArgFPR64s []
 
static const MCPhysReg ArgVRs []
 
static const MCPhysReg ArgVRM2s []
 
static const MCPhysReg ArgVRM4s []
 
static const MCPhysReg ArgVRM8s [] = {RISCV::V8M8, RISCV::V16M8}
 
static const Intrinsic::ID FixedVlsegIntrIds []
 
static const Intrinsic::ID FixedVssegIntrIds []
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "riscv-lower"

Definition at line 51 of file RISCVISelLowering.cpp.

◆ GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 21356 of file RISCVISelLowering.cpp.

◆ GET_RISCVVIntrinsicsTable_IMPL

#define GET_RISCVVIntrinsicsTable_IMPL

Definition at line 21689 of file RISCVISelLowering.cpp.

◆ NODE_NAME_CASE

#define NODE_NAME_CASE (   NODE)
Value:
case RISCVISD::NODE: \
return "RISCVISD::" #NODE;
#define NODE(NodeKind)

◆ OP_CASE

#define OP_CASE (   NODE)
Value:
case ISD::NODE: \
return RISCVISD::NODE##_VL;

◆ VP_CASE

#define VP_CASE (   NODE)
Value:
case ISD::VP_##NODE: \
return RISCVISD::NODE##_VL;

Function Documentation

◆ CC_RISCVAssign2XLen()

static bool CC_RISCVAssign2XLen ( unsigned  XLen,
CCState State,
CCValAssign  VA1,
ISD::ArgFlagsTy  ArgFlags1,
unsigned  ValNo2,
MVT  ValVT2,
MVT  LocVT2,
ISD::ArgFlagsTy  ArgFlags2,
bool  EABI 
)
static

◆ combine_CC()

static bool combine_CC ( SDValue LHS,
SDValue RHS,
SDValue CC,
const SDLoc DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ combineAddOfBooleanXor()

static SDValue combineAddOfBooleanXor ( SDNode N,
SelectionDAG DAG 
)
static

◆ combineBinOp_VLToVWBinOp_VL()

static SDValue combineBinOp_VLToVWBinOp_VL ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const RISCVSubtarget Subtarget 
)
static

Combine a binary operation to its equivalent VW or VW_W form.

The supported combines are: add | add_vl | or disjoint -> vwadd(u) | vwadd(u)_w sub | sub_vl -> vwsub(u) | vwsub(u)_w mul | mul_vl -> vwmul(u) | vwmul_su shl | shl_vl -> vwsll fadd_vl -> vfwadd | vfwadd_w fsub_vl -> vfwsub | vfwsub_w fmul_vl -> vfwmul vwadd_w(u) -> vwadd(u) vwsub_w(u) -> vwsub(u) vfwadd_w -> vfwadd vfwsub_w -> vfwsub

Definition at line 14598 of file RISCVISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorBase< Size_T >::empty(), ExtensionMaxWebSize, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), LHS, N, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SmallVectorImpl< T >::reserve(), RHS, llvm::SmallVectorBase< Size_T >::size(), and std::swap().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine(), and performVWADDSUBW_VLCombine().

◆ combineBinOpOfExtractToReduceTree()

static SDValue combineBinOpOfExtractToReduceTree ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ combineBinOpOfZExt()

static SDValue combineBinOpOfZExt ( SDNode N,
SelectionDAG DAG 
)
static

◆ combineBinOpToReduce()

static SDValue combineBinOpToReduce ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ combineDeMorganOfBoolean()

static SDValue combineDeMorganOfBoolean ( SDNode N,
SelectionDAG DAG 
)
static

◆ combineOrOfCZERO()

static SDValue combineOrOfCZERO ( SDNode N,
SDValue  N0,
SDValue  N1,
SelectionDAG DAG 
)
static

◆ combineSelectAndUse()

static SDValue combineSelectAndUse ( SDNode N,
SDValue  Slct,
SDValue  OtherOp,
SelectionDAG DAG,
bool  AllOnes,
const RISCVSubtarget Subtarget 
)
static

◆ combineSelectAndUseCommutative()

static SDValue combineSelectAndUseCommutative ( SDNode N,
SelectionDAG DAG,
bool  AllOnes,
const RISCVSubtarget Subtarget 
)
static

Definition at line 13078 of file RISCVISelLowering.cpp.

References llvm::AllOnes, combineSelectAndUse(), and N.

◆ combineSelectToBinOp()

static SDValue combineSelectToBinOp ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ combineSubOfBoolean()

static SDValue combineSubOfBoolean ( SDNode N,
SelectionDAG DAG 
)
static

◆ combineToVWMACC()

static SDValue combineToVWMACC ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ combineVFMADD_VLWithVFNEG_VL()

static SDValue combineVFMADD_VLWithVFNEG_VL ( SDNode N,
SelectionDAG DAG 
)
static

◆ combineVWADDSUBWSelect()

static SDValue combineVWADDSUBWSelect ( SDNode N,
SelectionDAG DAG 
)
static

◆ computeGREVOrGORC()

static uint64_t computeGREVOrGORC ( uint64_t  x,
unsigned  ShAmt,
bool  IsGORC 
)
static

◆ convertFromScalableVector()

static SDValue convertFromScalableVector ( EVT  VT,
SDValue  V,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ convertLocVTToValVT()

static SDValue convertLocVTToValVT ( SelectionDAG DAG,
SDValue  Val,
const CCValAssign VA,
const SDLoc DL,
const RISCVSubtarget Subtarget 
)
static

◆ convertToScalableVector()

static SDValue convertToScalableVector ( EVT  VT,
SDValue  V,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ convertValVTToLocVT()

static SDValue convertValVTToLocVT ( SelectionDAG DAG,
SDValue  Val,
const CCValAssign VA,
const SDLoc DL,
const RISCVSubtarget Subtarget 
)
static

◆ customLegalizeToWOp()

static SDValue customLegalizeToWOp ( SDNode N,
SelectionDAG DAG,
unsigned  ExtOpc = ISD::ANY_EXTEND 
)
static

◆ customLegalizeToWOpWithSExt()

static SDValue customLegalizeToWOpWithSExt ( SDNode N,
SelectionDAG DAG 
)
static

◆ emitBuildPairF64Pseudo()

static MachineBasicBlock * emitBuildPairF64Pseudo ( MachineInstr MI,
MachineBasicBlock BB,
const RISCVSubtarget Subtarget 
)
static

◆ emitFROUND()

static MachineBasicBlock * emitFROUND ( MachineInstr MI,
MachineBasicBlock MBB,
const RISCVSubtarget Subtarget 
)
static

◆ EmitLoweredCascadedSelect()

static MachineBasicBlock * EmitLoweredCascadedSelect ( MachineInstr First,
MachineInstr Second,
MachineBasicBlock ThisMBB,
const RISCVSubtarget Subtarget 
)
static

◆ emitQuietFCMP()

static MachineBasicBlock * emitQuietFCMP ( MachineInstr MI,
MachineBasicBlock BB,
unsigned  RelOpcode,
unsigned  EqOpcode,
const RISCVSubtarget Subtarget 
)
static

◆ emitReadCounterWidePseudo()

static MachineBasicBlock * emitReadCounterWidePseudo ( MachineInstr MI,
MachineBasicBlock BB 
)
static

◆ emitSelectPseudo()

static MachineBasicBlock * emitSelectPseudo ( MachineInstr MI,
MachineBasicBlock BB,
const RISCVSubtarget Subtarget 
)
static

◆ emitSplitF64Pseudo()

static MachineBasicBlock * emitSplitF64Pseudo ( MachineInstr MI,
MachineBasicBlock BB,
const RISCVSubtarget Subtarget 
)
static

◆ emitVFROUND_NOEXCEPT_MASK()

static MachineBasicBlock * emitVFROUND_NOEXCEPT_MASK ( MachineInstr MI,
MachineBasicBlock BB,
unsigned  CVTXOpc 
)
static

◆ expandMul()

static SDValue expandMul ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const RISCVSubtarget Subtarget 
)
static

◆ foldBinOpIntoSelectIfProfitable()

static SDValue foldBinOpIntoSelectIfProfitable ( SDNode BO,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ foldSelectOfCTTZOrCTLZ()

static SDValue foldSelectOfCTTZOrCTLZ ( SDNode N,
SelectionDAG DAG 
)
static

◆ getAllOnesMask()

static SDValue getAllOnesMask ( MVT  VecVT,
SDValue  VL,
const SDLoc DL,
SelectionDAG DAG 
)
static

Creates an all ones mask suitable for masking a vector of type VecTy with vector length VL.

Definition at line 2714 of file RISCVISelLowering.cpp.

References DL, getMaskTypeFor(), llvm::SelectionDAG::getNode(), and llvm::RISCVISD::VMSET_VL.

Referenced by getDefaultScalableVLOps(), getDefaultVLOps(), and lowerVectorIntrinsicScalars().

◆ getContainerForFixedLengthVector() [1/2]

static MVT getContainerForFixedLengthVector ( const TargetLowering TLI,
MVT  VT,
const RISCVSubtarget Subtarget 
)
static

◆ getContainerForFixedLengthVector() [2/2]

static MVT getContainerForFixedLengthVector ( SelectionDAG DAG,
MVT  VT,
const RISCVSubtarget Subtarget 
)
static

◆ getDefaultScalableVLOps()

static std::pair< SDValue, SDValue > getDefaultScalableVLOps ( MVT  VecVT,
const SDLoc DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ getDefaultVLOps() [1/2]

static std::pair< SDValue, SDValue > getDefaultVLOps ( MVT  VecVT,
MVT  ContainerVT,
const SDLoc DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ getDefaultVLOps() [2/2]

static std::pair< SDValue, SDValue > getDefaultVLOps ( uint64_t  NumElts,
MVT  ContainerVT,
const SDLoc DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ getDeinterleaveViaVNSRL()

static SDValue getDeinterleaveViaVNSRL ( const SDLoc DL,
MVT  VT,
SDValue  Src,
bool  EvenElts,
const RISCVSubtarget Subtarget,
SelectionDAG DAG 
)
static

◆ getExactInteger()

static std::optional< uint64_t > getExactInteger ( const APFloat APF,
uint32_t  BitWidth 
)
static

◆ getFastCCArgGPRs()

static ArrayRef< MCPhysReg > getFastCCArgGPRs ( const RISCVABI::ABI  ABI)
static

◆ getIntrinsicForMaskedAtomicRMWBinOp()

static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp ( unsigned  XLen,
AtomicRMWInst::BinOp  BinOp 
)
static

◆ getLMUL1VT()

static MVT getLMUL1VT ( MVT  VT)
static

◆ getMaskTypeFor()

static MVT getMaskTypeFor ( MVT  VecVT)
static

Return the type of the mask type suitable for masking the provided vector type.

This is simply an i1 element type vector of the same (possibly scalable) length.

Definition at line 2706 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), and llvm::MVT::isVector().

◆ getPrefTypeAlign()

static Align getPrefTypeAlign ( EVT  VT,
SelectionDAG DAG 
)
static

◆ getRISCVVLOp()

static unsigned getRISCVVLOp ( SDValue  Op)
static

◆ getRISCVWOpcode()

static RISCVISD::NodeType getRISCVWOpcode ( unsigned  Opcode)
static

◆ getRVVFPReductionOpAndOperands()

static std::tuple< unsigned, SDValue, SDValue > getRVVFPReductionOpAndOperands ( SDValue  Op,
SelectionDAG DAG,
EVT  EltVT,
const RISCVSubtarget Subtarget 
)
static

◆ getRVVReductionOp()

static unsigned getRVVReductionOp ( unsigned  ISDOpcode)
static

◆ getSmallestVTForIndex()

static std::optional< MVT > getSmallestVTForIndex ( MVT  VecVT,
unsigned  MaxIdx,
SDLoc  DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ getTargetNode() [1/4]

static SDValue getTargetNode ( BlockAddressSDNode N,
const SDLoc DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 7128 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getTargetBlockAddress(), and N.

◆ getTargetNode() [2/4]

static SDValue getTargetNode ( ConstantPoolSDNode N,
const SDLoc DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 7134 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getTargetConstantPool(), and N.

◆ getTargetNode() [3/4]

static SDValue getTargetNode ( GlobalAddressSDNode N,
const SDLoc DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 7123 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getTargetGlobalAddress(), and N.

◆ getTargetNode() [4/4]

static SDValue getTargetNode ( JumpTableSDNode N,
const SDLoc DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 7140 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getTargetJumpTable(), and N.

◆ getVCIXISDNodeVOID()

static SDValue getVCIXISDNodeVOID ( SDValue Op,
SelectionDAG DAG,
unsigned  Type 
)
inlinestatic

◆ getVCIXISDNodeWCHAIN()

static SDValue getVCIXISDNodeWCHAIN ( SDValue Op,
SelectionDAG DAG,
unsigned  Type 
)
inlinestatic

◆ getVecReduceOpcode()

static unsigned getVecReduceOpcode ( unsigned  Opc)
static

◆ getVLOp()

static SDValue getVLOp ( uint64_t  NumElts,
MVT  ContainerVT,
const SDLoc DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ getVLOperand()

static SDValue getVLOperand ( SDValue  Op)
static

◆ getVSlidedown()

static SDValue getVSlidedown ( SelectionDAG DAG,
const RISCVSubtarget Subtarget,
const SDLoc DL,
EVT  VT,
SDValue  Merge,
SDValue  Op,
SDValue  Offset,
SDValue  Mask,
SDValue  VL,
unsigned  Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED 
)
static

◆ getVSlideup()

static SDValue getVSlideup ( SelectionDAG DAG,
const RISCVSubtarget Subtarget,
const SDLoc DL,
EVT  VT,
SDValue  Merge,
SDValue  Op,
SDValue  Offset,
SDValue  Mask,
SDValue  VL,
unsigned  Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED 
)
static

◆ getWideningInterleave()

static SDValue getWideningInterleave ( SDValue  EvenV,
SDValue  OddV,
const SDLoc DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ hasMaskOp()

static bool hasMaskOp ( unsigned  Opcode)
static

◆ hasMergeOp()

static bool hasMergeOp ( unsigned  Opcode)
static

◆ isDeinterleaveShuffle()

static bool isDeinterleaveShuffle ( MVT  VT,
MVT  ContainerVT,
SDValue  V1,
SDValue  V2,
ArrayRef< int >  Mask,
const RISCVSubtarget Subtarget 
)
static

◆ isElementRotate()

static int isElementRotate ( int &  LoSrc,
int &  HiSrc,
ArrayRef< int >  Mask 
)
static

Match shuffles that concatenate two vectors, rotate the concatenation, and then extract the original number of elements from the rotated result.

This is equivalent to vector.splice or X86's PALIGNR instruction. The returned rotation amount is for a rotate right, where elements move from higher elements to lower elements. LoSrc indicates the first source vector of the rotate or -1 for undef. HiSrc indicates the second vector of the rotate or -1 for undef. At least one of LoSrc and HiSrc will be 0 or 1 if a rotation is found.

NOTE: We talk about rotate to the right which matches how bit shift and rotate instructions are described where LSBs are on the right, but LLVM IR and the table below write vectors with the lowest elements on the left.

Definition at line 4344 of file RISCVISelLowering.cpp.

References assert(), and Size.

Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal(), and lowerVECTOR_SHUFFLE().

◆ isInterleaveShuffle()

static bool isInterleaveShuffle ( ArrayRef< int >  Mask,
MVT  VT,
int &  EvenSrc,
int &  OddSrc,
const RISCVSubtarget Subtarget 
)
static

Is this shuffle interleaving contiguous elements from one vector into the even elements and contiguous elements from another vector into the odd elements.

EvenSrc will contain the element that should be in the first even element. OddSrc will contain the element that should be in the first odd element. These can be the first element in a source or the element half way through the source.

Definition at line 4300 of file RISCVISelLowering.cpp.

References assert(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::ShuffleVectorInst::isInterleaveMask(), and Size.

Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal(), and lowerVECTOR_SHUFFLE().

◆ isLegalBitRotate()

static bool isLegalBitRotate ( ShuffleVectorSDNode SVN,
SelectionDAG DAG,
const RISCVSubtarget Subtarget,
MVT RotateVT,
unsigned RotateAmt 
)
static

◆ isNonZeroAVL()

static bool isNonZeroAVL ( SDValue  AVL)
static

Definition at line 9629 of file RISCVISelLowering.cpp.

Referenced by combineBinOpToReduce(), and lowerReductionSeq().

◆ isSelectPseudo()

static bool isSelectPseudo ( MachineInstr MI)
static

Definition at line 17717 of file RISCVISelLowering.cpp.

References MI.

Referenced by emitSelectPseudo().

◆ isSimpleVIDSequence()

static std::optional< VIDSequence > isSimpleVIDSequence ( SDValue  Op,
unsigned  EltSizeInBits 
)
static

◆ isValidEGW()

static bool isValidEGW ( int  EGS,
EVT  VT,
const RISCVSubtarget Subtarget 
)
inlinestatic

◆ legalizeScatterGatherIndexType()

static bool legalizeScatterGatherIndexType ( SDLoc  DL,
SDValue Index,
ISD::MemIndexType IndexType,
RISCVTargetLowering::DAGCombinerInfo &  DCI 
)
static

◆ lookupMaskedIntrinsic()

static const RISCV::RISCVMaskedPseudoInfo * lookupMaskedIntrinsic ( uint16_t  MCOpcode,
RISCVII::VLMUL  LMul,
unsigned  SEW 
)
static

Definition at line 18020 of file RISCVISelLowering.cpp.

References assert().

Referenced by emitVFROUND_NOEXCEPT_MASK().

◆ LowerATOMIC_FENCE()

static SDValue LowerATOMIC_FENCE ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerBitreverseShuffle()

static SDValue lowerBitreverseShuffle ( ShuffleVectorSDNode SVN,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerBUILD_VECTOR()

static SDValue lowerBUILD_VECTOR ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

Definition at line 3873 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLE(), llvm::ISD::BUILD_VECTOR, llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), llvm::count_if(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getFixedSizeInBits(), llvm::RISCVSubtarget::getFLen(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::RISCVTargetLowering::getLMUL(), getLMUL1VT(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealVLen(), llvm::SelectionDAG::getSetCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplatBuildVector(), llvm::getSplatValue(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MVT::getVectorMinNumElements(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), getVSlidedown(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::isBuildVectorOfConstantFPSDNodes(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::RISCVII::LMUL_2, llvm::RISCVII::LMUL_4, llvm::RISCVII::LMUL_8, lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), llvm::RISCVII::MASK_AGNOSTIC, matchSplatAsGather(), llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::reserve(), llvm::ISD::SETNE, llvm::SmallVectorBase< Size_T >::size(), llvm::ArrayRef< T >::slice(), llvm::Splat, llvm::RISCVII::TAIL_AGNOSTIC, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VFSLIDE1DOWN_VL, llvm::RISCVISD::VMV_V_X_VL, llvm::ISD::VSELECT, and llvm::RISCVISD::VSLIDE1DOWN_VL.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

◆ lowerBuildVectorOfConstants()

static SDValue lowerBuildVectorOfConstants ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

Definition at line 3572 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLE(), llvm::MVT::changeVectorElementType(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::SelectionDAG::ComputeNumSignBits(), convertFromScalableVector(), convertToScalableVector(), llvm::divideCeil(), DL, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getSizeInBits(), llvm::getSplatValue(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::ISD::INSERT_VECTOR_ELT, INT64_MIN, llvm::RISCVSubtarget::is64Bit(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), llvm::isPowerOf2_32(), llvm::isPowerOf2_64(), isSimpleVIDSequence(), llvm::Log2_64(), lowerBuildVectorViaDominantValues(), llvm::ISD::MUL, llvm::ISD::SHL, llvm::SelectionDAG::shouldOptForSize(), llvm::ISD::SINT_TO_FP, llvm::Splat, llvm::ISD::SRL, llvm::ISD::SUB, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VID_VL, llvm::RISCVISD::VMCLR_VL, llvm::RISCVISD::VMSET_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::RISCVISD::VSEXT_VL.

Referenced by lowerBUILD_VECTOR().

◆ lowerBuildVectorViaDominantValues()

static SDValue lowerBuildVectorViaDominantValues ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

Try and optimize BUILD_VECTORs with "dominant values" - these are values which constitute a large proportion of the elements.

In such cases we can splat a vector with the dominant element and make up the shortfall with INSERT_VECTOR_ELTs. Returns SDValue if not profitable. Note that this includes vectors of 2 elements by association. The upper-most element is the "dominant" one, allowing us to use a splat to "insert" the upper element, and an insert of the lower element at position 0, which improves codegen.

Definition at line 3465 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), llvm::count_if(), DL, llvm::enumerate(), llvm::SelectionDAG::getBuildVector(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::SelectionDAG::getSplatBuildVector(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::Log2_32(), llvm::SelectionDAG::shouldOptForSize(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::size(), llvm::transform(), llvm::RISCVISD::VFSLIDE1DOWN_VL, llvm::ISD::VSELECT, and llvm::RISCVISD::VSLIDE1DOWN_VL.

Referenced by lowerBUILD_VECTOR(), and lowerBuildVectorOfConstants().

◆ lowerConstant()

static SDValue lowerConstant ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerCttzElts()

static SDValue lowerCttzElts ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerFMAXIMUM_FMINIMUM()

static SDValue lowerFMAXIMUM_FMINIMUM ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerFP_TO_INT_SAT()

static SDValue lowerFP_TO_INT_SAT ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerFTRUNC_FCEIL_FFLOOR_FROUND()

static SDValue lowerFTRUNC_FCEIL_FFLOOR_FROUND ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerGetVectorLength()

static SDValue lowerGetVectorLength ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerReductionSeq()

static SDValue lowerReductionSeq ( unsigned  RVVOpcode,
MVT  ResVT,
SDValue  StartValue,
SDValue  Vec,
SDValue  Mask,
SDValue  VL,
const SDLoc DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerSADDO_SSUBO()

static SDValue lowerSADDO_SSUBO ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ lowerSADDSAT_SSUBSAT()

static SDValue lowerSADDSAT_SSUBSAT ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ lowerScalarInsert()

static SDValue lowerScalarInsert ( SDValue  Scalar,
SDValue  VL,
MVT  VT,
const SDLoc DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerScalarSplat()

static SDValue lowerScalarSplat ( SDValue  Passthru,
SDValue  Scalar,
SDValue  VL,
MVT  VT,
const SDLoc DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerShuffleViaVRegSplitting()

static SDValue lowerShuffleViaVRegSplitting ( ShuffleVectorSDNode SVN,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerSMULO()

static SDValue lowerSMULO ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ lowerUADDSAT_USUBSAT()

static SDValue lowerUADDSAT_USUBSAT ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ lowerVECTOR_SHUFFLE()

static SDValue lowerVECTOR_SHUFFLE ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

Definition at line 4929 of file RISCVISelLowering.cpp.

References llvm::all_of(), llvm::any_of(), assert(), llvm::MVT::bitsGT(), llvm::MVT::changeTypeToInteger(), llvm::MVT::changeVectorElementType(), llvm::ISD::CONCAT_VECTORS, convertFromScalableVector(), convertToScalableVector(), DL, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), getDeinterleaveViaVNSRL(), llvm::SelectionDAG::getExtLoad(), llvm::TypeSize::getFixed(), llvm::SDNode::getFlags(), llvm::MVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::SelectionDAG::getRegister(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getScalarType(), llvm::SelectionDAG::getSetCC(), llvm::MVT::getSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::MVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), getVSlidedown(), getVSlideup(), llvm::SelectionDAG::getVTList(), getWideningInterleave(), llvm::RISCVSubtarget::getXLenVT(), Idx, llvm::ISD::INTRINSIC_W_CHAIN, isDeinterleaveShuffle(), isElementRotate(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), isInterleaveShuffle(), llvm::ISD::isNormalLoad(), IsSelect(), llvm::ShuffleVectorSDNode::isSplat(), llvm::SelectionDAG::isSplatValue(), llvm::SDValue::isUndef(), lowerBitreverseShuffle(), lowerShuffleViaVRegSplitting(), lowerVECTOR_SHUFFLEAsRotate(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SETNE, llvm::ISD::SEXTLOAD, llvm::SmallVectorBase< Size_T >::size(), Size, llvm::Splat, std::swap(), llvm::RISCVII::TAIL_AGNOSTIC, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_V_X_VL, llvm::RISCVISD::VRGATHER_VV_VL, llvm::RISCVISD::VRGATHER_VX_VL, llvm::RISCVISD::VRGATHEREI16_VV_VL, llvm::ISD::VSELECT, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::RISCVTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

◆ lowerVECTOR_SHUFFLEAsRotate()

static SDValue lowerVECTOR_SHUFFLEAsRotate ( ShuffleVectorSDNode SVN,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerVECTOR_SHUFFLEAsVSlide1()

static SDValue lowerVECTOR_SHUFFLEAsVSlide1 ( const SDLoc DL,
MVT  VT,
SDValue  V1,
SDValue  V2,
ArrayRef< int >  Mask,
const RISCVSubtarget Subtarget,
SelectionDAG DAG 
)
static

◆ lowerVECTOR_SHUFFLEAsVSlidedown()

static SDValue lowerVECTOR_SHUFFLEAsVSlidedown ( const SDLoc DL,
MVT  VT,
SDValue  V1,
SDValue  V2,
ArrayRef< int >  Mask,
const RISCVSubtarget Subtarget,
SelectionDAG DAG 
)
static

◆ lowerVECTOR_SHUFFLEAsVSlideup()

static SDValue lowerVECTOR_SHUFFLEAsVSlideup ( const SDLoc DL,
MVT  VT,
SDValue  V1,
SDValue  V2,
ArrayRef< int >  Mask,
const RISCVSubtarget Subtarget,
SelectionDAG DAG 
)
static

◆ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()

static SDValue lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerVectorIntrinsicScalars()

static SDValue lowerVectorIntrinsicScalars ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()

static SDValue lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerVectorXRINT()

static SDValue lowerVectorXRINT ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ matchIndexAsShuffle()

static bool matchIndexAsShuffle ( EVT  VT,
SDValue  Index,
SDValue  Mask,
SmallVector< int > &  ShuffleMask 
)
static

Match the index vector of a scatter or gather node as the shuffle mask which performs the rearrangement if possible.

Will only match if all lanes are touched, and thus replacing the scatter or gather with a unit strided access and shuffle is legal.

Definition at line 16014 of file RISCVISelLowering.cpp.

References llvm::BitVector::all(), assert(), llvm::CallingConv::C, llvm::SmallVectorBase< Size_T >::empty(), llvm::EVT::getScalarStoreSize(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVectorAllOnes(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::BitVector::set().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ matchIndexAsWiderOp()

static bool matchIndexAsWiderOp ( EVT  VT,
SDValue  Index,
SDValue  Mask,
Align  BaseAlign,
const RISCVSubtarget ST 
)
static

Match the index of a gather or scatter operation as an operation with twice the element width and half the number of elements.

This is generally profitable (if legal) because these operations are linear in VL, so even if we cause some extract VTYPE/VL toggles, we still come out ahead.

Definition at line 16049 of file RISCVISelLowering.cpp.

References llvm::CallingConv::C, llvm::EVT::getScalarStoreSize(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVectorAllOnes(), and llvm::Last.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ matchRoundingOp()

static RISCVFPRndMode::RoundingMode matchRoundingOp ( unsigned  Opc)
static

◆ matchSetCC()

static std::optional< bool > matchSetCC ( SDValue  LHS,
SDValue  RHS,
ISD::CondCode  CC,
SDValue  Val 
)
static

◆ matchSplatAsGather()

static SDValue matchSplatAsGather ( SDValue  SplatVal,
MVT  VT,
const SDLoc DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ narrowIndex()

static bool narrowIndex ( SDValue N,
ISD::MemIndexType  IndexType,
SelectionDAG DAG 
)
static

◆ negateFMAOpcode()

static unsigned negateFMAOpcode ( unsigned  Opcode,
bool  NegMul,
bool  NegAcc 
)
static

◆ performADDCombine()

static SDValue performADDCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const RISCVSubtarget Subtarget 
)
static

◆ performANDCombine()

static SDValue performANDCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const RISCVSubtarget Subtarget 
)
static

◆ performBITREVERSECombine()

static SDValue performBITREVERSECombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performBUILD_VECTORCombine()

static SDValue performBUILD_VECTORCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget,
const RISCVTargetLowering TLI 
)
static

If we have a build_vector where each lane is binop X, C, where C is a constant (but not necessarily the same constant on all lanes), form binop (build_vector x1, x2, ...), (build_vector c1, c2, c3, ..).

We assume that materializing a constant build vector will be no more expensive that performing O(n) binops.

Definition at line 15649 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::TargetLoweringBase::isBinOp(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::SelectionDAG::isSafeToSpeculativelyExecute(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), N, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ performCONCAT_VECTORSCombine()

static SDValue performCONCAT_VECTORSCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget,
const RISCVTargetLowering TLI 
)
static

◆ performFP_TO_INT_SATCombine()

static SDValue performFP_TO_INT_SATCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const RISCVSubtarget Subtarget 
)
static

◆ performFP_TO_INTCombine()

static SDValue performFP_TO_INTCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const RISCVSubtarget Subtarget 
)
static

◆ performINSERT_VECTOR_ELTCombine()

static SDValue performINSERT_VECTOR_ELTCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget,
const RISCVTargetLowering TLI 
)
static

◆ performMemPairCombine()

static SDValue performMemPairCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ performMULCombine()

static SDValue performMULCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const RISCVSubtarget Subtarget 
)
static

◆ performORCombine()

static SDValue performORCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const RISCVSubtarget Subtarget 
)
static

◆ performSELECTCombine()

static SDValue performSELECTCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performSETCCCombine()

static SDValue performSETCCCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performSIGN_EXTEND_INREGCombine()

static SDValue performSIGN_EXTEND_INREGCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performSRACombine()

static SDValue performSRACombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performSUBCombine()

static SDValue performSUBCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performTRUNCATECombine()

static SDValue performTRUNCATECombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performVFMADD_VLCombine()

static SDValue performVFMADD_VLCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performVWADDSUBW_VLCombine()

static SDValue performVWADDSUBW_VLCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const RISCVSubtarget Subtarget 
)
static

◆ performXORCombine()

static SDValue performXORCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ preAssignMask()

template<typename ArgTy >
static std::optional< unsigned > preAssignMask ( const ArgTy &  Args)
static

◆ processVCIXOperands()

static void processVCIXOperands ( SDValue OrigOp,
SmallVectorImpl< SDValue > &  Operands,
SelectionDAG DAG 
)
static

◆ promoteVCIXScalar()

static void promoteVCIXScalar ( const SDValue Op,
SmallVectorImpl< SDValue > &  Operands,
SelectionDAG DAG 
)
inlinestatic

◆ splatPartsI64WithVL()

static SDValue splatPartsI64WithVL ( const SDLoc DL,
MVT  VT,
SDValue  Passthru,
SDValue  Lo,
SDValue  Hi,
SDValue  VL,
SelectionDAG DAG 
)
static

◆ splatSplitI64WithVL()

static SDValue splatSplitI64WithVL ( const SDLoc DL,
MVT  VT,
SDValue  Passthru,
SDValue  Scalar,
SDValue  VL,
SelectionDAG DAG 
)
static

◆ SplitStrictFPVectorOp()

static SDValue SplitStrictFPVectorOp ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ SplitVectorOp()

static SDValue SplitVectorOp ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ SplitVectorReductionOp()

static SDValue SplitVectorReductionOp ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ SplitVPOp()

static SDValue SplitVPOp ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ STATISTIC()

STATISTIC ( NumTailCalls  ,
"Number of tail calls"   
)

◆ transformAddImmMulImm()

static SDValue transformAddImmMulImm ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ transformAddShlImm()

static SDValue transformAddShlImm ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ translateSetCCForBranch()

static void translateSetCCForBranch ( const SDLoc DL,
SDValue LHS,
SDValue RHS,
ISD::CondCode CC,
SelectionDAG DAG 
)
static

◆ tryDemorganOfBooleanCondition()

static SDValue tryDemorganOfBooleanCondition ( SDValue  Cond,
SelectionDAG DAG 
)
static

◆ tryFoldSelectIntoOp()

static SDValue tryFoldSelectIntoOp ( SDNode N,
SelectionDAG DAG,
SDValue  TrueVal,
SDValue  FalseVal,
bool  Swapped 
)
static

◆ tryMemPairCombine()

static SDValue tryMemPairCombine ( SelectionDAG DAG,
LSBaseSDNode LSNode1,
LSBaseSDNode LSNode2,
SDValue  BasePtr,
uint64_t  Imm 
)
static

◆ unpackF64OnRV32DSoftABI()

static SDValue unpackF64OnRV32DSoftABI ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const CCValAssign HiVA,
const SDLoc DL 
)
static

◆ unpackFromMemLoc()

static SDValue unpackFromMemLoc ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const SDLoc DL 
)
static

◆ unpackFromRegLoc()

static SDValue unpackFromRegLoc ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const SDLoc DL,
const ISD::InputArg In,
const RISCVTargetLowering TLI 
)
static

◆ useInversedSetcc()

static SDValue useInversedSetcc ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ useRVVForFixedLengthVectorVT()

static bool useRVVForFixedLengthVectorVT ( MVT  VT,
const RISCVSubtarget Subtarget 
)
static

◆ useTpOffset()

static Value * useTpOffset ( IRBuilderBase IRB,
unsigned  Offset 
)
static

◆ widenVectorOpsToi8()

static SDValue widenVectorOpsToi8 ( SDValue  N,
const SDLoc DL,
SelectionDAG DAG 
)
static

Variable Documentation

◆ AllowSplatInVW_W

cl::opt< bool > AllowSplatInVW_W(DEBUG_TYPE "-form-vw-w-with-splat", cl::Hidden, cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants"), cl::init(false)) ( DEBUG_TYPE "-form-vw-w-with-splat"  ,
cl::Hidden  ,
cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants")  ,
cl::init(false)   
)
static

◆ ArgFPR16s

const MCPhysReg ArgFPR16s[]
static
Initial value:
= {
RISCV::F10_H, RISCV::F11_H, RISCV::F12_H, RISCV::F13_H,
RISCV::F14_H, RISCV::F15_H, RISCV::F16_H, RISCV::F17_H
}

Definition at line 18365 of file RISCVISelLowering.cpp.

Referenced by llvm::RISCV::CC_RISCV().

◆ ArgFPR32s

const MCPhysReg ArgFPR32s[]
static
Initial value:
= {
RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F,
RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F
}

Definition at line 18369 of file RISCVISelLowering.cpp.

◆ ArgFPR64s

const MCPhysReg ArgFPR64s[]
static
Initial value:
= {
RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D,
RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D
}

Definition at line 18373 of file RISCVISelLowering.cpp.

◆ ArgVRM2s

const MCPhysReg ArgVRM2s[]
static
Initial value:
= {RISCV::V8M2, RISCV::V10M2, RISCV::V12M2,
RISCV::V14M2, RISCV::V16M2, RISCV::V18M2,
RISCV::V20M2, RISCV::V22M2}

Definition at line 18382 of file RISCVISelLowering.cpp.

◆ ArgVRM4s

const MCPhysReg ArgVRM4s[]
static
Initial value:
= {RISCV::V8M4, RISCV::V12M4, RISCV::V16M4,
RISCV::V20M4}

Definition at line 18385 of file RISCVISelLowering.cpp.

◆ ArgVRM8s

const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8}
static

Definition at line 18387 of file RISCVISelLowering.cpp.

◆ ArgVRs

const MCPhysReg ArgVRs[]
static
Initial value:
= {
RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13,
RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19,
RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23}

Definition at line 18378 of file RISCVISelLowering.cpp.

◆ ExtensionMaxWebSize

cl::opt< unsigned > ExtensionMaxWebSize(DEBUG_TYPE "-ext-max-web-size", cl::Hidden, cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion"), cl::init(18)) ( DEBUG_TYPE "-ext-max-web-size"  ,
cl::Hidden  ,
cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion")  ,
cl::init(18)   
)
static

◆ FixedVlsegIntrIds

const Intrinsic::ID FixedVlsegIntrIds[]
static
Initial value:
= {
Intrinsic::riscv_seg2_load, Intrinsic::riscv_seg3_load,
Intrinsic::riscv_seg4_load, Intrinsic::riscv_seg5_load,
Intrinsic::riscv_seg6_load, Intrinsic::riscv_seg7_load,
Intrinsic::riscv_seg8_load}

Definition at line 21133 of file RISCVISelLowering.cpp.

Referenced by llvm::RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(), and llvm::RISCVTargetLowering::lowerInterleavedLoad().

◆ FixedVssegIntrIds

const Intrinsic::ID FixedVssegIntrIds[]
static
Initial value:
= {
Intrinsic::riscv_seg2_store, Intrinsic::riscv_seg3_store,
Intrinsic::riscv_seg4_store, Intrinsic::riscv_seg5_store,
Intrinsic::riscv_seg6_store, Intrinsic::riscv_seg7_store,
Intrinsic::riscv_seg8_store}

Definition at line 21181 of file RISCVISelLowering.cpp.

Referenced by llvm::RISCVTargetLowering::lowerInterleavedStore(), and llvm::RISCVTargetLowering::lowerInterleaveIntrinsicToStore().

◆ FPImmCost

cl::opt< int > FPImmCost(DEBUG_TYPE "-fpimm-cost", cl::Hidden, cl::desc("Give the maximum number of instructions that we will " "use for creating a floating-point immediate value"), cl::init(2)) ( DEBUG_TYPE "-fpimm-cost"  ,
cl::Hidden  ,
cl::desc("Give the maximum number of instructions that we will " "use for creating a floating-point immediate value")  ,
cl::init(2)   
)
static

◆ NumRepeatedDivisors

cl::opt< unsigned > NumRepeatedDivisors(DEBUG_TYPE "-fp-repeated-divisors", cl::Hidden, cl::desc("Set the minimum number of repetitions of a divisor to allow " "transformation to multiplications by the reciprocal"), cl::init(2)) ( DEBUG_TYPE "-fp-repeated-divisors"  ,
cl::Hidden  ,
cl::desc("Set the minimum number of repetitions of a divisor to allow " "transformation to multiplications by the reciprocal")  ,
cl::init(2)   
)
static

◆ RV64LegalI32

cl::opt< bool > RV64LegalI32("riscv-experimental-rv64-legal-i32", cl::ReallyHidden, cl::desc("Make i32 a legal type for SelectionDAG on RV64.")) ( "riscv-experimental-rv64-legal-i32"  ,
cl::ReallyHidden  ,
cl::desc("Make i32 a legal type for SelectionDAG on RV64.")   
)
static