RISCVISelLowering.cpp File Reference

#include "RISCVISelLowering.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVRegisterInfo.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/DiagnosticPrinter.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "RISCVGenAsmMatcher.inc"
#include "RISCVGenSearchableTables.inc"

Include dependency graph for RISCVISelLowering.cpp:

Go to the source code of this file.

Classes
struct	VIDSequence
struct	RISCVBitmanipPat

Namespaces
	llvm
	This is an optimization pass for GlobalISel generic memory operations.
	llvm::RISCVVIntrinsicsTable

Macros
#define	DEBUG_TYPE   "riscv-lower"
#define	NODE_NAME_CASE(NODE)
#define	GET_REGISTER_MATCHER
#define	GET_RISCVVIntrinsicsTable_IMPL

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")
static void	translateSetCCForBranch (const SDLoc &DL, SDValue &LHS, SDValue &RHS, ISD::CondCode &CC, SelectionDAG &DAG)
static bool	useRVVForFixedLengthVectorVT (MVT VT, const RISCVSubtarget &Subtarget)
static MVT	getContainerForFixedLengthVector (const TargetLowering &TLI, MVT VT, const RISCVSubtarget &Subtarget)
static MVT	getContainerForFixedLengthVector (SelectionDAG &DAG, MVT VT, const RISCVSubtarget &Subtarget)
static SDValue	convertToScalableVector (EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	convertFromScalableVector (EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static std::pair< SDValue, SDValue >	getDefaultVLOps (MVT VecVT, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static std::pair< SDValue, SDValue >	getDefaultScalableVLOps (MVT VecVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerFP_TO_INT_SAT (SDValue Op, SelectionDAG &DAG)
static SDValue	lowerFTRUNC_FCEIL_FFLOOR (SDValue Op, SelectionDAG &DAG)
static SDValue	lowerSPLAT_VECTOR (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static Optional< VIDSequence >	isSimpleVIDSequence (SDValue Op)
static SDValue	lowerBUILD_VECTOR (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	splatPartsI64WithVL (const SDLoc &DL, MVT VT, SDValue Lo, SDValue Hi, SDValue VL, SelectionDAG &DAG)
static SDValue	splatSplitI64WithVL (const SDLoc &DL, MVT VT, SDValue Scalar, SDValue VL, SelectionDAG &DAG)
static SDValue	lowerScalarSplat (SDValue Scalar, SDValue VL, MVT VT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	getRVVFPExtendOrRound (SDValue Op, MVT VT, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerCTLZ_CTTZ_ZERO_UNDEF (SDValue Op, SelectionDAG &DAG)
static SDValue	getTargetNode (GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (BlockAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (ConstantPoolSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (JumpTableSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	lowerVectorIntrinsicSplats (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static MVT	getLMUL1VT (MVT VT)
static unsigned	getRVVReductionOp (unsigned ISDOpcode)
static std::tuple< unsigned, SDValue, SDValue >	getRVVFPReductionOpAndOperands (SDValue Op, SelectionDAG &DAG, EVT EltVT)
static unsigned	getRVVVPReductionOp (unsigned ISDOpcode)
static RISCVISD::NodeType	getRISCVWOpcode (unsigned Opcode)
static SDValue	customLegalizeToWOp (SDNode *N, SelectionDAG &DAG, unsigned ExtOpc=ISD::ANY_EXTEND)
static SDValue	customLegalizeToWOpWithSExt (SDNode *N, SelectionDAG &DAG)
static Optional< RISCVBitmanipPat >	matchRISCVBitmanipPat (SDValue Op, ArrayRef< uint64_t > BitmanipMasks)
static Optional< RISCVBitmanipPat >	matchGREVIPat (SDValue Op)
static SDValue	combineORToGREV (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	combineORToGORC (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static Optional< RISCVBitmanipPat >	matchSHFLPat (SDValue Op)
static SDValue	combineORToSHFL (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	transformAddShlImm (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	combineGREVI_GORCI (SDNode *N, SelectionDAG &DAG)
static SDValue	combineSelectAndUse (SDNode *N, SDValue Slct, SDValue OtherOp, SelectionDAG &DAG, bool AllOnes)
static SDValue	combineSelectAndUseCommutative (SDNode *N, SelectionDAG &DAG, bool AllOnes)
static SDValue	transformAddImmMulImm (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	performADDCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	performSUBCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performANDCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performORCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	performXORCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performANY_EXTENDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static SDValue	combineMUL_VLToVWMUL (SDNode *N, SDValue Op0, SDValue Op1, SelectionDAG &DAG)
static void	computeGREV (APInt &Src, unsigned ShAmt)
static MachineBasicBlock *	emitReadCycleWidePseudo (MachineInstr &MI, MachineBasicBlock *BB)
static MachineBasicBlock *	emitSplitF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB)
static MachineBasicBlock *	emitBuildPairF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB)
static bool	isSelectPseudo (MachineInstr &MI)
static MachineBasicBlock *	emitSelectPseudo (MachineInstr &MI, MachineBasicBlock *BB, const RISCVSubtarget &Subtarget)
static bool	CC_RISCVAssign2XLen (unsigned XLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
static unsigned	allocateRVVReg (MVT ValVT, unsigned ValNo, Optional< unsigned > FirstMaskArgument, CCState &State, const RISCVTargetLowering &TLI)
static bool	CC_RISCV (const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, Optional< unsigned > FirstMaskArgument)
template<typename ArgTy >
static Optional< unsigned >	preAssignMask (const ArgTy &Args)
static SDValue	convertLocVTToValVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget)
static SDValue	unpackFromRegLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const RISCVTargetLowering &TLI)
static SDValue	convertValVTToLocVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget)
static SDValue	unpackFromMemLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static SDValue	unpackF64OnRV32DSoftABI (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static bool	CC_RISCV_FastCC (const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, Optional< unsigned > FirstMaskArgument)
static bool	CC_RISCV_GHC (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static Align	getPrefTypeAlign (EVT VT, SelectionDAG &DAG)
static Intrinsic::ID	getIntrinsicForMaskedAtomicRMWBinOp (unsigned XLen, AtomicRMWInst::BinOp BinOp)

Variables
static const MCPhysReg	ArgGPRs []
static const MCPhysReg	ArgFPR16s []
static const MCPhysReg	ArgFPR32s []
static const MCPhysReg	ArgFPR64s []
static const MCPhysReg	ArgVRs []
static const MCPhysReg	ArgVRM2s []
static const MCPhysReg	ArgVRM4s []
static const MCPhysReg	ArgVRM8s [] = {RISCV::V8M8, RISCV::V16M8}

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "riscv-lower"

Definition at line 43 of file RISCVISelLowering.cpp.

GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 10174 of file RISCVISelLowering.cpp.

GET_RISCVVIntrinsicsTable_IMPL

#define GET_RISCVVIntrinsicsTable_IMPL

Definition at line 10196 of file RISCVISelLowering.cpp.

NODE_NAME_CASE

#define NODE_NAME_CASE

(

NODE

)

Value:

  case RISCVISD::NODE:                                                         \
    return "RISCVISD::" #NODE;

Function Documentation

allocateRVVReg()

static unsigned allocateRVVReg ( MVT  ValVT, unsigned  ValNo, Optional< unsigned >  FirstMaskArgument, CCState &  State, const RISCVTargetLowering &  TLI  )

static

Definition at line 8110 of file RISCVISelLowering.cpp.

References llvm::CCState::AllocateReg(), ArgVRM2s, ArgVRM4s, ArgVRM8s, ArgVRs, llvm::TargetLoweringBase::getRegClassFor(), llvm::Optional< T >::getValue(), llvm::Optional< T >::hasValue(), and llvm_unreachable.

Referenced by CC_RISCV(), and CC_RISCV_FastCC().

CC_RISCV()

static bool CC_RISCV ( const DataLayout &  DL, RISCVABI::ABI  ABI, unsigned  ValNo, MVT  ValVT, MVT  LocVT, CCValAssign::LocInfo  LocInfo, ISD::ArgFlagsTy  ArgFlags, CCState &  State, bool  IsFixed, bool  IsRet, Type *  OrigTy, const RISCVTargetLowering &  TLI, Optional< unsigned >  FirstMaskArgument  )

static

Definition at line 8132 of file RISCVISelLowering.cpp.

References ABI, llvm::RISCVABI::ABI_ILP32, llvm::RISCVABI::ABI_ILP32D, llvm::RISCVABI::ABI_ILP32F, llvm::RISCVABI::ABI_LP64, llvm::RISCVABI::ABI_LP64D, llvm::RISCVABI::ABI_LP64F, llvm::CCState::addLoc(), Align, llvm::CCState::AllocateReg(), allocateRVVReg(), llvm::CCState::AllocateStack(), ArgFPR16s, ArgFPR32s, ArgFPR64s, ArgGPRs, llvm::array_lengthof(), assert(), llvm::CCValAssign::BCvt, CC_RISCVAssign2XLen(), llvm::SmallVectorImpl< T >::clear(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::CCValAssign::Full, llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), llvm::CCState::getFirstUnallocated(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getPending(), llvm::CCState::getPendingArgFlags(), llvm::CCState::getPendingLocs(), llvm::CCValAssign::getReg(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getStoreSize(), llvm::RISCVTargetLowering::getSubtarget(), llvm::RISCVSubtarget::hasVInstructions(), llvm::MVT::i32, llvm::MVT::i64, llvm::CCValAssign::Indirect, llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::MVT::isScalableVector(), llvm::MVT::isScalarInteger(), llvm::ISD::ArgFlagsTy::isSplit(), llvm::ISD::ArgFlagsTy::isSplitEnd(), llvm::MVT::isVector(), llvm_unreachable, Reg, llvm::report_fatal_error(), and llvm::MaybeAlign::valueOrOne().

Referenced by llvm::RISCVTargetLowering::CanLowerReturn(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerFormalArguments(), and llvm::RISCVTargetLowering::LowerReturn().

CC_RISCV_FastCC()

static bool CC_RISCV_FastCC ( const DataLayout &  DL, RISCVABI::ABI  ABI, unsigned  ValNo, MVT  ValVT, MVT  LocVT, CCValAssign::LocInfo  LocInfo, ISD::ArgFlagsTy  ArgFlags, CCState &  State, bool  IsFixed, bool  IsRet, Type *  OrigTy, const RISCVTargetLowering &  TLI, Optional< unsigned >  FirstMaskArgument  )

static

Definition at line 8552 of file RISCVISelLowering.cpp.

References llvm::CCState::addLoc(), Align, llvm::CCState::AllocateReg(), allocateRVVReg(), llvm::CCState::AllocateStack(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), llvm::CCValAssign::getMem(), llvm::CCValAssign::getReg(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getStoreSize(), llvm::RISCVTargetLowering::getSubtarget(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::CCValAssign::Indirect, llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), Reg, and llvm::MaybeAlign::valueOrOne().

Referenced by llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerFormalArguments().

CC_RISCV_GHC()

static bool CC_RISCV_GHC ( unsigned  ValNo, MVT  ValVT, MVT  LocVT, CCValAssign::LocInfo  LocInfo, ISD::ArgFlagsTy  ArgFlags, CCState &  State  )

static

Definition at line 8654 of file RISCVISelLowering.cpp.

References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::MVT::f32, llvm::MVT::f64, llvm::CCValAssign::getReg(), llvm::MVT::i32, llvm::MVT::i64, Reg, and llvm::report_fatal_error().

Referenced by llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerFormalArguments().

CC_RISCVAssign2XLen()

static bool CC_RISCVAssign2XLen ( unsigned  XLen, CCState &  State, CCValAssign  VA1, ISD::ArgFlagsTy  ArgFlags1, unsigned  ValNo2, MVT  ValVT2, MVT  LocVT2, ISD::ArgFlagsTy  ArgFlags2  )

static

Definition at line 8073 of file RISCVISelLowering.cpp.

References llvm::CCState::addLoc(), Align, llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), ArgGPRs, llvm::CCValAssign::Full, llvm::CCValAssign::getLocVT(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getReg(), llvm::CCValAssign::getValNo(), llvm::CCValAssign::getValVT(), llvm::max(), and Reg.

Referenced by CC_RISCV().

combineGREVI_GORCI()

static SDValue combineGREVI_GORCI ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 6558 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::RISCVISD::GORC, llvm::RISCVISD::GORCW, and N.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

combineMUL_VLToVWMUL()

static SDValue combineMUL_VLToVWMUL ( SDNode *  N, SDValue  Op0, SDValue  Op1, SelectionDAG &  DAG  )

static

Definition at line 6853 of file RISCVISelLowering.cpp.

References assert(), llvm::SelectionDAG::ComputeNumSignBits(), DL, llvm::APInt::getBitsSetFrom(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::RISCVISD::MUL_VL, N, llvm::RISCVISD::VMV_V_X_VL, llvm::RISCVISD::VSEXT_VL, llvm::RISCVISD::VWMUL_VL, llvm::RISCVISD::VWMULU_VL, and llvm::RISCVISD::VZEXT_VL.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

combineORToGORC()

static SDValue combineORToGORC ( SDValue  Op, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 6356 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVISD::GORC, llvm::RISCVISD::GREV, llvm::RISCVSubtarget::hasStdExtZbp(), llvm::MVT::i32, llvm::RISCVSubtarget::is64Bit(), llvm::isPowerOf2_32(), matchGREVIPat(), llvm::ISD::OR, llvm::ISD::ROTL, llvm::ISD::ROTR, std::swap(), and X.

Referenced by performORCombine().

combineORToGREV()

static SDValue combineORToGREV ( SDValue  Op, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 6330 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVISD::GREV, llvm::RISCVSubtarget::hasStdExtZbp(), llvm::MVT::i32, llvm::RISCVSubtarget::is64Bit(), and matchGREVIPat().

Referenced by performORCombine().

combineORToSHFL()

static SDValue combineORToSHFL ( SDValue  Op, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 6435 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, assert(), B, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasStdExtZbp(), llvm::MVT::i32, llvm::MVT::i64, llvm::Log2_32(), llvm::BitmaskEnumDetail::Mask(), matchSHFLPat(), llvm::ISD::OR, llvm::RISCVISD::SHFL, and std::swap().

Referenced by performORCombine().

combineSelectAndUse()

static SDValue combineSelectAndUse ( SDNode *  N, SDValue  Slct, SDValue  OtherOp, SelectionDAG &  DAG, bool  AllOnes  )

static

Definition at line 6599 of file RISCVISelLowering.cpp.

References llvm::tgtok::FalseVal, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::isNullConstant(), llvm::EVT::isVector(), isZeroOrAllOnes(), N, llvm::ISD::SELECT, llvm::RISCVISD::SELECT_CC, std::swap(), and llvm::tgtok::TrueVal.

Referenced by combineSelectAndUseCommutative(), and performSUBCombine().

combineSelectAndUseCommutative()

static SDValue combineSelectAndUseCommutative ( SDNode *  N, SelectionDAG &  DAG, bool  AllOnes  )

static

Definition at line 6647 of file RISCVISelLowering.cpp.

References combineSelectAndUse(), and N.

Referenced by performADDCombine(), performANDCombine(), performORCombine(), and performXORCombine().

computeGREV()

static void computeGREV ( APInt &  Src, unsigned  ShAmt  )

static

Definition at line 7550 of file RISCVISelLowering.cpp.

References x.

Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode().

convertFromScalableVector()

static SDValue convertFromScalableVector ( EVT  VT, SDValue  V, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 1577 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::RISCVSubtarget::getXLenVT(), llvm::EVT::isFixedLengthVector(), and llvm::EVT::isScalableVector().

Referenced by convertLocVTToValVT(), lowerBUILD_VECTOR(), llvm::RISCVTargetLowering::LowerOperation(), lowerSPLAT_VECTOR(), and lowerVECTOR_SHUFFLE().

convertLocVTToValVT()

static SDValue convertLocVTToValVT ( SelectionDAG &  DAG, SDValue  Val, const CCValAssign &  VA, const SDLoc &  DL, const RISCVSubtarget &  Subtarget  )

static

Definition at line 8417 of file RISCVISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertFromScalableVector(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::RISCVISD::FMV_H_X, llvm::RISCVISD::FMV_W_X_RV64, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::i64, llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::MVT::isScalableVector(), and llvm_unreachable.

Referenced by llvm::RISCVTargetLowering::LowerCall(), and unpackFromRegLoc().

convertToScalableVector()

static SDValue convertToScalableVector ( EVT  VT, SDValue  V, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 1565 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INSERT_SUBVECTOR, llvm::EVT::isFixedLengthVector(), and llvm::EVT::isScalableVector().

Referenced by convertValVTToLocVT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), and llvm::RISCVTargetLowering::ReplaceNodeResults().

convertValVTToLocVT()

static SDValue convertValVTToLocVT ( SelectionDAG &  DAG, SDValue  Val, const CCValAssign &  VA, const SDLoc &  DL, const RISCVSubtarget &  Subtarget  )

static

Definition at line 8459 of file RISCVISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertToScalableVector(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::RISCVISD::FMV_X_ANYEXTH, llvm::RISCVISD::FMV_X_ANYEXTW_RV64, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::i64, llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::EVT::isScalableVector(), and llvm_unreachable.

Referenced by llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerReturn().

customLegalizeToWOp()

static SDValue customLegalizeToWOp ( SDNode *  N, SelectionDAG &  DAG, unsigned  ExtOpc = ISD::ANY_EXTEND  )

static

Definition at line 5667 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), getRISCVWOpcode(), llvm::MVT::i64, N, and llvm::ISD::TRUNCATE.

Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().

customLegalizeToWOpWithSExt()

static SDValue customLegalizeToWOpWithSExt ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 5680 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), llvm::MVT::i32, llvm::MVT::i64, N, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::TRUNCATE.

Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().

emitBuildPairF64Pseudo()

static MachineBasicBlock* emitBuildPairF64Pseudo ( MachineInstr &  MI, MachineBasicBlock *  BB  )

static

Definition at line 7827 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), Align, assert(), BB, llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), llvm::HexagonInstrInfo::loadRegFromStackSlot(), MI, llvm::MachineMemOperand::MOStore, and TII.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

emitReadCycleWidePseudo()

static MachineBasicBlock* emitReadCycleWidePseudo ( MachineInstr &  MI, MachineBasicBlock *  BB  )

static

Definition at line 7732 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), BB, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::insert(), llvm::AArch64SysReg::lookupSysRegByName(), MI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

emitSelectPseudo()

static MachineBasicBlock* emitSelectPseudo ( MachineInstr &  MI, MachineBasicBlock *  BB, const RISCVSubtarget &  Subtarget  )

static

Definition at line 7874 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::any_of(), BB, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineInstr::collectDebugValues(), llvm::SmallSet< T, N, C >::count(), DL, E, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), I, llvm::SmallSet< T, N, C >::insert(), isSelectPseudo(), MI, llvm::MachineFunctionProperties::NoPHIs, llvm::MachineBasicBlock::push_back(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

emitSplitF64Pseudo()

static MachineBasicBlock* emitSplitF64Pseudo ( MachineInstr &  MI, MachineBasicBlock *  BB  )

static

Definition at line 7794 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), Align, assert(), BB, llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), MI, llvm::MachineMemOperand::MOLoad, llvm::HexagonInstrInfo::storeRegToStackSlot(), and TII.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

getContainerForFixedLengthVector() [1/2]

static MVT getContainerForFixedLengthVector ( const TargetLowering &  TLI, MVT  VT, const RISCVSubtarget &  Subtarget  )

static

Definition at line 1520 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::RISCVSubtarget::getMaxELENForFixedLengthVectors(), llvm::RISCVSubtarget::getMinRVVVectorSizeInBits(), llvm::MVT::getScalableVectorVT(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::MVT::isFixedLengthVector(), llvm::isPowerOf2_32(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::max(), llvm::RISCV::RVVBitsPerBlock, and llvm::MVT::SimpleTy.

Referenced by llvm::RISCVTargetLowering::getContainerForFixedLengthVector().

getContainerForFixedLengthVector() [2/2]

static MVT getContainerForFixedLengthVector ( SelectionDAG &  DAG, MVT  VT, const RISCVSubtarget &  Subtarget  )

static

Definition at line 1554 of file RISCVISelLowering.cpp.

References llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), and llvm::SelectionDAG::getTargetLoweringInfo().

getDefaultScalableVLOps()

static std::pair<SDValue, SDValue> getDefaultScalableVLOps ( MVT  VecVT, SDLoc  DL, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 1606 of file RISCVISelLowering.cpp.

References assert(), DL, getDefaultVLOps(), and llvm::MVT::isScalableVector().

getDefaultVLOps()

static std::pair<SDValue, SDValue> getDefaultVLOps ( MVT  VecVT, MVT  ContainerVT, SDLoc  DL, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 1592 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i1, llvm::MVT::isFixedLengthVector(), llvm::MVT::isScalableVector(), llvm::BitmaskEnumDetail::Mask(), llvm::RISCV::VLMaxSentinel, and llvm::RISCVISD::VMSET_VL.

Referenced by getDefaultScalableVLOps(), getRVVFPExtendOrRound(), lowerBUILD_VECTOR(), llvm::RISCVTargetLowering::LowerOperation(), lowerSPLAT_VECTOR(), and lowerVECTOR_SHUFFLE().

getIntrinsicForMaskedAtomicRMWBinOp()

static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp ( unsigned  XLen, AtomicRMWInst::BinOp  BinOp  )

static

Definition at line 9822 of file RISCVISelLowering.cpp.

References llvm::AtomicRMWInst::Add, llvm_unreachable, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, and llvm::AtomicRMWInst::Xchg.

Referenced by llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic().

getLMUL1VT()

static MVT getLMUL1VT ( MVT  VT )

static

Definition at line 4335 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::getScalableVectorVT(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), and llvm::RISCV::RVVBitsPerBlock.

getPrefTypeAlign()

static Align getPrefTypeAlign ( EVT  VT, SelectionDAG &  DAG  )

static

Definition at line 8927 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), and llvm::EVT::getTypeForEVT().

Referenced by llvm::SelectionDAG::CreateStackTemporary(), and llvm::RISCVTargetLowering::LowerCall().

getRISCVWOpcode()

static RISCVISD::NodeType getRISCVWOpcode ( unsigned  Opcode )

static

Definition at line 5635 of file RISCVISelLowering.cpp.

References llvm::RISCVISD::DIVUW, llvm::RISCVISD::DIVW, llvm::RISCVISD::GORC, llvm::RISCVISD::GORCW, llvm::RISCVISD::GREV, llvm::RISCVISD::GREVW, llvm_unreachable, llvm::RISCVISD::REMUW, llvm::RISCVISD::ROLW, llvm::RISCVISD::RORW, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::RISCVISD::SLLW, llvm::ISD::SRA, llvm::RISCVISD::SRAW, llvm::ISD::SRL, llvm::RISCVISD::SRLW, llvm::ISD::UDIV, and llvm::ISD::UREM.

Referenced by customLegalizeToWOp(), and llvm::RISCVTargetLowering::ReplaceNodeResults().

getRVVFPExtendOrRound()

static SDValue getRVVFPExtendOrRound ( SDValue  Op, MVT  VT, MVT  ContainerVT, SDLoc  DL, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 2426 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::bitsGT(), DL, llvm::RISCVISD::FP_EXTEND_VL, llvm::RISCVISD::FP_ROUND_VL, getDefaultVLOps(), llvm::SelectionDAG::getFPExtendOrRound(), llvm::SelectionDAG::getNode(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isScalableVector(), and llvm::BitmaskEnumDetail::Mask().

Referenced by llvm::RISCVTargetLowering::LowerOperation().

getRVVFPReductionOpAndOperands()

static std::tuple<unsigned, SDValue, SDValue> getRVVFPReductionOpAndOperands ( SDValue  Op, SelectionDAG &  DAG, EVT  EltVT  )

static

Definition at line 4503 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getNeutralElement(), llvm::ISD::getVecReduceBaseOpcode(), llvm_unreachable, llvm::ISD::VECREDUCE_FADD, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::ISD::VECREDUCE_FMAX, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::ISD::VECREDUCE_FMIN, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::ISD::VECREDUCE_SEQ_FADD, and llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL.

getRVVReductionOp()

static unsigned getRVVReductionOp ( unsigned  ISDOpcode )

static

Definition at line 4343 of file RISCVISelLowering.cpp.

References llvm_unreachable, llvm::ISD::VECREDUCE_ADD, llvm::RISCVISD::VECREDUCE_ADD_VL, llvm::ISD::VECREDUCE_AND, llvm::RISCVISD::VECREDUCE_AND_VL, llvm::ISD::VECREDUCE_OR, llvm::RISCVISD::VECREDUCE_OR_VL, llvm::ISD::VECREDUCE_SMAX, llvm::RISCVISD::VECREDUCE_SMAX_VL, llvm::ISD::VECREDUCE_SMIN, llvm::RISCVISD::VECREDUCE_SMIN_VL, llvm::ISD::VECREDUCE_UMAX, llvm::RISCVISD::VECREDUCE_UMAX_VL, llvm::ISD::VECREDUCE_UMIN, llvm::RISCVISD::VECREDUCE_UMIN_VL, llvm::ISD::VECREDUCE_XOR, and llvm::RISCVISD::VECREDUCE_XOR_VL.

getRVVVPReductionOp()

static unsigned getRVVVPReductionOp ( unsigned  ISDOpcode )

static

Definition at line 4557 of file RISCVISelLowering.cpp.

References llvm_unreachable, llvm::RISCVISD::VECREDUCE_ADD_VL, llvm::RISCVISD::VECREDUCE_AND_VL, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::RISCVISD::VECREDUCE_OR_VL, llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL, llvm::RISCVISD::VECREDUCE_SMAX_VL, llvm::RISCVISD::VECREDUCE_SMIN_VL, llvm::RISCVISD::VECREDUCE_UMAX_VL, llvm::RISCVISD::VECREDUCE_UMIN_VL, and llvm::RISCVISD::VECREDUCE_XOR_VL.

getTargetNode() [1/4]

static SDValue getTargetNode ( BlockAddressSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 3189 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getTargetBlockAddress(), and N.

getTargetNode() [2/4]

static SDValue getTargetNode ( ConstantPoolSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 3195 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getTargetConstantPool(), and N.

getTargetNode() [3/4]

static SDValue getTargetNode ( GlobalAddressSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 3184 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getTargetGlobalAddress(), and N.

getTargetNode() [4/4]

static SDValue getTargetNode ( JumpTableSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 3201 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getTargetJumpTable(), and N.

isSelectPseudo()

static bool isSelectPseudo ( MachineInstr &  MI )

static

Definition at line 7862 of file RISCVISelLowering.cpp.

References MI.

Referenced by emitSelectPseudo().

isSimpleVIDSequence()

static Optional<VIDSequence> isSimpleVIDSequence ( SDValue  Op )

static

Definition at line 1752 of file RISCVISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, llvm::None, and llvm::SignExtend64().

Referenced by lowerBUILD_VECTOR().

lowerBUILD_VECTOR()

static SDValue lowerBUILD_VECTOR ( SDValue  Op, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 1829 of file RISCVISelLowering.cpp.

References llvm::abs(), llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::tgtok::Bits, llvm::MVT::bitsLE(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), llvm::count_if(), llvm::divideCeil(), DL, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplatBuildVector(), llvm::getSplatValue(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::insert(), llvm::ISD::INSERT_VECTOR_ELT, llvm::RISCVSubtarget::is64Bit(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::isInt< 32 >(), llvm::MVT::isInteger(), llvm::isPowerOf2_32(), llvm::isPowerOf2_64(), isSimpleVIDSequence(), llvm::SDValue::isUndef(), llvm::Log2_32(), llvm::Log2_64(), llvm::BitmaskEnumDetail::Mask(), llvm::max(), llvm::min(), llvm::ISD::MUL, llvm::ISD::SETNE, llvm::ISD::SHL, llvm::SelectionDAG::shouldOptForSize(), llvm::SignExtend64(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::size(), llvm::ISD::SRL, llvm::ISD::SUB, llvm::transform(), llvm::MVT::v1i8, llvm::MVT::v8i1, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VID_VL, llvm::RISCVISD::VMCLR_VL, llvm::RISCVISD::VMSET_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::ISD::VSELECT.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerCTLZ_CTTZ_ZERO_UNDEF()

static SDValue lowerCTLZ_CTTZ_ZERO_UNDEF ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 2443 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::LegacyLegalizeActions::Bitcast, llvm::MVT::changeVectorElementTypeToInteger(), llvm::ISD::CTTZ_ZERO_UNDEF, DL, llvm::MVT::f32, llvm::MVT::f64, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::TargetLoweringBase::isTypeLegal(), Shift, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::TRUNCATE, and llvm::ISD::UINT_TO_FP.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerFP_TO_INT_SAT()

static SDValue lowerFP_TO_INT_SAT ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 1633 of file RISCVISelLowering.cpp.

References DL, llvm::RISCVISD::FCVT_W_RTZ_RV64, llvm::RISCVISD::FCVT_WU_RTZ_RV64, llvm::RISCVISD::FCVT_X_RTZ, llvm::RISCVISD::FCVT_XU_RTZ, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::MVT::i32, llvm::MVT::i64, and llvm::ISD::SETUO.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerFTRUNC_FCEIL_FFLOOR()

static SDValue lowerFTRUNC_FCEIL_FFLOOR ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 1664 of file RISCVISelLowering.cpp.

References llvm::lltok::APFloat, assert(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::APFloat::convertFromAPInt(), DL, llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FFLOOR, llvm::ISD::FP_TO_SINT, llvm::ISD::FREEZE, llvm::ISD::FSUB, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::MVT::i1, llvm::MVT::isVector(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), llvm::ISD::SETOGT, llvm::ISD::SETOLT, and llvm::ISD::SINT_TO_FP.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerScalarSplat()

static SDValue lowerScalarSplat ( SDValue  Scalar, SDValue  VL, MVT  VT, SDLoc  DL, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 2178 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), DL, llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::isFloatingPoint(), llvm::ISD::SIGN_EXTEND, splatSplitI64WithVL(), llvm::RISCVISD::VFMV_V_F_VL, and llvm::RISCVISD::VMV_V_X_VL.

Referenced by lowerVECTOR_SHUFFLE().

lowerSPLAT_VECTOR()

static SDValue lowerSPLAT_VECTOR ( SDValue  Op, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 1719 of file RISCVISelLowering.cpp.

References assert(), convertFromScalableVector(), DL, llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::BitmaskEnumDetail::Mask(), llvm::RISCVISD::VFMV_V_F_VL, and llvm::RISCVISD::VMV_V_X_VL.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerVECTOR_SHUFFLE()

static SDValue lowerVECTOR_SHUFFLE ( SDValue  Op, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 2205 of file RISCVISelLowering.cpp.

References llvm::all_of(), assert(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::begin(), llvm::MVT::bitsGT(), llvm::MVT::changeTypeToInteger(), llvm::MVT::changeVectorElementType(), llvm::ISD::CONCAT_VECTORS, convertFromScalableVector(), convertToScalableVector(), DL, llvm::enumerate(), llvm::TypeSize::Fixed(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtLoad(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getScalarType(), llvm::SDValue::getSimpleValueType(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getSplatValue(), llvm::MVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i1, llvm::MVT::i16, int, llvm::ISD::INTRINSIC_W_CHAIN, llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), llvm::ISD::isNormalLoad(), llvm::ShuffleVectorSDNode::isSplat(), llvm::SelectionDAG::isSplatValue(), llvm::SDValue::isUndef(), lowerScalarSplat(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), Offset, llvm::MVT::Other, llvm::ISD::SEXTLOAD, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::size(), std::swap(), llvm::NVPTX::PTXLdStInstCode::V2, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_V_X_VL, llvm::RISCVISD::VRGATHER_VV_VL, llvm::RISCVISD::VRGATHER_VX_VL, llvm::RISCVISD::VRGATHEREI16_VV_VL, llvm::ISD::VSELECT, and llvm::RISCVISD::VSELECT_VL.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerVectorIntrinsicSplats()

static SDValue lowerVectorIntrinsicSplats ( SDValue  Op, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 3995 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLT(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasVInstructions(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isInt< 32 >(), llvm::MVT::isScalarInteger(), Operands, llvm::ISD::SIGN_EXTEND, llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::SplatOperand, and splatSplitI64WithVL().

matchGREVIPat()

static Optional<RISCVBitmanipPat> matchGREVIPat ( SDValue  Op )

static

Definition at line 6318 of file RISCVISelLowering.cpp.

References matchRISCVBitmanipPat().

Referenced by combineORToGORC(), and combineORToGREV().

matchRISCVBitmanipPat()

static Optional<RISCVBitmanipPat> matchRISCVBitmanipPat ( SDValue  Op, ArrayRef< uint64_t >  BitmanipMasks  )

static

Definition at line 6242 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::MVT::i64, llvm::isPowerOf2_64(), llvm::Log2_32(), llvm::BitmaskEnumDetail::Mask(), llvm::None, llvm::ISD::SHL, llvm::ArrayRef< T >::size(), and llvm::ISD::SRL.

Referenced by matchGREVIPat(), and matchSHFLPat().

matchSHFLPat()

static Optional<RISCVBitmanipPat> matchSHFLPat ( SDValue  Op )

static

Definition at line 6424 of file RISCVISelLowering.cpp.

References matchRISCVBitmanipPat().

Referenced by combineORToSHFL().

performADDCombine()

static SDValue performADDCombine ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 6720 of file RISCVISelLowering.cpp.

References combineSelectAndUseCommutative(), N, transformAddImmMulImm(), and transformAddShlImm().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performANDCombine()

static SDValue performANDCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 6739 of file RISCVISelLowering.cpp.

References combineSelectAndUseCommutative(), and N.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performANY_EXTENDCombine()

static SDValue performANY_EXTENDCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const RISCVSubtarget &  Subtarget  )

static

Definition at line 6772 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::RISCVSubtarget::hasStdExtM(), llvm::MVT::i32, llvm::MVT::i64, llvm::RISCVSubtarget::is64Bit(), j(), LLVM_FALLTHROUGH, llvm::ISD::MUL, N, llvm::none_of(), llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND, and llvm::ISD::SUB.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performORCombine()

static SDValue performORCombine ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 6745 of file RISCVISelLowering.cpp.

References combineORToGORC(), combineORToGREV(), combineORToSHFL(), combineSelectAndUseCommutative(), llvm::RISCVISD::GORC, llvm::RISCVISD::GREV, llvm::RISCVSubtarget::hasStdExtZbp(), N, and llvm::RISCVISD::SHFL.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performSUBCombine()

static SDValue performSUBCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 6731 of file RISCVISelLowering.cpp.

References combineSelectAndUse(), and N.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performXORCombine()

static SDValue performXORCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 6761 of file RISCVISelLowering.cpp.

References combineSelectAndUseCommutative(), and N.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

preAssignMask()

template<typename ArgTy >

static Optional<unsigned> preAssignMask ( const ArgTy &  Args )

static

Definition at line 8348 of file RISCVISelLowering.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Key::Args, llvm::enumerate(), llvm::MVT::getVectorElementType(), llvm::MVT::i1, llvm::MVT::isVector(), and llvm::None.

Referenced by llvm::RISCVTargetLowering::CanLowerReturn().

splatPartsI64WithVL()

static SDValue splatPartsI64WithVL ( const SDLoc &  DL, MVT  VT, SDValue  Lo, SDValue  Hi, SDValue  VL, SelectionDAG &  DAG  )

static

Definition at line 2147 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), llvm::MipsISD::Hi, llvm::MipsISD::Lo, llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, and llvm::RISCVISD::VMV_V_X_VL.

Referenced by splatSplitI64WithVL().

splatSplitI64WithVL()

static SDValue splatSplitI64WithVL ( const SDLoc &  DL, MVT  VT, SDValue  Scalar, SDValue  VL, SelectionDAG &  DAG  )

static

Definition at line 2165 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::MipsISD::Lo, and splatPartsI64WithVL().

Referenced by lowerScalarSplat(), and lowerVectorIntrinsicSplats().

STATISTIC()

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"
	)

transformAddImmMulImm()

static SDValue transformAddImmMulImm ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 6676 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, C1, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::EVT::isVector(), llvm::ISD::MUL, and N.

Referenced by performADDCombine().

transformAddShlImm()

static SDValue transformAddShlImm ( SDNode *  N, SelectionDAG &  DAG, const RISCVSubtarget &  Subtarget  )

static

Definition at line 6510 of file RISCVISelLowering.cpp.

References llvm::abs(), llvm::ISD::ADD, llvm::tgtok::Bits, C1, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::RISCVSubtarget::hasStdExtZba(), llvm::EVT::isVector(), llvm::min(), N, NL, and llvm::ISD::SHL.

Referenced by performADDCombine().

translateSetCCForBranch()

static void translateSetCCForBranch ( const SDLoc &  DL, SDValue &  LHS, SDValue &  RHS, ISD::CondCode &  CC, SelectionDAG &  DAG  )

static

Definition at line 1282 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::ISD::getSetCCSwappedOperands(), llvm::SDValue::getValueType(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETUGT, llvm::ISD::SETULE, and std::swap().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

unpackF64OnRV32DSoftABI()

static SDValue unpackF64OnRV32DSoftABI ( SelectionDAG &  DAG, SDValue  Chain, const CCValAssign &  VA, const SDLoc &  DL  )

static

Definition at line 8513 of file RISCVISelLowering.cpp.

References llvm::MachineRegisterInfo::addLiveIn(), assert(), llvm::RISCVISD::BuildPairF64, llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::MVT::f64, llvm::SelectionDAG::getCopyFromReg(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getRegInfo(), llvm::CCValAssign::getValVT(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), and llvm::MipsISD::Lo.

Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().

unpackFromMemLoc()

static SDValue unpackFromMemLoc ( SelectionDAG &  DAG, SDValue  Chain, const CCValAssign &  VA, const SDLoc &  DL  )

static

Definition at line 8485 of file RISCVISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::CCValAssign::Full, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MVT::getIntegerVT(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::DataLayout::getPointerSizeInBits(), llvm::EVT::getStoreSize(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, llvm_unreachable, and llvm::ISD::NON_EXTLOAD.

Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().

unpackFromRegLoc()

static SDValue unpackFromRegLoc ( SelectionDAG &  DAG, SDValue  Chain, const CCValAssign &  VA, const SDLoc &  DL, const RISCVTargetLowering &  TLI  )

static

Definition at line 8441 of file RISCVISelLowering.cpp.

References llvm::MachineRegisterInfo::addLiveIn(), convertLocVTToValVT(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::SelectionDAG::getCopyFromReg(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MachineFunction::getRegInfo(), llvm::EVT::getSimpleVT(), llvm::RISCVTargetLowering::getSubtarget(), and llvm::CCValAssign::Indirect.

Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().

useRVVForFixedLengthVectorVT()

static bool useRVVForFixedLengthVectorVT ( MVT  VT, const RISCVSubtarget &  Subtarget  )

static

Definition at line 1448 of file RISCVISelLowering.cpp.

References assert(), llvm::divideCeil(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::getFixedSizeInBits(), llvm::RISCVSubtarget::getMaxELENForFixedLengthVectors(), llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors(), llvm::RISCVSubtarget::getMinRVVVectorSizeInBits(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::hasVInstructionsF16(), llvm::RISCVSubtarget::hasVInstructionsF32(), llvm::RISCVSubtarget::hasVInstructionsF64(), llvm::RISCVSubtarget::hasVInstructionsI64(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::MVT::isFixedLengthVector(), llvm::MVT::isPow2VectorType(), llvm::MVT::SimpleTy, and llvm::RISCVSubtarget::useRVVForFixedLengthVectors().

Variable Documentation

ArgFPR16s

const MCPhysReg ArgFPR16s[]

static

Initial value:

= {
  RISCV::F10_H, RISCV::F11_H, RISCV::F12_H, RISCV::F13_H,
  RISCV::F14_H, RISCV::F15_H, RISCV::F16_H, RISCV::F17_H
}

Definition at line 8047 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV().

ArgFPR32s

const MCPhysReg ArgFPR32s[]

static

Initial value:

= {
  RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F,
  RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F
}

Definition at line 8051 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV().

ArgFPR64s

const MCPhysReg ArgFPR64s[]

static

Initial value:

= {
  RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D,
  RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D
}

Definition at line 8055 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV().

ArgGPRs

const MCPhysReg ArgGPRs[]

static

Initial value:

= {
  RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13,
  RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
}

Definition at line 8043 of file RISCVISelLowering.cpp.

Referenced by llvm::CC_CSKY_ABIV2_SOFT_64(), CC_RISCV(), CC_RISCVAssign2XLen(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerFormalArguments(), and llvm::Ret_CSKY_ABIV2_SOFT_64().

ArgVRM2s

const MCPhysReg ArgVRM2s[]

static

Initial value:

= {RISCV::V8M2,  RISCV::V10M2, RISCV::V12M2,
                                     RISCV::V14M2, RISCV::V16M2, RISCV::V18M2,
                                     RISCV::V20M2, RISCV::V22M2}

Definition at line 8064 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

ArgVRM4s

const MCPhysReg ArgVRM4s[]

static

Initial value:

= {RISCV::V8M4, RISCV::V12M4, RISCV::V16M4,
                                     RISCV::V20M4}

Definition at line 8067 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

ArgVRM8s

const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8}

static

Definition at line 8069 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

ArgVRs

const MCPhysReg ArgVRs[]

static

Initial value:

= {
    RISCV::V8,  RISCV::V9,  RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13,
    RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19,
    RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23}

Definition at line 8060 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().