#include "RISCVISelLowering.h"#include "MCTargetDesc/RISCVMatInt.h"#include "RISCV.h"#include "RISCVConstantPoolValue.h"#include "RISCVMachineFunctionInfo.h"#include "RISCVRegisterInfo.h"#include "RISCVSelectionDAGInfo.h"#include "RISCVSubtarget.h"#include "llvm/ADT/SmallSet.h"#include "llvm/ADT/SmallVector.h"#include "llvm/ADT/Statistic.h"#include "llvm/Analysis/MemoryLocation.h"#include "llvm/Analysis/ValueTracking.h"#include "llvm/Analysis/VectorUtils.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineJumpTableInfo.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/SDPatternMatch.h"#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"#include "llvm/CodeGen/ValueTypes.h"#include "llvm/IR/DiagnosticInfo.h"#include "llvm/IR/DiagnosticPrinter.h"#include "llvm/IR/IRBuilder.h"#include "llvm/IR/Instructions.h"#include "llvm/IR/IntrinsicInst.h"#include "llvm/IR/IntrinsicsRISCV.h"#include "llvm/MC/MCCodeEmitter.h"#include "llvm/MC/MCInstBuilder.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/InstructionCost.h"#include "llvm/Support/KnownBits.h"#include "llvm/Support/MathExtras.h"#include "llvm/Support/raw_ostream.h"#include <optional>#include "RISCVGenAsmMatcher.inc"#include "RISCVGenSearchableTables.inc"Go to the source code of this file.
Classes | |
| struct | VIDSequence |
Namespaces | |
| namespace | llvm |
| This is an optimization pass for GlobalISel generic memory operations. | |
| namespace | llvm::RISCVVIntrinsicsTable |
Macros | |
| #define | DEBUG_TYPE "riscv-lower" |
| #define | OP_CASE(NODE) |
| #define | VP_CASE(NODE) |
| #define | CC_VLS_CASE(ABI_VLEN) |
| #define | GET_REGISTER_MATCHER |
| #define | GET_RISCVVIntrinsicsTable_IMPL |
Variables | |
| static cl::opt< unsigned > | ExtensionMaxWebSize (DEBUG_TYPE "-ext-max-web-size", cl::Hidden, cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion"), cl::init(18)) |
| static cl::opt< bool > | AllowSplatInVW_W (DEBUG_TYPE "-form-vw-w-with-splat", cl::Hidden, cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants"), cl::init(false)) |
| static cl::opt< unsigned > | NumRepeatedDivisors (DEBUG_TYPE "-fp-repeated-divisors", cl::Hidden, cl::desc("Set the minimum number of repetitions of a divisor to allow " "transformation to multiplications by the reciprocal"), cl::init(2)) |
| static cl::opt< int > | FPImmCost (DEBUG_TYPE "-fpimm-cost", cl::Hidden, cl::desc("Give the maximum number of instructions that we will " "use for creating a floating-point immediate value"), cl::init(3)) |
| static cl::opt< bool > | ReassocShlAddiAdd ("reassoc-shl-addi-add", cl::Hidden, cl::desc("Swap add and addi in cases where the add may " "be combined with a shift"), cl::init(true)) |
| static const unsigned | ZvfbfaOps [] |
| const uint64_t | ModeMask64 = ~RISCVExceptFlags::ALL |
| const uint32_t | ModeMask32 = ~RISCVExceptFlags::ALL |
Macro Definition Documentation
◆ CC_VLS_CASE
| #define CC_VLS_CASE | ( | ABI_VLEN | ) |
◆ DEBUG_TYPE
| #define DEBUG_TYPE "riscv-lower" |
Definition at line 56 of file RISCVISelLowering.cpp.
◆ GET_REGISTER_MATCHER
| #define GET_REGISTER_MATCHER |
Definition at line 26075 of file RISCVISelLowering.cpp.
◆ GET_RISCVVIntrinsicsTable_IMPL
| #define GET_RISCVVIntrinsicsTable_IMPL |
Definition at line 26314 of file RISCVISelLowering.cpp.
◆ OP_CASE
| #define OP_CASE | ( | NODE | ) |
Referenced by getRISCVVLOp().
◆ VP_CASE
| #define VP_CASE | ( | NODE | ) |
Referenced by getRISCVVLOp().
Function Documentation
◆ combine_CC()
|
static |
Definition at line 19573 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::cast(), llvm::ISD::Constant, DL, llvm::dyn_cast(), llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueSizeInBits(), llvm::RISCVSubtarget::getXLenVT(), llvm::isa(), llvm::isInt(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::isPowerOf2_64(), LHS, llvm::Log2_64(), llvm::SelectionDAG::MaskedValueIsZero(), RHS, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, translateSetCCForBranch(), tryDemorganOfBooleanCondition(), and llvm::ISD::XOR.
◆ combineAddOfBooleanXor()
|
static |
Definition at line 16120 of file RISCVISelLowering.cpp.
References DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getNegative(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::SelectionDAG::MaskedValueIsZero(), N, SDValue(), and llvm::ISD::XOR.
Referenced by performADDCombine().
◆ combineANDOfSETCCToCZERO()
|
static |
Definition at line 16629 of file RISCVISelLowering.cpp.
References llvm::cast(), llvm::SelectionDAG::computeKnownBits(), DL, llvm::KnownBits::getMaxValue(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::RISCVSubtarget::hasCZEROLike(), llvm::SDValue::hasOneUse(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), N, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETNE, std::swap(), and llvm::APInt::ugt().
Referenced by performANDCombine().
◆ combineBinOpOfExtractToReduceTree()
|
static |
Perform two related transforms whose purpose is to incrementally recognize an explode_vector followed by scalar reduction as a vector reduction node.
This exists to recover from a deficiency in SLP which can't handle forests with multiple roots sharing common nodes. In some cases, one of the trees will be vectorized, and the other will remain (unprofitably) scalarized.
Definition at line 15600 of file RISCVISelLowering.cpp.
References assert(), llvm::cast(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::SelectionDAG::getContext(), llvm::RISCVSubtarget::getELen(), llvm::SelectionDAG::getExtractSubvector(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::ISD::getVecReduceBaseOpcode(), getVecReduceOpcode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::hasVInstructions(), llvm::isa(), llvm::EVT::isInteger(), llvm::isNullConstant(), llvm::EVT::isScalableVector(), LHS, N, llvm::SelectionDAG::NewNodesMustHaveLegalTypes, Opc, RHS, SDValue(), and std::swap().
Referenced by performADDCombine(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performORCombine(), and performXORCombine().
◆ combineBinOpOfZExt()
|
static |
Definition at line 16078 of file RISCVISelLowering.cpp.
References llvm::CallingConv::C, llvm::SelectionDAG::getContext(), llvm::EVT::getHalfSizedIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), N, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SUB, and llvm::ISD::ZERO_EXTEND.
Referenced by performADDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performMULCombine(), and performSUBCombine().
◆ combineBinOpToReduce()
|
static |
Definition at line 15702 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, llvm::ISD::AND, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_SUBVECTOR, llvm::isNeutralConstant(), isNonZeroAVL(), llvm::isNullConstant(), llvm::SDNode::isUndef(), llvm_unreachable, lowerScalarInsert(), N, Opc, llvm::ISD::OR, SDValue(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMAX, llvm::ISD::UMIN, and llvm::ISD::XOR.
Referenced by performADDCombine(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performORCombine(), and performXORCombine().
◆ combineDeMorganOfBoolean()
|
static |
Definition at line 16301 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::SelectionDAG::MaskedValueIsZero(), N, Opc, llvm::ISD::OR, SDValue(), and llvm::ISD::XOR.
Referenced by performANDCombine(), and performORCombine().
◆ combineMinMaxToSat()
|
static |
Definition at line 21031 of file RISCVISelLowering.cpp.
References llvm::APInt::countr_one(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SDValue::getConstantOperandAPInt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), N, SDValue(), llvm::ISD::SMAX, llvm::ISD::SMIN, and std::swap().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ combineNarrowableShiftedLoad()
|
static |
Definition at line 16703 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::EVT::getSizeInBits(), llvm::APInt::getZExtValue(), llvm::EVT::isScalarInteger(), llvm::ISD::LOAD, llvm::APInt::lshr(), llvm::PatternMatch::m_And(), llvm::SDPatternMatch::m_ConstInt(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Shl(), llvm::SDPatternMatch::m_SpecificOpc(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), and llvm::ISD::SHL.
Referenced by performANDCombine().
◆ combineOp_VLToVWOp_VL()
|
static |
Combine a binary or FMA operation to its equivalent VW or VW_W form.
The supported combines are: add | add_vl | or disjoint | or_vl disjoint -> vwadd(u) | vwadd(u)_w sub | sub_vl -> vwsub(u) | vwsub(u)_w mul | mul_vl -> vwmul(u) | vwmul_su shl | shl_vl -> vwsll fadd_vl -> vfwadd | vfwadd_w fsub_vl -> vfwsub | vfwsub_w fmul_vl -> vfwmul vwadd_w(u) -> vwadd(u) vwsub_w(u) -> vwsub(u) vfwadd_w -> vfwadd vfwsub_w -> vfwsub
Definition at line 18489 of file RISCVISelLowering.cpp.
References assert(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::SmallPtrSetImpl< PtrType >::contains(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), ExtensionMaxWebSize, llvm::Use::getOperandNo(), llvm::Use::getUser(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), LHS, N, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::reserve(), RHS, SDValue(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and std::swap().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine(), performSHLCombine(), performVFMADD_VLCombine(), and performVWADDSUBW_VLCombine().
◆ combineOrAndToBitfieldInsert()
|
static |
Definition at line 16906 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::SelectionDAG::computeKnownBits(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getSExtValue(), llvm::SelectionDAG::getSignedConstant(), llvm::APInt::isShiftedMask(), llvm::APInt::isSubsetOf(), llvm::PatternMatch::m_And(), llvm::SDPatternMatch::m_ConstInt(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Or(), llvm::SDPatternMatch::m_SpecificVT(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), and llvm::KnownBits::Zero.
Referenced by performORCombine().
◆ combineOrOfCZERO()
|
static |
Definition at line 16793 of file RISCVISelLowering.cpp.
References assert(), Cond, llvm::SDNodeFlags::Disjoint, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::isOneConstant(), N, llvm::ISD::OR, SDValue(), and llvm::ISD::XOR.
Referenced by performORCombine().
◆ combineOrToBitfieldInsert()
|
static |
Definition at line 16868 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSignedConstant(), llvm::APInt::isShiftedMask(), llvm::APInt::isSignedIntN(), llvm::SDPatternMatch::m_ConstInt(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Or(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), and X.
Referenced by performORCombine().
◆ combinePExtTruncate()
|
static |
Definition at line 16419 of file RISCVISelLowering.cpp.
References A(), llvm::ISD::ADD, B(), llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::dyn_cast(), llvm::dyn_cast_or_null(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::BuildVectorSDNode::getSplatValue(), LHS, llvm::ISD::MUL, N, Opc, RHS, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::Splat, llvm::ISD::SRL, llvm::ISD::SUB, std::swap(), and llvm::ISD::ZERO_EXTEND.
Referenced by performTRUNCATECombine().
◆ combineSelectAndUse()
|
static |
Definition at line 15925 of file RISCVISelLowering.cpp.
References llvm::AllOnes, llvm::ISD::AND, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::hasConditionalMoveFusion(), llvm::RISCVSubtarget::hasCZEROLike(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::isNullConstant(), llvm::EVT::isVector(), isZeroOrAllOnes(), N, SDValue(), llvm::ISD::SELECT, and std::swap().
◆ combineSelectAndUseCommutative()
|
static |
Definition at line 15988 of file RISCVISelLowering.cpp.
References llvm::AllOnes, combineSelectAndUse(), N, and SDValue().
◆ combineShlAddIAdd()
|
static |
Definition at line 15893 of file RISCVISelLowering.cpp.
References combineShlAddIAddImpl(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasShlAdd(), N, llvm::Other, ReassocShlAddiAdd, and SDValue().
Referenced by performADDCombine().
◆ combineShlAddIAddImpl()
|
static |
Definition at line 15854 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::APInt::getSExtValue(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getTargetConstant(), llvm::APInt::getZExtValue(), llvm::isa(), llvm::PatternMatch::m_Add(), llvm::SDPatternMatch::m_ConstInt(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Shl(), llvm::PatternMatch::m_Value(), N, llvm::Other, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::APInt::sgt(), llvm::APInt::slt(), and llvm::SDNode::use_size().
Referenced by combineShlAddIAdd().
◆ combineSubOfBoolean()
|
static |
Definition at line 16170 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::cast(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::EVT::isInteger(), llvm::isOneConstant(), llvm::APInt::isSignedIntN(), N, SDValue(), llvm::ISD::SETCC, and llvm::ISD::XOR.
Referenced by performSUBCombine().
◆ combineSubShiftToOrcB()
|
static |
Definition at line 16214 of file RISCVISelLowering.cpp.
References llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::APInt::getSplat(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDValue::hasOneUse(), llvm::SelectionDAG::MaskedValueIsZero(), N, SDValue(), llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by performSUBCombine().
◆ combineToVCPOP()
|
static |
Definition at line 20884 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::RISCVTargetLowering::computeVLMAX(), convertToScalableVector(), llvm::ISD::CTPOP, DL, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::EVT::getFixedSizeInBits(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealMaxVLen(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::MVT::isFixedLengthVector(), llvm::EVT::isScalarInteger(), llvm::EVT::isSimple(), llvm::TargetLoweringBase::isTypeLegal(), llvm::MVT::isVector(), llvm::Log2_32(), N, Opc, SDValue(), llvm::ISD::VECREDUCE_ADD, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ combineToVWMACC()
|
static |
Definition at line 20448 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, assert(), DL, getDefaultScalableVLOps(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSelectionDAGInfo(), llvm::SDValue::isUndef(), N, Opc, SDValue(), and std::swap().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ combineTruncOfSraSext()
|
static |
Definition at line 20694 of file RISCVISelLowering.cpp.
References llvm::cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isa(), llvm::isAllOnesConstant(), llvm::EVT::isVector(), N, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SMIN, llvm::SMin, llvm::ISD::SRA, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ combineTruncSelectToSMaxUSat()
|
static |
Definition at line 16351 of file RISCVISelLowering.cpp.
References llvm::cast(), Cond, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isConstOrConstSplat(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::ConstantSDNode::isZero(), N, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETULT, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::TRUNCATE, and llvm::ISD::VSELECT.
Referenced by performTRUNCATECombine().
◆ combineTruncToVnclip()
|
static |
Definition at line 20748 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementType(), DL, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignedMinValue(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::isConstantSplatVector(), llvm::APInt::isMask(), llvm::APInt::isNonNegative(), llvm::isNullConstant(), N, Opc, SDValue(), llvm::APInt::sext(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::APInt::uge(), and llvm::ISD::UMIN.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ combineVdota4Accum()
|
static |
Definition at line 20513 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, assert(), DL, getDefaultScalableVLOps(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::isUndef(), N, Opc, SDValue(), and std::swap().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ combineVectorMulToSraBitcast()
|
static |
Definition at line 17276 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::BITCAST, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::ISD::isConstantSplatVector(), llvm::APInt::isMask(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), N, SDValue(), llvm::ISD::SRA, and llvm::ISD::SRL.
Referenced by performMULCombine().
◆ combineVectorSizedSetCCEquality()
|
static |
Try to map an integer comparison with size > XLEN to vector instructions before type legalization splits it up into chunks.
Definition at line 17431 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), llvm::Function::hasFnAttribute(), llvm::RISCVSubtarget::hasVInstructions(), llvm::isa(), llvm::EVT::isByteSized(), llvm::ISD::isIntEqualitySetCC(), llvm::EVT::isScalarInteger(), llvm::ISD::LOAD, llvm::peekThroughBitcasts(), SDValue(), llvm::ISD::SETNE, X, and Y.
Referenced by combineSetCC(), performSETCCCombine(), and performSETCCCombine().
◆ combineVFMADD_VLWithVFNEG_VL()
|
static |
Definition at line 19343 of file RISCVISelLowering.cpp.
References A(), B(), llvm::CallingConv::C, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectionDAGInfo(), llvm::SelectionDAGTargetInfo::isTargetStrictFPOpcode(), N, negateFMAOpcode(), llvm::Offset, and SDValue().
Referenced by performVFMADD_VLCombine().
◆ combineVWADDSUBWSelect()
|
static |
Definition at line 18606 of file RISCVISelLowering.cpp.
References assert(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::isConstantSplatVectorAllZeros(), llvm::isNullOrNullSplat(), llvm::SDValue::isUndef(), N, Opc, SDValue(), llvm::ISD::VSELECT, X, and Y.
Referenced by performVWADDSUBW_VLCombine().
◆ combineXorToBitfieldInsert()
|
static |
Definition at line 16832 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::sampleprof::Base, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::APInt::isShiftedMask(), llvm::PatternMatch::m_And(), llvm::SDPatternMatch::m_ConstInt(), llvm::PatternMatch::m_Deferred(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Xor(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::SDPatternMatch::sd_match(), SDValue(), and llvm::ISD::SRA.
Referenced by performXORCombine().
◆ compressShuffleOfShuffles()
|
static |
Definition at line 5468 of file RISCVISelLowering.cpp.
References llvm::cast(), DL, llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::SDValue::hasOneUse(), SDValue(), llvm::seq(), and llvm::ISD::VECTOR_SHUFFLE.
Referenced by performVECTOR_SHUFFLECombine().
◆ computeGREVOrGORC()
Definition at line 22739 of file RISCVISelLowering.cpp.
Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(), and llvm::RISCVTargetLowering::SimplifyDemandedBitsForTargetNode().
◆ convertFromScalableVector()
|
static |
Definition at line 3239 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getExtractSubvector(), and llvm::EVT::isFixedLengthVector().
◆ convertLocVTToValVT()
|
static |
Definition at line 23937 of file RISCVISelLowering.cpp.
References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertFromScalableVector(), DL, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::MVT::isScalableVector(), llvm_unreachable, and llvm::CCValAssign::needsCustom().
◆ convertToScalableVector()
|
static |
Definition at line 3228 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getUNDEF(), and llvm::EVT::isScalableVector().
◆ convertValVTToLocVT()
|
static |
Definition at line 23998 of file RISCVISelLowering.cpp.
References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertToScalableVector(), DL, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::isFixedLengthVector(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm_unreachable, and llvm::CCValAssign::needsCustom().
◆ customLegalizeToWOp()
|
static |
Definition at line 14644 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), getRISCVWOpcode(), N, and llvm::ISD::TRUNCATE.
◆ customLegalizeToWOpWithSExt()
|
static |
Definition at line 14657 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), N, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::TRUNCATE.
◆ emitBuildPairF64Pseudo()
|
static |
Definition at line 23257 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), llvm::RISCVSubtarget::isLittleEndian(), MI, llvm::MachineMemOperand::MOStore, Register, std::swap(), and TII.
◆ emitFROUND()
|
static |
Definition at line 23672 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::MachineBasicBlock::end(), F, llvm::RISCVSubtarget::getInstrInfo(), I, llvm::RISCVSubtarget::is64Bit(), llvm_unreachable, MBB, MI, llvm::MachineInstr::NoFPExcept, llvm::MachineInstr::setFlag(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
◆ EmitLoweredCascadedSelect()
|
static |
Definition at line 23340 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::First, llvm::MachineBasicBlock::getBasicBlock(), llvm::RISCVCC::getBrCond(), llvm::getImm(), llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by emitSelectPseudo().
◆ emitQuietFCMP()
|
static |
Definition at line 23303 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::Kill, MI, llvm::MachineInstr::NoFPExcept, llvm::MachineInstr::setFlag(), and TII.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
◆ emitReadCounterWidePseudo()
|
static |
Definition at line 23153 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getBasicBlock(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::insert(), MI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
◆ emitSelectPseudo()
|
static |
Definition at line 23443 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::any_of(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineInstr::collectDebugValues(), llvm::SmallSet< T, N, C >::count(), DL, E(), EmitLoweredCascadedSelect(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::RISCVCC::getBrCond(), llvm::getImm(), llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), I, llvm::SmallSet< T, N, C >::insert(), llvm::MachineBasicBlock::instr_end(), LHS, MI, llvm::Next, llvm::next_nodbg(), llvm::MachineBasicBlock::push_back(), RHS, llvm::MachineBasicBlock::setCallFrameSize(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
◆ emitSplitF64Pseudo()
|
static |
Definition at line 23218 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), assert(), llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), llvm::RISCVSubtarget::isLittleEndian(), MI, llvm::MachineMemOperand::MOLoad, std::swap(), and TII.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
◆ emitVFROUND_NOEXCEPT_MASK()
|
static |
Definition at line 23609 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::RISCVII::getLMul(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::RISCVII::getSEWOpNum(), llvm::MachineFunction::getSubtarget(), llvm::Kill, lookupMaskedIntrinsic(), llvm::RISCV::RISCVMaskedPseudoInfo::MaskedPseudo, MI, TII, and TRI.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
◆ expandMul()
|
static |
Definition at line 17175 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::countr_zero(), DL, llvm::dyn_cast(), expandMulToAddOrSubOfShl(), expandMulToNAFSequence(), expandMulToShlAddShlAdd(), llvm::SelectionDAG::getConstant(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::ConstantSDNode::getZExtValue(), llvm::Function::hasMinSize(), llvm::RISCVSubtarget::hasShlAdd(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isInt(), llvm::isPowerOf2_64(), llvm::Log2_64(), N, llvm::Offset, SDValue(), llvm::ISD::SHL, llvm::ISD::SUB, and X.
Referenced by performMULCombine().
◆ expandMulToAddOrSubOfShl()
|
static |
Definition at line 17067 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::isPowerOf2_64(), llvm::Log2_64(), llvm::SDPatternMatch::m_ExactSr(), llvm::PatternMatch::m_SpecificInt(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SHL, llvm::ISD::SUB, and X.
Referenced by expandMul().
◆ expandMulToNAFSequence()
|
static |
Definition at line 17042 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::BitWidth, DL, E(), llvm::SelectionDAG::getConstant(), llvm::EVT::getFixedSizeInBits(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getShiftAmountConstant(), I, N, llvm::ISD::SHL, and llvm::ISD::SUB.
Referenced by expandMul().
◆ expandMulToShlAddShlAdd()
|
static |
Definition at line 17128 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), getShlAddShlAdd(), llvm::SelectionDAG::getTargetConstant(), llvm::isShifted359(), N, SDValue(), llvm::ISD::SHL, and X.
Referenced by expandMul().
◆ foldBinOpIntoSelectIfProfitable()
|
static |
Definition at line 9638 of file RISCVISelLowering.cpp.
References DL, llvm::dyn_cast(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SDNode::getAsAPIntVal(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSelect(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::isa(), llvm::APInt::isAllOnes(), llvm::ConstantSDNode::isOpaque(), llvm::APInt::isZero(), SDValue(), llvm::ISD::SELECT, and std::swap().
◆ foldConcatVector()
If concat_vector(V1,V2) could be folded away to some existing vector source, return it.
Note that the source may be larger than the requested concat_vector (i.e. a extract_subvector might be required.)
Definition at line 5116 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::isScalableVector(), and SDValue().
Referenced by getSingleShuffleSrc().
◆ foldReduceOperandViaVDOTA4()
|
static |
Definition at line 20090 of file RISCVISelLowering.cpp.
References A(), B(), DL, foldReduceOperandViaVDOTA4(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getQDOTXResultType(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), getZeroPaddedAdd(), llvm::ISD::isExtOpcode(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownMultipleOf(), llvm::TargetLoweringBase::isTypeLegal(), llvm::PatternMatch::m_AddLike(), llvm::PatternMatch::m_Mul(), llvm::PatternMatch::m_Value(), Opc, llvm::ISD::PARTIAL_REDUCE_SMLA, llvm::ISD::PARTIAL_REDUCE_SUMLA, llvm::ISD::PARTIAL_REDUCE_UMLA, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SIGN_EXTEND, std::swap(), and llvm::ISD::ZERO_EXTEND.
Referenced by foldReduceOperandViaVDOTA4(), and performVECREDUCECombine().
◆ foldSelectOfCTTZOrCTLZ()
|
static |
Definition at line 19774 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::BitWidth, llvm::cast(), Cond, llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::isNullConstant(), llvm::isPowerOf2_32(), N, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by performSELECTCombine().
◆ foldSelectToUSATI()
|
static |
Definition at line 19926 of file RISCVISelLowering.cpp.
References llvm::EVT::bitsGE(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::EVT::isScalarInteger(), llvm::PatternMatch::m_AllOnes(), llvm::PatternMatch::m_Select(), llvm::SDPatternMatch::m_SetCC(), llvm::PatternMatch::m_SExt(), llvm::PatternMatch::m_Specific(), llvm::SDPatternMatch::m_SpecificCondCode(), llvm::PatternMatch::m_SpecificInt(), llvm::SDPatternMatch::m_SpecificVT(), llvm::PatternMatch::m_Trunc(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SETGT, llvm::ISD::SETUGT, llvm::ISD::SIGN_EXTEND, and llvm::ISD::TRUNCATE.
Referenced by performSELECTCombine().
◆ getAllOnesMask()
Creates an all ones mask suitable for masking a vector of type VecTy with vector length VL.
Definition at line 3260 of file RISCVISelLowering.cpp.
References DL, getMaskTypeFor(), and llvm::SelectionDAG::getNode().
Referenced by getDefaultScalableVLOps(), getDefaultVLOps(), lowerVectorIntrinsicScalars(), and lowerVZIP().
◆ getContainerForFixedLengthVector() [1/2]
|
static |
Definition at line 3182 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVSubtarget::getELen(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalableVectorVT(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::isFixedLengthVector(), llvm::isPowerOf2_32(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::RISCV::RVVBitsPerBlock, llvm::MVT::SimpleTy, and useRVVForFixedLengthVectorVT().
◆ getContainerForFixedLengthVector() [2/2]
|
static |
Definition at line 3217 of file RISCVISelLowering.cpp.
References getContainerForFixedLengthVector(), and llvm::SelectionDAG::getTargetLoweringInfo().
◆ getDefaultScalableVLOps()
|
static |
Definition at line 3267 of file RISCVISelLowering.cpp.
References assert(), DL, getAllOnesMask(), llvm::SelectionDAG::getRegister(), llvm::RISCVSubtarget::getXLenVT(), and llvm::MVT::isScalableVector().
Referenced by combineToVWMACC(), combineVdota4Accum(), getDefaultVLOps(), and performSHLCombine().
◆ getDefaultVLOps() [1/2]
|
static |
Definition at line 3289 of file RISCVISelLowering.cpp.
References assert(), DL, getDefaultScalableVLOps(), getDefaultVLOps(), llvm::MVT::getVectorNumElements(), llvm::MVT::isFixedLengthVector(), and llvm::MVT::isScalableVector().
◆ getDefaultVLOps() [2/2]
|
static |
Definition at line 3276 of file RISCVISelLowering.cpp.
References assert(), DL, getAllOnesMask(), llvm::SelectionDAG::getConstant(), llvm::RISCVSubtarget::getXLenVT(), and llvm::MVT::isScalableVector().
Referenced by combineToVCPOP(), getDefaultVLOps(), getWideningInterleave(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaVID(), lowerCttzElts(), lowerFMAXIMUM_FMINIMUM(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT_XROUND(), lowerVZIP(), matchSplatAsGather(), performFP_TO_INTCombine(), and llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getDeinterleaveShiftAndTrunc()
|
static |
Definition at line 5275 of file RISCVISelLowering.cpp.
References llvm::MVT::changeVectorElementType(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getInsertSubvector(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::ISD::SRL, and llvm::ISD::TRUNCATE.
◆ getExactInteger()
Definition at line 3891 of file RISCVISelLowering.cpp.
References llvm::BitWidth, llvm::APFloat::convertToInteger(), llvm::APInt::extractBits(), llvm::APFloatBase::opInvalidOp, and llvm::TowardZero.
Referenced by isSimpleVIDSequence().
◆ getIntrinsicForMaskedAtomicRMWBinOp()
|
static |
Definition at line 25317 of file RISCVISelLowering.cpp.
References llvm::AtomicRMWInst::Add, llvm_unreachable, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, and llvm::AtomicRMWInst::Xchg.
◆ getLargeExternalSymbol()
|
static |
Definition at line 9258 of file RISCVISelLowering.cpp.
References llvm::RISCVConstantPoolValue::Create(), DL, llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstantPool(), and N.
Referenced by llvm::RISCVTargetLowering::LowerCall().
◆ getLargeGlobalAddress()
|
static |
Definition at line 9248 of file RISCVISelLowering.cpp.
References llvm::RISCVConstantPoolValue::Create(), DL, llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstantPool(), and N.
Referenced by llvm::RISCVTargetLowering::LowerCall().
◆ getMaskTypeFor()
Return the type of the mask type suitable for masking the provided vector type.
This is simply an i1 element type vector of the same (possibly scalable) length.
Definition at line 3252 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), and llvm::MVT::isVector().
◆ getPACKOpcode()
|
static |
Definition at line 4510 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVSubtarget::is64Bit(), and llvm_unreachable.
Referenced by lowerBuildVectorViaPacking().
◆ getPrefTypeAlign()
|
static |
Definition at line 24348 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), and llvm::EVT::getTypeForEVT().
◆ getQDOTXResultType()
Definition at line 20063 of file RISCVISelLowering.cpp.
References assert(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownMultipleOf().
Referenced by foldReduceOperandViaVDOTA4().
◆ getRISCVVLOp()
Get a RISC-V target specified VL op for a given SDNode.
Definition at line 7476 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::ISD::FMA, llvm::ISD::FMAXIMUMNUM, llvm::ISD::FMAXNUM, llvm::ISD::FMINIMUMNUM, llvm::ISD::FMINNUM, llvm::ISD::LLRINT, llvm_unreachable, llvm::ISD::LRINT, llvm::ISD::MASKED_SDIV, llvm::ISD::MASKED_SREM, llvm::ISD::MASKED_UDIV, llvm::ISD::MASKED_UREM, OP_CASE, llvm::ISD::OR, ROTR, llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND, llvm::ISD::STRICT_FMA, VP_CASE, llvm::ISD::VSELECT, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ getRISCVWOpcode()
Definition at line 14616 of file RISCVISelLowering.cpp.
References llvm_unreachable, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::UDIV, and llvm::ISD::UREM.
◆ getRVVFPReductionOpAndOperands()
|
static |
Definition at line 12153 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getExtractVectorElt(), llvm_unreachable, llvm::ISD::VECREDUCE_FADD, llvm::ISD::VECREDUCE_FMAX, llvm::ISD::VECREDUCE_FMAXIMUM, llvm::ISD::VECREDUCE_FMIN, llvm::ISD::VECREDUCE_FMINIMUM, and llvm::ISD::VECREDUCE_SEQ_FADD.
◆ getRVVReductionOp()
Definition at line 11937 of file RISCVISelLowering.cpp.
References llvm_unreachable, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, and llvm::ISD::VECREDUCE_XOR.
◆ getShlAddShlAdd()
|
static |
Definition at line 17101 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::PatternMatch::m_And(), llvm::SDPatternMatch::m_AnyOf(), llvm::SDPatternMatch::m_ConstInt(), llvm::SDPatternMatch::m_ExactSr(), llvm::PatternMatch::m_SpecificInt(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), llvm::ISD::SHL, and X.
Referenced by expandMulToShlAddShlAdd().
◆ getSingleShuffleSrc()
Definition at line 5139 of file RISCVISelLowering.cpp.
References foldConcatVector(), llvm::SDValue::getValueType(), llvm::MVT::getVectorNumElements(), llvm::SDValue::isUndef(), and SDValue().
◆ getSmallestVTForIndex()
|
static |
Definition at line 10653 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::bitsGT(), DL, llvm::MVT::getDoubleNumVectorElementsVT(), llvm::RISCVTargetLowering::getM1VT(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::isScalableVector(), and llvm::MVT::isValid().
◆ getTargetNode() [1/4]
|
static |
Definition at line 9231 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getTargetBlockAddress(), and N.
◆ getTargetNode() [2/4]
|
static |
Definition at line 9237 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getTargetConstantPool(), and N.
◆ getTargetNode() [3/4]
|
static |
Definition at line 9226 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getTargetGlobalAddress(), and N.
◆ getTargetNode() [4/4]
|
static |
Definition at line 9243 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getTargetJumpTable(), and N.
◆ getVCIXISDNodeVOID()
|
inlinestatic |
Definition at line 11641 of file RISCVISelLowering.cpp.
References llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::SmallVectorImpl< T >::erase(), llvm::SelectionDAG::getNode(), and processVCIXOperands().
◆ getVCIXISDNodeWCHAIN()
|
inlinestatic |
Definition at line 11604 of file RISCVISelLowering.cpp.
References llvm::SmallVectorTemplateCommon< T, typename >::begin(), convertFromScalableVector(), DL, llvm::SmallVectorImpl< T >::erase(), llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getSubtarget(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), and processVCIXOperands().
◆ getVecReduceOpcode()
Given a binary operator, return the associative generic ISD::VECREDUCE_OP which corresponds to it.
Definition at line 15563 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::FADD, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm_unreachable, Opc, llvm::ISD::OR, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_FADD, llvm::ISD::VECREDUCE_FMAX, llvm::ISD::VECREDUCE_FMIN, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, llvm::ISD::VECREDUCE_XOR, and llvm::ISD::XOR.
Referenced by combineBinOpOfExtractToReduceTree().
◆ getVLOperand()
Definition at line 3093 of file RISCVISelLowering.cpp.
References assert(), II, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, and SDValue().
Referenced by lowerVectorIntrinsicScalars().
◆ getVSlidedown()
|
static |
Definition at line 3862 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDValue::isUndef(), llvm::RISCVVType::MASK_AGNOSTIC, llvm::Offset, llvm::RISCVVType::TAIL_AGNOSTIC, and llvm::RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED.
Referenced by lowerBUILD_VECTOR(), lowerVECTOR_SHUFFLEAsVSlidedown(), and llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getVSlideup()
|
static |
Definition at line 3874 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDValue::isUndef(), llvm::RISCVVType::MASK_AGNOSTIC, llvm::Offset, llvm::RISCVVType::TAIL_AGNOSTIC, and llvm::RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED.
Referenced by lowerBUILD_VECTOR(), lowerVECTOR_SHUFFLEAsVSlideup(), and llvm::RISCVTargetLowering::PerformDAGCombine().
◆ getWideningInterleave()
|
static |
Definition at line 5693 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeTypeToInteger(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), getWideningSpread(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::SDValue::isUndef(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::multiplyCoefficientBy().
◆ getWideningSpread()
|
static |
Definition at line 5668 of file RISCVISelLowering.cpp.
References llvm::MVT::changeTypeToInteger(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::ISD::SHL, and llvm::ISD::ZERO_EXTEND.
Referenced by getWideningInterleave().
◆ getZeroPaddedAdd()
Given fixed length vectors A and B with equal element types, but possibly different number of elements, return A + B where either A or B is zero padded to the larger number of elements.
Definition at line 20072 of file RISCVISelLowering.cpp.
References A(), llvm::ISD::ADD, assert(), B(), DL, llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), and std::swap().
Referenced by foldReduceOperandViaVDOTA4().
◆ isAlternating()
|
static |
Definition at line 5222 of file RISCVISelLowering.cpp.
References assert(), llvm::CallingConv::C, and llvm::enumerate().
Referenced by isPairEven(), and isPairOdd().
◆ isCompressMask()
Definition at line 6011 of file RISCVISelLowering.cpp.
References llvm::enumerate(), and llvm::Last.
◆ isElementRotate()
|
static |
Definition at line 5214 of file RISCVISelLowering.cpp.
Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal().
◆ isInterleaveShuffle()
|
static |
Is this shuffle interleaving contiguous elements from one vector into the even elements and contiguous elements from another vector into the odd elements.
EvenSrc will contain the element that should be in the first even element. OddSrc will contain the element that should be in the first odd element. These can be the first element in a source or the element half way through the source.
Definition at line 5160 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::ShuffleVectorInst::isInterleaveMask(), and Size.
Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal().
◆ isLegalBitRotate()
|
static |
Definition at line 5836 of file RISCVISelLowering.cpp.
References llvm::MVT::getIntegerVT(), llvm::EVT::getScalarSizeInBits(), llvm::RISCVSubtarget::getTargetLowering(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ShuffleVectorInst::isBitRotateMask(), and llvm::TargetLoweringBase::isTypeLegal().
Referenced by lowerShuffleViaVRegSplitting(), and lowerVECTOR_SHUFFLEAsRotate().
◆ isLocalRepeatingShuffle()
Is this mask local (i.e.
elements only move within their local span), and repeating (that is, the same rearrangement is being done within each span)?
Definition at line 6093 of file RISCVISelLowering.cpp.
References llvm::enumerate(), and I.
◆ isLowSourceShuffle()
Is this mask only using elements from the first span of the input?
Definition at line 6110 of file RISCVISelLowering.cpp.
References llvm::all_of().
◆ isMaskedSlidePair()
|
static |
Is this mask representing a masked combination of two slides?
Definition at line 5195 of file RISCVISelLowering.cpp.
References assert(), llvm::isMaskedSlidePair(), and std::swap().
◆ isNonZeroAVL()
Definition at line 12060 of file RISCVISelLowering.cpp.
References llvm::dyn_cast().
Referenced by combineBinOpToReduce(), and lowerReductionSeq().
◆ isPairEven()
|
static |
Given a shuffle which can be represented as a pair of two slides, see if it is a pair-even idiom.
Pair-even is: vs2: a0 a1 a2 a3 vs1: b0 b1 b2 b3 vd: a0 b0 a2 b2
Definition at line 5246 of file RISCVISelLowering.cpp.
References isAlternating(), and llvm::isPowerOf2_32().
◆ isPairOdd()
|
static |
Given a shuffle which can be represented as a pair of two slides, see if it is a pair-odd idiom.
Pair-odd is: vs2: a0 a1 a2 a3 vs1: b0 b1 b2 b3 vd: a1 b1 a3 b3 Note that the operand order is swapped due to the way we canonicalize the slides, so SrCInfo[0] is vs1, and SrcInfo[1] is vs2.
Definition at line 5262 of file RISCVISelLowering.cpp.
References isAlternating(), and llvm::isPowerOf2_32().
◆ isPromotedOpNeedingSplit()
|
static |
Definition at line 7599 of file RISCVISelLowering.cpp.
References llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::hasVInstructionsBF16(), llvm::RISCVSubtarget::hasVInstructionsBF16Minimal(), llvm::RISCVSubtarget::hasVInstructionsF16(), llvm::RISCVSubtarget::hasVInstructionsF16Minimal(), llvm::is_contained(), llvm::TargetLoweringBase::isTypeLegal(), llvm::MVT::isVector(), and ZvfbfaOps.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ isSimm12Constant()
Definition at line 9537 of file RISCVISelLowering.cpp.
References llvm::isa().
Referenced by lowerSelectToBinOp().
◆ isSimpleVIDSequence()
|
static |
Definition at line 3924 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, llvm::cast(), llvm::enumerate(), getExactInteger(), llvm::APInt::getSExtValue(), isConstant(), llvm::APInt::sdiv(), and llvm::APInt::srem().
Referenced by lowerBuildVectorViaVID(), and llvm::RISCVTargetLowering::PerformDAGCombine().
◆ isSpanSplatShuffle()
Return true for a mask which performs an arbitrary shuffle within the first span, and then repeats that same result across all remaining spans.
Note that this doesn't check if all the inputs come from a single span!
Definition at line 6117 of file RISCVISelLowering.cpp.
References llvm::enumerate(), and I.
◆ isValidEGW()
|
inlinestatic |
◆ legalizeScatterGatherIndexType()
|
static |
Definition at line 20577 of file RISCVISelLowering.cpp.
References llvm::EVT::bitsLT(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getSubtarget(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::UNSIGNED_SCALED.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ lookupMaskedIntrinsic()
|
static |
Definition at line 23599 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVVInversePseudosTable::getBaseInfo(), and llvm::Masked.
Referenced by emitVFROUND_NOEXCEPT_MASK().
◆ LowerATOMIC_FENCE()
|
static |
Definition at line 7199 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::ISD::MEMBARRIER, llvm::SequentiallyConsistent, llvm::SyncScope::SingleThread, and llvm::SyncScope::System.
◆ lowerBitreverseShuffle()
|
static |
Definition at line 5786 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BITREVERSE, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getInsertSubvector(), llvm::EVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getSimpleValueType(), llvm::RISCVSubtarget::getTargetLowering(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::ShuffleVectorInst::isReverseMask(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::PowerOf2Ceil(), SDValue(), llvm::ArrayRef< T >::size(), and llvm::ISD::SRL.
◆ lowerBUILD_VECTOR()
|
static |
Definition at line 4587 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::all_of(), llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ArrayRef(), assert(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::ISD::BITCAST, llvm::MVT::bitsLE(), llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::cast(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), llvm::count_if(), DL, llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::enumerate(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtractSubvector(), llvm::MVT::getFixedSizeInBits(), llvm::RISCVSubtarget::getFLen(), llvm::SelectionDAG::getInsertSubvector(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::RISCVTargetLowering::getLMUL(), llvm::RISCVTargetLowering::getM1VT(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealVLen(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplatBuildVector(), llvm::getSplatValue(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorMinNumElements(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), getVSlidedown(), getVSlideup(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasVInstructionsBF16(), llvm::RISCVSubtarget::hasVInstructionsF16(), I, llvm::ISD::isBuildVectorOfConstantFPSDNodes(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::RISCVVType::LMUL_2, llvm::RISCVVType::LMUL_4, llvm::RISCVVType::LMUL_8, lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaPacking(), llvm::PatternMatch::m_ExtractElt(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Zero(), llvm::RISCVVType::MASK_AGNOSTIC, matchSplatAsGather(), llvm::Offset, Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::reserve(), llvm::ISD::SCALAR_TO_VECTOR, SDValue(), llvm::ISD::SETNE, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::Splat, llvm::RISCVVType::TAIL_AGNOSTIC, and llvm::ISD::VSELECT.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerBuildVectorOfConstants()
|
static |
Definition at line 4270 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLE(), llvm::cast(), llvm::MVT::changeVectorElementType(), llvm::SelectionDAG::ComputeMaxSignificantBits(), convertFromScalableVector(), convertToScalableVector(), llvm::divideCeil(), DL, llvm::enumerate(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::RISCVSubtarget::getELen(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getInsertVectorElt(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getSignedConstant(), llvm::MVT::getSizeInBits(), llvm::getSplatValue(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::RISCVSubtarget::is64Bit(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::isInt(), llvm::MVT::isInteger(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaVID(), llvm::maskTrailingOnes(), Opc, OpIdx, SDValue(), llvm::SelectionDAG::shouldOptForSize(), llvm::SignExtend64(), and llvm::Splat.
Referenced by lowerBUILD_VECTOR().
◆ lowerBuildVectorViaDominantValues()
|
static |
Try and optimize BUILD_VECTORs with "dominant values" - these are values which constitute a large proportion of the elements.
In such cases we can splat a vector with the dominant element and make up the shortfall with INSERT_VECTOR_ELTs. Returns SDValue if not profitable. Note that this includes vectors of 2 elements by association. The upper-most element is the "dominant" one, allowing us to use a splat to "insert" the upper element, and an insert of the lower element at position 0, which improves codegen.
Definition at line 4165 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), llvm::Count, llvm::count_if(), DL, llvm::dyn_cast(), llvm::enumerate(), llvm::SelectionDAG::getBuildVector(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getInsertVectorElt(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSplatBuildVector(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::Log2_32(), OpIdx, SDValue(), llvm::SelectionDAG::shouldOptForSize(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::size(), llvm::transform(), and llvm::ISD::VSELECT.
Referenced by lowerBUILD_VECTOR(), and lowerBuildVectorOfConstants().
◆ lowerBuildVectorViaPacking()
|
static |
Double the element size of the build vector to reduce the number of vslide1down in the build vector chain.
In the worst case, this trades three scalar operations for 1 vector operation. Scalar operations are generally lower latency, and for out-of-order cores we also benefit from additional parallelism.
Definition at line 4530 of file RISCVISelLowering.cpp.
References A(), llvm::ISD::AND, assert(), B(), llvm::ISD::BITCAST, llvm::SDNodeFlags::Disjoint, DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getIntegerVT(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), getPACKOpcode(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::ISD::OR, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::reserve(), SDValue(), llvm::ISD::SHL, and llvm::SmallVectorTemplateCommon< T, typename >::size().
Referenced by lowerBUILD_VECTOR().
◆ lowerBuildVectorViaVID()
|
static |
Definition at line 4085 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::MVT::changeVectorElementTypeToInteger(), convertFromScalableVector(), DL, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSignedConstant(), INT64_MIN, llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::isInt(), llvm::isPowerOf2_32(), llvm::isPowerOf2_64(), isSimpleVIDSequence(), llvm::isUInt(), llvm::Log2_64(), llvm::ISD::MUL, SDValue(), llvm::ISD::SHL, llvm::ISD::SINT_TO_FP, llvm::ISD::SRL, and llvm::ISD::SUB.
Referenced by lowerBuildVectorOfConstants(), and llvm::RISCVTargetLowering::LowerOperation().
◆ lowerConstant()
|
static |
Definition at line 7118 of file RISCVISelLowering.cpp.
References assert(), llvm::cast(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::RISCVMatInt::generateInstSeq(), llvm::RISCVMatInt::generateTwoRegInstSeq(), llvm::RISCVSubtarget::getMaxBuildIntsCost(), llvm::isInt(), SDValue(), llvm::SelectionDAG::shouldOptForSize(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and llvm::RISCVSubtarget::useConstantPoolForLargeInts().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerCttzElts()
|
static |
Definition at line 11288 of file RISCVISelLowering.cpp.
References convertToScalableVector(), llvm::ISD::CTTZ_ELTS_ZERO_POISON, DL, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getElementCount(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorElementCount(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), and llvm::ISD::SETLT.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerDisjointIndicesShuffle()
|
static |
Given a shuffle where the indices are disjoint between the two sources, e.g.:
t2:v4i8 = vector_shuffle t0:v4i8, t1:v4i8, <2, 7, 1, 4>
Merge the two sources into one and do a single source shuffle:
t2:v4i8 = vselect t1:v4i8, t0:v4i8, <0, 1, 0, 1> t3:v4i8 = vector_shuffle t2:v4i8, undef, <2, 3, 1, 0>
A vselect will either be merged into a masked instruction or be lowered as a vmerge.vvm, which is cheaper than a vrgather.vv.
Definition at line 6042 of file RISCVISelLowering.cpp.
References llvm::MVT::changeVectorElementType(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), Select, and llvm::ISD::VSELECT.
◆ lowerFABSorFNEG()
|
static |
Definition at line 7392 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, assert(), DL, llvm::ISD::FABS, llvm::ISD::FNEG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignMask(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), and llvm::ISD::XOR.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerFCOPYSIGN()
|
static |
Definition at line 7415 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, assert(), llvm::ISD::BITCAST, llvm::SDNodeFlags::Disjoint, DL, llvm::ISD::FCOPYSIGN, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignMask(), llvm::SDValue::getValueSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), llvm_unreachable, llvm::ISD::OR, llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerFixedVectorSegLoadIntrinsics()
|
static |
Definition at line 11651 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::cast(), convertFromScalableVector(), convertToScalableVector(), DL, getContainerForFixedLengthVector(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::MVT::getRISCVVectorTupleVT(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorMinNumElements(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INTRINSIC_W_CHAIN, llvm_unreachable, llvm::Log2_64(), llvm::RISCVVType::MASK_AGNOSTIC, Results, and llvm::RISCVVType::TAIL_AGNOSTIC.
◆ lowerFixedVectorSegStoreIntrinsics()
|
static |
Definition at line 11797 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::cast(), convertToScalableVector(), DL, getContainerForFixedLengthVector(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::MVT::getRISCVVectorTupleVT(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorMinNumElements(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INTRINSIC_VOID, llvm_unreachable, and llvm::Log2_64().
◆ lowerFMAXIMUM_FMINIMUM()
|
static |
Definition at line 7319 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::FMAXIMUM, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::MVT::isVector(), Opc, llvm::ISD::SETOEQ, X, and Y.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerFP_TO_INT()
|
static |
Definition at line 3539 of file RISCVISelLowering.cpp.
References DL, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::RISCVSubtarget::hasStdExtZfhOrZhinx(), and llvm::ISD::STRICT_FP_EXTEND.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerFP_TO_INT_SAT()
|
static |
Definition at line 3426 of file RISCVISelLowering.cpp.
References assert(), llvm::cast(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::FP_EXTEND, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::RISCVSubtarget::hasStdExtZfhOrZhinx(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), Opc, llvm::RISCVFPRndMode::RTZ, SDValue(), and llvm::ISD::SETUO.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerFTRUNC_FCEIL_FFLOOR_FROUND()
|
static |
Definition at line 3793 of file RISCVISelLowering.cpp.
References llvm::APFloat::convertFromAPInt(), DL, llvm::SelectionDAG::getConstantFP(), llvm::MVT::getFltSemantics(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isVector(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, SDValue(), llvm::APFloatBase::semanticsPrecision(), and llvm::SelectionDAG::shouldOptForSize().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerGetVectorLength()
|
static |
Definition at line 11253 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::RISCVVType::encodeLMUL(), llvm::RISCVVType::encodeSEW(), llvm::RISCVSubtarget::getELen(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isPowerOf2_32(), N, llvm::RISCV::RVVBitsPerBlock, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ lowerINT_TO_FP()
|
static |
Definition at line 3399 of file RISCVISelLowering.cpp.
References DL, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::RISCVSubtarget::hasStdExtZfhOrZhinx(), and llvm::ISD::STRICT_FP_ROUND.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ LowerPREFETCH()
|
static |
Definition at line 7188 of file RISCVISelLowering.cpp.
◆ lowerReductionSeq()
|
static |
Helper to lower a reduction sequence of the form: scalar = reduce_op vec, scalar_start.
Definition at line 12069 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::MVT::bitsLE(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getExtractVectorElt(), llvm::SelectionDAG::getInsertSubvector(), llvm::RISCVTargetLowering::getM1VT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), isNonZeroAVL(), lowerScalarInsert(), and llvm::RISCVVType::TAIL_AGNOSTIC.
◆ lowerScalarInsert()
|
static |
Definition at line 5062 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLE(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::isa(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::isNullConstant(), llvm::MVT::isScalableVector(), lowerScalarSplat(), and llvm::ISD::SIGN_EXTEND.
Referenced by combineBinOpToReduce(), and lowerReductionSeq().
◆ lowerScalarSplat()
|
static |
Definition at line 5008 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, llvm::MVT::changeVectorElementType(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasVInstructionsBF16(), llvm::RISCVSubtarget::hasVInstructionsF16(), llvm::isa(), llvm::MVT::isFloatingPoint(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::SDValue::isUndef(), lowerScalarSplat(), llvm::ISD::SIGN_EXTEND, llvm::Splat, and splatSplitI64WithVL().
Referenced by lowerScalarInsert(), lowerScalarSplat(), and llvm::RISCVTargetLowering::PerformDAGCombine().
◆ lowerSelectToBinOp()
|
static |
Definition at line 9541 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::cast(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getAllOnesConstant(), llvm::SDNode::getAsAPIntVal(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::hasConditionalMoveFusion(), llvm::RISCVSubtarget::hasCZEROLike(), llvm::RISCVSubtarget::hasShlAdd(), INT64_MIN, llvm::isa(), llvm::isAllOnesConstant(), llvm::isInt(), llvm::isNullConstant(), llvm::isPowerOf2_64(), llvm::MVT::isScalarInteger(), isSimm12Constant(), LHS, llvm::Log2_64(), matchSetCC(), N, llvm::ISD::OR, RHS, SDValue(), llvm::ISD::SETCC, and llvm::ISD::XOR.
◆ lowerShuffleViaVRegSplitting()
|
static |
Definition at line 5883 of file RISCVISelLowering.cpp.
References assert(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), convertToScalableVector(), llvm::Data, DL, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorTemplateCommon< T, typename >::end(), getContainerForFixedLengthVector(), llvm::MVT::getFixedSizeInBits(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::RISCVTargetLowering::getM1VT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::RISCVSubtarget::getRealVLen(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), llvm::MVT::getVectorMinNumElements(), llvm::MVT::getVectorVT(), isLegalBitRotate(), N, llvm::processShuffleMasks(), SDValue(), and llvm::SmallVectorTemplateCommon< T, typename >::size().
◆ lowerVECTOR_SHUFFLEAsRotate()
|
static |
Definition at line 5855 of file RISCVISelLowering.cpp.
References llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::getScalarType(), llvm::SDNode::getValueType(), isLegalBitRotate(), llvm::ISD::ROTL, and SDValue().
◆ lowerVECTOR_SHUFFLEAsVRGatherVX()
|
static |
Match a single source shuffle which is an identity except that some particular element is repeated.
This can be lowered as a masked vrgather.vi/vx. Note that the two source form of this is handled by the recursive splitting logic and doesn't need special handling.
Definition at line 5299 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::enumerate(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::SDValue::isUndef(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::Splat, and llvm::ISD::VSELECT.
◆ lowerVECTOR_SHUFFLEAsVSlide1()
|
static |
Match v(f)slide1up/down idioms.
These operations involve sliding N-1 elements to make room for an inserted scalar at one end.
Definition at line 5518 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::sampleprof::Base, llvm::cast(), llvm::MVT::changeVectorElementTypeToInteger(), convertFromScalableVector(), convertToScalableVector(), DL, E(), llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasVInstructionsBF16(), llvm::RISCVSubtarget::hasVInstructionsF16(), llvm::isa(), llvm::MVT::isFloatingPoint(), llvm::Offset, SDValue(), llvm::Splat, and std::swap().
◆ lowerVECTOR_SHUFFLEAsVSlidedown()
|
static |
Definition at line 5348 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getUNDEF(), getVSlidedown(), llvm::RISCVSubtarget::getXLenVT(), llvm::Offset, SDValue(), and llvm::SmallVectorTemplateCommon< T, typename >::size().
◆ lowerVECTOR_SHUFFLEAsVSlideup()
|
static |
Definition at line 5423 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorNumElements(), getVSlideup(), llvm::RISCVSubtarget::getXLenVT(), llvm::ShuffleVectorInst::isInsertSubvectorMask(), llvm::RISCVVType::MASK_AGNOSTIC, SDValue(), llvm::RISCVVType::TAIL_AGNOSTIC, and llvm::RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED.
◆ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
|
static |
Definition at line 3601 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::APFloat::convertFromAPInt(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::FCEIL, llvm::ISD::FFLOOR, llvm::ISD::FNEARBYINT, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FTRUNC, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstantFP(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getFltSemantics(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVFPRndMode::Invalid, llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), llvm_unreachable, matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), and llvm::ISD::SETOLT.
Referenced by lowerFTRUNC_FCEIL_FFLOOR_FROUND().
◆ lowerVectorIntrinsicScalars()
|
static |
Definition at line 11072 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::NumOps, llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLT(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::RISCVTargetLowering::computeVLMAXBounds(), DL, llvm::RISCVVType::encodeSEW(), getAllOnesMask(), llvm::SDNode::getAsZExtVal(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), getVLOperand(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasVInstructions(), II, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isa(), llvm::MVT::isScalarInteger(), llvm::SDValue::isUndef(), SDValue(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, splatSplitI64WithVL(), llvm::SelectionDAG::SplitScalar(), llvm::RISCVVType::TAIL_AGNOSTIC, and llvm::ISD::TRUNCATE.
◆ lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()
|
static |
Definition at line 3692 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::APFloat::convertFromAPInt(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstantFP(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getFltSemantics(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVFPRndMode::Invalid, llvm::MVT::isFixedLengthVector(), llvm_unreachable, matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), llvm::ISD::SETOLT, llvm::ISD::STRICT_FCEIL, llvm::ISD::STRICT_FFLOOR, llvm::ISD::STRICT_FNEARBYINT, llvm::ISD::STRICT_FROUND, llvm::ISD::STRICT_FROUNDEVEN, and llvm::ISD::STRICT_FTRUNC.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerVectorXRINT_XROUND()
|
static |
Definition at line 3821 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), DL, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), and matchRoundingOp().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerVZIP()
|
static |
Definition at line 5619 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::bitsGT(), llvm::MVT::bitsLT(), llvm::MVT::changeVectorElementTypeToInteger(), convertFromScalableVector(), convertToScalableVector(), DL, getAllOnesMask(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtractSubvector(), llvm::MVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getInsertSubvector(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::RISCVTargetLowering::getM1VT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::SDValue::isUndef(), and Opc.
◆ matchIndexAsShuffle()
|
static |
Match the index vector of a scatter or gather node as the shuffle mask which performs the rearrangement if possible.
Will only match if all lanes are touched, and thus replacing the scatter or gather with a unit strided access and shuffle is legal.
Definition at line 20612 of file RISCVISelLowering.cpp.
References llvm::BitVector::all(), assert(), llvm::CallingConv::C, llvm::EVT::getScalarStoreSize(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVectorAllOnes(), and llvm::BitVector::set().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ matchIndexAsWiderOp()
|
static |
Match the index of a gather or scatter operation as an operation with twice the element width and half the number of elements.
This is generally profitable (if legal) because these operations are linear in VL, so even if we cause some extract VTYPE/VL toggles, we still come out ahead.
Definition at line 20647 of file RISCVISelLowering.cpp.
References llvm::CallingConv::C, llvm::EVT::getScalarStoreSize(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVectorAllOnes(), and llvm::Last.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ matchRoundingOp()
|
static |
Definition at line 3564 of file RISCVISelLowering.cpp.
References llvm::RISCVFPRndMode::DYN, llvm::ISD::FCEIL, llvm::ISD::FFLOOR, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FTRUNC, llvm::RISCVFPRndMode::Invalid, llvm::ISD::LLRINT, llvm::ISD::LLROUND, llvm::ISD::LRINT, llvm::ISD::LROUND, Opc, llvm::RISCVFPRndMode::RDN, llvm::RISCVFPRndMode::RMM, llvm::RISCVFPRndMode::RNE, llvm::RISCVFPRndMode::RTZ, llvm::RISCVFPRndMode::RUP, llvm::ISD::STRICT_FCEIL, llvm::ISD::STRICT_FFLOOR, llvm::ISD::STRICT_FRINT, llvm::ISD::STRICT_FROUND, llvm::ISD::STRICT_FROUNDEVEN, llvm::ISD::STRICT_FTRUNC, llvm::ISD::STRICT_LLRINT, llvm::ISD::STRICT_LLROUND, llvm::ISD::STRICT_LRINT, and llvm::ISD::STRICT_LROUND.
Referenced by lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT_XROUND(), performFP_TO_INT_SATCombine(), and performFP_TO_INTCombine().
◆ matchSelectAddSub()
Definition at line 19867 of file RISCVISelLowering.cpp.
References A(), llvm::ISD::ADD, B(), llvm::ISD::SUB, and std::swap().
Referenced by performVECTOR_SHUFFLECombine(), and performVSELECTCombine().
◆ matchSetCC()
|
static |
Definition at line 9514 of file RISCVISelLowering.cpp.
References assert(), llvm::cast(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::ISD::getSetCCSwappedOperands(), llvm::SDValue::getValueType(), LHS, RHS, and llvm::ISD::SETCC.
◆ matchSplatAsGather()
|
static |
Definition at line 4030 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), convertToScalableVector(), DL, llvm::dyn_cast(), llvm::ISD::EXTRACT_VECTOR_ELT, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorMinNumElements(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLE(), llvm::TargetLoweringBase::isTypeLegal(), and SDValue().
Referenced by lowerBUILD_VECTOR(), and llvm::RISCVTargetLowering::PerformDAGCombine().
◆ narrowIndex()
|
static |
According to the property that indexed load/store instructions zero-extend their indices, try to narrow the type of index operand.
Definition at line 17363 of file RISCVISelLowering.cpp.
References llvm::EVT::bitsLT(), llvm::CallingConv::C, llvm::EVT::changeVectorElementType(), llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::countMaxActiveBits(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getRoundIntegerType(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::APInt::getZExtValue(), llvm::SDNode::hasOneUse(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVector(), N, llvm::SDNode::ops(), llvm::PowerOf2Ceil(), llvm::ISD::SHL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ negateFMAOpcode()
Definition at line 19305 of file RISCVISelLowering.cpp.
References llvm_unreachable.
Referenced by combineFMA(), combineFMADDSUB(), combineVFMADD_VLWithVFNEG_VL(), and llvm::X86TargetLowering::getNegatedExpression().
◆ performADDCombine()
|
static |
Definition at line 16143 of file RISCVISelLowering.cpp.
References combineAddOfBooleanXor(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBinOpToReduce(), combineSelectAndUseCommutative(), combineShlAddIAdd(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), N, transformAddImmMulImm(), and transformAddShlImm().
◆ performANDCombine()
|
static |
Definition at line 16744 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, combineANDOfSETCCToCZERO(), combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineDeMorganOfBoolean(), combineNarrowableShiftedLoad(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::isOneConstant(), N, reduceANDOfAtomicLoad(), reverseZExtICmpCombine(), llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
◆ performBITREVERSECombine()
|
static |
Definition at line 19087 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::has_single_bit(), llvm::EVT::isScalarInteger(), N, and SDValue().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performBUILD_VECTORCombine()
|
static |
If we have a build_vector where each lane is binop X, C, where C is a constant (but not necessarily the same constant on all lanes), form binop (build_vector x1, x2, ...), (build_vector c1, c2, c3, ..).
We assume that materializing a constant build vector will be no more expensive that performing O(n) binops.
Definition at line 20005 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::isa(), llvm::TargetLoweringBase::isBinOp(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::SelectionDAG::isSafeToSpeculativelyExecute(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and SDValue().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performCONCAT_VECTORSCombine()
|
static |
Definition at line 20260 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::cast(), llvm::MVT::changeVectorElementType(), DL, llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::LoadSDNode::getBasePtr(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getNegative(), llvm::getOffset(), llvm::GISelAddressing::BaseIndexOffset::getOffset(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSignedConstant(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getStridedLoadVP(), getValueType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVTargetLowering::isLegalStridedLoadStore(), llvm::ISD::isNormalLoad(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::BaseIndexOffset::match(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), and llvm::MemoryLocation::UnknownSize.
◆ performFP_TO_INT_SATCombine()
|
static |
Definition at line 19024 of file RISCVISelLowering.cpp.
References llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::RISCVFPRndMode::Invalid, llvm::TargetLoweringBase::isTypeLegal(), matchRoundingOp(), N, Opc, SDValue(), and llvm::ISD::SETUO.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performFP_TO_INTCombine()
|
static |
Definition at line 18925 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), convertToScalableVector(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::FP_TO_SINT, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVFPRndMode::Invalid, llvm::EVT::isFixedLengthVector(), llvm::MVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), matchRoundingOp(), N, Opc, llvm::RISCVFPRndMode::RTZ, SDValue(), and llvm::ISD::TRUNCATE.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performINSERT_VECTOR_ELTCombine()
|
static |
Definition at line 20190 of file RISCVISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, llvm::dyn_cast(), llvm::SelectionDAG::getInsertVectorElt(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_VECTOR_ELT, llvm::isa(), llvm::TargetLoweringBase::isBinOp(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::EVT::isScalableVector(), LHS, N, llvm::SDNode::ops(), RHS, and SDValue().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performMemPairCombine()
|
static |
Definition at line 18840 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), getExtensionType(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemoryVT(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MachineFunction::getSubtarget(), llvm::Use::getUser(), llvm::LSBaseSDNode::isIndexed(), llvm::isShiftedUInt(), llvm::MemSDNode::isSimple(), llvm::ISD::LOAD, N, SDValue(), tryMemPairCombine(), and llvm::SDNode::uses().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performMULCombine()
|
static |
Definition at line 17312 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, combineBinOpOfZExt(), combineVectorMulToSraBitcast(), DL, expandMul(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::isOneOrOneSplat(), llvm::EVT::isVector(), llvm::ISD::MUL, N, SDValue(), llvm::ISD::SUB, and std::swap().
◆ performORCombine()
|
static |
Definition at line 16950 of file RISCVISelLowering.cpp.
References combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineDeMorganOfBoolean(), combineOrAndToBitfieldInsert(), combineOrOfCZERO(), combineOrToBitfieldInsert(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), and N.
◆ performSELECTCombine()
|
static |
Definition at line 19979 of file RISCVISelLowering.cpp.
References foldSelectOfCTTZOrCTLZ(), foldSelectToUSATI(), llvm::RISCVSubtarget::hasConditionalMoveFusion(), N, SDValue(), tryFoldSelectIntoOp(), and useInversedSetcc().
◆ performSETCCCombine()
|
static |
Definition at line 17487 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::bit_width(), llvm::cast(), combineVectorSizedSetCCEquality(), llvm::SelectionDAG::ComputeMaxSignificantBits(), Cond, llvm::countr_one(), llvm::APInt::countr_zero(), llvm::countr_zero(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::APInt::getActiveBits(), llvm::SelectionDAG::getBoolConstant(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandAPInt(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::APInt::getSExtValue(), llvm::SelectionDAG::getSignedConstant(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::APInt::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::isInt(), llvm::isMask_64(), llvm::APInt::isNegatedPowerOf2(), llvm::isNullConstant(), llvm::isPowerOf2_32(), llvm::isUInt(), llvm::SelectionDAG::MaskedValueIsZero(), N, SDValue(), llvm::ISD::SETNE, llvm::APInt::sext(), llvm::ISD::SIGN_EXTEND_INREG, llvm::SignExtend64(), llvm::ISD::SRA, llvm::ISD::SRL, and llvm::APInt::trunc().
◆ performSHLCombine()
|
static |
Definition at line 20950 of file RISCVISelLowering.cpp.
References combineOp_VLToVWOp_VL(), llvm::ISD::Constant, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), getDefaultScalableVLOps(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::APInt::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::ISD::isConstantSplatVector(), LHS, llvm_unreachable, N, RHS, SDValue(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.
◆ performSIGN_EXTEND_INREGCombine()
|
static |
Definition at line 17590 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::EVT::bitsGE(), llvm::cast(), llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::countMaxActiveBits(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::MVT::getVT(), llvm::RISCVSubtarget::is64Bit(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::isAllOnesConstant(), N, Opc, SDValue(), llvm::ISD::SETCC, llvm::ISD::SHL, and llvm::ISD::XOR.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performSRACombine()
|
static |
Definition at line 19397 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::cast(), llvm::countr_zero(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getValueType(), llvm::RISCVSubtarget::getXLenVT(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::isa(), N, SDValue(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, Size, llvm::ISD::SRA, llvm::ISD::SUB, and llvm::SDNode::users().
◆ performSUBCombine()
|
static |
Definition at line 16267 of file RISCVISelLowering.cpp.
References llvm::cast(), combineBinOpOfZExt(), combineSelectAndUse(), combineSubOfBoolean(), combineSubShiftToOrcB(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isNullConstant(), N, llvm::ISD::SETCC, llvm::ISD::SETLT, and llvm::ISD::SRA.
◆ performTRUNCATECombine()
|
static |
Definition at line 16535 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, combinePExtTruncate(), combineTruncSelectToSMaxUSat(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), llvm::isa(), llvm::EVT::isFixedLengthVector(), N, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVECREDUCECombine()
|
static |
Definition at line 20176 of file RISCVISelLowering.cpp.
References DL, foldReduceOperandViaVDOTA4(), llvm::SelectionDAG::getNode(), N, SDValue(), and llvm::ISD::VECREDUCE_ADD.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVECTOR_SHUFFLECombine()
|
static |
Definition at line 20386 of file RISCVISelLowering.cpp.
References A(), llvm::ISD::ADD, assert(), B(), llvm::CallingConv::C, llvm::cast(), compressShuffleOfShuffles(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::RISCVSubtarget::getELen(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLogicalNOT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::EVT::isFloatingPoint(), llvm::isPowerOf2_64(), llvm::ShuffleVectorInst::isSelectMask(), llvm::RISCVTargetLowering::isShuffleMaskLegal(), llvm::TargetLoweringBase::isTypeLegal(), matchSelectAddSub(), N, llvm::narrowShuffleMaskElts(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::Sub, and llvm::ISD::VSELECT.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVFMADD_VLCombine()
|
static |
Definition at line 19382 of file RISCVISelLowering.cpp.
References combineOp_VLToVWOp_VL(), combineVFMADD_VLWithVFNEG_VL(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getSelectionDAGInfo(), llvm::SelectionDAGTargetInfo::isTargetStrictFPOpcode(), N, and SDValue().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVP_REVERSECombine()
|
static |
Definition at line 19104 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::sampleprof::Base, llvm::LocationSize::beforeOrAfterPointer(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getStridedLoadVP(), llvm::SDValue::getValue(), llvm::EVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::EVT::isByteSized(), llvm::isOneOrOneSplat(), llvm::ISD::MUL, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), and llvm::ISD::SUB.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVP_STORECombine()
|
static |
Definition at line 19161 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::sampleprof::Base, llvm::LocationSize::beforeOrAfterPointer(), llvm::cast(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getStridedStoreVP(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDValue::hasOneUse(), llvm::EVT::isByteSized(), llvm::isOneOrOneSplat(), llvm::ISD::MUL, N, SDValue(), and llvm::ISD::SUB.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVP_TRUNCATECombine()
|
static |
Definition at line 19226 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::drop_end(), llvm::find_if(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), I, llvm::isOneOrOneSplat(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), LHS, N, llvm::Other, SDValue(), llvm::ISD::SRL, std::swap(), and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVSELECTCombine()
|
static |
Convert vselect CC, (add a, b), (sub a, b) to add a, (vselect CC, -b, b).
This allows us match a vadd.vv fed by a masked vrsub, which reduces register pressure over the add followed by masked vsub sequence.
Definition at line 19890 of file RISCVISelLowering.cpp.
References A(), llvm::ISD::ADD, B(), DL, llvm::SelectionDAG::getLogicalNOT(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::SDNode::getValueType(), matchSelectAddSub(), N, SDValue(), llvm::Sub, and llvm::ISD::VSELECT.
◆ performVWABDACombine()
|
static |
Definition at line 18650 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getVectorElementType(), llvm::SDNode::isUndef(), N, and SDValue().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVWABDACombineWV()
|
static |
Definition at line 18694 of file RISCVISelLowering.cpp.
References llvm::ISD::ABDS, llvm::ISD::ABDU, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getVectorElementType(), llvm::SDNode::isUndef(), N, Opc, SDValue(), and std::swap().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVWADDSUBW_VLCombine()
|
static |
Definition at line 18766 of file RISCVISelLowering.cpp.
References assert(), combineOp_VLToVWOp_VL(), combineVWADDSUBWSelect(), llvm::TargetLowering::DAGCombinerInfo::DAG, N, and Opc.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performXORCombine()
|
static |
Definition at line 16982 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::cast(), combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineSelectAndUseCommutative(), combineXorToBitfieldInsert(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), llvm::isa(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::TargetLoweringBase::isOperationLegal(), N, llvm::ISD::ROTL, llvm::ISD::SETCC, llvm::ISD::SETLT, llvm::ISD::SHL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
◆ processVCIXOperands()
|
static |
Definition at line 11347 of file RISCVISelLowering.cpp.
References convertToScalableVector(), llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getSubtarget(), llvm::MVT::getVectorVT(), and promoteVCIXScalar().
Referenced by getVCIXISDNodeVOID(), and getVCIXISDNodeWCHAIN().
◆ promoteVCIXScalar()
|
inlinestatic |
Definition at line 11311 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLT(), DL, llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::MachineFunction::getSubtarget(), llvm::RISCVSubtarget::getXLenVT(), II, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::isa(), llvm::MVT::isScalarInteger(), and llvm::ISD::SIGN_EXTEND.
Referenced by processVCIXOperands().
◆ reduceANDOfAtomicLoad()
|
static |
Definition at line 16665 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::ATOMIC_LOAD, llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getAtomicLoad(), llvm::AtomicSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::MemSDNode::getSuccessOrdering(), llvm::SDValue::getValue(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::isStrongerThanMonotonic(), llvm::maskTrailingOnes(), N, llvm::TargetLowering::DAGCombinerInfo::recursivelyDeleteUnusedNodes(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), and llvm::ISD::ZEXTLOAD.
Referenced by performANDCombine().
◆ reverseZExtICmpCombine()
|
static |
Definition at line 16583 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::APInt::getZExtValue(), llvm::RISCVSubtarget::hasVInstructions(), llvm::EVT::isVector(), llvm::PatternMatch::m_And(), llvm::SDPatternMatch::m_ConstInt(), llvm::MIPatternMatch::m_Not(), llvm::PatternMatch::m_One(), llvm::MIPatternMatch::m_OneUse(), llvm::SDPatternMatch::m_Srl(), llvm::PatternMatch::m_Trunc(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SETEQ, llvm::ISD::SETNE, X, and llvm::ISD::ZERO_EXTEND.
Referenced by performANDCombine().
◆ simplifyOp_VL()
Definition at line 18457 of file RISCVISelLowering.cpp.
References A(), assert(), B(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::isConstantSplatVectorAllZeros(), llvm::SDValue::isUndef(), N, and SDValue().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ splatPartsI64WithVL()
|
static |
Definition at line 4948 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::cast(), DL, llvm::SDNode::getAsZExtVal(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::Hi, llvm::isa(), llvm::isUInt(), llvm::Lo, and llvm::ISD::SRA.
Referenced by splatSplitI64WithVL().
◆ splatSplitI64WithVL()
|
static |
Definition at line 4996 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::Hi, llvm::Lo, splatPartsI64WithVL(), and llvm::SelectionDAG::SplitScalar().
Referenced by lowerScalarSplat(), and lowerVectorIntrinsicScalars().
◆ SplitStrictFPVectorOp()
|
static |
Definition at line 7657 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), and llvm::SelectionDAG::SplitVector().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ SplitVectorOp()
|
static |
Definition at line 7617 of file RISCVISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::GetSplitDestVTs(), and llvm::SelectionDAG::SplitVector().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ SplitVectorReductionOp()
|
static |
Definition at line 7642 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::Hi, llvm::Lo, llvm::SelectionDAG::SplitEVL(), and llvm::SelectionDAG::SplitVector().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ STATISTIC()
| STATISTIC | ( | NumTailCalls | , |
| "Number of tail calls" | ) |
◆ transformAddImmMulImm()
|
static |
Definition at line 16018 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSignedConstant(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::isInt(), llvm::EVT::isVector(), llvm::ISD::MUL, N, and SDValue().
Referenced by performADDCombine().
◆ transformAddShlImm()
|
static |
Definition at line 15809 of file RISCVISelLowering.cpp.
References DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::RISCVSubtarget::hasShlAdd(), llvm::EVT::isVector(), N, SDValue(), and llvm::ISD::SHL.
Referenced by performADDCombine().
◆ translateSetCCForBranch()
|
static |
Definition at line 2776 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::bit_width(), llvm::CallingConv::C, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::getSetCCSwappedOperands(), llvm::SelectionDAG::getSignedConstant(), INT64_MAX, llvm::isa(), llvm::isInt(), llvm::isMask_64(), llvm::isNullConstant(), llvm::isPowerOf2_64(), llvm::isUInt(), LHS, llvm::Log2_64(), RHS, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SHL, and std::swap().
◆ tryDemorganOfBooleanCondition()
|
static |
Definition at line 19514 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::cast(), Cond, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::EVT::isScalarInteger(), llvm::SelectionDAG::MaskedValueIsZero(), Opc, llvm::ISD::OR, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETLT, std::swap(), llvm::ISD::XOR, and llvm::Xor.
Referenced by combine_CC().
◆ tryFoldSelectIntoOp()
|
static |
Definition at line 19720 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNeutralElement(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SDValue::getValueType(), N, Opc, llvm::ISD::OR, llvm::ISD::ROTL, llvm::ISD::ROTR, SDValue(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, std::swap(), llvm::ISD::UMAX, llvm::ISD::UMIN, and llvm::ISD::XOR.
Referenced by performSELECTCombine().
◆ tryMemPairCombine()
|
static |
Definition at line 18782 of file RISCVISelLowering.cpp.
References llvm::cast(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::MachineMemOperand::getPointerInfo(), llvm::MachineFunction::getSubtarget(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDNode::hasPredecessorHelper(), llvm::ISD::LOAD, llvm::SelectionDAG::ReplaceAllUsesWith(), SDValue(), and llvm::ISD::ZEXTLOAD.
Referenced by performMemPairCombine().
◆ tryWidenMaskForShuffle()
|
static |
Try to widen element type to get a new mask value for a better permutation sequence.
This doesn't try to inspect the widened mask for profitability; we speculate the widened form is equal or better. This has the effect of reducing mask constant sizes - allowing cheaper materialization sequences
- and index sequence sizes - reducing register pressure and materialization cost, at the cost of (possibly) an extra VTYPE toggle.
Definition at line 6136 of file RISCVISelLowering.cpp.
References llvm::cast(), DL, llvm::SelectionDAG::getBitcast(), llvm::MVT::getFixedSizeInBits(), llvm::MVT::getFloatingPointVT(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), llvm::MVT::isFloatingPoint(), llvm::TargetLoweringBase::isTypeLegal(), SDValue(), and llvm::widenShuffleMaskElts().
◆ unpackF64OnRV32DSoftABI()
|
static |
Definition at line 24048 of file RISCVISelLowering.cpp.
References assert(), llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::SelectionDAG::getCopyFromReg(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getRegInfo(), llvm::SelectionDAG::getSubtarget(), llvm::CCValAssign::getValVT(), llvm::Hi, llvm::RISCVSubtarget::isLittleEndian(), llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), llvm::Lo, and std::swap().
Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().
◆ unpackFromMemLoc()
|
static |
Definition at line 24028 of file RISCVISelLowering.cpp.
References convertLocVTToValVT(), llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::SelectionDAG::getDataLayout(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::DataLayout::getPointerSizeInBits(), llvm::EVT::getStoreSize(), llvm::RISCVTargetLowering::getSubtarget(), and llvm::CCValAssign::Indirect.
◆ unpackFromRegLoc()
|
static |
Definition at line 23965 of file RISCVISelLowering.cpp.
References llvm::RISCVMachineFunctionInfo::addSExt32Register(), llvm::BitWidth, convertLocVTToValVT(), DL, llvm::Function::getArg(), llvm::SelectionDAG::getCopyFromReg(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::Type::getIntegerBitWidth(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MachineFunction::getRegInfo(), llvm::EVT::getSimpleVT(), llvm::RISCVTargetLowering::getSubtarget(), llvm::Value::getType(), llvm::CCValAssign::Indirect, and llvm::Type::isIntegerTy().
◆ useInversedSetcc()
|
static |
Definition at line 19836 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::cast(), Cond, DL, llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::RISCVSubtarget::hasBEXTILike(), llvm::RISCVSubtarget::hasCZEROLike(), llvm::isa(), llvm::isNullConstant(), llvm::APInt::isPowerOf2(), llvm::EVT::isScalarInteger(), llvm::APInt::isSignedIntN(), LHS, N, RHS, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETEQ, and llvm::ISD::SETNE.
Referenced by performSELECTCombine().
◆ useRVVForFixedLengthVectorVT()
|
static |
Definition at line 3106 of file RISCVISelLowering.cpp.
References assert(), llvm::divideCeil(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getFixedSizeInBits(), llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::hasVInstructionsBF16Minimal(), llvm::RISCVSubtarget::hasVInstructionsF16Minimal(), llvm::RISCVSubtarget::hasVInstructionsF32(), llvm::RISCVSubtarget::hasVInstructionsF64(), llvm::RISCVSubtarget::hasVInstructionsI64(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isPow2VectorType(), llvm::MVT::SimpleTy, and llvm::RISCVSubtarget::useRVVForFixedLengthVectors().
Referenced by getContainerForFixedLengthVector().
◆ useTpOffset()
|
static |
Definition at line 25989 of file RISCVISelLowering.cpp.
References llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateConstGEP1_32(), llvm::IRBuilderBase::GetInsertBlock(), llvm::IRBuilderBase::getInt8Ty(), llvm::BasicBlock::getModule(), llvm::Intrinsic::getOrInsertDeclaration(), llvm::IRBuilderBase::getPtrTy(), and llvm::Offset.
Referenced by llvm::RISCVTargetLowering::getIRStackGuard().
◆ widenVectorOpsToi8()
|
static |
Definition at line 12684 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementType(), DL, llvm::SmallVectorTemplateCommon< T, typename >::front(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), I, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SETNE, llvm::SmallVectorTemplateCommon< T, typename >::size(), and llvm::ISD::ZERO_EXTEND.
Variable Documentation
◆ AllowSplatInVW_W
|
static |
◆ ExtensionMaxWebSize
|
static |
Referenced by combineOp_VLToVWOp_VL().
◆ FPImmCost
|
static |
Referenced by llvm::RISCVTargetLowering::isFPImmLegal().
◆ ModeMask32
Definition at line 14558 of file RISCVISelLowering.cpp.
◆ ModeMask64
Definition at line 14557 of file RISCVISelLowering.cpp.
◆ NumRepeatedDivisors
|
static |
◆ ReassocShlAddiAdd
|
static |
Referenced by combineShlAddIAdd().
◆ ZvfbfaOps
Definition at line 91 of file RISCVISelLowering.cpp.
Referenced by isPromotedOpNeedingSplit(), and llvm::RISCVTargetLowering::RISCVTargetLowering().
Generated on for LLVM by
1.14.0