RISCVISelLowering.cpp File Reference

#include "RISCVISelLowering.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVConstantPoolValue.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVRegisterInfo.h"
#include "RISCVSelectionDAGInfo.h"
#include "RISCVSubtarget.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SDPatternMatch.h"
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/DiagnosticPrinter.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/InstructionCost.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <optional>
#include "RISCVGenAsmMatcher.inc"
#include "RISCVGenSearchableTables.inc"

Go to the source code of this file.

Classes
struct	VIDSequence

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::RISCVVIntrinsicsTable

Macros
#define	DEBUG_TYPE   "riscv-lower"
#define	OP_CASE(NODE)
#define	VP_CASE(NODE)
#define	CC_VLS_CASE(ABI_VLEN)
#define	GET_REGISTER_MATCHER
#define	GET_RISCVVIntrinsicsTable_IMPL

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")
static void	translateSetCCForBranch (const SDLoc &DL, SDValue &LHS, SDValue &RHS, ISD::CondCode &CC, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	getVLOperand (SDValue Op)
static bool	useRVVForFixedLengthVectorVT (MVT VT, const RISCVSubtarget &Subtarget)
static MVT	getContainerForFixedLengthVector (const TargetLowering &TLI, MVT VT, const RISCVSubtarget &Subtarget)
static MVT	getContainerForFixedLengthVector (SelectionDAG &DAG, MVT VT, const RISCVSubtarget &Subtarget)
static SDValue	convertToScalableVector (EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	convertFromScalableVector (EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static MVT	getMaskTypeFor (MVT VecVT)
	Return the type of the mask type suitable for masking the provided vector type.
static SDValue	getAllOnesMask (MVT VecVT, SDValue VL, const SDLoc &DL, SelectionDAG &DAG)
	Creates an all ones mask suitable for masking a vector of type VecTy with vector length VL.
static std::pair< SDValue, SDValue >	getDefaultScalableVLOps (MVT VecVT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static std::pair< SDValue, SDValue >	getDefaultVLOps (uint64_t NumElts, MVT ContainerVT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static std::pair< SDValue, SDValue >	getDefaultVLOps (MVT VecVT, MVT ContainerVT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerINT_TO_FP (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerFP_TO_INT_SAT (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerFP_TO_INT (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static RISCVFPRndMode::RoundingMode	matchRoundingOp (unsigned Opc)
static SDValue	lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerFTRUNC_FCEIL_FFLOOR_FROUND (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerVectorXRINT_XROUND (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	getVSlidedown (SelectionDAG &DAG, const RISCVSubtarget &Subtarget, const SDLoc &DL, EVT VT, SDValue Passthru, SDValue Op, SDValue Offset, SDValue Mask, SDValue VL, unsigned Policy=RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED)
static SDValue	getVSlideup (SelectionDAG &DAG, const RISCVSubtarget &Subtarget, const SDLoc &DL, EVT VT, SDValue Passthru, SDValue Op, SDValue Offset, SDValue Mask, SDValue VL, unsigned Policy=RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED)
static std::optional< APInt >	getExactInteger (const APFloat &APF, uint32_t BitWidth)
static std::optional< VIDSequence >	isSimpleVIDSequence (SDValue Op, unsigned EltSizeInBits)
static SDValue	matchSplatAsGather (SDValue SplatVal, MVT VT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerBuildVectorViaVID (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerBuildVectorViaDominantValues (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
	Try and optimize BUILD_VECTORs with "dominant values" - these are values which constitute a large proportion of the elements.
static SDValue	lowerBuildVectorOfConstants (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static unsigned	getPACKOpcode (unsigned DestBW, const RISCVSubtarget &Subtarget)
static SDValue	lowerBuildVectorViaPacking (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
	Double the element size of the build vector to reduce the number of vslide1down in the build vector chain.
static SDValue	lowerBUILD_VECTOR (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	splatPartsI64WithVL (const SDLoc &DL, MVT VT, SDValue Passthru, SDValue Lo, SDValue Hi, SDValue VL, SelectionDAG &DAG)
static SDValue	splatSplitI64WithVL (const SDLoc &DL, MVT VT, SDValue Passthru, SDValue Scalar, SDValue VL, SelectionDAG &DAG)
static SDValue	lowerScalarSplat (SDValue Passthru, SDValue Scalar, SDValue VL, MVT VT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerScalarInsert (SDValue Scalar, SDValue VL, MVT VT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	foldConcatVector (SDValue V1, SDValue V2)
	If concat_vector(V1,V2) could be folded away to some existing vector source, return it.
static SDValue	getSingleShuffleSrc (MVT VT, SDValue V1, SDValue V2)
static bool	isInterleaveShuffle (ArrayRef< int > Mask, MVT VT, int &EvenSrc, int &OddSrc, const RISCVSubtarget &Subtarget)
	Is this shuffle interleaving contiguous elements from one vector into the even elements and contiguous elements from another vector into the odd elements.
static bool	isMaskedSlidePair (ArrayRef< int > Mask, std::array< std::pair< int, int >, 2 > &SrcInfo)
	Is this mask representing a masked combination of two slides?
static bool	isElementRotate (const std::array< std::pair< int, int >, 2 > &SrcInfo, unsigned NumElts)
static bool	isAlternating (const std::array< std::pair< int, int >, 2 > &SrcInfo, ArrayRef< int > Mask, unsigned Factor, bool RequiredPolarity)
static bool	isZipEven (const std::array< std::pair< int, int >, 2 > &SrcInfo, ArrayRef< int > Mask, unsigned &Factor)
	Given a shuffle which can be represented as a pair of two slides, see if it is a zipeven idiom.
static bool	isZipOdd (const std::array< std::pair< int, int >, 2 > &SrcInfo, ArrayRef< int > Mask, unsigned &Factor)
	Given a shuffle which can be represented as a pair of two slides, see if it is a zipodd idiom.
static SDValue	getDeinterleaveShiftAndTrunc (const SDLoc &DL, MVT VT, SDValue Src, unsigned Factor, unsigned Index, SelectionDAG &DAG)
static SDValue	lowerVECTOR_SHUFFLEAsVRGatherVX (ShuffleVectorSDNode *SVN, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
	Match a single source shuffle which is an identity except that some particular element is repeated.
static SDValue	lowerVECTOR_SHUFFLEAsVSlidedown (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
static SDValue	lowerVECTOR_SHUFFLEAsVSlideup (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
static SDValue	lowerVECTOR_SHUFFLEAsVSlide1 (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
	Match v(f)slide1up/down idioms.
static SDValue	lowerVZIP (unsigned Opc, SDValue Op0, SDValue Op1, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	getWideningSpread (SDValue V, unsigned Factor, unsigned Index, const SDLoc &DL, SelectionDAG &DAG)
static SDValue	getWideningInterleave (SDValue EvenV, SDValue OddV, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerBitreverseShuffle (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static bool	isLegalBitRotate (ArrayRef< int > Mask, EVT VT, const RISCVSubtarget &Subtarget, MVT &RotateVT, unsigned &RotateAmt)
static SDValue	lowerVECTOR_SHUFFLEAsRotate (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerShuffleViaVRegSplitting (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static bool	isCompressMask (ArrayRef< int > Mask)
static SDValue	lowerDisjointIndicesShuffle (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
	Given a shuffle where the indices are disjoint between the two sources, e.g.:
static bool	isLocalRepeatingShuffle (ArrayRef< int > Mask, int Span)
	Is this mask local (i.e.
static bool	isLowSourceShuffle (ArrayRef< int > Mask, int Span)
	Is this mask only using elements from the first span of the input?
static bool	isSpanSplatShuffle (ArrayRef< int > Mask, int Span)
	Return true for a mask which performs an arbitrary shuffle within the first span, and then repeats that same result across all remaining spans.
static SDValue	tryWidenMaskForShuffle (SDValue Op, SelectionDAG &DAG)
	Try to widen element type to get a new mask value for a better permutation sequence.
static SDValue	lowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerConstant (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	LowerPREFETCH (SDValue Op, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerATOMIC_FENCE (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerFMAXIMUM_FMINIMUM (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerFABSorFNEG (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerFCOPYSIGN (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static unsigned	getRISCVVLOp (SDValue Op)
	Get a RISC-V target specified VL op for a given SDNode.
static bool	isPromotedOpNeedingSplit (SDValue Op, const RISCVSubtarget &Subtarget)
static SDValue	SplitVectorOp (SDValue Op, SelectionDAG &DAG)
static SDValue	SplitVPOp (SDValue Op, SelectionDAG &DAG)
static SDValue	SplitVectorReductionOp (SDValue Op, SelectionDAG &DAG)
static SDValue	SplitStrictFPVectorOp (SDValue Op, SelectionDAG &DAG)
static SDValue	getTargetNode (GlobalAddressSDNode *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (BlockAddressSDNode *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (ConstantPoolSDNode *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (JumpTableSDNode *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getLargeGlobalAddress (GlobalAddressSDNode *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG)
static SDValue	getLargeExternalSymbol (ExternalSymbolSDNode *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG)
static std::optional< bool >	matchSetCC (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue Val)
static bool	isSimm12Constant (SDValue V)
static SDValue	lowerSelectToBinOp (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	foldBinOpIntoSelectIfProfitable (SDNode *BO, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static std::optional< MVT >	getSmallestVTForIndex (MVT VecVT, unsigned MaxIdx, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static bool	isValidVisniInsertExtractIndex (SDValue Idx)
static SDValue	lowerVectorIntrinsicScalars (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerGetVectorLength (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	lowerCttzElts (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static void	promoteVCIXScalar (SDValue Op, MutableArrayRef< SDValue > Operands, SelectionDAG &DAG)
static void	processVCIXOperands (SDValue OrigOp, MutableArrayRef< SDValue > Operands, SelectionDAG &DAG)
static bool	isValidEGW (int EGS, EVT VT, const RISCVSubtarget &Subtarget)
static SDValue	getVCIXISDNodeWCHAIN (SDValue Op, SelectionDAG &DAG, unsigned Type)
static SDValue	getVCIXISDNodeVOID (SDValue Op, SelectionDAG &DAG, unsigned Type)
static SDValue	lowerFixedVectorSegLoadIntrinsics (unsigned IntNo, SDValue Op, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
static SDValue	lowerFixedVectorSegStoreIntrinsics (unsigned IntNo, SDValue Op, const RISCVSubtarget &Subtarget, SelectionDAG &DAG)
static unsigned	getRVVReductionOp (unsigned ISDOpcode)
static bool	isNonZeroAVL (SDValue AVL)
static SDValue	lowerReductionSeq (unsigned RVVOpcode, MVT ResVT, SDValue StartValue, SDValue Vec, SDValue Mask, SDValue VL, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
	Helper to lower a reduction sequence of the form: scalar = reduce_op vec, scalar_start.
static std::tuple< unsigned, SDValue, SDValue >	getRVVFPReductionOpAndOperands (SDValue Op, SelectionDAG &DAG, EVT EltVT, const RISCVSubtarget &Subtarget)
static SDValue	widenVectorOpsToi8 (SDValue N, const SDLoc &DL, SelectionDAG &DAG)
static unsigned	getRISCVWOpcode (unsigned Opcode)
static SDValue	customLegalizeToWOp (SDNode *N, SelectionDAG &DAG, unsigned ExtOpc=ISD::ANY_EXTEND)
static SDValue	customLegalizeToWOpWithSExt (SDNode *N, SelectionDAG &DAG)
static unsigned	getVecReduceOpcode (unsigned Opc)
	Given a binary operator, return the associative generic ISD::VECREDUCE_OP which corresponds to it.
static SDValue	combineBinOpOfExtractToReduceTree (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
	Perform two related transforms whose purpose is to incrementally recognize an explode_vector followed by scalar reduction as a vector reduction node.
static SDValue	combineBinOpToReduce (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	transformAddShlImm (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	combineShlAddIAddImpl (SDNode *N, SDValue AddI, SDValue Other, SelectionDAG &DAG)
static SDValue	combineShlAddIAdd (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	combineSelectAndUse (SDNode *N, SDValue Slct, SDValue OtherOp, SelectionDAG &DAG, bool AllOnes, const RISCVSubtarget &Subtarget)
static SDValue	combineSelectAndUseCommutative (SDNode *N, SelectionDAG &DAG, bool AllOnes, const RISCVSubtarget &Subtarget)
static SDValue	transformAddImmMulImm (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	combineBinOpOfZExt (SDNode *N, SelectionDAG &DAG)
static SDValue	combineAddOfBooleanXor (SDNode *N, SelectionDAG &DAG)
static SDValue	performADDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static SDValue	combineSubOfBoolean (SDNode *N, SelectionDAG &DAG)
static SDValue	combineSubShiftToOrcB (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	performSUBCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	combineDeMorganOfBoolean (SDNode *N, SelectionDAG &DAG)
static SDValue	combineTruncSelectToSMaxUSat (SDNode *N, SelectionDAG &DAG)
static SDValue	performTRUNCATECombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	reverseZExtICmpCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	combineANDOfSETCCToCZERO (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	reduceANDOfAtomicLoad (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performANDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static SDValue	combineOrOfCZERO (SDNode *N, SDValue N0, SDValue N1, SelectionDAG &DAG)
static SDValue	combineXorToBitfieldInsert (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	combineOrToBitfieldInsert (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	combineOrAndToBitfieldInsert (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	performORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static SDValue	performXORCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	expandMulToNAFSequence (SDNode *N, SelectionDAG &DAG, uint64_t MulAmt)
static SDValue	expandMulToAddOrSubOfShl (SDNode *N, SelectionDAG &DAG, uint64_t MulAmt)
static SDValue	getShlAddShlAdd (SDNode *N, SelectionDAG &DAG, unsigned ShX, unsigned ShY, bool AddX, unsigned Shift)
static SDValue	expandMulToShlAddShlAdd (SDNode *N, SelectionDAG &DAG, uint64_t MulAmt, unsigned Shift)
static SDValue	expandMul (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static SDValue	combineVectorMulToSraBitcast (SDNode *N, SelectionDAG &DAG)
static SDValue	performMULCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static bool	narrowIndex (SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &DAG)
	According to the property that indexed load/store instructions zero-extend their indices, try to narrow the type of index operand.
static SDValue	combineVectorSizedSetCCEquality (EVT VT, SDValue X, SDValue Y, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
	Try to map an integer comparison with size > XLEN to vector instructions before type legalization splits it up into chunks.
static SDValue	performSETCCCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static SDValue	performSIGN_EXTEND_INREGCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static SDValue	simplifyOp_VL (SDNode *N)
static SDValue	combineOp_VLToVWOp_VL (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
	Combine a binary or FMA operation to its equivalent VW or VW_W form.
static SDValue	combineVWADDSUBWSelect (SDNode *N, SelectionDAG &DAG)
static SDValue	performVWADDSUBW_VLCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static SDValue	tryMemPairCombine (SelectionDAG &DAG, LSBaseSDNode *LSNode1, LSBaseSDNode *LSNode2, SDValue BasePtr, uint64_t Imm)
static SDValue	performMemPairCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performFP_TO_INTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static SDValue	performFP_TO_INT_SATCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static SDValue	performBITREVERSECombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	performVP_REVERSECombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	performVP_STORECombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	performVP_TRUNCATECombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static unsigned	negateFMAOpcode (unsigned Opcode, bool NegMul, bool NegAcc)
static SDValue	combineVFMADD_VLWithVFNEG_VL (SDNode *N, SelectionDAG &DAG)
static SDValue	performVFMADD_VLCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static SDValue	performSRACombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	tryDemorganOfBooleanCondition (SDValue Cond, SelectionDAG &DAG)
static bool	combine_CC (SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	tryFoldSelectIntoOp (SDNode *N, SelectionDAG &DAG, SDValue TrueVal, SDValue FalseVal, bool Swapped)
static SDValue	foldSelectOfCTTZOrCTLZ (SDNode *N, SelectionDAG &DAG)
static SDValue	useInversedSetcc (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static bool	matchSelectAddSub (SDValue TrueVal, SDValue FalseVal, bool &SwapCC)
static SDValue	performVSELECTCombine (SDNode *N, SelectionDAG &DAG)
	Convert vselect CC, (add a, b), (sub a, b) to add a, (vselect CC, -b, b).
static SDValue	performSELECTCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	performBUILD_VECTORCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget, const RISCVTargetLowering &TLI)
	If we have a build_vector where each lane is binop X, C, where C is a constant (but not necessarily the same constant on all lanes), form binop (build_vector x1, x2, ...), (build_vector c1, c2, c3, ..).
static MVT	getQDOTXResultType (MVT OpVT)
static SDValue	getZeroPaddedAdd (const SDLoc &DL, SDValue A, SDValue B, SelectionDAG &DAG)
	Given fixed length vectors A and B with equal element types, but possibly different number of elements, return A + B where either A or B is zero padded to the larger number of elements.
static SDValue	foldReduceOperandViaVQDOT (SDValue InVec, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget, const RISCVTargetLowering &TLI)
static SDValue	performVECREDUCECombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget, const RISCVTargetLowering &TLI)
static SDValue	performINSERT_VECTOR_ELTCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget, const RISCVTargetLowering &TLI)
static SDValue	performCONCAT_VECTORSCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget, const RISCVTargetLowering &TLI)
static SDValue	performVECTOR_SHUFFLECombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget, const RISCVTargetLowering &TLI)
static SDValue	combineToVWMACC (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	combineVqdotAccum (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static bool	legalizeScatterGatherIndexType (SDLoc DL, SDValue &Index, ISD::MemIndexType &IndexType, RISCVTargetLowering::DAGCombinerInfo &DCI)
static bool	matchIndexAsShuffle (EVT VT, SDValue Index, SDValue Mask, SmallVector< int > &ShuffleMask)
	Match the index vector of a scatter or gather node as the shuffle mask which performs the rearrangement if possible.
static bool	matchIndexAsWiderOp (EVT VT, SDValue Index, SDValue Mask, Align BaseAlign, const RISCVSubtarget &ST)
	Match the index of a gather or scatter operation as an operation with twice the element width and half the number of elements.
static SDValue	combineTruncOfSraSext (SDNode *N, SelectionDAG &DAG)
static SDValue	combineTruncToVnclip (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	combineToVCPOP (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue	performSHLCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
static uint64_t	computeGREVOrGORC (uint64_t x, unsigned ShAmt, bool IsGORC)
static MachineBasicBlock *	emitReadCounterWidePseudo (MachineInstr &MI, MachineBasicBlock *BB)
static MachineBasicBlock *	emitSplitF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB, const RISCVSubtarget &Subtarget)
static MachineBasicBlock *	emitBuildPairF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB, const RISCVSubtarget &Subtarget)
static MachineBasicBlock *	emitQuietFCMP (MachineInstr &MI, MachineBasicBlock *BB, unsigned RelOpcode, unsigned EqOpcode, const RISCVSubtarget &Subtarget)
static MachineBasicBlock *	EmitLoweredCascadedSelect (MachineInstr &First, MachineInstr &Second, MachineBasicBlock *ThisMBB, const RISCVSubtarget &Subtarget)
static MachineBasicBlock *	emitSelectPseudo (MachineInstr &MI, MachineBasicBlock *BB, const RISCVSubtarget &Subtarget)
static const RISCV::RISCVMaskedPseudoInfo *	lookupMaskedIntrinsic (uint16_t MCOpcode, RISCVVType::VLMUL LMul, unsigned SEW)
static MachineBasicBlock *	emitVFROUND_NOEXCEPT_MASK (MachineInstr &MI, MachineBasicBlock *BB, unsigned CVTXOpc)
static MachineBasicBlock *	emitFROUND (MachineInstr &MI, MachineBasicBlock *MBB, const RISCVSubtarget &Subtarget)
static SDValue	convertLocVTToValVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget)
static SDValue	unpackFromRegLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const ISD::InputArg &In, const RISCVTargetLowering &TLI)
static SDValue	convertValVTToLocVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget)
static SDValue	unpackFromMemLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static SDValue	unpackF64OnRV32DSoftABI (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const CCValAssign &HiVA, const SDLoc &DL)
static Align	getPrefTypeAlign (EVT VT, SelectionDAG &DAG)
static Intrinsic::ID	getIntrinsicForMaskedAtomicRMWBinOp (unsigned XLen, AtomicRMWInst::BinOp BinOp)
static Value *	useTpOffset (IRBuilderBase &IRB, unsigned Offset)

Variables
static cl::opt< unsigned >	ExtensionMaxWebSize (DEBUG_TYPE "-ext-max-web-size", cl::Hidden, cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion"), cl::init(18))
static cl::opt< bool >	AllowSplatInVW_W (DEBUG_TYPE "-form-vw-w-with-splat", cl::Hidden, cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants"), cl::init(false))
static cl::opt< unsigned >	NumRepeatedDivisors (DEBUG_TYPE "-fp-repeated-divisors", cl::Hidden, cl::desc("Set the minimum number of repetitions of a divisor to allow " "transformation to multiplications by the reciprocal"), cl::init(2))
static cl::opt< int >	FPImmCost (DEBUG_TYPE "-fpimm-cost", cl::Hidden, cl::desc("Give the maximum number of instructions that we will " "use for creating a floating-point immediate value"), cl::init(3))
static cl::opt< bool >	ReassocShlAddiAdd ("reassoc-shl-addi-add", cl::Hidden, cl::desc("Swap add and addi in cases where the add may " "be combined with a shift"), cl::init(true))
static const unsigned	ZvfbfaVPOps []
static const unsigned	ZvfbfaOps [] = {ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN}
const uint64_t	ModeMask64 = ~RISCVExceptFlags::ALL
const uint32_t	ModeMask32 = ~RISCVExceptFlags::ALL

Macro Definition Documentation

CC_VLS_CASE

#define CC_VLS_CASE

(

ABI_VLEN

)

Value:

case CallingConv::RISCV_VLSCall_##ABI_VLEN:

DEBUG_TYPE

#define DEBUG_TYPE   "riscv-lower"

Definition at line 56 of file RISCVISelLowering.cpp.

GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 25062 of file RISCVISelLowering.cpp.

GET_RISCVVIntrinsicsTable_IMPL

#define GET_RISCVVIntrinsicsTable_IMPL

Definition at line 25300 of file RISCVISelLowering.cpp.

OP_CASE

#define OP_CASE

(

NODE

)

Value:

  case ISD::NODE:                                                              \
    return RISCVISD::NODE##_VL;

Referenced by getRISCVVLOp().

VP_CASE

#define VP_CASE

(

NODE

)

Value:

  case ISD::VP_##NODE:                                                         \
    return RISCVISD::NODE##_VL;

Referenced by getRISCVVLOp().

Function Documentation

combine_CC()

bool combine_CC ( SDValue & LHS, SDValue & RHS, SDValue & CC, const SDLoc & DL, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 18947 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, llvm::cast(), llvm::ISD::Constant, DL, llvm::dyn_cast(), llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueSizeInBits(), llvm::RISCVSubtarget::getXLenVT(), llvm::isa(), llvm::isInt(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::isPowerOf2_64(), LHS, llvm::Log2_64(), llvm::SelectionDAG::MaskedValueIsZero(), RHS, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, translateSetCCForBranch(), tryDemorganOfBooleanCondition(), and llvm::ISD::XOR.

combineAddOfBooleanXor()

SDValue combineAddOfBooleanXor ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 15812 of file RISCVISelLowering.cpp.

References DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getNegative(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::SelectionDAG::MaskedValueIsZero(), N, SDValue(), and llvm::ISD::XOR.

Referenced by performADDCombine().

combineANDOfSETCCToCZERO()

SDValue combineANDOfSETCCToCZERO ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 16198 of file RISCVISelLowering.cpp.

References llvm::cast(), llvm::SelectionDAG::computeKnownBits(), DL, llvm::KnownBits::getMaxValue(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::RISCVSubtarget::hasCZEROLike(), llvm::SDValue::hasOneUse(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), N, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETNE, std::swap(), and llvm::APInt::ugt().

Referenced by performANDCombine().

combineBinOpOfExtractToReduceTree()

SDValue combineBinOpOfExtractToReduceTree ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Perform two related transforms whose purpose is to incrementally recognize an explode_vector followed by scalar reduction as a vector reduction node.

This exists to recover from a deficiency in SLP which can't handle forests with multiple roots sharing common nodes. In some cases, one of the trees will be vectorized, and the other will remain (unprofitably) scalarized.

Definition at line 15292 of file RISCVISelLowering.cpp.

References assert(), llvm::cast(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::SelectionDAG::getContext(), llvm::RISCVSubtarget::getELen(), llvm::SelectionDAG::getExtractSubvector(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::ISD::getVecReduceBaseOpcode(), getVecReduceOpcode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::hasVInstructions(), llvm::isa(), llvm::EVT::isInteger(), llvm::isNullConstant(), llvm::EVT::isScalableVector(), LHS, N, llvm::SelectionDAG::NewNodesMustHaveLegalTypes, Opc, RHS, SDValue(), and std::swap().

Referenced by performADDCombine(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performORCombine(), and performXORCombine().

combineBinOpOfZExt()

SDValue combineBinOpOfZExt ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 15770 of file RISCVISelLowering.cpp.

References llvm::CallingConv::C, llvm::SelectionDAG::getContext(), llvm::EVT::getHalfSizedIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), N, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SUB, and llvm::ISD::ZERO_EXTEND.

Referenced by performADDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performMULCombine(), and performSUBCombine().

combineBinOpToReduce()

SDValue combineBinOpToReduce ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 15394 of file RISCVISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, llvm::ISD::AND, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_SUBVECTOR, llvm::isNeutralConstant(), isNonZeroAVL(), llvm::isNullConstant(), llvm::SDNode::isUndef(), llvm_unreachable, lowerScalarInsert(), N, Opc, llvm::ISD::OR, SDValue(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMAX, llvm::ISD::UMIN, and llvm::ISD::XOR.

Referenced by performADDCombine(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performORCombine(), and performXORCombine().

combineDeMorganOfBoolean()

SDValue combineDeMorganOfBoolean ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 15993 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::SelectionDAG::MaskedValueIsZero(), N, Opc, llvm::ISD::OR, SDValue(), and llvm::ISD::XOR.

Referenced by performANDCombine(), and performORCombine().

combineOp_VLToVWOp_VL()

SDValue combineOp_VLToVWOp_VL ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const RISCVSubtarget & Subtarget )

static

Combine a binary or FMA operation to its equivalent VW or VW_W form.

The supported combines are: add | add_vl | or disjoint | or_vl disjoint -> vwadd(u) | vwadd(u)_w sub | sub_vl -> vwsub(u) | vwsub(u)_w mul | mul_vl -> vwmul(u) | vwmul_su shl | shl_vl -> vwsll fadd_vl -> vfwadd | vfwadd_w fsub_vl -> vfwsub | vfwsub_w fmul_vl -> vfwmul vwadd_w(u) -> vwadd(u) vwsub_w(u) -> vwsub(u) vfwadd_w -> vfwadd vfwsub_w -> vfwsub

Definition at line 17970 of file RISCVISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), assert(), llvm::SmallPtrSetImpl< PtrType >::contains(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), ExtensionMaxWebSize, llvm::Use::getOperandNo(), llvm::Use::getUser(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), LHS, N, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SmallVectorImpl< T >::reserve(), RHS, SDValue(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and std::swap().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine(), performSHLCombine(), performVFMADD_VLCombine(), and performVWADDSUBW_VLCombine().

combineOrAndToBitfieldInsert()

SDValue combineOrAndToBitfieldInsert ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 16431 of file RISCVISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::SelectionDAG::computeKnownBits(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getSExtValue(), llvm::SelectionDAG::getSignedConstant(), llvm::APInt::isShiftedMask(), llvm::APInt::isSubsetOf(), llvm::PatternMatch::m_And(), llvm::SDPatternMatch::m_ConstInt(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Or(), llvm::SDPatternMatch::m_SpecificVT(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), and llvm::KnownBits::Zero.

Referenced by performORCombine().

combineOrOfCZERO()

SDValue combineOrOfCZERO ( SDNode * N, SDValue N0, SDValue N1, SelectionDAG & DAG )

static

Definition at line 16318 of file RISCVISelLowering.cpp.

References assert(), Cond, llvm::SDNodeFlags::Disjoint, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::isOneConstant(), N, llvm::ISD::OR, SDValue(), and llvm::ISD::XOR.

Referenced by performORCombine().

combineOrToBitfieldInsert()

SDValue combineOrToBitfieldInsert ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 16393 of file RISCVISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSignedConstant(), llvm::APInt::isShiftedMask(), llvm::APInt::isSignedIntN(), llvm::SDPatternMatch::m_ConstInt(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Or(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), and X.

Referenced by performORCombine().

combineSelectAndUse()

SDValue combineSelectAndUse ( SDNode * N, SDValue Slct, SDValue OtherOp, SelectionDAG & DAG, bool AllOnes, const RISCVSubtarget & Subtarget )

static

Definition at line 15617 of file RISCVISelLowering.cpp.

References llvm::AllOnes, llvm::ISD::AND, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::hasConditionalMoveFusion(), llvm::RISCVSubtarget::hasCZEROLike(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::isNullConstant(), llvm::EVT::isVector(), isZeroOrAllOnes(), N, SDValue(), llvm::ISD::SELECT, and std::swap().

combineSelectAndUseCommutative()

SDValue combineSelectAndUseCommutative ( SDNode * N, SelectionDAG & DAG, bool AllOnes, const RISCVSubtarget & Subtarget )

static

Definition at line 15680 of file RISCVISelLowering.cpp.

References llvm::AllOnes, combineSelectAndUse(), N, and SDValue().

combineShlAddIAdd()

SDValue combineShlAddIAdd ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 15585 of file RISCVISelLowering.cpp.

References combineShlAddIAddImpl(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasShlAdd(), N, llvm::Other, ReassocShlAddiAdd, and SDValue().

Referenced by performADDCombine().

combineShlAddIAddImpl()

SDValue combineShlAddIAddImpl ( SDNode * N, SDValue AddI, SDValue Other, SelectionDAG & DAG )

static

Definition at line 15546 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::APInt::getSExtValue(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getTargetConstant(), llvm::APInt::getZExtValue(), llvm::isa(), llvm::PatternMatch::m_Add(), llvm::SDPatternMatch::m_ConstInt(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Shl(), llvm::PatternMatch::m_Value(), N, llvm::Other, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::APInt::sgt(), llvm::APInt::slt(), and llvm::SDNode::use_size().

Referenced by combineShlAddIAdd().

combineSubOfBoolean()

SDValue combineSubOfBoolean ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 15862 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::cast(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::EVT::isInteger(), llvm::isOneConstant(), llvm::APInt::isSignedIntN(), N, SDValue(), llvm::ISD::SETCC, and llvm::ISD::XOR.

Referenced by performSUBCombine().

combineSubShiftToOrcB()

SDValue combineSubShiftToOrcB ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 15906 of file RISCVISelLowering.cpp.

References llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::APInt::getSplat(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDValue::hasOneUse(), llvm::SelectionDAG::MaskedValueIsZero(), N, SDValue(), llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by performSUBCombine().

combineToVCPOP()

SDValue combineToVCPOP ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 20186 of file RISCVISelLowering.cpp.

References assert(), llvm::RISCVTargetLowering::computeVLMAX(), convertToScalableVector(), llvm::ISD::CTPOP, DL, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::EVT::getFixedSizeInBits(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealMaxVLen(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::MVT::isFixedLengthVector(), llvm::EVT::isScalarInteger(), llvm::EVT::isSimple(), llvm::TargetLoweringBase::isTypeLegal(), llvm::MVT::isVector(), llvm::Log2_32(), N, Opc, SDValue(), and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

combineToVWMACC()

SDValue combineToVWMACC ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 19750 of file RISCVISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, assert(), DL, getDefaultScalableVLOps(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSelectionDAGInfo(), llvm::SDValue::isUndef(), N, Opc, SDValue(), and std::swap().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

combineTruncOfSraSext()

SDValue combineTruncOfSraSext ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 19996 of file RISCVISelLowering.cpp.

References llvm::cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isa(), llvm::isAllOnesConstant(), llvm::EVT::isVector(), N, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SMIN, llvm::SMin, llvm::ISD::SRA, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

combineTruncSelectToSMaxUSat()

SDValue combineTruncSelectToSMaxUSat ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 16043 of file RISCVISelLowering.cpp.

References llvm::cast(), Cond, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isConstOrConstSplat(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::ConstantSDNode::isZero(), N, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETULT, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::TRUNCATE, and llvm::ISD::VSELECT.

Referenced by performTRUNCATECombine().

combineTruncToVnclip()

SDValue combineTruncToVnclip ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 20050 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::changeVectorElementType(), DL, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignedMinValue(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::isConstantSplatVector(), llvm::APInt::isMask(), llvm::APInt::isNonNegative(), llvm::isNullConstant(), N, Opc, SDValue(), llvm::APInt::sext(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::APInt::uge(), and llvm::ISD::UMIN.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

combineVectorMulToSraBitcast()

SDValue combineVectorMulToSraBitcast ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 16775 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::ISD::isConstantSplatVector(), llvm::APInt::isMask(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), N, SDValue(), llvm::ISD::SRA, and llvm::ISD::SRL.

Referenced by performMULCombine().

combineVectorSizedSetCCEquality()

SDValue combineVectorSizedSetCCEquality ( EVT VT, SDValue X, SDValue Y, ISD::CondCode CC, const SDLoc & DL, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Try to map an integer comparison with size > XLEN to vector instructions before type legalization splits it up into chunks.

Definition at line 16930 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), llvm::Function::hasFnAttribute(), llvm::RISCVSubtarget::hasVInstructions(), llvm::isa(), llvm::EVT::isByteSized(), llvm::ISD::isIntEqualitySetCC(), llvm::EVT::isScalarInteger(), llvm::peekThroughBitcasts(), SDValue(), llvm::ISD::SETNE, X, and Y.

Referenced by combineSetCC(), performSETCCCombine(), and performSETCCCombine().

combineVFMADD_VLWithVFNEG_VL()

SDValue combineVFMADD_VLWithVFNEG_VL ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 18717 of file RISCVISelLowering.cpp.

References A(), B(), llvm::CallingConv::C, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectionDAGInfo(), llvm::SelectionDAGTargetInfo::isTargetStrictFPOpcode(), N, negateFMAOpcode(), llvm::Offset, and SDValue().

Referenced by performVFMADD_VLCombine().

combineVqdotAccum()

SDValue combineVqdotAccum ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 19815 of file RISCVISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, assert(), DL, getDefaultScalableVLOps(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::isUndef(), N, Opc, SDValue(), and std::swap().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

combineVWADDSUBWSelect()

SDValue combineVWADDSUBWSelect ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 18088 of file RISCVISelLowering.cpp.

References assert(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::isConstantSplatVectorAllZeros(), llvm::isNullOrNullSplat(), llvm::SDValue::isUndef(), N, Opc, SDValue(), llvm::ISD::VSELECT, X, and Y.

Referenced by performVWADDSUBW_VLCombine().

combineXorToBitfieldInsert()

SDValue combineXorToBitfieldInsert ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 16357 of file RISCVISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::sampleprof::Base, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::APInt::isShiftedMask(), llvm::PatternMatch::m_And(), llvm::SDPatternMatch::m_ConstInt(), llvm::PatternMatch::m_Deferred(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Xor(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::SDPatternMatch::sd_match(), SDValue(), and llvm::ISD::SRA.

Referenced by performXORCombine().

computeGREVOrGORC()

uint64_t computeGREVOrGORC ( uint64_t x, unsigned ShAmt, bool IsGORC )

static

Definition at line 21746 of file RISCVISelLowering.cpp.

Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(), and llvm::RISCVTargetLowering::SimplifyDemandedBitsForTargetNode().

convertFromScalableVector()

SDValue convertFromScalableVector ( EVT VT, SDValue V, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 3012 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getExtractSubvector(), and llvm::EVT::isFixedLengthVector().

convertLocVTToValVT()

SDValue convertLocVTToValVT ( SelectionDAG & DAG, SDValue Val, const CCValAssign & VA, const SDLoc & DL, const RISCVSubtarget & Subtarget )

static

Definition at line 22937 of file RISCVISelLowering.cpp.

References llvm::CCValAssign::BCvt, convertFromScalableVector(), DL, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::MVT::isScalableVector(), llvm_unreachable, and llvm::CCValAssign::needsCustom().

convertToScalableVector()

SDValue convertToScalableVector ( EVT VT, SDValue V, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 3001 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getUNDEF(), and llvm::EVT::isScalableVector().

convertValVTToLocVT()

SDValue convertValVTToLocVT ( SelectionDAG & DAG, SDValue Val, const CCValAssign & VA, const SDLoc & DL, const RISCVSubtarget & Subtarget )

static

Definition at line 22998 of file RISCVISelLowering.cpp.

References llvm::CCValAssign::BCvt, convertToScalableVector(), DL, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::isFixedLengthVector(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm_unreachable, and llvm::CCValAssign::needsCustom().

customLegalizeToWOp()

SDValue customLegalizeToWOp ( SDNode * N, SelectionDAG & DAG, unsigned ExtOpc = ISD::ANY_EXTEND )

static

Definition at line 14466 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), getRISCVWOpcode(), N, and llvm::ISD::TRUNCATE.

customLegalizeToWOpWithSExt()

SDValue customLegalizeToWOpWithSExt ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 14479 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), N, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::TRUNCATE.

emitBuildPairF64Pseudo()

MachineBasicBlock * emitBuildPairF64Pseudo ( MachineInstr & MI, MachineBasicBlock * BB, const RISCVSubtarget & Subtarget )

static

Definition at line 22233 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), MI, llvm::MachineMemOperand::MOStore, Register, and TII.

emitFROUND()

MachineBasicBlock * emitFROUND ( MachineInstr & MI, MachineBasicBlock * MBB, const RISCVSubtarget & Subtarget )

static

Definition at line 22638 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), F, llvm::RISCVSubtarget::getInstrInfo(), I, llvm::RISCVSubtarget::is64Bit(), llvm_unreachable, MBB, MI, MRI, llvm::MachineInstr::NoFPExcept, llvm::MachineInstr::setFlag(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

EmitLoweredCascadedSelect()

MachineBasicBlock * EmitLoweredCascadedSelect ( MachineInstr & First, MachineInstr & Second, MachineBasicBlock * ThisMBB, const RISCVSubtarget & Subtarget )

static

Definition at line 22306 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::First, llvm::MachineBasicBlock::getBasicBlock(), llvm::RISCVCC::getBrCond(), llvm::getImm(), llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

Referenced by emitSelectPseudo().

emitQuietFCMP()

MachineBasicBlock * emitQuietFCMP ( MachineInstr & MI, MachineBasicBlock * BB, unsigned RelOpcode, unsigned EqOpcode, const RISCVSubtarget & Subtarget )

static

Definition at line 22269 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::RegState::Kill, MI, MRI, llvm::MachineInstr::NoFPExcept, llvm::MachineInstr::setFlag(), and TII.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

emitReadCounterWidePseudo()

MachineBasicBlock * emitReadCounterWidePseudo ( MachineInstr & MI, MachineBasicBlock * BB )

static

Definition at line 22134 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getBasicBlock(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::insert(), MI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

emitSelectPseudo()

MachineBasicBlock * emitSelectPseudo ( MachineInstr & MI, MachineBasicBlock * BB, const RISCVSubtarget & Subtarget )

static

Definition at line 22409 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::any_of(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineInstr::collectDebugValues(), llvm::SmallSet< T, N, C >::count(), DL, E(), EmitLoweredCascadedSelect(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::RISCVCC::getBrCond(), llvm::getImm(), llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), I, llvm::SmallSet< T, N, C >::insert(), llvm::MachineBasicBlock::instr_end(), LHS, MI, llvm::Next, llvm::next_nodbg(), llvm::MachineBasicBlock::push_back(), RHS, llvm::MachineBasicBlock::setCallFrameSize(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

emitSplitF64Pseudo()

MachineBasicBlock * emitSplitF64Pseudo ( MachineInstr & MI, MachineBasicBlock * BB, const RISCVSubtarget & Subtarget )

static

Definition at line 22199 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), assert(), llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), MI, llvm::MachineMemOperand::MOLoad, and TII.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

emitVFROUND_NOEXCEPT_MASK()

MachineBasicBlock * emitVFROUND_NOEXCEPT_MASK ( MachineInstr & MI, MachineBasicBlock * BB, unsigned CVTXOpc )

static

Definition at line 22575 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::RISCVII::getLMul(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::RISCVII::getSEWOpNum(), llvm::MachineFunction::getSubtarget(), llvm::RegState::Kill, lookupMaskedIntrinsic(), llvm::RISCV::RISCVMaskedPseudoInfo::MaskedPseudo, MI, MRI, TII, and TRI.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

expandMul()

SDValue expandMul ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const RISCVSubtarget & Subtarget )

static

Definition at line 16674 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::countr_zero(), DL, llvm::dyn_cast(), expandMulToAddOrSubOfShl(), expandMulToNAFSequence(), expandMulToShlAddShlAdd(), llvm::SelectionDAG::getConstant(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::ConstantSDNode::getZExtValue(), llvm::Function::hasMinSize(), llvm::RISCVSubtarget::hasShlAdd(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isInt(), llvm::isPowerOf2_64(), llvm::Log2_64(), N, llvm::Offset, SDValue(), llvm::ISD::SHL, llvm::ISD::SUB, and X.

Referenced by performMULCombine().

expandMulToAddOrSubOfShl()

SDValue expandMulToAddOrSubOfShl ( SDNode * N, SelectionDAG & DAG, uint64_t MulAmt )

static

Definition at line 16591 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::isPowerOf2_64(), llvm::Log2_64(), N, SDValue(), llvm::ISD::SHL, and llvm::ISD::SUB.

Referenced by expandMul().

expandMulToNAFSequence()

SDValue expandMulToNAFSequence ( SDNode * N, SelectionDAG & DAG, uint64_t MulAmt )

static

Definition at line 16566 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::BitWidth, DL, E(), llvm::SelectionDAG::getConstant(), llvm::EVT::getFixedSizeInBits(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getShiftAmountConstant(), I, N, llvm::ISD::SHL, and llvm::ISD::SUB.

Referenced by expandMul().

expandMulToShlAddShlAdd()

SDValue expandMulToShlAddShlAdd ( SDNode * N, SelectionDAG & DAG, uint64_t MulAmt, unsigned Shift )

static

Definition at line 16638 of file RISCVISelLowering.cpp.

References assert(), getShlAddShlAdd(), llvm::isShifted359(), N, and SDValue().

Referenced by expandMul().

foldBinOpIntoSelectIfProfitable()

SDValue foldBinOpIntoSelectIfProfitable ( SDNode * BO, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 9316 of file RISCVISelLowering.cpp.

References DL, llvm::dyn_cast(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SDNode::getAsAPIntVal(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSelect(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::isa(), llvm::APInt::isAllOnes(), llvm::ConstantSDNode::isOpaque(), llvm::APInt::isZero(), SDValue(), llvm::ISD::SELECT, and std::swap().

foldConcatVector()

SDValue foldConcatVector ( SDValue V1, SDValue V2 )

static

If concat_vector(V1,V2) could be folded away to some existing vector source, return it.

Note that the source may be larger than the requested concat_vector (i.e. a extract_subvector might be required.)

Definition at line 4892 of file RISCVISelLowering.cpp.

References assert(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::isScalableVector(), and SDValue().

Referenced by getSingleShuffleSrc(), and lowerVECTOR_SHUFFLE().

foldReduceOperandViaVQDOT()

SDValue foldReduceOperandViaVQDOT ( SDValue InVec, const SDLoc & DL, SelectionDAG & DAG, const RISCVSubtarget & Subtarget, const RISCVTargetLowering & TLI )

static

Definition at line 19396 of file RISCVISelLowering.cpp.

References A(), B(), DL, foldReduceOperandViaVQDOT(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getQDOTXResultType(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), getZeroPaddedAdd(), llvm::ISD::isExtOpcode(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownMultipleOf(), llvm::TargetLoweringBase::isTypeLegal(), llvm::PatternMatch::m_AddLike(), llvm::PatternMatch::m_Mul(), llvm::PatternMatch::m_Value(), Opc, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SIGN_EXTEND, std::swap(), and llvm::ISD::ZERO_EXTEND.

Referenced by foldReduceOperandViaVQDOT(), and performVECREDUCECombine().

foldSelectOfCTTZOrCTLZ()

SDValue foldSelectOfCTTZOrCTLZ ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 19148 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, llvm::BitWidth, llvm::cast(), Cond, llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::isNullConstant(), llvm::isPowerOf2_32(), N, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by performSELECTCombine().

getAllOnesMask()

SDValue getAllOnesMask ( MVT VecVT, SDValue VL, const SDLoc & DL, SelectionDAG & DAG )

static

Creates an all ones mask suitable for masking a vector of type VecTy with vector length VL.

Definition at line 3033 of file RISCVISelLowering.cpp.

References DL, getMaskTypeFor(), and llvm::SelectionDAG::getNode().

Referenced by getDefaultScalableVLOps(), getDefaultVLOps(), lowerVectorIntrinsicScalars(), and lowerVZIP().

getContainerForFixedLengthVector() [1/2]

MVT getContainerForFixedLengthVector ( const TargetLowering & TLI, MVT VT, const RISCVSubtarget & Subtarget )

static

Definition at line 2955 of file RISCVISelLowering.cpp.

References assert(), llvm::RISCVSubtarget::getELen(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalableVectorVT(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::isFixedLengthVector(), llvm::isPowerOf2_32(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::RISCV::RVVBitsPerBlock, llvm::MVT::SimpleTy, and useRVVForFixedLengthVectorVT().

getContainerForFixedLengthVector() [2/2]

MVT getContainerForFixedLengthVector ( SelectionDAG & DAG, MVT VT, const RISCVSubtarget & Subtarget )

static

Definition at line 2990 of file RISCVISelLowering.cpp.

References getContainerForFixedLengthVector(), and llvm::SelectionDAG::getTargetLoweringInfo().

getDefaultScalableVLOps()

std::pair< SDValue, SDValue > getDefaultScalableVLOps ( MVT VecVT, const SDLoc & DL, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 3040 of file RISCVISelLowering.cpp.

References assert(), DL, getAllOnesMask(), llvm::SelectionDAG::getRegister(), llvm::RISCVSubtarget::getXLenVT(), and llvm::MVT::isScalableVector().

Referenced by combineToVWMACC(), combineVqdotAccum(), getDefaultVLOps(), lowerVECTOR_SHUFFLE(), and performSHLCombine().

getDefaultVLOps() [1/2]

std::pair< SDValue, SDValue > getDefaultVLOps ( MVT VecVT, MVT ContainerVT, const SDLoc & DL, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 3062 of file RISCVISelLowering.cpp.

References assert(), DL, getDefaultScalableVLOps(), getDefaultVLOps(), llvm::MVT::getVectorNumElements(), llvm::MVT::isFixedLengthVector(), and llvm::MVT::isScalableVector().

getDefaultVLOps() [2/2]

std::pair< SDValue, SDValue > getDefaultVLOps ( uint64_t NumElts, MVT ContainerVT, const SDLoc & DL, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 3049 of file RISCVISelLowering.cpp.

References assert(), DL, getAllOnesMask(), llvm::SelectionDAG::getConstant(), llvm::RISCVSubtarget::getXLenVT(), and llvm::MVT::isScalableVector().

Referenced by combineToVCPOP(), getDefaultVLOps(), getWideningInterleave(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaVID(), lowerCttzElts(), lowerFMAXIMUM_FMINIMUM(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT_XROUND(), lowerVZIP(), matchSplatAsGather(), performFP_TO_INTCombine(), and llvm::RISCVTargetLowering::ReplaceNodeResults().

getDeinterleaveShiftAndTrunc()

SDValue getDeinterleaveShiftAndTrunc ( const SDLoc & DL, MVT VT, SDValue Src, unsigned Factor, unsigned Index, SelectionDAG & DAG )

static

Definition at line 5049 of file RISCVISelLowering.cpp.

References llvm::MVT::changeVectorElementType(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getInsertSubvector(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::ISD::SRL, and llvm::ISD::TRUNCATE.

Referenced by lowerVECTOR_SHUFFLE().

getExactInteger()

std::optional< APInt > getExactInteger ( const APFloat & APF, uint32_t BitWidth )

static

Definition at line 3689 of file RISCVISelLowering.cpp.

References llvm::BitWidth, llvm::APFloat::convertToInteger(), llvm::APInt::extractBits(), llvm::APFloatBase::opInvalidOp, and llvm::TowardZero.

Referenced by isSimpleVIDSequence().

getIntrinsicForMaskedAtomicRMWBinOp()

Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp ( unsigned XLen, AtomicRMWInst::BinOp BinOp )

static

Definition at line 24312 of file RISCVISelLowering.cpp.

References llvm::AtomicRMWInst::Add, llvm_unreachable, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, and llvm::AtomicRMWInst::Xchg.

getLargeExternalSymbol()

SDValue getLargeExternalSymbol ( ExternalSymbolSDNode * N, const SDLoc & DL, EVT Ty, SelectionDAG & DAG )

static

Definition at line 8944 of file RISCVISelLowering.cpp.

References llvm::RISCVConstantPoolValue::Create(), DL, llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstantPool(), and N.

Referenced by llvm::RISCVTargetLowering::LowerCall().

getLargeGlobalAddress()

SDValue getLargeGlobalAddress ( GlobalAddressSDNode * N, const SDLoc & DL, EVT Ty, SelectionDAG & DAG )

static

Definition at line 8934 of file RISCVISelLowering.cpp.

References llvm::RISCVConstantPoolValue::Create(), DL, llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstantPool(), and N.

Referenced by llvm::RISCVTargetLowering::LowerCall().

getMaskTypeFor()

MVT getMaskTypeFor ( MVT VecVT )

static

Return the type of the mask type suitable for masking the provided vector type.

This is simply an i1 element type vector of the same (possibly scalable) length.

Definition at line 3025 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), and llvm::MVT::isVector().

getPACKOpcode()

unsigned getPACKOpcode ( unsigned DestBW, const RISCVSubtarget & Subtarget )

static

Definition at line 4308 of file RISCVISelLowering.cpp.

References assert(), llvm::RISCVSubtarget::is64Bit(), and llvm_unreachable.

Referenced by lowerBuildVectorViaPacking().

getPrefTypeAlign()

Align getPrefTypeAlign ( EVT VT, SelectionDAG & DAG )

static

Definition at line 23360 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), and llvm::EVT::getTypeForEVT().

getQDOTXResultType()

MVT getQDOTXResultType ( MVT OpVT )

static

Definition at line 19369 of file RISCVISelLowering.cpp.

References assert(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownMultipleOf().

Referenced by foldReduceOperandViaVQDOT().

getRISCVVLOp()

unsigned getRISCVVLOp ( SDValue Op )

static

Get a RISC-V target specified VL op for a given SDNode.

Definition at line 7156 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::ISD::FMA, llvm_unreachable, OP_CASE, llvm::ISD::OR, ROTR, llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND, llvm::ISD::STRICT_FMA, VP_CASE, llvm::ISD::VSELECT, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

getRISCVWOpcode()

unsigned getRISCVWOpcode ( unsigned Opcode )

static

Definition at line 14438 of file RISCVISelLowering.cpp.

References llvm_unreachable, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::UDIV, and llvm::ISD::UREM.

getRVVFPReductionOpAndOperands()

std::tuple< unsigned, SDValue, SDValue > getRVVFPReductionOpAndOperands ( SDValue Op, SelectionDAG & DAG, EVT EltVT, const RISCVSubtarget & Subtarget )

static

Definition at line 11672 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getExtractVectorElt(), and llvm_unreachable.

getRVVReductionOp()

unsigned getRVVReductionOp ( unsigned ISDOpcode )

static

Definition at line 11460 of file RISCVISelLowering.cpp.

References llvm_unreachable.

getShlAddShlAdd()

SDValue getShlAddShlAdd ( SDNode * N, SelectionDAG & DAG, unsigned ShX, unsigned ShY, bool AddX, unsigned Shift )

static

Definition at line 16614 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::PatternMatch::m_And(), llvm::PatternMatch::m_SpecificInt(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), llvm::ISD::SHL, and X.

Referenced by expandMulToShlAddShlAdd().

getSingleShuffleSrc()

SDValue getSingleShuffleSrc ( MVT VT, SDValue V1, SDValue V2 )

static

Definition at line 4915 of file RISCVISelLowering.cpp.

References foldConcatVector(), llvm::SDValue::getValueType(), llvm::MVT::getVectorNumElements(), llvm::SDValue::isUndef(), and SDValue().

Referenced by lowerVECTOR_SHUFFLE().

getSmallestVTForIndex()

std::optional< MVT > getSmallestVTForIndex ( MVT VecVT, unsigned MaxIdx, SDLoc DL, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 10203 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::bitsGT(), DL, llvm::MVT::getDoubleNumVectorElementsVT(), llvm::RISCVTargetLowering::getM1VT(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::isScalableVector(), and llvm::MVT::isValid().

getTargetNode() [1/4]

SDValue getTargetNode ( BlockAddressSDNode * N, const SDLoc & DL, EVT Ty, SelectionDAG & DAG, unsigned Flags )

static

Definition at line 8917 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getTargetBlockAddress(), and N.

getTargetNode() [2/4]

SDValue getTargetNode ( ConstantPoolSDNode * N, const SDLoc & DL, EVT Ty, SelectionDAG & DAG, unsigned Flags )

static

Definition at line 8923 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getTargetConstantPool(), and N.

getTargetNode() [3/4]

SDValue getTargetNode ( GlobalAddressSDNode * N, const SDLoc & DL, EVT Ty, SelectionDAG & DAG, unsigned Flags )

static

Definition at line 8912 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getTargetGlobalAddress(), and N.

getTargetNode() [4/4]

SDValue getTargetNode ( JumpTableSDNode * N, const SDLoc & DL, EVT Ty, SelectionDAG & DAG, unsigned Flags )

static

Definition at line 8929 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getTargetJumpTable(), and N.

getVCIXISDNodeVOID()

SDValue getVCIXISDNodeVOID ( SDValue Op, SelectionDAG & DAG, unsigned Type )

inlinestatic

Definition at line 11164 of file RISCVISelLowering.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::SmallVectorImpl< T >::erase(), llvm::SelectionDAG::getNode(), and processVCIXOperands().

getVCIXISDNodeWCHAIN()

SDValue getVCIXISDNodeWCHAIN ( SDValue Op, SelectionDAG & DAG, unsigned Type )

inlinestatic

Definition at line 11127 of file RISCVISelLowering.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::begin(), convertFromScalableVector(), DL, llvm::SmallVectorImpl< T >::erase(), llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getSubtarget(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), and processVCIXOperands().

getVecReduceOpcode()

unsigned getVecReduceOpcode ( unsigned Opc )

static

Given a binary operator, return the associative generic ISD::VECREDUCE_OP which corresponds to it.

Definition at line 15255 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::FADD, llvm_unreachable, Opc, llvm::ISD::OR, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMAX, llvm::ISD::UMIN, and llvm::ISD::XOR.

Referenced by combineBinOpOfExtractToReduceTree().

getVLOperand()

SDValue getVLOperand ( SDValue Op )

static

Definition at line 2866 of file RISCVISelLowering.cpp.

References assert(), II, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, and SDValue().

Referenced by lowerVectorIntrinsicScalars().

getVSlidedown()

SDValue getVSlidedown ( SelectionDAG & DAG, const RISCVSubtarget & Subtarget, const SDLoc & DL, EVT VT, SDValue Passthru, SDValue Op, SDValue Offset, SDValue Mask, SDValue VL, unsigned Policy = RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED )

static

Definition at line 3660 of file RISCVISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDValue::isUndef(), llvm::RISCVVType::MASK_AGNOSTIC, llvm::Offset, llvm::RISCVVType::TAIL_AGNOSTIC, and llvm::RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED.

Referenced by lowerBUILD_VECTOR(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlidedown(), and llvm::RISCVTargetLowering::ReplaceNodeResults().

getVSlideup()

SDValue getVSlideup ( SelectionDAG & DAG, const RISCVSubtarget & Subtarget, const SDLoc & DL, EVT VT, SDValue Passthru, SDValue Op, SDValue Offset, SDValue Mask, SDValue VL, unsigned Policy = RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED )

static

Definition at line 3672 of file RISCVISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDValue::isUndef(), llvm::RISCVVType::MASK_AGNOSTIC, llvm::Offset, llvm::RISCVVType::TAIL_AGNOSTIC, and llvm::RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED.

Referenced by lowerBUILD_VECTOR(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlideup(), and llvm::RISCVTargetLowering::PerformDAGCombine().

getWideningInterleave()

SDValue getWideningInterleave ( SDValue EvenV, SDValue OddV, const SDLoc & DL, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 5415 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::changeTypeToInteger(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), getWideningSpread(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::SDValue::isUndef(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::multiplyCoefficientBy().

Referenced by lowerVECTOR_SHUFFLE().

getWideningSpread()

SDValue getWideningSpread ( SDValue V, unsigned Factor, unsigned Index, const SDLoc & DL, SelectionDAG & DAG )

static

Definition at line 5390 of file RISCVISelLowering.cpp.

References llvm::MVT::changeTypeToInteger(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::ISD::SHL, and llvm::ISD::ZERO_EXTEND.

Referenced by getWideningInterleave(), and lowerVECTOR_SHUFFLE().

getZeroPaddedAdd()

SDValue getZeroPaddedAdd ( const SDLoc & DL, SDValue A, SDValue B, SelectionDAG & DAG )

static

Given fixed length vectors A and B with equal element types, but possibly different number of elements, return A + B where either A or B is zero padded to the larger number of elements.

Definition at line 19378 of file RISCVISelLowering.cpp.

References A(), llvm::ISD::ADD, assert(), B(), DL, llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), and std::swap().

Referenced by foldReduceOperandViaVQDOT().

isAlternating()

bool isAlternating ( const std::array< std::pair< int, int >, 2 > & SrcInfo, ArrayRef< int > Mask, unsigned Factor, bool RequiredPolarity )

static

Definition at line 4998 of file RISCVISelLowering.cpp.

References assert(), llvm::CallingConv::C, and llvm::enumerate().

Referenced by isZipEven(), and isZipOdd().

isCompressMask()

bool isCompressMask ( ArrayRef< int > Mask )

static

Definition at line 5733 of file RISCVISelLowering.cpp.

References llvm::enumerate(), and llvm::Last.

Referenced by lowerVECTOR_SHUFFLE().

isElementRotate()

bool isElementRotate ( const std::array< std::pair< int, int >, 2 > & SrcInfo, unsigned NumElts )

static

Definition at line 4990 of file RISCVISelLowering.cpp.

Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal(), and lowerVECTOR_SHUFFLE().

isInterleaveShuffle()

bool isInterleaveShuffle ( ArrayRef< int > Mask, MVT VT, int & EvenSrc, int & OddSrc, const RISCVSubtarget & Subtarget )

static

Is this shuffle interleaving contiguous elements from one vector into the even elements and contiguous elements from another vector into the odd elements.

EvenSrc will contain the element that should be in the first even element. OddSrc will contain the element that should be in the first odd element. These can be the first element in a source or the element half way through the source.

Definition at line 4936 of file RISCVISelLowering.cpp.

References assert(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::ShuffleVectorInst::isInterleaveMask(), and Size.

Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal(), and lowerVECTOR_SHUFFLE().

isLegalBitRotate()

bool isLegalBitRotate ( ArrayRef< int > Mask, EVT VT, const RISCVSubtarget & Subtarget, MVT & RotateVT, unsigned & RotateAmt )

static

Definition at line 5558 of file RISCVISelLowering.cpp.

References llvm::MVT::getIntegerVT(), llvm::EVT::getScalarSizeInBits(), llvm::RISCVSubtarget::getTargetLowering(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ShuffleVectorInst::isBitRotateMask(), and llvm::TargetLoweringBase::isTypeLegal().

Referenced by lowerShuffleViaVRegSplitting(), lowerVECTOR_SHUFFLE(), and lowerVECTOR_SHUFFLEAsRotate().

isLocalRepeatingShuffle()

bool isLocalRepeatingShuffle ( ArrayRef< int > Mask, int Span )

static

Is this mask local (i.e.

elements only move within their local span), and repeating (that is, the same rearrangement is being done within each span)?

Definition at line 5815 of file RISCVISelLowering.cpp.

References llvm::enumerate(), and I.

Referenced by lowerVECTOR_SHUFFLE().

isLowSourceShuffle()

bool isLowSourceShuffle ( ArrayRef< int > Mask, int Span )

static

Is this mask only using elements from the first span of the input?

Definition at line 5832 of file RISCVISelLowering.cpp.

References llvm::all_of().

Referenced by lowerVECTOR_SHUFFLE().

isMaskedSlidePair()

bool isMaskedSlidePair ( ArrayRef< int > Mask, std::array< std::pair< int, int >, 2 > & SrcInfo )

static

Is this mask representing a masked combination of two slides?

Definition at line 4971 of file RISCVISelLowering.cpp.

References assert(), llvm::isMaskedSlidePair(), and std::swap().

isNonZeroAVL()

bool isNonZeroAVL ( SDValue AVL )

static

Definition at line 11583 of file RISCVISelLowering.cpp.

References llvm::dyn_cast().

Referenced by combineBinOpToReduce(), and lowerReductionSeq().

isPromotedOpNeedingSplit()

bool isPromotedOpNeedingSplit ( SDValue Op, const RISCVSubtarget & Subtarget )

static

Definition at line 7313 of file RISCVISelLowering.cpp.

References llvm::RISCVSubtarget::hasVInstructionsBF16(), llvm::RISCVSubtarget::hasVInstructionsBF16Minimal(), llvm::RISCVSubtarget::hasVInstructionsF16(), llvm::RISCVSubtarget::hasVInstructionsF16Minimal(), llvm::is_contained(), ZvfbfaOps, and ZvfbfaVPOps.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

isSimm12Constant()

bool isSimm12Constant ( SDValue V )

static

Definition at line 9222 of file RISCVISelLowering.cpp.

References llvm::isa().

Referenced by lowerSelectToBinOp().

isSimpleVIDSequence()

std::optional< VIDSequence > isSimpleVIDSequence ( SDValue Op, unsigned EltSizeInBits )

static

Definition at line 3722 of file RISCVISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, llvm::cast(), llvm::enumerate(), getExactInteger(), llvm::APInt::getSExtValue(), isConstant(), llvm::APInt::sdiv(), and llvm::APInt::srem().

Referenced by lowerBuildVectorViaVID(), and llvm::RISCVTargetLowering::PerformDAGCombine().

isSpanSplatShuffle()

bool isSpanSplatShuffle ( ArrayRef< int > Mask, int Span )

static

Return true for a mask which performs an arbitrary shuffle within the first span, and then repeats that same result across all remaining spans.

Note that this doesn't check if all the inputs come from a single span!

Definition at line 5839 of file RISCVISelLowering.cpp.

References llvm::enumerate(), and I.

Referenced by lowerVECTOR_SHUFFLE().

isValidEGW()

bool isValidEGW ( int EGS, EVT VT, const RISCVSubtarget & Subtarget )

inlinestatic

Definition at line 10887 of file RISCVISelLowering.cpp.

References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), and llvm::RISCV::RVVBitsPerBlock.

isValidVisniInsertExtractIndex()

bool isValidVisniInsertExtractIndex ( SDValue Idx )

static

Definition at line 10224 of file RISCVISelLowering.cpp.

References llvm::dyn_cast(), llvm::isNullConstant(), and llvm::isUInt().

isZipEven()

bool isZipEven ( const std::array< std::pair< int, int >, 2 > & SrcInfo, ArrayRef< int > Mask, unsigned & Factor )

static

Given a shuffle which can be represented as a pair of two slides, see if it is a zipeven idiom.

Zipeven is: vs2: a0 a1 a2 a3 vs1: b0 b1 b2 b3 vd: a0 b0 a2 b2

Definition at line 5021 of file RISCVISelLowering.cpp.

References isAlternating(), and llvm::isPowerOf2_32().

Referenced by lowerVECTOR_SHUFFLE().

isZipOdd()

bool isZipOdd ( const std::array< std::pair< int, int >, 2 > & SrcInfo, ArrayRef< int > Mask, unsigned & Factor )

static

Given a shuffle which can be represented as a pair of two slides, see if it is a zipodd idiom.

Zipodd is: vs2: a0 a1 a2 a3 vs1: b0 b1 b2 b3 vd: a1 b1 a3 b3 Note that the operand order is swapped due to the way we canonicalize the slides, so SrCInfo[0] is vs1, and SrcInfo[1] is vs2.

Definition at line 5036 of file RISCVISelLowering.cpp.

References isAlternating(), and llvm::isPowerOf2_32().

Referenced by lowerVECTOR_SHUFFLE().

legalizeScatterGatherIndexType()

bool legalizeScatterGatherIndexType ( SDLoc DL, SDValue & Index, ISD::MemIndexType & IndexType, RISCVTargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 19879 of file RISCVISelLowering.cpp.

References llvm::EVT::bitsLT(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getSubtarget(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::UNSIGNED_SCALED.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

lookupMaskedIntrinsic()

const RISCV::RISCVMaskedPseudoInfo * lookupMaskedIntrinsic ( uint16_t MCOpcode, RISCVVType::VLMUL LMul, unsigned SEW )

static

Definition at line 22565 of file RISCVISelLowering.cpp.

References assert(), and llvm::Masked.

Referenced by emitVFROUND_NOEXCEPT_MASK().

LowerATOMIC_FENCE()

SDValue LowerATOMIC_FENCE ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 6857 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::SequentiallyConsistent, llvm::SyncScope::SingleThread, and llvm::SyncScope::System.

lowerBitreverseShuffle()

SDValue lowerBitreverseShuffle ( ShuffleVectorSDNode * SVN, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 5508 of file RISCVISelLowering.cpp.

References assert(), llvm::ISD::BITREVERSE, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getInsertSubvector(), llvm::EVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getSimpleValueType(), llvm::RISCVSubtarget::getTargetLowering(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::ShuffleVectorInst::isReverseMask(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::PowerOf2Ceil(), SDValue(), llvm::ArrayRef< T >::size(), and llvm::ISD::SRL.

Referenced by lowerVECTOR_SHUFFLE().

lowerBUILD_VECTOR()

SDValue lowerBUILD_VECTOR ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 4385 of file RISCVISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::all_of(), llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ArrayRef(), assert(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::MVT::bitsLE(), llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::cast(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), llvm::count_if(), DL, llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::enumerate(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtractSubvector(), llvm::MVT::getFixedSizeInBits(), llvm::RISCVSubtarget::getFLen(), llvm::SelectionDAG::getInsertSubvector(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::RISCVTargetLowering::getLMUL(), llvm::RISCVTargetLowering::getM1VT(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealVLen(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplatBuildVector(), llvm::getSplatValue(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorMinNumElements(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), getVSlidedown(), getVSlideup(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::ISD::isBuildVectorOfConstantFPSDNodes(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::RISCVVType::LMUL_2, llvm::RISCVVType::LMUL_4, llvm::RISCVVType::LMUL_8, lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaPacking(), llvm::PatternMatch::m_ExtractElt(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Zero(), llvm::RISCVVType::MASK_AGNOSTIC, matchSplatAsGather(), llvm::Offset, Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::reserve(), SDValue(), llvm::ISD::SETNE, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::Splat, llvm::RISCVVType::TAIL_AGNOSTIC, and llvm::ISD::VSELECT.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerBuildVectorOfConstants()

SDValue lowerBuildVectorOfConstants ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 4068 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLE(), llvm::cast(), llvm::MVT::changeVectorElementType(), llvm::SelectionDAG::ComputeMaxSignificantBits(), convertFromScalableVector(), convertToScalableVector(), llvm::divideCeil(), DL, llvm::enumerate(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::RISCVSubtarget::getELen(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getInsertVectorElt(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getSignedConstant(), llvm::MVT::getSizeInBits(), llvm::getSplatValue(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::RISCVSubtarget::is64Bit(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::isInt(), llvm::MVT::isInteger(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaVID(), llvm::maskTrailingOnes(), Opc, OpIdx, SDValue(), llvm::SelectionDAG::shouldOptForSize(), llvm::SignExtend64(), and llvm::Splat.

Referenced by lowerBUILD_VECTOR().

lowerBuildVectorViaDominantValues()

SDValue lowerBuildVectorViaDominantValues ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Try and optimize BUILD_VECTORs with "dominant values" - these are values which constitute a large proportion of the elements.

In such cases we can splat a vector with the dominant element and make up the shortfall with INSERT_VECTOR_ELTs. Returns SDValue if not profitable. Note that this includes vectors of 2 elements by association. The upper-most element is the "dominant" one, allowing us to use a splat to "insert" the upper element, and an insert of the lower element at position 0, which improves codegen.

Definition at line 3963 of file RISCVISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), llvm::Count, llvm::count_if(), DL, llvm::dyn_cast(), llvm::enumerate(), llvm::SelectionDAG::getBuildVector(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getInsertVectorElt(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSplatBuildVector(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::Log2_32(), OpIdx, SDValue(), llvm::SelectionDAG::shouldOptForSize(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::size(), llvm::transform(), and llvm::ISD::VSELECT.

Referenced by lowerBUILD_VECTOR(), and lowerBuildVectorOfConstants().

lowerBuildVectorViaPacking()

SDValue lowerBuildVectorViaPacking ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Double the element size of the build vector to reduce the number of vslide1down in the build vector chain.

In the worst case, this trades three scalar operations for 1 vector operation. Scalar operations are generally lower latency, and for out-of-order cores we also benefit from additional parallelism.

Definition at line 4328 of file RISCVISelLowering.cpp.

References A(), llvm::ISD::AND, assert(), B(), llvm::SDNodeFlags::Disjoint, DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getIntegerVT(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), getPACKOpcode(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::ISD::OR, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::reserve(), SDValue(), llvm::ISD::SHL, and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by lowerBUILD_VECTOR().

lowerBuildVectorViaVID()

SDValue lowerBuildVectorViaVID ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 3883 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::MVT::changeVectorElementTypeToInteger(), convertFromScalableVector(), DL, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSignedConstant(), INT64_MIN, llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::isInt(), llvm::isPowerOf2_32(), llvm::isPowerOf2_64(), isSimpleVIDSequence(), llvm::isUInt(), llvm::Log2_64(), llvm::ISD::MUL, SDValue(), llvm::ISD::SHL, llvm::ISD::SINT_TO_FP, llvm::ISD::SRL, and llvm::ISD::SUB.

Referenced by lowerBuildVectorOfConstants(), and llvm::RISCVTargetLowering::LowerOperation().

lowerConstant()

SDValue lowerConstant ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 6776 of file RISCVISelLowering.cpp.

References assert(), llvm::cast(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::RISCVMatInt::generateInstSeq(), llvm::RISCVMatInt::generateTwoRegInstSeq(), llvm::RISCVSubtarget::getMaxBuildIntsCost(), llvm::isInt(), SDValue(), llvm::SelectionDAG::shouldOptForSize(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and llvm::RISCVSubtarget::useConstantPoolForLargeInts().

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerCttzElts()

SDValue lowerCttzElts ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 10805 of file RISCVISelLowering.cpp.

References convertToScalableVector(), DL, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getElementCount(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorElementCount(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::isOneConstant(), N, and llvm::ISD::SETLT.

Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().

lowerDisjointIndicesShuffle()

SDValue lowerDisjointIndicesShuffle ( ShuffleVectorSDNode * SVN, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Given a shuffle where the indices are disjoint between the two sources, e.g.:

t2:v4i8 = vector_shuffle t0:v4i8, t1:v4i8, <2, 7, 1, 4>

Merge the two sources into one and do a single source shuffle:

t2:v4i8 = vselect t1:v4i8, t0:v4i8, <0, 1, 0, 1> t3:v4i8 = vector_shuffle t2:v4i8, undef, <2, 3, 1, 0>

A vselect will either be merged into a masked instruction or be lowered as a vmerge.vvm, which is cheaper than a vrgather.vv.

Definition at line 5764 of file RISCVISelLowering.cpp.

References llvm::MVT::changeVectorElementType(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), Select, and llvm::ISD::VSELECT.

Referenced by lowerVECTOR_SHUFFLE().

lowerFABSorFNEG()

SDValue lowerFABSorFNEG ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 7072 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignMask(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), and llvm::ISD::XOR.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerFCOPYSIGN()

SDValue lowerFCOPYSIGN ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 7095 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::SDNodeFlags::Disjoint, DL, llvm::ISD::FCOPYSIGN, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignMask(), llvm::SDValue::getValueSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), llvm_unreachable, llvm::ISD::OR, llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerFixedVectorSegLoadIntrinsics()

SDValue lowerFixedVectorSegLoadIntrinsics ( unsigned IntNo, SDValue Op, const RISCVSubtarget & Subtarget, SelectionDAG & DAG )

static

Definition at line 11174 of file RISCVISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::cast(), convertFromScalableVector(), convertToScalableVector(), DL, getContainerForFixedLengthVector(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::MVT::getRISCVVectorTupleVT(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorMinNumElements(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INTRINSIC_W_CHAIN, llvm_unreachable, llvm::Log2_64(), llvm::RISCVVType::MASK_AGNOSTIC, Results, and llvm::RISCVVType::TAIL_AGNOSTIC.

lowerFixedVectorSegStoreIntrinsics()

SDValue lowerFixedVectorSegStoreIntrinsics ( unsigned IntNo, SDValue Op, const RISCVSubtarget & Subtarget, SelectionDAG & DAG )

static

Definition at line 11320 of file RISCVISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::cast(), convertToScalableVector(), DL, getContainerForFixedLengthVector(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::MVT::getRISCVVectorTupleVT(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorMinNumElements(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INTRINSIC_VOID, llvm_unreachable, llvm::Log2_64(), and Ptr.

lowerFMAXIMUM_FMINIMUM()

SDValue lowerFMAXIMUM_FMINIMUM ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 6988 of file RISCVISelLowering.cpp.

References convertFromScalableVector(), convertToScalableVector(), DL, getContainerForFixedLengthVector(), getDefaultVLOps(), getMaskTypeFor(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::MVT::isVector(), Opc, llvm::ISD::SETOEQ, X, and Y.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerFP_TO_INT()

SDValue lowerFP_TO_INT ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 3312 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::RISCVSubtarget::hasStdExtZfhOrZhinx(), and llvm::ISD::STRICT_FP_EXTEND.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerFP_TO_INT_SAT()

SDValue lowerFP_TO_INT_SAT ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 3199 of file RISCVISelLowering.cpp.

References assert(), llvm::cast(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::RISCVSubtarget::hasStdExtZfhOrZhinx(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), Opc, llvm::RISCVFPRndMode::RTZ, SDValue(), and llvm::ISD::SETUO.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerFTRUNC_FCEIL_FFLOOR_FROUND()

SDValue lowerFTRUNC_FCEIL_FFLOOR_FROUND ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 3591 of file RISCVISelLowering.cpp.

References llvm::APFloat::convertFromAPInt(), DL, llvm::SelectionDAG::getConstantFP(), llvm::MVT::getFltSemantics(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isVector(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, SDValue(), llvm::APFloatBase::semanticsPrecision(), and llvm::SelectionDAG::shouldOptForSize().

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerGetVectorLength()

SDValue lowerGetVectorLength ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 10770 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::RISCVVType::encodeLMUL(), llvm::RISCVVType::encodeSEW(), llvm::RISCVSubtarget::getELen(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isPowerOf2_32(), N, llvm::RISCV::RVVBitsPerBlock, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().

lowerINT_TO_FP()

SDValue lowerINT_TO_FP ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 3172 of file RISCVISelLowering.cpp.

References DL, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::RISCVSubtarget::hasStdExtZfhOrZhinx(), and llvm::ISD::STRICT_FP_ROUND.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

LowerPREFETCH()

SDValue LowerPREFETCH ( SDValue Op, const RISCVSubtarget & Subtarget, SelectionDAG & DAG )

static

Definition at line 6846 of file RISCVISelLowering.cpp.

lowerReductionSeq()

SDValue lowerReductionSeq ( unsigned RVVOpcode, MVT ResVT, SDValue StartValue, SDValue Vec, SDValue Mask, SDValue VL, const SDLoc & DL, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Helper to lower a reduction sequence of the form: scalar = reduce_op vec, scalar_start.

Definition at line 11592 of file RISCVISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::MVT::bitsLE(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getExtractVectorElt(), llvm::SelectionDAG::getInsertSubvector(), llvm::RISCVTargetLowering::getM1VT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), isNonZeroAVL(), lowerScalarInsert(), and llvm::RISCVVType::TAIL_AGNOSTIC.

lowerScalarInsert()

SDValue lowerScalarInsert ( SDValue Scalar, SDValue VL, MVT VT, const SDLoc & DL, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 4838 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLE(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::isa(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::isNullConstant(), llvm::MVT::isScalableVector(), lowerScalarSplat(), and llvm::ISD::SIGN_EXTEND.

Referenced by combineBinOpToReduce(), and lowerReductionSeq().

lowerScalarSplat()

SDValue lowerScalarSplat ( SDValue Passthru, SDValue Scalar, SDValue VL, MVT VT, const SDLoc & DL, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 4784 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::changeVectorElementType(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::isa(), llvm::MVT::isFloatingPoint(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::SDValue::isUndef(), lowerScalarSplat(), llvm::ISD::SIGN_EXTEND, llvm::Splat, and splatSplitI64WithVL().

Referenced by lowerScalarInsert(), and lowerScalarSplat().

lowerSelectToBinOp()

SDValue lowerSelectToBinOp ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 9226 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::cast(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getAllOnesConstant(), llvm::SDNode::getAsAPIntVal(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::hasConditionalMoveFusion(), llvm::RISCVSubtarget::hasCZEROLike(), llvm::RISCVSubtarget::hasShlAdd(), llvm::isa(), llvm::isAllOnesConstant(), llvm::isNullConstant(), llvm::isPowerOf2_64(), llvm::MVT::isScalarInteger(), isSimm12Constant(), LHS, llvm::Log2_64(), matchSetCC(), N, llvm::ISD::OR, RHS, SDValue(), llvm::ISD::SETCC, and llvm::ISD::XOR.

lowerShuffleViaVRegSplitting()

SDValue lowerShuffleViaVRegSplitting ( ShuffleVectorSDNode * SVN, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 5605 of file RISCVISelLowering.cpp.

References assert(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), convertToScalableVector(), llvm::Data, DL, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorTemplateCommon< T, typename >::end(), getContainerForFixedLengthVector(), llvm::MVT::getFixedSizeInBits(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::RISCVTargetLowering::getM1VT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::RISCVSubtarget::getRealVLen(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), llvm::MVT::getVectorMinNumElements(), llvm::MVT::getVectorVT(), isLegalBitRotate(), N, llvm::processShuffleMasks(), SDValue(), and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by lowerVECTOR_SHUFFLE().

lowerVECTOR_SHUFFLE()

SDValue lowerVECTOR_SHUFFLE ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 5885 of file RISCVISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::any_of(), assert(), llvm::MVT::bitsGT(), llvm::CallingConv::C, llvm::cast(), llvm::MVT::changeTypeToInteger(), llvm::MVT::changeVectorElementType(), Concat, llvm::ISD::CONCAT_VECTORS, convertFromScalableVector(), convertToScalableVector(), llvm::count_if(), DL, llvm::enumerate(), llvm::ISD::EXTLOAD, foldConcatVector(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultScalableVLOps(), getDefaultVLOps(), getDeinterleaveShiftAndTrunc(), llvm::MVT::getDoubleNumVectorElementsVT(), llvm::SelectionDAG::getElementCount(), llvm::RISCVSubtarget::getELen(), llvm::SelectionDAG::getExtLoad(), llvm::SelectionDAG::getExtractSubvector(), llvm::TypeSize::getFixed(), llvm::SDNode::getFlags(), llvm::MVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getInsertSubvector(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::SelectionDAG::getLoad(), llvm::RISCVTargetLowering::getM1VT(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::RISCVSubtarget::getRealVLen(), llvm::SelectionDAG::getRegister(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getScalarType(), llvm::SelectionDAG::getSetCC(), getSingleShuffleSrc(), llvm::MVT::getSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::MVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorMinNumElements(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), getVSlidedown(), getVSlideup(), llvm::SelectionDAG::getVTList(), getWideningInterleave(), getWideningSpread(), llvm::RISCVSubtarget::getXLenVT(), llvm::Hi, I, Info, llvm::ISD::INTRINSIC_W_CHAIN, isCompressMask(), llvm::ShuffleVectorInst::isDeInterleaveMaskOfFactor(), isElementRotate(), llvm::MVT::isFloatingPoint(), llvm::ShuffleVectorInst::isIdentityMask(), llvm::MVT::isInteger(), isInterleaveShuffle(), isLegalBitRotate(), isLocalRepeatingShuffle(), isLowSourceShuffle(), llvm::isMaskedSlidePair(), llvm::ISD::isNormalLoad(), llvm::isPowerOf2_32(), llvm::ShuffleVectorInst::isReverseMask(), llvm::ShuffleVectorInst::isSingleSourceMask(), isSpanSplatShuffle(), llvm::ShuffleVectorSDNode::isSplat(), llvm::ShuffleVectorSDNode::isSplatMask(), llvm::SelectionDAG::isSplatValue(), llvm::RISCVTargetLowering::isSpreadMask(), llvm::isUInt(), llvm::SDValue::isUndef(), isZipEven(), isZipOdd(), llvm::Lo, lowerBitreverseShuffle(), lowerDisjointIndicesShuffle(), lowerShuffleViaVRegSplitting(), lowerVECTOR_SHUFFLEAsRotate(), lowerVECTOR_SHUFFLEAsVRGatherVX(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVZIP(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), N, llvm::Offset, Opc, llvm::PowerOf2Ceil(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::ISD::SETNE, Size, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::Splat, llvm::RISCVVType::TAIL_AGNOSTIC, tryWidenMaskForShuffle(), llvm::ISD::VECTOR_COMPRESS, llvm::ISD::VECTOR_REVERSE, llvm::ISD::VSELECT, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::RISCVTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

lowerVECTOR_SHUFFLEAsRotate()

SDValue lowerVECTOR_SHUFFLEAsRotate ( ShuffleVectorSDNode * SVN, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 5577 of file RISCVISelLowering.cpp.

References llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::getScalarType(), llvm::SDNode::getValueType(), isLegalBitRotate(), llvm::ISD::ROTL, and SDValue().

Referenced by lowerVECTOR_SHUFFLE().

lowerVECTOR_SHUFFLEAsVRGatherVX()

SDValue lowerVECTOR_SHUFFLEAsVRGatherVX ( ShuffleVectorSDNode * SVN, const RISCVSubtarget & Subtarget, SelectionDAG & DAG )

static

Match a single source shuffle which is an identity except that some particular element is repeated.

This can be lowered as a masked vrgather.vi/vx. Note that the two source form of this is handled by the recursive splitting logic and doesn't need special handling.

Definition at line 5073 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::enumerate(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::SDValue::isUndef(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::Splat, and llvm::ISD::VSELECT.

Referenced by lowerVECTOR_SHUFFLE().

lowerVECTOR_SHUFFLEAsVSlide1()

SDValue lowerVECTOR_SHUFFLEAsVSlide1 ( const SDLoc & DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const RISCVSubtarget & Subtarget, SelectionDAG & DAG )

static

Match v(f)slide1up/down idioms.

These operations involve sliding N-1 elements to make room for an inserted scalar at one end.

Definition at line 5242 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::sampleprof::Base, llvm::cast(), llvm::MVT::changeVectorElementTypeToInteger(), convertFromScalableVector(), convertToScalableVector(), DL, E(), llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasVInstructionsF16(), llvm::isa(), llvm::MVT::isFloatingPoint(), llvm::Offset, SDValue(), llvm::Splat, and std::swap().

Referenced by lowerVECTOR_SHUFFLE().

lowerVECTOR_SHUFFLEAsVSlidedown()

SDValue lowerVECTOR_SHUFFLEAsVSlidedown ( const SDLoc & DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const RISCVSubtarget & Subtarget, SelectionDAG & DAG )

static

Definition at line 5122 of file RISCVISelLowering.cpp.

References convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getUNDEF(), getVSlidedown(), llvm::RISCVSubtarget::getXLenVT(), llvm::Offset, SDValue(), and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by lowerVECTOR_SHUFFLE().

lowerVECTOR_SHUFFLEAsVSlideup()

SDValue lowerVECTOR_SHUFFLEAsVSlideup ( const SDLoc & DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const RISCVSubtarget & Subtarget, SelectionDAG & DAG )

static

Definition at line 5197 of file RISCVISelLowering.cpp.

References convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorNumElements(), getVSlideup(), llvm::RISCVSubtarget::getXLenVT(), llvm::ShuffleVectorInst::isInsertSubvectorMask(), llvm::RISCVVType::MASK_AGNOSTIC, SDValue(), llvm::RISCVVType::TAIL_AGNOSTIC, and llvm::RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED.

Referenced by lowerVECTOR_SHUFFLE().

lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()

SDValue lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 3383 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::APFloat::convertFromAPInt(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstantFP(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getFltSemantics(), llvm::SelectionDAG::getFreeze(), getMaskTypeFor(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVFPRndMode::Invalid, llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), llvm_unreachable, matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), and llvm::ISD::SETOLT.

Referenced by lowerFTRUNC_FCEIL_FFLOOR_FROUND(), and llvm::RISCVTargetLowering::LowerOperation().

lowerVectorIntrinsicScalars()

SDValue lowerVectorIntrinsicScalars ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 10589 of file RISCVISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLT(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::RISCVTargetLowering::computeVLMAXBounds(), DL, llvm::RISCVVType::encodeSEW(), getAllOnesMask(), llvm::SDNode::getAsZExtVal(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), getVLOperand(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasVInstructions(), II, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isa(), llvm::MVT::isScalarInteger(), llvm::SDValue::isUndef(), SDValue(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, splatSplitI64WithVL(), llvm::SelectionDAG::SplitScalar(), llvm::RISCVVType::TAIL_AGNOSTIC, and llvm::ISD::TRUNCATE.

lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()

SDValue lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 3490 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::APFloat::convertFromAPInt(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstantFP(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getFltSemantics(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVFPRndMode::Invalid, llvm::MVT::isFixedLengthVector(), llvm_unreachable, matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), llvm::ISD::SETOLT, llvm::ISD::STRICT_FCEIL, llvm::ISD::STRICT_FFLOOR, llvm::ISD::STRICT_FNEARBYINT, llvm::ISD::STRICT_FROUND, llvm::ISD::STRICT_FROUNDEVEN, and llvm::ISD::STRICT_FTRUNC.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerVectorXRINT_XROUND()

SDValue lowerVectorXRINT_XROUND ( SDValue Op, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 3619 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), DL, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), and matchRoundingOp().

Referenced by llvm::RISCVTargetLowering::LowerOperation().

lowerVZIP()

SDValue lowerVZIP ( unsigned Opc, SDValue Op0, SDValue Op1, const SDLoc & DL, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 5342 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::bitsGT(), llvm::MVT::bitsLT(), llvm::MVT::changeVectorElementTypeToInteger(), convertFromScalableVector(), convertToScalableVector(), DL, getAllOnesMask(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtractSubvector(), llvm::MVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getInsertSubvector(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::RISCVTargetLowering::getM1VT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::SDValue::isUndef(), and Opc.

Referenced by lowerVECTOR_SHUFFLE().

matchIndexAsShuffle()

bool matchIndexAsShuffle ( EVT VT, SDValue Index, SDValue Mask, SmallVector< int > & ShuffleMask )

static

Match the index vector of a scatter or gather node as the shuffle mask which performs the rearrangement if possible.

Will only match if all lanes are touched, and thus replacing the scatter or gather with a unit strided access and shuffle is legal.

Definition at line 19914 of file RISCVISelLowering.cpp.

References llvm::BitVector::all(), assert(), llvm::CallingConv::C, llvm::EVT::getScalarStoreSize(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVectorAllOnes(), and llvm::BitVector::set().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

matchIndexAsWiderOp()

bool matchIndexAsWiderOp ( EVT VT, SDValue Index, SDValue Mask, Align BaseAlign, const RISCVSubtarget & ST )

static

Match the index of a gather or scatter operation as an operation with twice the element width and half the number of elements.

This is generally profitable (if legal) because these operations are linear in VL, so even if we cause some extract VTYPE/VL toggles, we still come out ahead.

Definition at line 19949 of file RISCVISelLowering.cpp.

References llvm::CallingConv::C, llvm::EVT::getScalarStoreSize(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVectorAllOnes(), and llvm::Last.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

matchRoundingOp()

RISCVFPRndMode::RoundingMode matchRoundingOp ( unsigned Opc )

static

Definition at line 3337 of file RISCVISelLowering.cpp.

References llvm::RISCVFPRndMode::DYN, llvm::RISCVFPRndMode::Invalid, Opc, llvm::RISCVFPRndMode::RDN, llvm::RISCVFPRndMode::RMM, llvm::RISCVFPRndMode::RNE, llvm::RISCVFPRndMode::RTZ, llvm::RISCVFPRndMode::RUP, llvm::ISD::STRICT_FCEIL, llvm::ISD::STRICT_FFLOOR, llvm::ISD::STRICT_FRINT, llvm::ISD::STRICT_FROUND, llvm::ISD::STRICT_FROUNDEVEN, llvm::ISD::STRICT_FTRUNC, llvm::ISD::STRICT_LLRINT, llvm::ISD::STRICT_LLROUND, llvm::ISD::STRICT_LRINT, and llvm::ISD::STRICT_LROUND.

Referenced by lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT_XROUND(), performFP_TO_INT_SATCombine(), and performFP_TO_INTCombine().

matchSelectAddSub()

bool matchSelectAddSub ( SDValue TrueVal, SDValue FalseVal, bool & SwapCC )

static

Definition at line 19241 of file RISCVISelLowering.cpp.

References A(), llvm::ISD::ADD, B(), llvm::ISD::SUB, and std::swap().

Referenced by performVECTOR_SHUFFLECombine(), and performVSELECTCombine().

matchSetCC()

std::optional< bool > matchSetCC ( SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue Val )

static

Definition at line 9199 of file RISCVISelLowering.cpp.

References assert(), llvm::cast(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::ISD::getSetCCSwappedOperands(), llvm::SDValue::getValueType(), LHS, RHS, and llvm::ISD::SETCC.

matchSplatAsGather()

SDValue matchSplatAsGather ( SDValue SplatVal, MVT VT, const SDLoc & DL, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 3828 of file RISCVISelLowering.cpp.

References convertFromScalableVector(), convertToScalableVector(), DL, llvm::dyn_cast(), llvm::ISD::EXTRACT_VECTOR_ELT, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorMinNumElements(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLE(), llvm::TargetLoweringBase::isTypeLegal(), and SDValue().

Referenced by lowerBUILD_VECTOR(), and llvm::RISCVTargetLowering::PerformDAGCombine().

narrowIndex()

bool narrowIndex ( SDValue & N, ISD::MemIndexType IndexType, SelectionDAG & DAG )

static

According to the property that indexed load/store instructions zero-extend their indices, try to narrow the type of index operand.

Definition at line 16862 of file RISCVISelLowering.cpp.

References llvm::EVT::bitsLT(), llvm::CallingConv::C, llvm::EVT::changeVectorElementType(), llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::countMaxActiveBits(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getRoundIntegerType(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::APInt::getZExtValue(), llvm::SDNode::hasOneUse(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVector(), N, llvm::SDNode::ops(), llvm::PowerOf2Ceil(), llvm::ISD::SHL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

negateFMAOpcode()

unsigned negateFMAOpcode ( unsigned Opcode, bool NegMul, bool NegAcc )

static

Definition at line 18679 of file RISCVISelLowering.cpp.

References llvm_unreachable.

Referenced by combineFMA(), combineFMADDSUB(), combineVFMADD_VLWithVFNEG_VL(), and llvm::X86TargetLowering::getNegatedExpression().

performADDCombine()

SDValue performADDCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const RISCVSubtarget & Subtarget )

static

Definition at line 15835 of file RISCVISelLowering.cpp.

References combineAddOfBooleanXor(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBinOpToReduce(), combineSelectAndUseCommutative(), combineShlAddIAdd(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), N, transformAddImmMulImm(), and transformAddShlImm().

performANDCombine()

SDValue performANDCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const RISCVSubtarget & Subtarget )

static

Definition at line 16271 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, combineANDOfSETCCToCZERO(), combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineDeMorganOfBoolean(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::isOneConstant(), N, reduceANDOfAtomicLoad(), reverseZExtICmpCombine(), llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

performBITREVERSECombine()

SDValue performBITREVERSECombine ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 18451 of file RISCVISelLowering.cpp.

References assert(), llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::has_single_bit(), llvm::EVT::isScalarInteger(), N, and SDValue().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performBUILD_VECTORCombine()

SDValue performBUILD_VECTORCombine ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget, const RISCVTargetLowering & TLI )

static

If we have a build_vector where each lane is binop X, C, where C is a constant (but not necessarily the same constant on all lanes), form binop (build_vector x1, x2, ...), (build_vector c1, c2, c3, ..).

We assume that materializing a constant build vector will be no more expensive that performing O(n) binops.

Definition at line 19311 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::isa(), llvm::TargetLoweringBase::isBinOp(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::SelectionDAG::isSafeToSpeculativelyExecute(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and SDValue().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performCONCAT_VECTORSCombine()

SDValue performCONCAT_VECTORSCombine ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget, const RISCVTargetLowering & TLI )

static

Definition at line 19566 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::cast(), llvm::MVT::changeVectorElementType(), DL, llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::LoadSDNode::getBasePtr(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getNegative(), llvm::getOffset(), llvm::GISelAddressing::BaseIndexOffset::getOffset(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSignedConstant(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getStridedLoadVP(), getValueType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVTargetLowering::isLegalStridedLoadStore(), llvm::ISD::isNormalLoad(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::BaseIndexOffset::match(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), and llvm::MemoryLocation::UnknownSize.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performFP_TO_INT_SATCombine()

SDValue performFP_TO_INT_SATCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const RISCVSubtarget & Subtarget )

static

Definition at line 18388 of file RISCVISelLowering.cpp.

References llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::RISCVFPRndMode::Invalid, llvm::TargetLoweringBase::isTypeLegal(), matchRoundingOp(), N, Opc, SDValue(), and llvm::ISD::SETUO.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performFP_TO_INTCombine()

SDValue performFP_TO_INTCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const RISCVSubtarget & Subtarget )

static

Definition at line 18289 of file RISCVISelLowering.cpp.

References convertFromScalableVector(), convertToScalableVector(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::FP_TO_SINT, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVFPRndMode::Invalid, llvm::EVT::isFixedLengthVector(), llvm::MVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), matchRoundingOp(), N, Opc, llvm::RISCVFPRndMode::RTZ, SDValue(), and llvm::ISD::TRUNCATE.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performINSERT_VECTOR_ELTCombine()

SDValue performINSERT_VECTOR_ELTCombine ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget, const RISCVTargetLowering & TLI )

static

Definition at line 19496 of file RISCVISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, DL, llvm::dyn_cast(), llvm::SelectionDAG::getInsertVectorElt(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_VECTOR_ELT, llvm::isa(), llvm::TargetLoweringBase::isBinOp(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::EVT::isScalableVector(), LHS, N, llvm::SDNode::ops(), RHS, and SDValue().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performMemPairCombine()

SDValue performMemPairCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 18204 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), getExtensionType(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemoryVT(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MachineFunction::getSubtarget(), llvm::Use::getUser(), llvm::LSBaseSDNode::isIndexed(), llvm::isShiftedUInt(), llvm::MemSDNode::isSimple(), N, Ptr, SDValue(), tryMemPairCombine(), and llvm::SDNode::uses().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performMULCombine()

SDValue performMULCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const RISCVSubtarget & Subtarget )

static

Definition at line 16811 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, combineBinOpOfZExt(), combineVectorMulToSraBitcast(), DL, expandMul(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::isOneOrOneSplat(), llvm::EVT::isVector(), llvm::ISD::MUL, N, SDValue(), llvm::ISD::SUB, and std::swap().

performORCombine()

SDValue performORCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const RISCVSubtarget & Subtarget )

static

Definition at line 16475 of file RISCVISelLowering.cpp.

References combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineDeMorganOfBoolean(), combineOrAndToBitfieldInsert(), combineOrOfCZERO(), combineOrToBitfieldInsert(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), and N.

performSELECTCombine()

SDValue performSELECTCombine ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 19288 of file RISCVISelLowering.cpp.

References foldSelectOfCTTZOrCTLZ(), llvm::RISCVSubtarget::hasConditionalMoveFusion(), N, SDValue(), tryFoldSelectIntoOp(), and useInversedSetcc().

performSETCCCombine()

SDValue performSETCCCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const RISCVSubtarget & Subtarget )

static

Definition at line 16987 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, llvm::cast(), combineVectorSizedSetCCEquality(), Cond, llvm::APInt::countr_zero(), llvm::countr_zero(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::APInt::getActiveBits(), llvm::SelectionDAG::getBoolConstant(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandAPInt(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::APInt::getSExtValue(), llvm::SelectionDAG::getSignedConstant(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::APInt::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::isInt(), llvm::APInt::isNegatedPowerOf2(), llvm::isNullConstant(), llvm::isPowerOf2_32(), llvm::isUInt(), llvm::SelectionDAG::MaskedValueIsZero(), N, SDValue(), llvm::ISD::SETNE, llvm::APInt::sext(), llvm::ISD::SIGN_EXTEND_INREG, llvm::SignExtend64(), llvm::ISD::SRA, llvm::ISD::SRL, and llvm::APInt::trunc().

performSHLCombine()

SDValue performSHLCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const RISCVSubtarget & Subtarget )

static

Definition at line 20252 of file RISCVISelLowering.cpp.

References combineOp_VLToVWOp_VL(), llvm::ISD::Constant, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), getDefaultScalableVLOps(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::APInt::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::ISD::isConstantSplatVector(), LHS, llvm_unreachable, N, RHS, SDValue(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

performSIGN_EXTEND_INREGCombine()

SDValue performSIGN_EXTEND_INREGCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const RISCVSubtarget & Subtarget )

static

Definition at line 17078 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::EVT::bitsGE(), llvm::cast(), llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::countMaxActiveBits(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::MVT::getVT(), llvm::RISCVSubtarget::is64Bit(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::isAllOnesConstant(), N, Opc, SDValue(), llvm::ISD::SETCC, llvm::ISD::SHL, and llvm::ISD::XOR.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performSRACombine()

SDValue performSRACombine ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 18771 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::cast(), llvm::countr_zero(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getValueType(), llvm::RISCVSubtarget::getXLenVT(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::isa(), N, SDValue(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, Size, llvm::ISD::SRA, llvm::ISD::SUB, and llvm::SDNode::users().

performSUBCombine()

SDValue performSUBCombine ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 15959 of file RISCVISelLowering.cpp.

References llvm::cast(), combineBinOpOfZExt(), combineSelectAndUse(), combineSubOfBoolean(), combineSubShiftToOrcB(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isNullConstant(), N, llvm::ISD::SETCC, llvm::ISD::SETLT, and llvm::ISD::SRA.

performTRUNCATECombine()

SDValue performTRUNCATECombine ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 16107 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, combineTruncSelectToSMaxUSat(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), llvm::isa(), N, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performVECREDUCECombine()

SDValue performVECREDUCECombine ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget, const RISCVTargetLowering & TLI )

static

Definition at line 19482 of file RISCVISelLowering.cpp.

References DL, foldReduceOperandViaVQDOT(), llvm::SelectionDAG::getNode(), N, and SDValue().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performVECTOR_SHUFFLECombine()

SDValue performVECTOR_SHUFFLECombine ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget, const RISCVTargetLowering & TLI )

static

Definition at line 19692 of file RISCVISelLowering.cpp.

References A(), llvm::ISD::ADD, assert(), B(), llvm::CallingConv::C, llvm::cast(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::RISCVSubtarget::getELen(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLogicalNOT(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::EVT::isFloatingPoint(), llvm::isPowerOf2_64(), llvm::ShuffleVectorInst::isSelectMask(), llvm::RISCVTargetLowering::isShuffleMaskLegal(), llvm::TargetLoweringBase::isTypeLegal(), matchSelectAddSub(), N, llvm::narrowShuffleMaskElts(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::Sub, and llvm::ISD::VSELECT.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performVFMADD_VLCombine()

SDValue performVFMADD_VLCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const RISCVSubtarget & Subtarget )

static

Definition at line 18756 of file RISCVISelLowering.cpp.

References combineOp_VLToVWOp_VL(), combineVFMADD_VLWithVFNEG_VL(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getSelectionDAGInfo(), llvm::SelectionDAGTargetInfo::isTargetStrictFPOpcode(), N, and SDValue().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performVP_REVERSECombine()

SDValue performVP_REVERSECombine ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 18468 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::sampleprof::Base, llvm::LocationSize::beforeOrAfterPointer(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getStridedLoadVP(), llvm::EVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::EVT::isByteSized(), llvm::isOneOrOneSplat(), llvm::ISD::MUL, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), and llvm::ISD::SUB.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performVP_STORECombine()

SDValue performVP_STORECombine ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 18530 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::sampleprof::Base, llvm::LocationSize::beforeOrAfterPointer(), llvm::cast(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getStridedStoreVP(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDValue::hasOneUse(), llvm::EVT::isByteSized(), llvm::isOneOrOneSplat(), llvm::ISD::MUL, N, SDValue(), and llvm::ISD::SUB.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performVP_TRUNCATECombine()

SDValue performVP_TRUNCATECombine ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 18596 of file RISCVISelLowering.cpp.

References DL, llvm::drop_end(), llvm::find_if(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), I, llvm::isOneOrOneSplat(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), LHS, N, llvm::Other, SDValue(), and std::swap().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performVSELECTCombine()

SDValue performVSELECTCombine ( SDNode * N, SelectionDAG & DAG )

static

Convert vselect CC, (add a, b), (sub a, b) to add a, (vselect CC, -b, b).

This allows us match a vadd.vv fed by a masked vrsub, which reduces register pressure over the add followed by masked vsub sequence.

Definition at line 19264 of file RISCVISelLowering.cpp.

References A(), llvm::ISD::ADD, B(), DL, llvm::SelectionDAG::getLogicalNOT(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::SDNode::getValueType(), matchSelectAddSub(), N, SDValue(), llvm::Sub, and llvm::ISD::VSELECT.

performVWADDSUBW_VLCombine()

SDValue performVWADDSUBW_VLCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const RISCVSubtarget & Subtarget )

static

Definition at line 18130 of file RISCVISelLowering.cpp.

References assert(), combineOp_VLToVWOp_VL(), combineVWADDSUBWSelect(), llvm::TargetLowering::DAGCombinerInfo::DAG, N, and Opc.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

performXORCombine()

SDValue performXORCombine ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 16506 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::cast(), combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineSelectAndUseCommutative(), combineXorToBitfieldInsert(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), llvm::isa(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::TargetLoweringBase::isOperationLegal(), N, llvm::ISD::ROTL, llvm::ISD::SETCC, llvm::ISD::SETLT, llvm::ISD::SHL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

processVCIXOperands()

void processVCIXOperands ( SDValue OrigOp, MutableArrayRef< SDValue > Operands, SelectionDAG & DAG )

static

Definition at line 10864 of file RISCVISelLowering.cpp.

References convertToScalableVector(), llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getSubtarget(), llvm::MVT::getVectorVT(), and promoteVCIXScalar().

Referenced by getVCIXISDNodeVOID(), and getVCIXISDNodeWCHAIN().

promoteVCIXScalar()

void promoteVCIXScalar ( SDValue Op, MutableArrayRef< SDValue > Operands, SelectionDAG & DAG )

inlinestatic

Definition at line 10828 of file RISCVISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLT(), DL, llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::MachineFunction::getSubtarget(), llvm::RISCVSubtarget::getXLenVT(), II, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::isa(), llvm::MVT::isScalarInteger(), and llvm::ISD::SIGN_EXTEND.

Referenced by processVCIXOperands().

reduceANDOfAtomicLoad()

SDValue reduceANDOfAtomicLoad ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 16234 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getAtomicLoad(), llvm::AtomicSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::MemSDNode::getSuccessOrdering(), llvm::SDValue::getValue(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::isStrongerThanMonotonic(), llvm::maskTrailingOnes(), N, llvm::TargetLowering::DAGCombinerInfo::recursivelyDeleteUnusedNodes(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), and llvm::ISD::ZEXTLOAD.

Referenced by performANDCombine().

reverseZExtICmpCombine()

SDValue reverseZExtICmpCombine ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 16152 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::APInt::getZExtValue(), llvm::RISCVSubtarget::hasVInstructions(), llvm::EVT::isVector(), llvm::PatternMatch::m_And(), llvm::SDPatternMatch::m_ConstInt(), llvm::MIPatternMatch::m_Not(), llvm::PatternMatch::m_One(), llvm::MIPatternMatch::m_OneUse(), llvm::SDPatternMatch::m_Srl(), llvm::PatternMatch::m_Trunc(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SETEQ, llvm::ISD::SETNE, X, and llvm::ISD::ZERO_EXTEND.

Referenced by performANDCombine().

simplifyOp_VL()

SDValue simplifyOp_VL ( SDNode * N )

static

Definition at line 17938 of file RISCVISelLowering.cpp.

References A(), assert(), B(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::isConstantSplatVectorAllZeros(), llvm::SDValue::isUndef(), N, and SDValue().

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

splatPartsI64WithVL()

SDValue splatPartsI64WithVL ( const SDLoc & DL, MVT VT, SDValue Passthru, SDValue Lo, SDValue Hi, SDValue VL, SelectionDAG & DAG )

static

Definition at line 4724 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::cast(), DL, llvm::SDNode::getAsZExtVal(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::Hi, llvm::isa(), llvm::isUInt(), llvm::Lo, and llvm::ISD::SRA.

Referenced by splatSplitI64WithVL().

splatSplitI64WithVL()

SDValue splatSplitI64WithVL ( const SDLoc & DL, MVT VT, SDValue Passthru, SDValue Scalar, SDValue VL, SelectionDAG & DAG )

static

Definition at line 4772 of file RISCVISelLowering.cpp.

References assert(), DL, llvm::Hi, llvm::Lo, splatPartsI64WithVL(), and llvm::SelectionDAG::SplitScalar().

Referenced by lowerScalarSplat(), and lowerVectorIntrinsicScalars().

SplitStrictFPVectorOp()

SDValue SplitStrictFPVectorOp ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 7396 of file RISCVISelLowering.cpp.

References assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), and llvm::SelectionDAG::SplitVector().

Referenced by llvm::RISCVTargetLowering::LowerOperation().

SplitVectorOp()

SDValue SplitVectorOp ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 7325 of file RISCVISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::GetSplitDestVTs(), and llvm::SelectionDAG::SplitVector().

Referenced by llvm::RISCVTargetLowering::LowerOperation().

SplitVectorReductionOp()

SDValue SplitVectorReductionOp ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 7381 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), llvm::Hi, llvm::Lo, llvm::SelectionDAG::SplitEVL(), and llvm::SelectionDAG::SplitVector().

Referenced by llvm::RISCVTargetLowering::LowerOperation().

SplitVPOp()

SDValue SplitVPOp ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 7350 of file RISCVISelLowering.cpp.

References assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::ISD::getVPExplicitVectorLengthIdx(), llvm::ISD::isVPOpcode(), llvm::SelectionDAG::SplitEVL(), and llvm::SelectionDAG::SplitVector().

Referenced by llvm::RISCVTargetLowering::LowerOperation().

STATISTIC()

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"	)

transformAddImmMulImm()

SDValue transformAddImmMulImm ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 15710 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSignedConstant(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::isInt(), llvm::EVT::isVector(), llvm::ISD::MUL, N, and SDValue().

Referenced by performADDCombine().

transformAddShlImm()

SDValue transformAddShlImm ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 15501 of file RISCVISelLowering.cpp.

References DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::RISCVSubtarget::hasShlAdd(), llvm::EVT::isVector(), N, SDValue(), and llvm::ISD::SHL.

Referenced by performADDCombine().

translateSetCCForBranch()

void translateSetCCForBranch ( const SDLoc & DL, SDValue & LHS, SDValue & RHS, ISD::CondCode & CC, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 2549 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, llvm::bit_width(), llvm::CallingConv::C, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::getSetCCSwappedOperands(), llvm::SelectionDAG::getSignedConstant(), INT64_MAX, llvm::isa(), llvm::isInt(), llvm::isMask_64(), llvm::isNullConstant(), llvm::isPowerOf2_64(), llvm::isUInt(), LHS, llvm::Log2_64(), RHS, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SHL, and std::swap().

tryDemorganOfBooleanCondition()

SDValue tryDemorganOfBooleanCondition ( SDValue Cond, SelectionDAG & DAG )

static

Definition at line 18888 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, llvm::cast(), Cond, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::EVT::isScalarInteger(), llvm::SelectionDAG::MaskedValueIsZero(), Opc, llvm::ISD::OR, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETLT, std::swap(), llvm::ISD::XOR, and llvm::Xor.

Referenced by combine_CC().

tryFoldSelectIntoOp()

SDValue tryFoldSelectIntoOp ( SDNode * N, SelectionDAG & DAG, SDValue TrueVal, SDValue FalseVal, bool Swapped )

static

Definition at line 19094 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNeutralElement(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SDValue::getValueType(), N, Opc, llvm::ISD::OR, llvm::ISD::ROTL, llvm::ISD::ROTR, SDValue(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, std::swap(), llvm::ISD::UMAX, llvm::ISD::UMIN, and llvm::ISD::XOR.

Referenced by performSELECTCombine().

tryMemPairCombine()

SDValue tryMemPairCombine ( SelectionDAG & DAG, LSBaseSDNode * LSNode1, LSBaseSDNode * LSNode2, SDValue BasePtr, uint64_t Imm )

static

Definition at line 18146 of file RISCVISelLowering.cpp.

References llvm::cast(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::MachineMemOperand::getPointerInfo(), llvm::MachineFunction::getSubtarget(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDNode::hasPredecessorHelper(), llvm::SelectionDAG::ReplaceAllUsesWith(), SDValue(), and llvm::ISD::ZEXTLOAD.

Referenced by performMemPairCombine().

tryWidenMaskForShuffle()

SDValue tryWidenMaskForShuffle ( SDValue Op, SelectionDAG & DAG )

static

Try to widen element type to get a new mask value for a better permutation sequence.

This doesn't try to inspect the widened mask for profitability; we speculate the widened form is equal or better. This has the effect of reducing mask constant sizes - allowing cheaper materialization sequences

• and index sequence sizes - reducing register pressure and materialization cost, at the cost of (possibly) an extra VTYPE toggle.

Definition at line 5858 of file RISCVISelLowering.cpp.

References llvm::cast(), DL, llvm::SelectionDAG::getBitcast(), llvm::MVT::getFixedSizeInBits(), llvm::MVT::getFloatingPointVT(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), llvm::MVT::isFloatingPoint(), llvm::TargetLoweringBase::isTypeLegal(), SDValue(), and llvm::widenShuffleMaskElts().

unpackF64OnRV32DSoftABI()

SDValue unpackF64OnRV32DSoftABI ( SelectionDAG & DAG, SDValue Chain, const CCValAssign & VA, const CCValAssign & HiVA, const SDLoc & DL )

static

Definition at line 23061 of file RISCVISelLowering.cpp.

References assert(), llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::SelectionDAG::getCopyFromReg(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getRegInfo(), llvm::CCValAssign::getValVT(), llvm::Hi, llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), and llvm::Lo.

Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().

unpackFromMemLoc()

SDValue unpackFromMemLoc ( SelectionDAG & DAG, SDValue Chain, const CCValAssign & VA, const SDLoc & DL )

static

Definition at line 23028 of file RISCVISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::CCValAssign::Full, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MVT::getIntegerVT(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::DataLayout::getPointerSizeInBits(), llvm::EVT::getStoreSize(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, llvm_unreachable, and llvm::ISD::NON_EXTLOAD.

unpackFromRegLoc()

SDValue unpackFromRegLoc ( SelectionDAG & DAG, SDValue Chain, const CCValAssign & VA, const SDLoc & DL, const ISD::InputArg & In, const RISCVTargetLowering & TLI )

static

Definition at line 22965 of file RISCVISelLowering.cpp.

References llvm::RISCVMachineFunctionInfo::addSExt32Register(), llvm::BitWidth, convertLocVTToValVT(), DL, llvm::Function::getArg(), llvm::SelectionDAG::getCopyFromReg(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::Type::getIntegerBitWidth(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MachineFunction::getRegInfo(), llvm::EVT::getSimpleVT(), llvm::RISCVTargetLowering::getSubtarget(), llvm::Value::getType(), llvm::CCValAssign::Indirect, and llvm::Type::isIntegerTy().

useInversedSetcc()

SDValue useInversedSetcc ( SDNode * N, SelectionDAG & DAG, const RISCVSubtarget & Subtarget )

static

Definition at line 19210 of file RISCVISelLowering.cpp.

References llvm::ISD::AND, llvm::cast(), Cond, DL, llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::RISCVSubtarget::hasBEXTILike(), llvm::RISCVSubtarget::hasCZEROLike(), llvm::isa(), llvm::isNullConstant(), llvm::APInt::isPowerOf2(), llvm::EVT::isScalarInteger(), llvm::APInt::isSignedIntN(), LHS, N, RHS, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETEQ, and llvm::ISD::SETNE.

Referenced by performSELECTCombine().

useRVVForFixedLengthVectorVT()

bool useRVVForFixedLengthVectorVT ( MVT VT, const RISCVSubtarget & Subtarget )

static

Definition at line 2879 of file RISCVISelLowering.cpp.

References assert(), llvm::divideCeil(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getFixedSizeInBits(), llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::hasVInstructionsBF16Minimal(), llvm::RISCVSubtarget::hasVInstructionsF16Minimal(), llvm::RISCVSubtarget::hasVInstructionsF32(), llvm::RISCVSubtarget::hasVInstructionsF64(), llvm::RISCVSubtarget::hasVInstructionsI64(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isPow2VectorType(), llvm::MVT::SimpleTy, and llvm::RISCVSubtarget::useRVVForFixedLengthVectors().

Referenced by getContainerForFixedLengthVector().

useTpOffset()

Value * useTpOffset ( IRBuilderBase & IRB, unsigned Offset )

static

Definition at line 24993 of file RISCVISelLowering.cpp.

References llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateConstGEP1_32(), llvm::IRBuilderBase::GetInsertBlock(), llvm::IRBuilderBase::getInt8Ty(), llvm::BasicBlock::getModule(), llvm::Intrinsic::getOrInsertDeclaration(), llvm::IRBuilderBase::getPtrTy(), and llvm::Offset.

Referenced by llvm::RISCVTargetLowering::getIRStackGuard().

widenVectorOpsToi8()

SDValue widenVectorOpsToi8 ( SDValue N, const SDLoc & DL, SelectionDAG & DAG )

static

Definition at line 12203 of file RISCVISelLowering.cpp.

References assert(), llvm::MVT::changeVectorElementType(), DL, llvm::SmallVectorTemplateCommon< T, typename >::front(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), I, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SETNE, llvm::SmallVectorTemplateCommon< T, typename >::size(), and llvm::ISD::ZERO_EXTEND.

Variable Documentation

AllowSplatInVW_W

cl::opt< bool > AllowSplatInVW_W(DEBUG_TYPE "-form-vw-w-with-splat", cl::Hidden, cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants"), cl::init(false)) ( DEBUG_TYPE "-form-vw-w-with-splat" , cl::Hidden , cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants") , cl::init(false)  )

static

ExtensionMaxWebSize

cl::opt< unsigned > ExtensionMaxWebSize(DEBUG_TYPE "-ext-max-web-size", cl::Hidden, cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion"), cl::init(18)) ( DEBUG_TYPE "-ext-max-web-size" , cl::Hidden , cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion") , cl::init(18)  )

static

Referenced by combineOp_VLToVWOp_VL().

FPImmCost

cl::opt< int > FPImmCost(DEBUG_TYPE "-fpimm-cost", cl::Hidden, cl::desc("Give the maximum number of instructions that we will " "use for creating a floating-point immediate value"), cl::init(3)) ( DEBUG_TYPE "-fpimm-cost" , cl::Hidden , cl::desc("Give the maximum number of instructions that we will " "use for creating a floating-point immediate value") , cl::init(3)  )

static

Referenced by llvm::RISCVTargetLowering::isFPImmLegal().

ModeMask32

const uint32_t ModeMask32 = ~RISCVExceptFlags::ALL

Definition at line 14380 of file RISCVISelLowering.cpp.

ModeMask64

const uint64_t ModeMask64 = ~RISCVExceptFlags::ALL

Definition at line 14379 of file RISCVISelLowering.cpp.

NumRepeatedDivisors

cl::opt< unsigned > NumRepeatedDivisors(DEBUG_TYPE "-fp-repeated-divisors", cl::Hidden, cl::desc("Set the minimum number of repetitions of a divisor to allow " "transformation to multiplications by the reciprocal"), cl::init(2)) ( DEBUG_TYPE "-fp-repeated-divisors" , cl::Hidden , cl::desc("Set the minimum number of repetitions of a divisor to allow " "transformation to multiplications by the reciprocal") , cl::init(2)  )

static

ReassocShlAddiAdd

cl::opt< bool > ReassocShlAddiAdd("reassoc-shl-addi-add", cl::Hidden, cl::desc("Swap add and addi in cases where the add may " "be combined with a shift"), cl::init(true)) ( "reassoc-shl-addi-add" , cl::Hidden , cl::desc("Swap add and addi in cases where the add may " "be combined with a shift") , cl::init(true)  )

static

Referenced by combineShlAddIAdd().

ZvfbfaOps

const unsigned ZvfbfaOps[] = {ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN}

static

Definition at line 93 of file RISCVISelLowering.cpp.

Referenced by isPromotedOpNeedingSplit(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

ZvfbfaVPOps

const unsigned ZvfbfaVPOps[]

static

Initial value:

= {ISD::VP_FNEG, ISD::VP_FABS,
                                       ISD::VP_FCOPYSIGN}

Definition at line 91 of file RISCVISelLowering.cpp.

Referenced by isPromotedOpNeedingSplit(), and llvm::RISCVTargetLowering::RISCVTargetLowering().