LLVM
15.0.0git
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#include "RISCVISelLowering.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVRegisterInfo.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/DiagnosticPrinter.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "RISCVGenAsmMatcher.inc"
#include "RISCVGenSearchableTables.inc"
Go to the source code of this file.
Classes | |
struct | VIDSequence |
struct | RISCVBitmanipPat |
Namespaces | |
llvm | |
This is an optimization pass for GlobalISel generic memory operations. | |
llvm::RISCVVIntrinsicsTable | |
Macros | |
#define | DEBUG_TYPE "riscv-lower" |
#define | NODE_NAME_CASE(NODE) |
#define | GET_REGISTER_MATCHER |
#define | GET_RISCVVIntrinsicsTable_IMPL |
Variables | |
static const MCPhysReg | ArgGPRs [] |
static const MCPhysReg | ArgFPR16s [] |
static const MCPhysReg | ArgFPR32s [] |
static const MCPhysReg | ArgFPR64s [] |
static const MCPhysReg | ArgVRs [] |
static const MCPhysReg | ArgVRM2s [] |
static const MCPhysReg | ArgVRM4s [] |
static const MCPhysReg | ArgVRM8s [] = {RISCV::V8M8, RISCV::V16M8} |
#define DEBUG_TYPE "riscv-lower" |
Definition at line 44 of file RISCVISelLowering.cpp.
#define GET_REGISTER_MATCHER |
Definition at line 11975 of file RISCVISelLowering.cpp.
#define GET_RISCVVIntrinsicsTable_IMPL |
Definition at line 11997 of file RISCVISelLowering.cpp.
#define NODE_NAME_CASE | ( | NODE | ) |
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Definition at line 9785 of file RISCVISelLowering.cpp.
References llvm::CCState::AllocateReg(), ArgVRM2s, ArgVRM4s, ArgVRM8s, ArgVRs, llvm::TargetLoweringBase::getRegClassFor(), llvm::Optional< T >::getValue(), llvm::Optional< T >::hasValue(), and llvm_unreachable.
Referenced by CC_RISCV(), and CC_RISCV_FastCC().
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Definition at line 9807 of file RISCVISelLowering.cpp.
References ABI, llvm::RISCVABI::ABI_ILP32, llvm::RISCVABI::ABI_ILP32D, llvm::RISCVABI::ABI_ILP32F, llvm::RISCVABI::ABI_LP64, llvm::RISCVABI::ABI_LP64D, llvm::RISCVABI::ABI_LP64F, llvm::CCState::addLoc(), Align, llvm::CCState::AllocateReg(), allocateRVVReg(), llvm::CCState::AllocateStack(), ArgFPR16s, ArgFPR32s, ArgFPR64s, ArgGPRs, llvm::array_lengthof(), assert(), llvm::CCValAssign::BCvt, CC_RISCVAssign2XLen(), llvm::SmallVectorImpl< T >::clear(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::CCValAssign::Full, llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), llvm::CCState::getFirstUnallocated(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getPending(), llvm::CCState::getPendingArgFlags(), llvm::CCState::getPendingLocs(), llvm::CCValAssign::getReg(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getStoreSize(), llvm::RISCVTargetLowering::getSubtarget(), llvm::RISCVSubtarget::hasVInstructions(), llvm::MVT::i32, llvm::MVT::i64, llvm::CCValAssign::Indirect, llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::MVT::isScalableVector(), llvm::MVT::isScalarInteger(), llvm::ISD::ArgFlagsTy::isSplit(), llvm::ISD::ArgFlagsTy::isSplitEnd(), llvm::MVT::isVector(), llvm_unreachable, and llvm::MaybeAlign::valueOrOne().
Referenced by llvm::RISCVTargetLowering::CanLowerReturn(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerFormalArguments(), and llvm::RISCVTargetLowering::LowerReturn().
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Definition at line 10235 of file RISCVISelLowering.cpp.
References llvm::CCState::addLoc(), Align, llvm::CCState::AllocateReg(), allocateRVVReg(), llvm::CCState::AllocateStack(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), llvm::CCValAssign::getMem(), llvm::CCValAssign::getReg(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getStoreSize(), llvm::RISCVTargetLowering::getSubtarget(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::CCValAssign::Indirect, llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), and llvm::MaybeAlign::valueOrOne().
Referenced by llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerFormalArguments().
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Definition at line 10337 of file RISCVISelLowering.cpp.
References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::MVT::f32, llvm::MVT::f64, llvm::CCValAssign::getReg(), llvm::MVT::i32, llvm::MVT::i64, and llvm::report_fatal_error().
Referenced by llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerFormalArguments().
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Definition at line 9748 of file RISCVISelLowering.cpp.
References llvm::CCState::addLoc(), Align, llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), ArgGPRs, llvm::CCValAssign::Full, llvm::CCValAssign::getLocVT(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getReg(), llvm::CCValAssign::getValNo(), llvm::CCValAssign::getValVT(), and llvm::max().
Referenced by CC_RISCV().
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Definition at line 8075 of file RISCVISelLowering.cpp.
References llvm::RISCVISD::ADD_VL, assert(), DL, llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::BitmaskEnumDetail::Mask(), N, llvm::RISCVISD::SUB_VL, std::swap(), llvm::RISCVISD::VSEXT_VL, llvm::RISCVISD::VWADD_W_VL, llvm::RISCVISD::VWADDU_W_VL, llvm::RISCVISD::VWSUB_W_VL, llvm::RISCVISD::VWSUBU_W_VL, and llvm::RISCVISD::VZEXT_VL.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 7384 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::SelectionDAG::getNeutralElement(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::EVT::isInteger(), llvm::isNullConstant(), llvm::isNullFPConstant(), llvm::isOneConstant(), llvm_unreachable, N, llvm::ISD::OR, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::RISCVISD::VECREDUCE_ADD_VL, llvm::RISCVISD::VECREDUCE_AND_VL, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::RISCVISD::VECREDUCE_OR_VL, llvm::RISCVISD::VECREDUCE_SMAX_VL, llvm::RISCVISD::VECREDUCE_SMIN_VL, llvm::RISCVISD::VECREDUCE_UMAX_VL, llvm::RISCVISD::VECREDUCE_UMIN_VL, llvm::RISCVISD::VECREDUCE_XOR_VL, llvm::RISCVISD::VFMV_S_F_VL, llvm::RISCVISD::VMV_S_X_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::ISD::XOR.
Referenced by performADDCombine(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performORCombine(), and performXORCombine().
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Definition at line 7774 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::RISCVISD::GORC, llvm::RISCVISD::GREV, and N.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 8199 of file RISCVISelLowering.cpp.
References assert(), llvm::SelectionDAG::ComputeNumSignBits(), DL, llvm::APInt::getBitsSetFrom(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::SDValue::isUndef(), llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::RISCVISD::MUL_VL, N, std::swap(), llvm::RISCVISD::VMV_V_X_VL, llvm::RISCVISD::VSEXT_VL, llvm::RISCVISD::VWMUL_VL, llvm::RISCVISD::VWMULSU_VL, llvm::RISCVISD::VWMULU_VL, and llvm::RISCVISD::VZEXT_VL.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 7515 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVISD::GORC, llvm::RISCVISD::GREV, llvm::RISCVSubtarget::hasStdExtZbp(), llvm::MVT::i32, llvm::RISCVSubtarget::is64Bit(), llvm::isPowerOf2_32(), LHS, matchGREVIPat(), llvm::ISD::OR, RHS, llvm::ISD::ROTL, llvm::ISD::ROTR, std::swap(), and X.
Referenced by performORCombine().
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Definition at line 7489 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVISD::GREV, llvm::RISCVSubtarget::hasStdExtZbp(), llvm::MVT::i32, llvm::RISCVSubtarget::is64Bit(), LHS, matchGREVIPat(), and RHS.
Referenced by performORCombine().
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Definition at line 7594 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, assert(), B, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasStdExtZbp(), llvm::MVT::i32, llvm::MVT::i64, llvm::Log2_32(), llvm::BitmaskEnumDetail::Mask(), matchSHFLPat(), llvm::ISD::OR, llvm::RISCVISD::SHFL, and std::swap().
Referenced by performORCombine().
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Definition at line 7723 of file RISCVISelLowering.cpp.
References assert(), llvm::BitWidth, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getValueType(), llvm::RISCVISD::GREV, llvm::RISCVSubtarget::hasStdExtZbp(), llvm::MVT::i32, llvm::isPowerOf2_32(), N, llvm::RISCVISD::ROLW, llvm::RISCVISD::RORW, llvm::ISD::ROTL, llvm::ISD::ROTR, and llvm::ISD::SIGN_EXTEND_INREG.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 7817 of file RISCVISelLowering.cpp.
References llvm::tgtok::FalseVal, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::isNullConstant(), llvm::EVT::isVector(), isZeroOrAllOnes(), N, llvm::ISD::SELECT, llvm::RISCVISD::SELECT_CC, std::swap(), and llvm::tgtok::TrueVal.
Referenced by combineSelectAndUseCommutative(), and performSUBCombine().
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Definition at line 7865 of file RISCVISelLowering.cpp.
References combineSelectAndUse(), and N.
Referenced by performADDCombine(), performANDCombine(), performORCombine(), and performXORCombine().
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Definition at line 8125 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::ComputeNumSignBits(), DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::SDValue::isUndef(), llvm_unreachable, llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::RISCVISD::VMV_V_X_VL, llvm::RISCVISD::VSEXT_VL, llvm::RISCVISD::VWADD_VL, llvm::RISCVISD::VWADD_W_VL, llvm::RISCVISD::VWADDU_VL, llvm::RISCVISD::VWADDU_W_VL, llvm::RISCVISD::VWSUB_VL, llvm::RISCVISD::VWSUB_W_VL, llvm::RISCVISD::VWSUBU_VL, llvm::RISCVISD::VWSUBU_W_VL, and llvm::RISCVISD::VZEXT_VL.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
Definition at line 9144 of file RISCVISelLowering.cpp.
References llvm::BitmaskEnumDetail::Mask(), Shift, and x.
Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode().
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Definition at line 1588 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::RISCVSubtarget::getXLenVT(), llvm::EVT::isFixedLengthVector(), and llvm::EVT::isScalableVector().
Referenced by convertLocVTToValVT(), lowerBUILD_VECTOR(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), and matchSplatAsGather().
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Definition at line 10093 of file RISCVISelLowering.cpp.
References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertFromScalableVector(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::RISCVISD::FMV_H_X, llvm::RISCVISD::FMV_W_X_RV64, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::i64, llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::MVT::isScalableVector(), and llvm_unreachable.
Referenced by llvm::RISCVTargetLowering::LowerCall(), and unpackFromRegLoc().
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Definition at line 1576 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INSERT_SUBVECTOR, llvm::EVT::isFixedLengthVector(), and llvm::EVT::isScalableVector().
Referenced by convertValVTToLocVT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), matchSplatAsGather(), and llvm::RISCVTargetLowering::ReplaceNodeResults().
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Definition at line 10135 of file RISCVISelLowering.cpp.
References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertToScalableVector(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::RISCVISD::FMV_X_ANYEXTH, llvm::RISCVISD::FMV_X_ANYEXTW_RV64, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::i64, llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::EVT::isScalableVector(), and llvm_unreachable.
Referenced by llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerReturn().
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Definition at line 6671 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), getRISCVWOpcode(), llvm::MVT::i64, N, and llvm::ISD::TRUNCATE.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
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Definition at line 6627 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, DL, llvm::drop_begin(), llvm::SelectionDAG::getNode(), getRISCVWOpcodeByIntr(), llvm::MVT::i64, N, and llvm::ISD::TRUNCATE.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
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Definition at line 6684 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), llvm::MVT::i32, llvm::MVT::i64, N, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::TRUNCATE.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
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Definition at line 9438 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), Align, assert(), BB, llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), llvm::HexagonInstrInfo::loadRegFromStackSlot(), MI, llvm::MachineMemOperand::MOStore, and TII.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 9485 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addReg(), BB, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::getKillRegState(), llvm::RegState::Kill, MI, MRI, llvm::MachineInstr::setFlag(), and TII.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 9343 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), BB, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::insert(), llvm::AArch64SysReg::lookupSysRegByName(), MI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 9521 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::any_of(), BB, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineInstr::collectDebugValues(), llvm::SmallSet< T, N, C >::count(), DL, E, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), I, llvm::SmallSet< T, N, C >::insert(), isSelectPseudo(), LHS, MI, llvm::MachineFunctionProperties::NoPHIs, llvm::MachineBasicBlock::push_back(), RHS, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 9405 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), Align, assert(), BB, llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), MI, llvm::MachineMemOperand::MOLoad, llvm::HexagonInstrInfo::storeRegToStackSlot(), and TII.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Creates an all ones mask suitable for masking a vector of type VecTy with vector length VL.
Definition at line 1610 of file RISCVISelLowering.cpp.
References DL, getMaskTypeFor(), llvm::SelectionDAG::getNode(), and llvm::RISCVISD::VMSET_VL.
Referenced by getDefaultVLOps(), lowerVECTOR_SHUFFLE(), lowerVectorIntrinsicScalars(), and llvm::RISCVTargetLowering::ReplaceNodeResults().
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Definition at line 1531 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::RISCVSubtarget::getELEN(), llvm::RISCVSubtarget::getMinRVVVectorSizeInBits(), llvm::MVT::getScalableVectorVT(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::MVT::isFixedLengthVector(), llvm::isPowerOf2_32(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::max(), llvm::RISCV::RVVBitsPerBlock, and llvm::MVT::SimpleTy.
Referenced by llvm::RISCVTargetLowering::getContainerForFixedLengthVector().
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Definition at line 1565 of file RISCVISelLowering.cpp.
References llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), and llvm::SelectionDAG::getTargetLoweringInfo().
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Definition at line 1633 of file RISCVISelLowering.cpp.
References assert(), DL, getDefaultVLOps(), and llvm::MVT::isScalableVector().
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Definition at line 1620 of file RISCVISelLowering.cpp.
References assert(), DL, getAllOnesMask(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getRegister(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isScalableVector(), and llvm::BitmaskEnumDetail::Mask().
Referenced by getDefaultScalableVLOps(), lowerBUILD_VECTOR(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), and matchSplatAsGather().
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Definition at line 11535 of file RISCVISelLowering.cpp.
References llvm::AtomicRMWInst::Add, llvm_unreachable, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, and llvm::AtomicRMWInst::Xchg.
Referenced by llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic().
Definition at line 4964 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::getScalableVectorVT(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), and llvm::RISCV::RVVBitsPerBlock.
Return the type of the mask type suitable for masking the provided vector type.
This is simply an i1 element type vector of the same (possibly scalable) length.
Definition at line 1602 of file RISCVISelLowering.cpp.
References assert(), llvm::EVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::MVT::i1, and llvm::EVT::isVector().
Referenced by getAllOnesMask(), and llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 10610 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), and llvm::EVT::getTypeForEVT().
Referenced by llvm::SelectionDAG::CreateStackTemporary(), and llvm::RISCVTargetLowering::LowerCall().
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Definition at line 6643 of file RISCVISelLowering.cpp.
References llvm::RISCVISD::DIVUW, llvm::RISCVISD::DIVW, llvm_unreachable, llvm::RISCVISD::REMUW, llvm::RISCVISD::ROLW, llvm::RISCVISD::RORW, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::RISCVISD::SLLW, llvm::ISD::SRA, llvm::RISCVISD::SRAW, llvm::ISD::SRL, llvm::RISCVISD::SRLW, llvm::ISD::UDIV, and llvm::ISD::UREM.
Referenced by customLegalizeToWOp().
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Definition at line 6609 of file RISCVISelLowering.cpp.
References llvm::RISCVISD::BCOMPRESSW, llvm::RISCVISD::BDECOMPRESSW, llvm::RISCVISD::BFPW, llvm::RISCVISD::FSLW, llvm::RISCVISD::FSRW, and llvm_unreachable.
Referenced by customLegalizeToWOpByIntr().
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Definition at line 5133 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getNeutralElement(), llvm::ISD::getVecReduceBaseOpcode(), llvm_unreachable, llvm::ISD::VECREDUCE_FADD, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::ISD::VECREDUCE_FMAX, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::ISD::VECREDUCE_FMIN, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::ISD::VECREDUCE_SEQ_FADD, and llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL.
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Definition at line 4972 of file RISCVISelLowering.cpp.
References llvm_unreachable, llvm::ISD::VECREDUCE_ADD, llvm::RISCVISD::VECREDUCE_ADD_VL, llvm::ISD::VECREDUCE_AND, llvm::RISCVISD::VECREDUCE_AND_VL, llvm::ISD::VECREDUCE_OR, llvm::RISCVISD::VECREDUCE_OR_VL, llvm::ISD::VECREDUCE_SMAX, llvm::RISCVISD::VECREDUCE_SMAX_VL, llvm::ISD::VECREDUCE_SMIN, llvm::RISCVISD::VECREDUCE_SMIN_VL, llvm::ISD::VECREDUCE_UMAX, llvm::RISCVISD::VECREDUCE_UMAX_VL, llvm::ISD::VECREDUCE_UMIN, llvm::RISCVISD::VECREDUCE_UMIN_VL, llvm::ISD::VECREDUCE_XOR, and llvm::RISCVISD::VECREDUCE_XOR_VL.
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Definition at line 5191 of file RISCVISelLowering.cpp.
References llvm_unreachable, llvm::RISCVISD::VECREDUCE_ADD_VL, llvm::RISCVISD::VECREDUCE_AND_VL, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::RISCVISD::VECREDUCE_OR_VL, llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL, llvm::RISCVISD::VECREDUCE_SMAX_VL, llvm::RISCVISD::VECREDUCE_SMIN_VL, llvm::RISCVISD::VECREDUCE_UMAX_VL, llvm::RISCVISD::VECREDUCE_UMIN_VL, and llvm::RISCVISD::VECREDUCE_XOR_VL.
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Definition at line 3500 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getTargetBlockAddress(), and N.
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Definition at line 3506 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getTargetConstantPool(), and N.
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Definition at line 3495 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getTargetGlobalAddress(), and N.
Referenced by llvm::RISCVTargetLowering::getAddr().
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Definition at line 3512 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getTargetJumpTable(), and N.
Definition at line 1446 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::VLOperand.
Referenced by lowerVectorIntrinsicScalars().
Match shuffles that concatenate two vectors, rotate the concatenation, and then extract the original number of elements from the rotated result.
This is equivalent to vector.splice or X86's PALIGNR instruction. The returned rotation amount is for a rotate right, where elements move from higher elements to lower elements. LoSrc
indicates the first source vector of the rotate or -1 for undef. HiSrc
indicates the second vector of the rotate or -1 for undef. At least one of LoSrc
and HiSrc
will be 0 or 1 if a rotation is found.
NOTE: We talk about rotate to the right which matches how bit shift and rotate instructions are described where LSBs are on the right, but LLVM IR and the table below write vectors with the lowest elements on the left.
Definition at line 2399 of file RISCVISelLowering.cpp.
References assert(), i, M, and llvm::BitmaskEnumDetail::Mask().
Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal(), and lowerVECTOR_SHUFFLE().
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Definition at line 2345 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVSubtarget::getELEN(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorNumElements(), i, and llvm::BitmaskEnumDetail::Mask().
Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal(), and lowerVECTOR_SHUFFLE().
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Definition at line 9473 of file RISCVISelLowering.cpp.
References MI.
Referenced by emitSelectPseudo().
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Definition at line 1809 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, llvm::None, and llvm::SignExtend64().
Referenced by lowerBUILD_VECTOR().
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Definition at line 1928 of file RISCVISelLowering.cpp.
References llvm::abs(), llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::tgtok::Bits, llvm::MVT::bitsLE(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), llvm::count_if(), llvm::divideCeil(), DL, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::RISCVSubtarget::getELEN(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplatBuildVector(), llvm::getSplatValue(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::insert(), llvm::ISD::INSERT_VECTOR_ELT, llvm::RISCVSubtarget::is64Bit(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::isInt< 32 >(), llvm::MVT::isInteger(), llvm::isPowerOf2_32(), llvm::isPowerOf2_64(), isSimpleVIDSequence(), llvm::SDValue::isUndef(), llvm::Log2_32(), llvm::Log2_64(), llvm::BitmaskEnumDetail::Mask(), matchSplatAsGather(), llvm::max(), llvm::min(), llvm::ISD::MUL, llvm::ISD::SETNE, llvm::ISD::SHL, llvm::SelectionDAG::shouldOptForSize(), llvm::SignExtend64(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::size(), llvm::ISD::SRL, llvm::ISD::SUB, llvm::transform(), llvm::MVT::v1i8, llvm::MVT::v8i1, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VID_VL, llvm::RISCVISD::VMCLR_VL, llvm::RISCVISD::VMSET_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::ISD::VSELECT.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 2817 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, assert(), llvm::LegacyLegalizeActions::Bitcast, llvm::MVT::changeVectorElementTypeToInteger(), llvm::ISD::CTTZ_ZERO_UNDEF, DL, llvm::MVT::f32, llvm::MVT::f64, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::TargetLoweringBase::isTypeLegal(), Shift, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::TRUNCATE, and llvm::ISD::UINT_TO_FP.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 1652 of file RISCVISelLowering.cpp.
References DL, llvm::RISCVISD::FCVT_W_RV64, llvm::RISCVISD::FCVT_WU_RV64, llvm::RISCVISD::FCVT_X, llvm::RISCVISD::FCVT_XU, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::RISCVFPRndMode::RTZ, and llvm::ISD::SETUO.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 1748 of file RISCVISelLowering.cpp.
References llvm::lltok::APFloat, assert(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::APFloat::convert(), llvm::APFloat::convertFromAPInt(), DL, llvm::SelectionDAG::EVTToAPFloatSemantics(), f(), llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCOPYSIGN, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::MVT::i1, llvm::MVT::isVector(), llvm::APFloat::next(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), llvm::ISD::SETOLT, and llvm::ISD::SINT_TO_FP.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 1686 of file RISCVISelLowering.cpp.
References llvm::lltok::APFloat, assert(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::APFloat::convertFromAPInt(), DL, llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FFLOOR, llvm::ISD::FP_TO_SINT, llvm::ISD::FSUB, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::MVT::i1, llvm::MVT::isVector(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), llvm::ISD::SETOGT, llvm::ISD::SETOLT, and llvm::ISD::SINT_TO_FP.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 2301 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::isFloatingPoint(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::SDValue::isUndef(), llvm::ISD::SIGN_EXTEND, splatSplitI64WithVL(), llvm::RISCVISD::VFMV_S_F_VL, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_S_X_VL, and llvm::RISCVISD::VMV_V_X_VL.
Referenced by lowerVECTOR_SHUFFLE().
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Definition at line 2460 of file RISCVISelLowering.cpp.
References llvm::RISCVISD::ADD_VL, llvm::all_of(), assert(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::begin(), llvm::MVT::bitsGT(), llvm::MVT::changeTypeToInteger(), llvm::MVT::changeVectorElementType(), llvm::ISD::CONCAT_VECTORS, convertFromScalableVector(), convertToScalableVector(), DL, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::TypeSize::Fixed(), llvm::SelectionDAG::getAllOnesConstant(), getAllOnesMask(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtLoad(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getFreeze(), llvm::MVT::getHalfNumVectorElementsVT(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getScalarType(), llvm::SDValue::getSimpleValueType(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getSplatValue(), llvm::MVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i1, llvm::MVT::i16, int, llvm::ISD::INTRINSIC_W_CHAIN, isElementRotate(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), isInterleaveShuffle(), llvm::ISD::isNormalLoad(), llvm::ShuffleVectorSDNode::isSplat(), llvm::SelectionDAG::isSplatValue(), llvm::SDValue::isUndef(), lowerScalarSplat(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::BitmaskEnumDetail::Mask(), llvm::MVT::Other, llvm::ISD::SEXTLOAD, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::size(), std::swap(), llvm::NVPTX::PTXLdStInstCode::V2, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_V_X_VL, llvm::RISCVISD::VRGATHER_VV_VL, llvm::RISCVISD::VRGATHER_VX_VL, llvm::RISCVISD::VRGATHEREI16_VV_VL, llvm::ISD::VSELECT, llvm::RISCVISD::VSELECT_VL, llvm::RISCVISD::VSLIDEDOWN_VL, llvm::RISCVISD::VSLIDEUP_VL, llvm::RISCVISD::VWADDU_VL, and llvm::RISCVISD::VWMULU_VL.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 4509 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLT(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::RISCVTargetLowering::computeVLMAX(), DL, llvm::RISCVVType::encodeSEW(), llvm::ISD::EXTRACT_ELEMENT, getAllOnesMask(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::LinearPolySize< LeafTy >::getKnownMinValue(), llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealMaxVLen(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), getVLOperand(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::hasScalarOperand(), llvm::RISCVSubtarget::hasVInstructions(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::MVT::isScalarInteger(), llvm::SDValue::isUndef(), llvm::XCoreISD::LMUL, llvm::BitmaskEnumDetail::Mask(), Operands, llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::ScalarOperand, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, splatSplitI64WithVL(), llvm::RISCVII::TAIL_AGNOSTIC, llvm::ISD::TRUNCATE, llvm::RISCVISD::VP_MERGE_VL, llvm::RISCVISD::VSELECT_VL, llvm::RISCVISD::VSLIDE1DOWN_VL, and llvm::RISCVISD::VSLIDE1UP_VL.
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Definition at line 7373 of file RISCVISelLowering.cpp.
References matchRISCVBitmanipPat().
Referenced by combineORToGORC(), and combineORToGREV().
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Definition at line 7297 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, assert(), llvm::MVT::i64, llvm::isPowerOf2_64(), llvm::Log2_32(), llvm::BitmaskEnumDetail::Mask(), llvm::None, llvm::ISD::SHL, llvm::ArrayRef< T >::size(), and llvm::ISD::SRL.
Referenced by matchGREVIPat(), and matchSHFLPat().
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Definition at line 8295 of file RISCVISelLowering.cpp.
References llvm::ISD::FCEIL, llvm::ISD::FFLOOR, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FTRUNC, llvm::RISCVFPRndMode::Invalid, llvm::RISCVFPRndMode::RDN, llvm::RISCVFPRndMode::RMM, llvm::RISCVFPRndMode::RNE, llvm::RISCVFPRndMode::RTZ, and llvm::RISCVFPRndMode::RUP.
Referenced by performFP_TO_INT_SATCombine(), and performFP_TO_INTCombine().
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Definition at line 7583 of file RISCVISelLowering.cpp.
References matchRISCVBitmanipPat().
Referenced by combineORToSHFL().
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Definition at line 1896 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::BitmaskEnumDetail::Mask(), and llvm::RISCVISD::VRGATHER_VX_VL.
Referenced by lowerBUILD_VECTOR(), and llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 7943 of file RISCVISelLowering.cpp.
References combineBinOpToReduce(), combineSelectAndUseCommutative(), N, transformAddImmMulImm(), and transformAddShlImm().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 7964 of file RISCVISelLowering.cpp.
References llvm::And, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, combineBinOpToReduce(), combineSelectAndUseCommutative(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::hasStdExtZbs(), llvm::MVT::i32, llvm::MVT::i64, llvm::RISCVSubtarget::is64Bit(), llvm::isOneConstant(), N, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 8414 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVISD::GREV, llvm::RISCVSubtarget::hasStdExtZbkb(), llvm::isPowerOf2_32(), llvm::EVT::isScalarInteger(), and N.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 8360 of file RISCVISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::MVT::f16, llvm::RISCVISD::FCVT_W_RV64, llvm::RISCVISD::FCVT_WU_RV64, llvm::RISCVISD::FCVT_X, llvm::RISCVISD::FCVT_XU, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasStdExtZfh(), llvm::MVT::i32, llvm::MVT::i64, llvm::RISCVFPRndMode::Invalid, llvm::TargetLoweringBase::isTypeLegal(), matchRoundingOp(), N, and llvm::ISD::SETUO.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 8313 of file RISCVISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::MVT::f16, llvm::RISCVISD::FCVT_W_RV64, llvm::RISCVISD::FCVT_WU_RV64, llvm::RISCVISD::FCVT_X, llvm::RISCVISD::FCVT_XU, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasStdExtZfh(), llvm::MVT::i32, llvm::RISCVFPRndMode::Invalid, llvm::TargetLoweringBase::isTypeLegal(), matchRoundingOp(), N, and llvm::ISD::TRUNCATE.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 7993 of file RISCVISelLowering.cpp.
References combineBinOpToReduce(), combineORToGORC(), combineORToGREV(), combineORToSHFL(), combineSelectAndUseCommutative(), llvm::RISCVISD::GORC, llvm::RISCVISD::GREV, llvm::RISCVSubtarget::hasStdExtZbp(), N, and llvm::RISCVISD::SHFL.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 8034 of file RISCVISelLowering.cpp.
References llvm::ISD::ABS, llvm::SelectionDAG::ComputeNumSignBits(), DL, llvm::RISCVISD::FMV_X_ANYEXTH, llvm::RISCVISD::FMV_X_SIGNEXTH, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), llvm::RISCVSubtarget::hasStdExtZbb(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::RISCVSubtarget::is64Bit(), N, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SMAX, and llvm::ISD::SUB.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 7956 of file RISCVISelLowering.cpp.
References combineSelectAndUse(), and N.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 8011 of file RISCVISelLowering.cpp.
References combineBinOpToReduce(), combineSelectAndUseCommutative(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::i64, llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::TargetLoweringBase::isOperationLegal(), N, llvm::RISCVISD::ROLW, llvm::ISD::ROTL, and llvm::RISCVISD::SLLW.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
Definition at line 10024 of file RISCVISelLowering.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Key::Args, llvm::enumerate(), llvm::MVT::getVectorElementType(), llvm::MVT::i1, llvm::MVT::isVector(), and llvm::None.
Referenced by llvm::RISCVTargetLowering::CanLowerReturn().
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Definition at line 2252 of file RISCVISelLowering.cpp.
References llvm::ISD::BITCAST, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::MVT::i32, llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, and llvm::RISCVISD::VMV_V_X_VL.
Referenced by splatSplitI64WithVL().
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Definition at line 2287 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::MVT::i64, and splatPartsI64WithVL().
Referenced by lowerScalarSplat(), and lowerVectorIntrinsicScalars().
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Definition at line 7894 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, C1, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::EVT::isVector(), llvm::ISD::MUL, and N.
Referenced by performADDCombine().
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Definition at line 7669 of file RISCVISelLowering.cpp.
References llvm::abs(), llvm::ISD::ADD, llvm::tgtok::Bits, C1, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::RISCVSubtarget::hasStdExtZba(), llvm::EVT::isVector(), llvm::min(), N, NL, and llvm::ISD::SHL.
Referenced by performADDCombine().
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Definition at line 1280 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::ISD::getSetCCSwappedOperands(), llvm::isAllOnesConstant(), llvm::isOneConstant(), LHS, RHS, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETUGT, llvm::ISD::SETULE, and std::swap().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 10195 of file RISCVISelLowering.cpp.
References llvm::MachineRegisterInfo::addLiveIn(), assert(), llvm::RISCVISD::BuildPairF64, llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::MVT::f64, llvm::SelectionDAG::getCopyFromReg(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getRegInfo(), llvm::CCValAssign::getValVT(), llvm::MVT::i32, llvm::CCValAssign::isMemLoc(), and llvm::CCValAssign::isRegLoc().
Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().
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Definition at line 10161 of file RISCVISelLowering.cpp.
References llvm::CCValAssign::BCvt, llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::CCValAssign::Full, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MVT::getIntegerVT(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::DataLayout::getPointerSizeInBits(), llvm::EVT::getStoreSize(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, llvm::EVT::isScalableVector(), llvm_unreachable, and llvm::ISD::NON_EXTLOAD.
Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().
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Definition at line 10117 of file RISCVISelLowering.cpp.
References llvm::MachineRegisterInfo::addLiveIn(), convertLocVTToValVT(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::SelectionDAG::getCopyFromReg(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MachineFunction::getRegInfo(), llvm::EVT::getSimpleVT(), llvm::RISCVTargetLowering::getSubtarget(), and llvm::CCValAssign::Indirect.
Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().
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Definition at line 1459 of file RISCVISelLowering.cpp.
References assert(), llvm::divideCeil(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::RISCVSubtarget::getELEN(), llvm::MVT::getFixedSizeInBits(), llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors(), llvm::RISCVSubtarget::getMinRVVVectorSizeInBits(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::hasVInstructionsF16(), llvm::RISCVSubtarget::hasVInstructionsF32(), llvm::RISCVSubtarget::hasVInstructionsF64(), llvm::RISCVSubtarget::hasVInstructionsI64(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::MVT::isFixedLengthVector(), llvm::MVT::isPow2VectorType(), llvm::MVT::SimpleTy, and llvm::RISCVSubtarget::useRVVForFixedLengthVectors().
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Definition at line 9722 of file RISCVISelLowering.cpp.
Referenced by CC_RISCV().
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Definition at line 9726 of file RISCVISelLowering.cpp.
Referenced by CC_RISCV().
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Definition at line 9730 of file RISCVISelLowering.cpp.
Referenced by CC_RISCV().
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Definition at line 9718 of file RISCVISelLowering.cpp.
Referenced by CC_RISCV(), CC_RISCVAssign2XLen(), llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerFormalArguments().
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Definition at line 9739 of file RISCVISelLowering.cpp.
Referenced by allocateRVVReg().
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Definition at line 9742 of file RISCVISelLowering.cpp.
Referenced by allocateRVVReg().
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Definition at line 9744 of file RISCVISelLowering.cpp.
Referenced by allocateRVVReg().
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Definition at line 9735 of file RISCVISelLowering.cpp.
Referenced by allocateRVVReg().