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LLVM 20.0.0git
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#include "RISCVISelLowering.h"#include "MCTargetDesc/RISCVMatInt.h"#include "RISCV.h"#include "RISCVConstantPoolValue.h"#include "RISCVMachineFunctionInfo.h"#include "RISCVRegisterInfo.h"#include "RISCVSelectionDAGInfo.h"#include "RISCVSubtarget.h"#include "llvm/ADT/SmallSet.h"#include "llvm/ADT/Statistic.h"#include "llvm/Analysis/MemoryLocation.h"#include "llvm/Analysis/VectorUtils.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineJumpTableInfo.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"#include "llvm/CodeGen/ValueTypes.h"#include "llvm/IR/DiagnosticInfo.h"#include "llvm/IR/DiagnosticPrinter.h"#include "llvm/IR/IRBuilder.h"#include "llvm/IR/Instructions.h"#include "llvm/IR/IntrinsicsRISCV.h"#include "llvm/IR/PatternMatch.h"#include "llvm/MC/MCCodeEmitter.h"#include "llvm/MC/MCInstBuilder.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/InstructionCost.h"#include "llvm/Support/KnownBits.h"#include "llvm/Support/MathExtras.h"#include "llvm/Support/raw_ostream.h"#include <optional>#include "RISCVGenAsmMatcher.inc"#include "RISCVGenSearchableTables.inc"Go to the source code of this file.
Classes | |
| struct | VIDSequence |
Namespaces | |
| namespace | llvm |
| This is an optimization pass for GlobalISel generic memory operations. | |
| namespace | llvm::RISCVVIntrinsicsTable |
Macros | |
| #define | DEBUG_TYPE "riscv-lower" |
| #define | OP_CASE(NODE) |
| #define | VP_CASE(NODE) |
| #define | NODE_NAME_CASE(NODE) |
| #define | GET_REGISTER_MATCHER |
| #define | GET_RISCVVIntrinsicsTable_IMPL |
Variables | |
| static cl::opt< unsigned > | ExtensionMaxWebSize (DEBUG_TYPE "-ext-max-web-size", cl::Hidden, cl::desc("Give the maximum size (in number of nodes) of the web of " "instructions that we will consider for VW expansion"), cl::init(18)) |
| static cl::opt< bool > | AllowSplatInVW_W (DEBUG_TYPE "-form-vw-w-with-splat", cl::Hidden, cl::desc("Allow the formation of VW_W operations (e.g., " "VWADD_W) with splat constants"), cl::init(false)) |
| static cl::opt< unsigned > | NumRepeatedDivisors (DEBUG_TYPE "-fp-repeated-divisors", cl::Hidden, cl::desc("Set the minimum number of repetitions of a divisor to allow " "transformation to multiplications by the reciprocal"), cl::init(2)) |
| static cl::opt< int > | FPImmCost (DEBUG_TYPE "-fpimm-cost", cl::Hidden, cl::desc("Give the maximum number of instructions that we will " "use for creating a floating-point immediate value"), cl::init(2)) |
| static const Intrinsic::ID | FixedVlsegIntrIds [] |
| static const Intrinsic::ID | FixedVssegIntrIds [] |
| #define DEBUG_TYPE "riscv-lower" |
Definition at line 53 of file RISCVISelLowering.cpp.
| #define GET_REGISTER_MATCHER |
Definition at line 22360 of file RISCVISelLowering.cpp.
| #define GET_RISCVVIntrinsicsTable_IMPL |
Definition at line 22579 of file RISCVISelLowering.cpp.
| #define NODE_NAME_CASE | ( | NODE | ) |
| #define OP_CASE | ( | NODE | ) |
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Definition at line 16503 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, CC, llvm::ISD::Constant, DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::RISCVSubtarget::getXLenVT(), llvm::Value::hasOneUse(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::isPowerOf2_64(), LHS, llvm::Log2_64(), llvm::SelectionDAG::MaskedValueIsZero(), RHS, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, translateSetCCForBranch(), tryDemorganOfBooleanCondition(), and llvm::ISD::XOR.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 14068 of file RISCVISelLowering.cpp.
References DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::ISD::SUB, and llvm::ISD::XOR.
Referenced by performADDCombine().
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Perform two related transforms whose purpose is to incrementally recognize an explode_vector followed by scalar reduction as a vector reduction node.
This exists to recover from a deficiency in SLP which can't handle forests with multiple roots sharing common nodes. In some cases, one of the trees will be vectorized, and the other will remain (unprofitably) scalarized.
Definition at line 13615 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::SelectionDAG::getContext(), llvm::RISCVSubtarget::getELen(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::ISD::getVecReduceBaseOpcode(), getVecReduceOpcode(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::Value::hasOneUse(), llvm::RISCVSubtarget::hasVInstructions(), llvm::EVT::isInteger(), llvm::isNullConstant(), llvm::EVT::isScalableVector(), LHS, N, llvm::SelectionDAG::NewNodesMustHaveLegalTypes, RHS, and std::swap().
Referenced by performADDCombine(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performORCombine(), and performXORCombine().
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Definition at line 14026 of file RISCVISelLowering.cpp.
References llvm::CallingConv::C, llvm::SelectionDAG::getContext(), llvm::EVT::getHalfSizedIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), N, llvm::ISD::SIGN_EXTEND, llvm::ISD::SUB, and llvm::ISD::ZERO_EXTEND.
Referenced by performADDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performMULCombine(), and performSUBCombine().
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Definition at line 13710 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_SUBVECTOR, llvm::isNeutralConstant(), isNonZeroAVL(), llvm::isNullConstant(), llvm::SDNode::isUndef(), llvm_unreachable, lowerScalarInsert(), N, llvm::ISD::OR, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::RISCVISD::VECREDUCE_ADD_VL, llvm::RISCVISD::VECREDUCE_AND_VL, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::RISCVISD::VECREDUCE_OR_VL, llvm::RISCVISD::VECREDUCE_SMAX_VL, llvm::RISCVISD::VECREDUCE_SMIN_VL, llvm::RISCVISD::VECREDUCE_UMAX_VL, llvm::RISCVISD::VECREDUCE_UMIN_VL, llvm::RISCVISD::VECREDUCE_XOR_VL, llvm::RISCVISD::VFMV_S_F_VL, llvm::RISCVISD::VMV_S_X_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::ISD::XOR.
Referenced by performADDCombine(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performORCombine(), and performXORCombine().
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Definition at line 14246 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::ISD::OR, and llvm::ISD::XOR.
Referenced by performANDCombine(), and performORCombine().
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Combine a binary or FMA operation to its equivalent VW or VW_W form.
The supported combines are: add | add_vl | or disjoint -> vwadd(u) | vwadd(u)_w sub | sub_vl -> vwsub(u) | vwsub(u)_w mul | mul_vl -> vwmul(u) | vwmul_su shl | shl_vl -> vwsll fadd_vl -> vfwadd | vfwadd_w fsub_vl -> vfwsub | vfwsub_w fmul_vl -> vfwmul vwadd_w(u) -> vwadd(u) vwsub_w(u) -> vwsub(u) vfwadd_w -> vfwadd vfwsub_w -> vfwsub
Definition at line 15747 of file RISCVISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorBase< Size_T >::empty(), ExtensionMaxWebSize, llvm::Use::getOperandNo(), llvm::Use::getUser(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), LHS, N, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SmallVectorImpl< T >::reserve(), RHS, llvm::SmallVectorBase< Size_T >::size(), and std::swap().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine(), performVFMADD_VLCombine(), and performVWADDSUBW_VLCombine().
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Definition at line 14426 of file RISCVISelLowering.cpp.
References assert(), Cond, llvm::RISCVISD::CZERO_EQZ, llvm::RISCVISD::CZERO_NEZ, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::isOneConstant(), N, llvm::ISD::OR, and llvm::ISD::XOR.
Referenced by performORCombine().
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Definition at line 17388 of file RISCVISelLowering.cpp.
References llvm::ISD::BITCAST, convertToScalableVector(), DL, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::EVT::getSimpleVT(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::EVT::isScalarInteger(), llvm::EVT::isSimple(), llvm::MVT::isVector(), N, useRVVForFixedLengthVectorVT(), llvm::RISCVISD::VCPOP_VL, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 13871 of file RISCVISelLowering.cpp.
References llvm::AllOnes, llvm::ISD::AND, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::hasConditionalMoveFusion(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::isNullConstant(), llvm::EVT::isVector(), isZeroOrAllOnes(), N, llvm::ISD::SELECT, llvm::RISCVISD::SELECT_CC, and std::swap().
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Definition at line 13936 of file RISCVISelLowering.cpp.
References llvm::AllOnes, combineSelectAndUse(), and N.
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Definition at line 8174 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, CC, DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SDNode::getAsAPIntVal(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::RISCVSubtarget::hasConditionalMoveFusion(), llvm::isAllOnesConstant(), llvm::isNullConstant(), LHS, matchSetCC(), N, llvm::ISD::OR, RHS, llvm::ISD::SETCC, and llvm::ISD::XOR.
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Definition at line 14116 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::EVT::isInteger(), llvm::isOneConstant(), llvm::APInt::isSignedIntN(), N, llvm::ISD::SETCC, and llvm::ISD::XOR.
Referenced by performSUBCombine().
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Definition at line 14160 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::APInt::getSplat(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDValue::hasOneUse(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::RISCVISD::ORC_B, llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by performSUBCombine().
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Definition at line 17015 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::RISCVISD::ADD_VL, assert(), DL, getDefaultScalableVLOps(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::isUndef(), N, std::swap(), llvm::RISCVISD::VWMACC_VL, llvm::RISCVISD::VWMACCSU_VL, llvm::RISCVISD::VWMACCU_VL, llvm::RISCVISD::VWMUL_VL, llvm::RISCVISD::VWMULSU_VL, and llvm::RISCVISD::VWMULU_VL.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 17202 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::EVT::isVector(), N, llvm::ISD::SIGN_EXTEND, llvm::SMin, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::RISCVISD::TRUNCATE_VECTOR_VL, llvm::RISCVISD::VMSET_VL, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 14296 of file RISCVISelLowering.cpp.
References Cond, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isConstOrConstSplat(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::ConstantSDNode::isZero(), N, llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETULT, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::TRUNCATE, and llvm::ISD::VSELECT.
Referenced by performTRUNCATECombine().
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Definition at line 17256 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementType(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignedMinValue(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::isConstantSplatVector(), llvm::APInt::isMask(), llvm::APInt::isNonNegative(), llvm::isNullConstant(), N, llvm::APInt::sext(), llvm::ISD::SMAX, llvm::RISCVISD::SMAX_VL, llvm::ISD::SMIN, llvm::RISCVISD::SMIN_VL, llvm::RISCVISD::TRUNCATE_VECTOR_VL, llvm::RISCVISD::TRUNCATE_VECTOR_VL_SSAT, llvm::RISCVISD::TRUNCATE_VECTOR_VL_USAT, llvm::APInt::uge(), llvm::ISD::UMIN, llvm::RISCVISD::UMIN_VL, and llvm::RISCVISD::VMV_V_X_VL.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 14722 of file RISCVISelLowering.cpp.
References llvm::And, llvm::ISD::AND, llvm::ISD::BITCAST, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::ISD::isConstantSplatVector(), llvm::APInt::isMask(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), N, llvm::ISD::SRA, and llvm::ISD::SRL.
Referenced by performMULCombine().
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Definition at line 16273 of file RISCVISelLowering.cpp.
References A, B, llvm::CallingConv::C, llvm::RISCVISD::FNEG_VL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectionDAGInfo(), llvm::SelectionDAGTargetInfo::isTargetStrictFPOpcode(), N, negateFMAOpcode(), and llvm::Offset.
Referenced by performVFMADD_VLCombine().
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Definition at line 15852 of file RISCVISelLowering.cpp.
References assert(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::isConstantSplatVectorAllZeros(), llvm::isNullOrNullSplat(), llvm::SDValue::isUndef(), N, llvm::RISCVISD::VMERGE_VL, llvm::RISCVISD::VMSET_VL, llvm::ISD::VSELECT, llvm::RISCVISD::VWADD_W_VL, llvm::RISCVISD::VWADDU_W_VL, llvm::RISCVISD::VWSUB_W_VL, llvm::RISCVISD::VWSUBU_W_VL, X, and Y.
Referenced by performVWADDSUBW_VLCombine().
Definition at line 18611 of file RISCVISelLowering.cpp.
Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode().
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Definition at line 2719 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getXLenVT(), and llvm::EVT::isFixedLengthVector().
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Definition at line 19732 of file RISCVISelLowering.cpp.
References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertFromScalableVector(), DL, llvm::RISCVISD::FMV_H_X, llvm::RISCVISD::FMV_W_X_RV64, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::MVT::isScalableVector(), llvm_unreachable, and llvm::CCValAssign::needsCustom().
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Definition at line 2707 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::ISD::INSERT_SUBVECTOR, and llvm::EVT::isScalableVector().
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Definition at line 19793 of file RISCVISelLowering.cpp.
References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertToScalableVector(), DL, llvm::RISCVISD::FMV_X_ANYEXTH, llvm::RISCVISD::FMV_X_ANYEXTW_RV64, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::isFixedLengthVector(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm_unreachable, and llvm::CCValAssign::needsCustom().
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Definition at line 12852 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), getRISCVWOpcode(), N, and llvm::ISD::TRUNCATE.
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Definition at line 12865 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), N, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::TRUNCATE.
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Definition at line 19019 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), llvm::HexagonInstrInfo::loadRegFromStackSlot(), MI, llvm::MachineMemOperand::MOStore, and TII.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 19437 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, llvm::RISCVSubtarget::is64Bit(), llvm_unreachable, MBB, MI, MRI, llvm::MachineInstr::NoFPExcept, llvm::MachineInstr::setFlag(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 19110 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::First, llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineOperand::getImm(), llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by emitSelectPseudo().
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Definition at line 19073 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::RegState::Kill, MI, MRI, llvm::MachineInstr::NoFPExcept, llvm::MachineInstr::setFlag(), and TII.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 18919 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getBasicBlock(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::insert(), MI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 19212 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::any_of(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), CC, llvm::MachineInstr::collectDebugValues(), llvm::SmallSet< T, N, C >::count(), DL, EmitLoweredCascadedSelect(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::RISCVSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), I, llvm::SmallSet< T, N, C >::insert(), llvm::MachineBasicBlock::instr_end(), isSelectPseudo(), LHS, MI, llvm::next_nodbg(), llvm::MachineFunctionProperties::NoPHIs, llvm::MachineBasicBlock::push_back(), RHS, llvm::MachineBasicBlock::setCallFrameSize(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
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Definition at line 18984 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), assert(), llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), MI, llvm::MachineMemOperand::MOLoad, llvm::HexagonInstrInfo::storeRegToStackSlot(), and TII.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 19374 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::RISCVII::getLMul(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::RISCVII::getSEWOpNum(), llvm::MachineFunction::getSubtarget(), llvm::RegState::Kill, lookupMaskedIntrinsic(), llvm::RISCV::RISCVMaskedPseudoInfo::MaskedPseudo, MI, MRI, TII, and TRI.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 14543 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::CallingConv::C, llvm::countr_zero(), DL, llvm::SelectionDAG::getConstant(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getXLenVT(), llvm::ConstantSDNode::getZExtValue(), llvm::Function::hasMinSize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isPowerOf2_64(), llvm::Log2_64(), N, llvm::Offset, llvm::ISD::SHL, llvm::RISCVISD::SHL_ADD, llvm::ISD::SUB, and X.
Referenced by performMULCombine().
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Definition at line 8250 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SDNode::getAsAPIntVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSelect(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::APInt::isAllOnes(), llvm::ConstantSDNode::isOpaque(), llvm::APInt::isZero(), llvm::ISD::SELECT, and std::swap().
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Definition at line 16646 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::BitWidth, Cond, llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::isNullConstant(), N, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by performSELECTCombine().
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Creates an all ones mask suitable for masking a vector of type VecTy with vector length VL.
Definition at line 2741 of file RISCVISelLowering.cpp.
References DL, getMaskTypeFor(), llvm::SelectionDAG::getNode(), and llvm::RISCVISD::VMSET_VL.
Referenced by getDefaultScalableVLOps(), getDefaultVLOps(), and lowerVectorIntrinsicScalars().
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Definition at line 2661 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVSubtarget::getELen(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalableVectorVT(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::isFixedLengthVector(), llvm::isPowerOf2_32(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::RISCV::RVVBitsPerBlock, llvm::MVT::SimpleTy, and useRVVForFixedLengthVectorVT().
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Definition at line 2696 of file RISCVISelLowering.cpp.
References getContainerForFixedLengthVector(), and llvm::SelectionDAG::getTargetLoweringInfo().
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Definition at line 2748 of file RISCVISelLowering.cpp.
References assert(), DL, getAllOnesMask(), llvm::SelectionDAG::getRegister(), llvm::RISCVSubtarget::getXLenVT(), and llvm::MVT::isScalableVector().
Referenced by combineToVWMACC(), and getDefaultVLOps().
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Definition at line 2770 of file RISCVISelLowering.cpp.
References assert(), DL, getDefaultScalableVLOps(), getDefaultVLOps(), llvm::MVT::getVectorNumElements(), llvm::MVT::isFixedLengthVector(), and llvm::MVT::isScalableVector().
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Definition at line 2757 of file RISCVISelLowering.cpp.
References assert(), DL, getAllOnesMask(), llvm::SelectionDAG::getConstant(), llvm::RISCVSubtarget::getXLenVT(), and llvm::MVT::isScalableVector().
Referenced by combineScalarCTPOPToVCPOP(), getDefaultVLOps(), getWideningInterleave(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerCttzElts(), lowerFMAXIMUM_FMINIMUM(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT(), matchSplatAsGather(), performFP_TO_INTCombine(), and llvm::RISCVTargetLowering::ReplaceNodeResults().
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Definition at line 4621 of file RISCVISelLowering.cpp.
References llvm::MVT::changeVectorElementTypeToInteger(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MVT::getVectorVT(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::SRL, and llvm::ISD::TRUNCATE.
Referenced by lowerVECTOR_SHUFFLE().
Definition at line 3371 of file RISCVISelLowering.cpp.
References llvm::BitWidth, llvm::APFloat::convertToInteger(), llvm::APInt::extractBits(), llvm::APFloatBase::opInvalidOp, and llvm::TowardZero.
Referenced by isSimpleVIDSequence().
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Definition at line 21300 of file RISCVISelLowering.cpp.
References llvm::AtomicRMWInst::Add, llvm_unreachable, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, and llvm::AtomicRMWInst::Xchg.
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Definition at line 7901 of file RISCVISelLowering.cpp.
References llvm::RISCVConstantPoolValue::Create(), DL, llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstantPool(), llvm::RISCVISD::LLA, and N.
Referenced by llvm::RISCVTargetLowering::LowerCall().
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Definition at line 7891 of file RISCVISelLowering.cpp.
References llvm::RISCVConstantPoolValue::Create(), DL, llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstantPool(), llvm::RISCVISD::LLA, and N.
Referenced by llvm::RISCVTargetLowering::LowerCall().
Definition at line 3357 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::getScalableVectorVT(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), and llvm::RISCV::RVVBitsPerBlock.
Referenced by getSmallestVTForIndex(), lowerBUILD_VECTOR(), llvm::RISCVTargetLowering::LowerOperation(), lowerReductionSeq(), lowerShuffleViaVRegSplitting(), and llvm::RISCVTargetLowering::PerformDAGCombine().
Return the type of the mask type suitable for masking the provided vector type.
This is simply an i1 element type vector of the same (possibly scalable) length.
Definition at line 2733 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), and llvm::MVT::isVector().
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Definition at line 3967 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVSubtarget::is64Bit(), and llvm_unreachable.
Referenced by lowerBuildVectorViaPacking().
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Definition at line 20115 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), and llvm::EVT::getTypeForEVT().
Get a RISC-V target specified VL op for a given SDNode.
Definition at line 6336 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::RISCVISD::AND_VL, llvm::RISCVISD::CTLZ_VL, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::RISCVISD::CTTZ_VL, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::ISD::FMA, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::RISCVISD::FSQRT_VL, llvm::ISD::LLRINT, llvm_unreachable, llvm::ISD::LRINT, OP_CASE, llvm::ISD::OR, llvm::RISCVISD::OR_VL, ROTL, ROTR, llvm::RISCVISD::SRA_VL, llvm::RISCVISD::SRL_VL, llvm::ISD::STRICT_FMA, llvm::RISCVISD::STRICT_VFMADD_VL, llvm::RISCVISD::VFCVT_RM_X_F_VL, llvm::RISCVISD::VFCVT_RTZ_X_F_VL, llvm::RISCVISD::VFCVT_RTZ_XU_F_VL, llvm::RISCVISD::VFMADD_VL, llvm::RISCVISD::VFMAX_VL, llvm::RISCVISD::VFMIN_VL, llvm::RISCVISD::VMAND_VL, llvm::RISCVISD::VMERGE_VL, llvm::RISCVISD::VMOR_VL, llvm::RISCVISD::VMXOR_VL, VP_CASE, llvm::RISCVISD::VSEXT_VL, llvm::RISCVISD::VZEXT_VL, llvm::ISD::XOR, and llvm::RISCVISD::XOR_VL.
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Definition at line 12824 of file RISCVISelLowering.cpp.
References llvm::RISCVISD::DIVUW, llvm::RISCVISD::DIVW, llvm_unreachable, llvm::RISCVISD::REMUW, llvm::RISCVISD::ROLW, llvm::RISCVISD::RORW, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::RISCVISD::SLLW, llvm::ISD::SRA, llvm::RISCVISD::SRAW, llvm::ISD::SRL, llvm::RISCVISD::SRLW, llvm::ISD::UDIV, and llvm::ISD::UREM.
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Definition at line 10377 of file RISCVISelLowering.cpp.
References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorIdxConstant(), llvm_unreachable, llvm::ISD::VECREDUCE_FADD, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::ISD::VECREDUCE_FMAX, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::ISD::VECREDUCE_FMAXIMUM, llvm::ISD::VECREDUCE_FMIN, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::ISD::VECREDUCE_FMINIMUM, llvm::ISD::VECREDUCE_SEQ_FADD, and llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL.
Definition at line 10162 of file RISCVISelLowering.cpp.
References llvm_unreachable, llvm::ISD::VECREDUCE_ADD, llvm::RISCVISD::VECREDUCE_ADD_VL, llvm::ISD::VECREDUCE_AND, llvm::RISCVISD::VECREDUCE_AND_VL, llvm::RISCVISD::VECREDUCE_FADD_VL, llvm::RISCVISD::VECREDUCE_FMAX_VL, llvm::RISCVISD::VECREDUCE_FMIN_VL, llvm::ISD::VECREDUCE_OR, llvm::RISCVISD::VECREDUCE_OR_VL, llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL, llvm::ISD::VECREDUCE_SMAX, llvm::RISCVISD::VECREDUCE_SMAX_VL, llvm::ISD::VECREDUCE_SMIN, llvm::RISCVISD::VECREDUCE_SMIN_VL, llvm::ISD::VECREDUCE_UMAX, llvm::RISCVISD::VECREDUCE_UMAX_VL, llvm::ISD::VECREDUCE_UMIN, llvm::RISCVISD::VECREDUCE_UMIN_VL, llvm::ISD::VECREDUCE_XOR, and llvm::RISCVISD::VECREDUCE_XOR_VL.
Definition at line 4475 of file RISCVISelLowering.cpp.
References llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getConstantOperandVal(), llvm::RISCVTargetLowering::getLMUL(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getVectorNumElements(), and llvm::RISCVII::LMUL_8.
Referenced by lowerVECTOR_SHUFFLE().
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Definition at line 9042 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::bitsGT(), llvm::MVT::getDoubleNumVectorElementsVT(), getLMUL1VT(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::isScalableVector(), and llvm::MVT::isValid().
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Definition at line 7874 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getTargetBlockAddress(), and N.
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Definition at line 7880 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getTargetConstantPool(), and N.
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Definition at line 7869 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getTargetGlobalAddress(), and N.
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Definition at line 7886 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getTargetJumpTable(), and N.
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Definition at line 9983 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getNode(), Operands, and processVCIXOperands().
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Definition at line 9946 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), DL, llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getSubtarget(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), Operands, and processVCIXOperands().
Given a binary operator, return the associative generic ISD::VECREDUCE_OP which corresponds to it.
Definition at line 13582 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::FADD, llvm_unreachable, llvm::ISD::OR, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_FADD, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, llvm::ISD::VECREDUCE_XOR, and llvm::ISD::XOR.
Referenced by combineBinOpOfExtractToReduceTree().
Definition at line 2572 of file RISCVISelLowering.cpp.
References assert(), II, llvm::ISD::INTRINSIC_W_CHAIN, and llvm::ISD::INTRINSIC_WO_CHAIN.
Referenced by lowerVectorIntrinsicScalars().
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Definition at line 3334 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDValue::isUndef(), llvm::RISCVII::MASK_AGNOSTIC, llvm::Offset, llvm::RISCVII::TAIL_AGNOSTIC, and llvm::RISCVISD::VSLIDEDOWN_VL.
Referenced by lowerBUILD_VECTOR(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlidedown(), and llvm::RISCVTargetLowering::ReplaceNodeResults().
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Definition at line 3346 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDValue::isUndef(), llvm::RISCVII::MASK_AGNOSTIC, llvm::Offset, llvm::RISCVII::TAIL_AGNOSTIC, and llvm::RISCVISD::VSLIDEUP_VL.
Referenced by lowerVECTOR_SHUFFLE(), and lowerVECTOR_SHUFFLEAsVSlideup().
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Definition at line 4903 of file RISCVISelLowering.cpp.
References llvm::RISCVISD::ADD_VL, assert(), llvm::MVT::changeTypeToInteger(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), getWideningSpread(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::SDValue::isUndef(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::multiplyCoefficientBy(), llvm::RISCVISD::VWADDU_VL, llvm::RISCVISD::VWADDU_W_VL, llvm::RISCVISD::VWMULU_VL, and llvm::RISCVISD::VWSLL_VL.
Referenced by lowerVECTOR_SHUFFLE().
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Definition at line 4878 of file RISCVISelLowering.cpp.
References llvm::MVT::changeTypeToInteger(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::ISD::SHL, and llvm::ISD::ZERO_EXTEND.
Referenced by getWideningInterleave(), and lowerVECTOR_SHUFFLE().
Return true if a RISC-V target specified op has a mask operand.
Definition at line 6506 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVISD::FIRST_NUMBER, llvm::RISCVISD::FIRST_STRICTFP_OPCODE, llvm::RISCVISD::FIRST_VL_VECTOR_OP, llvm::RISCVISD::LAST_STRICTFP_OPCODE, llvm::RISCVISD::LAST_VL_VECTOR_OP, llvm::RISCVISD::SETCC_VL, llvm::RISCVISD::STRICT_FADD_VL, llvm::RISCVISD::STRICT_VFROUND_NOEXCEPT_VL, llvm::RISCVISD::TRUNCATE_VECTOR_VL, llvm::RISCVISD::VFIRST_VL, and llvm::RISCVISD::VRGATHER_VX_VL.
Return true if a RISC-V target specified op has a passthru operand.
Definition at line 6482 of file RISCVISelLowering.cpp.
References llvm::RISCVISD::ADD_VL, assert(), llvm::RISCVISD::FCOPYSIGN_VL, llvm::RISCVISD::FIRST_NUMBER, llvm::RISCVISD::FIRST_STRICTFP_OPCODE, llvm::RISCVISD::FIRST_VL_VECTOR_OP, llvm::RISCVISD::LAST_STRICTFP_OPCODE, llvm::RISCVISD::LAST_VL_VECTOR_OP, llvm::RISCVISD::SETCC_VL, llvm::RISCVISD::STRICT_FADD_VL, llvm::RISCVISD::STRICT_FDIV_VL, llvm::RISCVISD::VFMAX_VL, llvm::RISCVISD::VFWSUB_W_VL, llvm::RISCVISD::VMERGE_VL, and llvm::RISCVISD::VWMUL_VL.
Definition at line 5227 of file RISCVISelLowering.cpp.
References llvm::Last.
Referenced by lowerVECTOR_SHUFFLE().
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Match shuffles that concatenate two vectors, rotate the concatenation, and then extract the original number of elements from the rotated result.
This is equivalent to vector.splice or X86's PALIGNR instruction. The returned rotation amount is for a rotate right, where elements move from higher elements to lower elements. LoSrc indicates the first source vector of the rotate or -1 for undef. HiSrc indicates the second vector of the rotate or -1 for undef. At least one of LoSrc and HiSrc will be 0 or 1 if a rotation is found.
NOTE: We talk about rotate to the right which matches how bit shift and rotate instructions are described where LSBs are on the right, but LLVM IR and the table below write vectors with the lowest elements on the left.
Definition at line 4555 of file RISCVISelLowering.cpp.
References assert(), and Size.
Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal(), and lowerVECTOR_SHUFFLE().
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Is this shuffle interleaving contiguous elements from one vector into the even elements and contiguous elements from another vector into the odd elements.
EvenSrc will contain the element that should be in the first even element. OddSrc will contain the element that should be in the first odd element. These can be the first element in a source or the element half way through the source.
Definition at line 4511 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::ShuffleVectorInst::isInterleaveMask(), and Size.
Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal(), and lowerVECTOR_SHUFFLE().
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Definition at line 5048 of file RISCVISelLowering.cpp.
References DL, llvm::MVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::EVT::getScalarSizeInBits(), llvm::RISCVSubtarget::getTargetLowering(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ShuffleVectorInst::isBitRotateMask(), and llvm::TargetLoweringBase::isTypeLegal().
Referenced by lowerShuffleViaVRegSplitting(), and lowerVECTOR_SHUFFLEAsRotate().
Definition at line 10285 of file RISCVISelLowering.cpp.
Referenced by combineBinOpToReduce(), and lowerReductionSeq().
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Definition at line 6524 of file RISCVISelLowering.cpp.
References llvm::RISCVSubtarget::hasVInstructionsF16(), and llvm::RISCVSubtarget::hasVInstructionsF16Minimal().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 19056 of file RISCVISelLowering.cpp.
References MI.
Referenced by emitSelectPseudo().
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Definition at line 3404 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, llvm::enumerate(), getExactInteger(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::APInt::getSExtValue(), Idx, isConstant(), llvm::APInt::sdiv(), and llvm::APInt::srem().
Referenced by lowerBuildVectorOfConstants(), and llvm::RISCVTargetLowering::PerformDAGCombine().
Definition at line 4849 of file RISCVISelLowering.cpp.
Referenced by llvm::RISCVTargetLowering::lowerInterleavedStore(), and lowerVECTOR_SHUFFLE().
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Definition at line 17087 of file RISCVISelLowering.cpp.
References llvm::EVT::bitsLT(), llvm::EVT::changeVectorElementType(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getSubtarget(), llvm::EVT::getVectorElementType(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::UNSIGNED_SCALED.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 19364 of file RISCVISelLowering.cpp.
References assert(), and llvm::Masked.
Referenced by emitVFROUND_NOEXCEPT_MASK().
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Definition at line 6037 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::ISD::MEMBARRIER, llvm::SequentiallyConsistent, llvm::SyncScope::SingleThread, and llvm::SyncScope::System.
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Definition at line 4996 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BITREVERSE, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getSimpleValueType(), llvm::RISCVSubtarget::getTargetLowering(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ISD::INSERT_SUBVECTOR, llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::ShuffleVectorInst::isReverseMask(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::PowerOf2Ceil(), llvm::ArrayRef< T >::size(), and llvm::ISD::SRL.
Referenced by lowerVECTOR_SHUFFLE().
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Definition at line 4044 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLE(), llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), llvm::count_if(), DL, llvm::RISCVISD::FMV_X_ANYEXTH, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getFixedSizeInBits(), llvm::RISCVSubtarget::getFLen(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::RISCVTargetLowering::getLMUL(), getLMUL1VT(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::RISCVSubtarget::getRealVLen(), llvm::SelectionDAG::getSetCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplatBuildVector(), llvm::getSplatValue(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MVT::getVectorMinNumElements(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), getVSlidedown(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::isBuildVectorOfConstantFPSDNodes(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::RISCVII::LMUL_2, llvm::RISCVII::LMUL_4, llvm::RISCVII::LMUL_8, lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaPacking(), llvm::RISCVII::MASK_AGNOSTIC, matchSplatAsGather(), llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::reserve(), llvm::ISD::SETNE, llvm::SmallVectorBase< Size_T >::size(), llvm::ArrayRef< T >::slice(), llvm::Splat, llvm::RISCVII::TAIL_AGNOSTIC, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VFSLIDE1DOWN_VL, llvm::RISCVISD::VMV_V_X_VL, llvm::ISD::VSELECT, and llvm::RISCVISD::VSLIDE1DOWN_VL.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 3666 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLE(), llvm::MVT::changeVectorElementType(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::SelectionDAG::ComputeMaxSignificantBits(), convertFromScalableVector(), convertToScalableVector(), llvm::divideCeil(), DL, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getSignedConstant(), llvm::MVT::getSizeInBits(), llvm::getSplatValue(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::ISD::INSERT_VECTOR_ELT, INT64_MIN, llvm::RISCVSubtarget::is64Bit(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), llvm::isPowerOf2_32(), llvm::isPowerOf2_64(), isSimpleVIDSequence(), llvm::Log2_64(), lowerBuildVectorViaDominantValues(), llvm::ISD::MUL, llvm::ISD::SHL, llvm::SelectionDAG::shouldOptForSize(), llvm::ISD::SINT_TO_FP, llvm::Splat, llvm::ISD::SRL, llvm::ISD::SUB, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VID_VL, llvm::RISCVISD::VMCLR_VL, llvm::RISCVISD::VMSET_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::RISCVISD::VSEXT_VL.
Referenced by lowerBUILD_VECTOR().
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Try and optimize BUILD_VECTORs with "dominant values" - these are values which constitute a large proportion of the elements.
In such cases we can splat a vector with the dominant element and make up the shortfall with INSERT_VECTOR_ELTs. Returns SDValue if not profitable. Note that this includes vectors of 2 elements by association. The upper-most element is the "dominant" one, allowing us to use a splat to "insert" the upper element, and an insert of the lower element at position 0, which improves codegen.
Definition at line 3560 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), llvm::count_if(), DL, llvm::enumerate(), llvm::SelectionDAG::getBuildVector(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::SelectionDAG::getSplatBuildVector(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::Log2_32(), llvm::SelectionDAG::shouldOptForSize(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::size(), llvm::transform(), llvm::RISCVISD::VFSLIDE1DOWN_VL, llvm::ISD::VSELECT, and llvm::RISCVISD::VSLIDE1DOWN_VL.
Referenced by lowerBUILD_VECTOR(), and lowerBuildVectorOfConstants().
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Double the element size of the build vector to reduce the number of vslide1down in the build vector chain.
In the worst case, this trades three scalar operations for 1 vector operation. Scalar operations are generally lower latency, and for out-of-order cores we also benefit from additional parallelism.
Definition at line 3987 of file RISCVISelLowering.cpp.
References A, llvm::ISD::AND, assert(), B, llvm::ISD::BITCAST, llvm::SDNodeFlags::Disjoint, DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getIntegerVT(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), getPACKOpcode(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::ISD::OR, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::reserve(), llvm::ISD::SHL, and llvm::SmallVectorBase< Size_T >::size().
Referenced by lowerBUILD_VECTOR().
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Definition at line 5967 of file RISCVISelLowering.cpp.
References assert(), llvm::SmallVectorBase< Size_T >::empty(), llvm::RISCVMatInt::generateInstSeq(), llvm::RISCVMatInt::generateTwoRegInstSeq(), llvm::RISCVSubtarget::getMaxBuildIntsCost(), llvm::SelectionDAG::shouldOptForSize(), llvm::SmallVectorBase< Size_T >::size(), and llvm::RISCVSubtarget::useConstantPoolForLargeInts().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 9623 of file RISCVISelLowering.cpp.
References convertToScalableVector(), DL, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getElementCount(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorElementCount(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::isOneConstant(), N, llvm::ISD::SETLT, and llvm::RISCVISD::VFIRST_VL.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
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Given a shuffle where the indices are disjoint between the two sources, e.g.:
t2:v4i8 = vector_shuffle t0:v4i8, t1:v4i8, <2, 7, 1, 4>
Merge the two sources into one and do a single source shuffle:
t2:v4i8 = vselect t1:v4i8, t0:v4i8, <0, 1, 0, 1> t3:v4i8 = vector_shuffle t2:v4i8, undef, <2, 3, 1, 0>
A vselect will either be merged into a masked instruction or be lowered as a vmerge.vvm, which is cheaper than a vrgather.vv.
Definition at line 5258 of file RISCVISelLowering.cpp.
References llvm::MVT::changeVectorElementType(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), llvm::RISCVSubtarget::getXLenVT(), I, Idx, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Select, and llvm::ISD::VSELECT.
Referenced by lowerVECTOR_SHUFFLE().
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Definition at line 6252 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, assert(), DL, llvm::ISD::FABS, llvm::RISCVISD::FMV_H_X, llvm::RISCVISD::FMV_X_ANYEXTH, llvm::ISD::FNEG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignMask(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), and llvm::ISD::XOR.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 6275 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, assert(), llvm::ISD::BITCAST, llvm::SDNodeFlags::Disjoint, DL, llvm::ISD::FCOPYSIGN, llvm::RISCVISD::FMV_H_X, llvm::RISCVISD::FMV_X_ANYEXTH, llvm::RISCVISD::FMV_X_ANYEXTW_RV64, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignMask(), llvm::SDValue::getValueSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), llvm_unreachable, llvm::ISD::OR, llvm::APInt::sext(), llvm::ISD::SHL, llvm::RISCVISD::SplitF64, and llvm::ISD::SRL.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 6168 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), convertToScalableVector(), DL, llvm::RISCVISD::FMAX, llvm::ISD::FMAXIMUM, llvm::RISCVISD::FMIN, getContainerForFixedLengthVector(), getDefaultVLOps(), getMaskTypeFor(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getUNDEF(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::MVT::isVector(), llvm::RISCVISD::SETCC_VL, llvm::ISD::SETOEQ, llvm::RISCVISD::VFMAX_VL, llvm::RISCVISD::VFMIN_VL, llvm::RISCVISD::VMERGE_VL, X, and Y.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 3011 of file RISCVISelLowering.cpp.
References DL, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::RISCVSubtarget::hasStdExtZfhOrZhinx(), and llvm::ISD::STRICT_FP_EXTEND.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 2898 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::RISCVISD::FCVT_W_RV64, llvm::RISCVISD::FCVT_WU_RV64, llvm::RISCVISD::FCVT_X, llvm::RISCVISD::FCVT_XU, llvm::ISD::FP_EXTEND, llvm::RISCVISD::FP_EXTEND_VL, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::RISCVSubtarget::hasStdExtZfhOrZhinx(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), llvm::RISCVFPRndMode::RTZ, llvm::RISCVISD::SETCC_VL, llvm::ISD::SETUO, llvm::RISCVISD::TRUNCATE_VECTOR_VL_SSAT, llvm::RISCVISD::TRUNCATE_VECTOR_VL_USAT, llvm::RISCVISD::VFCVT_RTZ_X_F_VL, llvm::RISCVISD::VFCVT_RTZ_XU_F_VL, llvm::RISCVISD::VMERGE_VL, and llvm::RISCVISD::VMV_V_X_VL.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 3279 of file RISCVISelLowering.cpp.
References llvm::APFloat::convertFromAPInt(), DL, llvm::RISCVISD::FROUND, llvm::SelectionDAG::getConstantFP(), llvm::MVT::getFltSemantics(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isVector(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), and llvm::SelectionDAG::shouldOptForSize().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 9588 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::RISCVVType::encodeLMUL(), llvm::RISCVVType::encodeSEW(), llvm::RISCVSubtarget::getELen(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isPowerOf2_32(), N, llvm::RISCV::RVVBitsPerBlock, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
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Definition at line 2871 of file RISCVISelLowering.cpp.
References DL, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::RISCVSubtarget::hasStdExtZfhOrZhinx(), and llvm::ISD::STRICT_FP_ROUND.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Helper to lower a reduction sequence of the form: scalar = reduce_op vec, scalar_start.
Definition at line 10294 of file RISCVISelLowering.cpp.
References llvm::MVT::bitsLE(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), getLMUL1VT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INSERT_SUBVECTOR, isNonZeroAVL(), lowerScalarInsert(), Reduction, and llvm::RISCVII::TAIL_AGNOSTIC.
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Definition at line 4421 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLE(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::ISD::INSERT_SUBVECTOR, llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::isNullConstant(), llvm::MVT::isScalableVector(), lowerScalarSplat(), llvm::ISD::SIGN_EXTEND, llvm::RISCVISD::VFMV_S_F_VL, and llvm::RISCVISD::VMV_S_X_VL.
Referenced by combineBinOpToReduce(), and lowerReductionSeq().
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Definition at line 4367 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, llvm::MVT::changeVectorElementType(), DL, llvm::RISCVISD::FMV_X_ANYEXTH, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFloatingPoint(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::SDValue::isUndef(), lowerScalarSplat(), llvm::ISD::SIGN_EXTEND, llvm::Splat, splatSplitI64WithVL(), llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_S_X_VL, and llvm::RISCVISD::VMV_V_X_VL.
Referenced by lowerScalarInsert(), and lowerScalarSplat().
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Definition at line 5099 of file RISCVISelLowering.cpp.
References assert(), llvm::ArrayRef< T >::begin(), convertToScalableVector(), llvm::Data, DL, llvm::ArrayRef< T >::end(), getContainerForFixedLengthVector(), llvm::MVT::getFixedSizeInBits(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getLMUL1VT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::RISCVSubtarget::getRealVLen(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), llvm::MVT::getVectorMinNumElements(), llvm::MVT::getVectorVT(), isLegalBitRotate(), N, Operands, and llvm::processShuffleMasks().
Referenced by lowerVECTOR_SHUFFLE().
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Definition at line 5340 of file RISCVISelLowering.cpp.
References llvm::any_of(), assert(), llvm::MVT::bitsGT(), llvm::MVT::changeTypeToInteger(), llvm::MVT::changeVectorElementType(), llvm::ISD::CONCAT_VECTORS, convertFromScalableVector(), convertToScalableVector(), llvm::count_if(), llvm::SmallVectorTemplateCommon< T, typename >::data(), DL, llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), getDeinterleaveShiftAndTrunc(), llvm::RISCVSubtarget::getELen(), llvm::SelectionDAG::getExtLoad(), llvm::TypeSize::getFixed(), llvm::SDNode::getFlags(), llvm::MVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::SelectionDAG::getRegister(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getScalarType(), llvm::SelectionDAG::getSetCC(), getSingleShuffleSrc(), llvm::MVT::getSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::MVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), getVSlidedown(), getVSlideup(), llvm::SelectionDAG::getVTList(), getWideningInterleave(), getWideningSpread(), llvm::RISCVSubtarget::getXLenVT(), Idx, llvm::ISD::INTRINSIC_W_CHAIN, isCompressMask(), llvm::ShuffleVectorInst::isDeInterleaveMaskOfFactor(), isElementRotate(), llvm::MVT::isFloatingPoint(), llvm::ShuffleVectorInst::isIdentityMask(), llvm::MVT::isInteger(), isInterleaveShuffle(), llvm::ISD::isNormalLoad(), llvm::ShuffleVectorInst::isReverseMask(), llvm::ShuffleVectorSDNode::isSplat(), llvm::ShuffleVectorSDNode::isSplatMask(), llvm::SelectionDAG::isSplatValue(), isSpreadMask(), llvm::SDValue::isUndef(), lowerBitreverseShuffle(), lowerDisjointIndicesShuffle(), lowerShuffleViaVRegSplitting(), lowerVECTOR_SHUFFLEAsRotate(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SETNE, llvm::SmallVectorBase< Size_T >::size(), Size, llvm::Splat, llvm::RISCVII::TAIL_AGNOSTIC, tryWidenMaskForShuffle(), llvm::ISD::VECTOR_COMPRESS, llvm::ISD::VECTOR_REVERSE, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_V_X_VL, llvm::RISCVISD::VRGATHER_VV_VL, llvm::RISCVISD::VRGATHER_VX_VL, llvm::RISCVISD::VRGATHEREI16_VV_VL, llvm::ISD::VSELECT, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().
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Definition at line 5071 of file RISCVISelLowering.cpp.
References llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::getScalarType(), llvm::SDNode::getValueType(), isLegalBitRotate(), and llvm::ISD::ROTL.
Referenced by lowerVECTOR_SHUFFLE().
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Match v(f)slide1up/down idioms.
These operations involve sliding N-1 elements to make room for an inserted scalar at one end.
Definition at line 4775 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::sampleprof::Base, llvm::MVT::changeVectorElementTypeToInteger(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::RISCVISD::FMV_X_ANYEXTH, llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasVInstructionsF16(), llvm::MVT::isFloatingPoint(), llvm::Offset, llvm::Splat, std::swap(), llvm::RISCVISD::VFSLIDE1DOWN_VL, llvm::RISCVISD::VFSLIDE1UP_VL, llvm::RISCVISD::VSLIDE1DOWN_VL, and llvm::RISCVISD::VSLIDE1UP_VL.
Referenced by lowerVECTOR_SHUFFLE().
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Definition at line 4654 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), getVSlidedown(), llvm::RISCVSubtarget::getXLenVT(), llvm::Offset, and llvm::SmallVectorBase< Size_T >::size().
Referenced by lowerVECTOR_SHUFFLE().
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Definition at line 4731 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorNumElements(), getVSlideup(), llvm::RISCVSubtarget::getXLenVT(), llvm::ShuffleVectorInst::isInsertSubvectorMask(), llvm::RISCVII::MASK_AGNOSTIC, llvm::RISCVII::TAIL_AGNOSTIC, llvm::RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED, and llvm::RISCVISD::VMV_V_V_VL.
Referenced by lowerVECTOR_SHUFFLE().
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Definition at line 3071 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::APFloat::convertFromAPInt(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::RISCVISD::FABS_VL, llvm::ISD::FCEIL, llvm::RISCVISD::FCOPYSIGN_VL, llvm::ISD::FFLOOR, llvm::ISD::FNEARBYINT, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FTRUNC, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstantFP(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getFltSemantics(), llvm::SelectionDAG::getFreeze(), getMaskTypeFor(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVFPRndMode::Invalid, llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), llvm_unreachable, matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), llvm::RISCVISD::SETCC_VL, llvm::ISD::SETOLT, llvm::RISCVISD::SINT_TO_FP_VL, llvm::RISCVISD::VFCVT_RM_X_F_VL, llvm::RISCVISD::VFCVT_RTZ_X_F_VL, llvm::RISCVISD::VFMV_V_F_VL, and llvm::RISCVISD::VFROUND_NOEXCEPT_VL.
Referenced by lowerFTRUNC_FCEIL_FFLOOR_FROUND(), and llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 9407 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLT(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::RISCVTargetLowering::computeVLMAXBounds(), DL, llvm::RISCVVType::encodeSEW(), getAllOnesMask(), llvm::SDNode::getAsZExtVal(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::SelectionDAG::getRegister(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), getVLOperand(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasVInstructions(), II, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::MVT::isScalarInteger(), llvm::SDValue::isUndef(), Operands, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, splatSplitI64WithVL(), llvm::SelectionDAG::SplitScalar(), llvm::RISCVII::TAIL_AGNOSTIC, llvm::ISD::TRUNCATE, llvm::RISCVISD::VMERGE_VL, llvm::RISCVISD::VSLIDE1DOWN_VL, and llvm::RISCVISD::VSLIDE1UP_VL.
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Definition at line 3178 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementTypeToInteger(), llvm::APFloat::convertFromAPInt(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::RISCVISD::FABS_VL, llvm::RISCVISD::FCOPYSIGN_VL, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstantFP(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getFltSemantics(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVFPRndMode::Invalid, llvm::MVT::isFixedLengthVector(), llvm_unreachable, matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), llvm::RISCVISD::SETCC_VL, llvm::ISD::SETOLT, llvm::RISCVISD::STRICT_FADD_VL, llvm::ISD::STRICT_FCEIL, llvm::ISD::STRICT_FFLOOR, llvm::ISD::STRICT_FNEARBYINT, llvm::ISD::STRICT_FROUND, llvm::ISD::STRICT_FROUNDEVEN, llvm::RISCVISD::STRICT_FSETCC_VL, llvm::ISD::STRICT_FTRUNC, llvm::RISCVISD::STRICT_SINT_TO_FP_VL, llvm::RISCVISD::STRICT_VFCVT_RM_X_F_VL, llvm::RISCVISD::STRICT_VFCVT_RTZ_X_F_VL, llvm::RISCVISD::STRICT_VFROUND_NOEXCEPT_VL, and llvm::RISCVISD::VFMV_V_F_VL.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 3307 of file RISCVISelLowering.cpp.
References assert(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::RISCVFPRndMode::DYN, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), and llvm::RISCVISD::VFCVT_RM_X_F_VL.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Match the index vector of a scatter or gather node as the shuffle mask which performs the rearrangement if possible.
Will only match if all lanes are touched, and thus replacing the scatter or gather with a unit strided access and shuffle is legal.
Definition at line 17120 of file RISCVISelLowering.cpp.
References llvm::BitVector::all(), assert(), llvm::CallingConv::C, llvm::SmallVectorBase< Size_T >::empty(), llvm::EVT::getScalarStoreSize(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVectorAllOnes(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::BitVector::set().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Match the index of a gather or scatter operation as an operation with twice the element width and half the number of elements.
This is generally profitable (if legal) because these operations are linear in VL, so even if we cause some extract VTYPE/VL toggles, we still come out ahead.
Definition at line 17155 of file RISCVISelLowering.cpp.
References llvm::CallingConv::C, llvm::EVT::getScalarStoreSize(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVectorAllOnes(), and llvm::Last.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 3036 of file RISCVISelLowering.cpp.
References llvm::RISCVFPRndMode::DYN, llvm::ISD::FCEIL, llvm::ISD::FFLOOR, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FTRUNC, llvm::RISCVFPRndMode::Invalid, llvm::RISCVFPRndMode::RDN, llvm::RISCVFPRndMode::RMM, llvm::RISCVFPRndMode::RNE, llvm::RISCVFPRndMode::RTZ, llvm::RISCVFPRndMode::RUP, llvm::ISD::STRICT_FCEIL, llvm::ISD::STRICT_FFLOOR, llvm::ISD::STRICT_FROUND, llvm::ISD::STRICT_FROUNDEVEN, and llvm::ISD::STRICT_FTRUNC.
Referenced by lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), performFP_TO_INT_SATCombine(), and performFP_TO_INTCombine().
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Definition at line 8151 of file RISCVISelLowering.cpp.
References assert(), CC, llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::ISD::getSetCCSwappedOperands(), llvm::SDValue::getValueType(), LHS, RHS, and llvm::ISD::SETCC.
Referenced by combineSelectToBinOp().
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Definition at line 3510 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::RISCVSubtarget::getXLenVT(), Idx, llvm::ISD::INSERT_SUBVECTOR, llvm::MVT::isFixedLengthVector(), llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLE(), and llvm::RISCVISD::VRGATHER_VX_VL.
Referenced by lowerBUILD_VECTOR(), and llvm::RISCVTargetLowering::PerformDAGCombine().
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According to the property that indexed load/store instructions zero-extend their indices, try to narrow the type of index operand.
Definition at line 14809 of file RISCVISelLowering.cpp.
References llvm::EVT::bitsLT(), llvm::CallingConv::C, llvm::EVT::changeVectorElementType(), llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::countMaxActiveBits(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getRoundIntegerType(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::APInt::getZExtValue(), llvm::SDNode::hasOneUse(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVector(), N, llvm::SDNode::ops(), llvm::PowerOf2Ceil(), llvm::ISD::SHL, llvm::ISD::TRUNCATE, llvm::RISCVISD::VZEXT_VL, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
Definition at line 16235 of file RISCVISelLowering.cpp.
References llvm_unreachable, llvm::RISCVISD::STRICT_VFMADD_VL, llvm::RISCVISD::STRICT_VFMSUB_VL, llvm::RISCVISD::STRICT_VFNMADD_VL, llvm::RISCVISD::STRICT_VFNMSUB_VL, llvm::RISCVISD::VFMADD_VL, llvm::RISCVISD::VFMSUB_VL, llvm::RISCVISD::VFNMADD_VL, and llvm::RISCVISD::VFNMSUB_VL.
Referenced by combineFMA(), combineFMADDSUB(), combineVFMADD_VLWithVFNEG_VL(), and llvm::X86TargetLowering::getNegatedExpression().
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Definition at line 14092 of file RISCVISelLowering.cpp.
References combineAddOfBooleanXor(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBinOpToReduce(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), N, transformAddImmMulImm(), and transformAddShlImm().
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Definition at line 14386 of file RISCVISelLowering.cpp.
References llvm::And, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineDeMorganOfBoolean(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::isOneConstant(), N, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
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Definition at line 16215 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVISD::BREV8, llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::EVT::isScalarInteger(), and N.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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If we have a build_vector where each lane is binop X, C, where C is a constant (but not necessarily the same constant on all lanes), form binop (build_vector x1, x2, ...), (build_vector c1, c2, c3, ..).
We assume that materializing a constant build vector will be no more expensive that performing O(n) binops.
Definition at line 16759 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::TargetLoweringBase::isBinOp(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::SelectionDAG::isSafeToSpeculativelyExecute(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), N, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 16889 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::MVT::changeVectorElementType(), DL, llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::LoadSDNode::getBasePtr(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getNegative(), llvm::GISelAddressing::BaseIndexOffset::getOffset(), llvm::getOffset(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSignedConstant(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getStridedLoadVP(), llvm::SDValue::getValueType(), getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVTargetLowering::isLegalStridedLoadStore(), llvm::ISD::isNormalLoad(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::BaseIndexOffset::match(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::MemoryLocation::UnknownSize.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 16152 of file RISCVISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::RISCVISD::FCVT_W_RV64, llvm::RISCVISD::FCVT_WU_RV64, llvm::RISCVISD::FCVT_X, llvm::RISCVISD::FCVT_XU, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::RISCVFPRndMode::Invalid, llvm::TargetLoweringBase::isTypeLegal(), matchRoundingOp(), N, and llvm::ISD::SETUO.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 16053 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), convertToScalableVector(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::RISCVISD::FCVT_W_RV64, llvm::RISCVISD::FCVT_WU_RV64, llvm::RISCVISD::FCVT_X, llvm::RISCVISD::FCVT_XU, llvm::ISD::FP_TO_SINT, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVFPRndMode::Invalid, llvm::EVT::isFixedLengthVector(), llvm::MVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), matchRoundingOp(), N, llvm::RISCVFPRndMode::RTZ, llvm::ISD::TRUNCATE, llvm::RISCVISD::VFCVT_RM_X_F_VL, llvm::RISCVISD::VFCVT_RM_XU_F_VL, llvm::RISCVISD::VFCVT_RTZ_X_F_VL, and llvm::RISCVISD::VFCVT_RTZ_XU_F_VL.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 16817 of file RISCVISelLowering.cpp.
References llvm::SmallVectorImpl< T >::append(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_VECTOR_ELT, llvm::TargetLoweringBase::isBinOp(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::EVT::isScalableVector(), LHS, N, llvm::SDNode::op_begin(), llvm::SDNode::op_end(), and RHS.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 15968 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::DAG, getExtensionType(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemoryVT(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MachineFunction::getSubtarget(), llvm::Use::getUser(), llvm::LSBaseSDNode::isIndexed(), llvm::MemSDNode::isSimple(), llvm::ISD::LOAD, N, Ptr, tryMemPairCombine(), and llvm::SDNode::uses().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 14758 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, combineBinOpOfZExt(), combineVectorMulToSraBitcast(), DL, expandMul(), llvm::SelectionDAG::getNode(), llvm::isOneOrOneSplat(), llvm::EVT::isVector(), llvm::ISD::MUL, N, llvm::ISD::SUB, and std::swap().
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Definition at line 14460 of file RISCVISelLowering.cpp.
References combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineDeMorganOfBoolean(), combineOrOfCZERO(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), and N.
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Definition at line 16736 of file RISCVISelLowering.cpp.
References foldSelectOfCTTZOrCTLZ(), llvm::RISCVSubtarget::hasConditionalMoveFusion(), N, tryFoldSelectIntoOp(), and useInversedSetcc().
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Definition at line 14878 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, Cond, llvm::APInt::getActiveBits(), llvm::SelectionDAG::getBoolConstant(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::ISD::SETNE, llvm::APInt::sext(), llvm::ISD::SIGN_EXTEND_INREG, and llvm::APInt::trunc().
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Definition at line 14925 of file RISCVISelLowering.cpp.
References llvm::EVT::bitsGE(), llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::countMaxActiveBits(), llvm::RISCVISD::FMV_X_ANYEXTH, llvm::RISCVISD::FMV_X_SIGNEXTH, llvm::SelectionDAG::getNode(), llvm::MVT::getVT(), llvm::RISCVSubtarget::is64Bit(), N, llvm::ISD::SHL, and llvm::RISCVISD::SLLW.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 16327 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::countr_zero(), DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getValueType(), llvm::RISCVSubtarget::getXLenVT(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), N, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, Size, llvm::ISD::SRA, llvm::ISD::SUB, and llvm::SDNode::users().
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Definition at line 14213 of file RISCVISelLowering.cpp.
References combineBinOpOfZExt(), combineSelectAndUse(), combineSubOfBoolean(), combineSubShiftToOrcB(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::hasOneUse(), llvm::isNullConstant(), N, llvm::ISD::SETCC, llvm::ISD::SETLT, and llvm::ISD::SRA.
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Definition at line 14360 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, combineTruncSelectToSMaxUSat(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), N, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 16312 of file RISCVISelLowering.cpp.
References combineOp_VLToVWOp_VL(), combineVFMADD_VLWithVFNEG_VL(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getSelectionDAGInfo(), llvm::SelectionDAGTargetInfo::isTargetStrictFPOpcode(), and N.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 15894 of file RISCVISelLowering.cpp.
References assert(), combineOp_VLToVWOp_VL(), combineVWADDSUBWSelect(), llvm::TargetLowering::DAGCombinerInfo::DAG, N, llvm::RISCVISD::VWADD_W_VL, llvm::RISCVISD::VWADDU_W_VL, llvm::RISCVISD::VWSUB_W_VL, and llvm::RISCVISD::VWSUBU_W_VL.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 14487 of file RISCVISelLowering.cpp.
References llvm::And, llvm::ISD::ANY_EXTEND, CC, combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineSelectAndUseCommutative(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::is64Bit(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::TargetLoweringBase::isOperationLegal(), N, llvm::RISCVISD::ROLW, llvm::ISD::ROTL, llvm::ISD::SETCC, llvm::ISD::SETLT, llvm::ISD::SHL, llvm::RISCVISD::SLLW, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
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Definition at line 9682 of file RISCVISelLowering.cpp.
References convertToScalableVector(), llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getSubtarget(), llvm::MVT::getVectorVT(), Operands, and promoteVCIXScalar().
Referenced by getVCIXISDNodeVOID(), and getVCIXISDNodeWCHAIN().
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Definition at line 9646 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLT(), DL, llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::SDValue::getSimpleValueType(), llvm::MachineFunction::getSubtarget(), llvm::RISCVSubtarget::getXLenVT(), II, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::MVT::isScalarInteger(), Operands, and llvm::ISD::SIGN_EXTEND.
Referenced by processVCIXOperands().
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Definition at line 4299 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BITCAST, DL, llvm::SDNode::getAsZExtVal(), llvm::SelectionDAG::getNode(), getReg(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::Hi, llvm::isAllOnesConstant(), llvm::Lo, llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, llvm::ISD::SRA, and llvm::RISCVISD::VMV_V_X_VL.
Referenced by splatSplitI64WithVL().
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Definition at line 4355 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::Hi, llvm::Lo, splatPartsI64WithVL(), and llvm::SelectionDAG::SplitScalar().
Referenced by lowerScalarSplat(), and lowerVectorIntrinsicScalars().
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Definition at line 6606 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), and llvm::SelectionDAG::SplitVector().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 6535 of file RISCVISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::SelectionDAG::GetSplitDestVTs(), and llvm::SelectionDAG::SplitVector().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 6591 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::Hi, llvm::Lo, llvm::SelectionDAG::SplitEVL(), and llvm::SelectionDAG::SplitVector().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 6560 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::ISD::getVPExplicitVectorLengthIdx(), llvm::ISD::isVPOpcode(), llvm::SelectionDAG::SplitEVL(), and llvm::SelectionDAG::SplitVector().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
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Definition at line 13966 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSignedConstant(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::EVT::isVector(), llvm::ISD::MUL, and N.
Referenced by performADDCombine().
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Definition at line 13816 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::RISCVSubtarget::getXLen(), llvm::SDNode::hasOneUse(), llvm::EVT::isVector(), N, llvm::ISD::SHL, and llvm::RISCVISD::SHL_ADD.
Referenced by performADDCombine().
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Definition at line 2289 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::bit_width(), llvm::CallingConv::C, CC, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::getSetCCSwappedOperands(), llvm::Value::hasOneUse(), llvm::isMask_64(), llvm::isNullConstant(), llvm::isPowerOf2_64(), LHS, llvm::Log2_64(), RHS, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SHL, and std::swap().
Referenced by combine_CC().
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Definition at line 16444 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, Cond, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::EVT::isScalarInteger(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETLT, std::swap(), llvm::Xor, and llvm::ISD::XOR.
Referenced by combine_CC().
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Definition at line 16596 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNeutralElement(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SDValue::getValueType(), N, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, std::swap(), and llvm::ISD::XOR.
Referenced by performSELECTCombine().
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Definition at line 15910 of file RISCVISelLowering.cpp.
References llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MachineMemOperand::getPointerInfo(), llvm::MachineFunction::getSubtarget(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::SDNode::hasPredecessorHelper(), llvm::ISD::LOAD, llvm::SelectionDAG::ReplaceAllUsesWith(), llvm::RISCVISD::TH_LDD, llvm::RISCVISD::TH_LWD, llvm::RISCVISD::TH_LWUD, llvm::RISCVISD::TH_SDD, llvm::RISCVISD::TH_SWD, and llvm::ISD::ZEXTLOAD.
Referenced by performMemPairCombine().
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Try to widen element type to get a new mask value for a better permutation sequence.
This doesn't try to inspect the widened mask for profitability; we speculate the widened form is equal or better. This has the effect of reducing mask constant sizes - allowing cheaper materialization sequences
Definition at line 5313 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getBitcast(), llvm::MVT::getFixedSizeInBits(), llvm::MVT::getFloatingPointVT(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), llvm::MVT::isFloatingPoint(), llvm::TargetLoweringBase::isTypeLegal(), and llvm::widenShuffleMaskElts().
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Definition at line 19856 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVISD::BuildPairF64, llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::SelectionDAG::getCopyFromReg(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getRegInfo(), llvm::CCValAssign::getValVT(), llvm::Hi, llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), and llvm::Lo.
Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().
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Definition at line 19823 of file RISCVISelLowering.cpp.
References llvm::CCValAssign::BCvt, llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::CCValAssign::Full, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MVT::getIntegerVT(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::DataLayout::getPointerSizeInBits(), llvm::EVT::getStoreSize(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, llvm_unreachable, and llvm::ISD::NON_EXTLOAD.
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Definition at line 19760 of file RISCVISelLowering.cpp.
References llvm::RISCVMachineFunctionInfo::addSExt32Register(), llvm::BitWidth, convertLocVTToValVT(), DL, llvm::Function::getArg(), llvm::SelectionDAG::getCopyFromReg(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::Type::getIntegerBitWidth(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MachineFunction::getRegInfo(), llvm::EVT::getSimpleVT(), llvm::RISCVTargetLowering::getSubtarget(), llvm::Value::getType(), llvm::CCValAssign::Indirect, and llvm::Type::isIntegerTy().
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Definition at line 16705 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, CC, Cond, DL, llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::isNullConstant(), llvm::APInt::isPowerOf2(), llvm::EVT::isScalarInteger(), llvm::APInt::isSignedIntN(), LHS, N, RHS, llvm::ISD::SETCC, llvm::ISD::SETEQ, and llvm::ISD::SETNE.
Referenced by performSELECTCombine().
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Definition at line 2585 of file RISCVISelLowering.cpp.
References assert(), llvm::divideCeil(), llvm::RISCVSubtarget::getELen(), llvm::MVT::getFixedSizeInBits(), llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors(), llvm::RISCVSubtarget::getRealMinVLen(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::RISCVSubtarget::hasVInstructionsBF16Minimal(), llvm::RISCVSubtarget::hasVInstructionsF16Minimal(), llvm::RISCVSubtarget::hasVInstructionsF32(), llvm::RISCVSubtarget::hasVInstructionsF64(), llvm::RISCVSubtarget::hasVInstructionsI64(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isPow2VectorType(), llvm::MVT::SimpleTy, and llvm::RISCVSubtarget::useRVVForFixedLengthVectors().
Referenced by combineScalarCTPOPToVCPOP(), and getContainerForFixedLengthVector().
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Definition at line 21974 of file RISCVISelLowering.cpp.
References llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateConstGEP1_32(), llvm::IRBuilderBase::GetInsertBlock(), llvm::IRBuilderBase::getInt8Ty(), llvm::BasicBlock::getModule(), llvm::Intrinsic::getOrInsertDeclaration(), and llvm::Offset.
Referenced by llvm::RISCVTargetLowering::getIRStackGuard().
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Definition at line 10921 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementType(), DL, llvm::SmallVectorTemplateCommon< T, typename >::front(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), I, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SETNE, llvm::SmallVectorBase< Size_T >::size(), and llvm::ISD::ZERO_EXTEND.
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Referenced by combineOp_VLToVWOp_VL().
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Definition at line 22063 of file RISCVISelLowering.cpp.
Referenced by llvm::RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(), and llvm::RISCVTargetLowering::lowerInterleavedLoad().
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Definition at line 22131 of file RISCVISelLowering.cpp.
Referenced by llvm::RISCVTargetLowering::lowerInterleavedStore(), and llvm::RISCVTargetLowering::lowerInterleaveIntrinsicToStore().
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Referenced by llvm::RISCVTargetLowering::isFPImmLegal().
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1.9.6