LLVM  15.0.0git
RISCVSubtarget.cpp
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1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVSubtarget.h"
14 #include "RISCV.h"
15 #include "RISCVCallLowering.h"
16 #include "RISCVFrameLowering.h"
17 #include "RISCVLegalizerInfo.h"
18 #include "RISCVMacroFusion.h"
19 #include "RISCVRegisterBankInfo.h"
20 #include "RISCVTargetMachine.h"
21 #include "llvm/MC/TargetRegistry.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "riscv-subtarget"
27 
28 #define GET_SUBTARGETINFO_TARGET_DESC
29 #define GET_SUBTARGETINFO_CTOR
30 #include "RISCVGenSubtargetInfo.inc"
31 
32 static cl::opt<bool> EnableSubRegLiveness("riscv-enable-subreg-liveness",
33  cl::init(false), cl::Hidden);
34 
36  "riscv-v-vector-bits-max",
37  cl::desc("Assume V extension vector registers are at most this big, "
38  "with zero meaning no maximum size is assumed."),
39  cl::init(0), cl::Hidden);
40 
42  "riscv-v-vector-bits-min",
43  cl::desc("Assume V extension vector registers are at least this big, "
44  "with zero meaning no minimum size is assumed. A value of -1 "
45  "means use Zvl*b extension. This is primarily used to enable "
46  "autovectorization with fixed width vectors."),
47  cl::init(0), cl::Hidden);
48 
50  "riscv-v-fixed-length-vector-lmul-max",
51  cl::desc("The maximum LMUL value to use for fixed length vectors. "
52  "Fractional LMUL values are not supported."),
53  cl::init(8), cl::Hidden);
54 
56  "riscv-disable-using-constant-pool-for-large-ints",
57  cl::desc("Disable using constant pool for large integers."),
58  cl::init(false), cl::Hidden);
59 
61  "riscv-max-build-ints-cost",
62  cl::desc("The maximum cost used for building integers."), cl::init(0),
63  cl::Hidden);
64 
65 void RISCVSubtarget::anchor() {}
66 
68 RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
69  StringRef TuneCPU, StringRef FS,
70  StringRef ABIName) {
71  // Determine default and user-specified characteristics
72  bool Is64Bit = TT.isArch64Bit();
73  if (CPU.empty() || CPU == "generic")
74  CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
75 
76  if (TuneCPU.empty())
77  TuneCPU = CPU;
78 
79  ParseSubtargetFeatures(CPU, TuneCPU, FS);
80  if (Is64Bit) {
81  XLenVT = MVT::i64;
82  XLen = 64;
83  }
84 
85  TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
86  RISCVFeatures::validate(TT, getFeatureBits());
87  return *this;
88 }
89 
91  StringRef TuneCPU, StringRef FS,
92  StringRef ABIName, const TargetMachine &TM)
93  : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
94  UserReservedRegister(RISCV::NUM_TARGET_REGS),
95  FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
96  InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
98  Legalizer.reset(new RISCVLegalizerInfo(*this));
99 
100  auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
101  RegBankInfo.reset(RBI);
103  *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
104 }
105 
107  return CallLoweringInfo.get();
108 }
109 
111  return InstSelector.get();
112 }
113 
115  return Legalizer.get();
116 }
117 
119  return RegBankInfo.get();
120 }
121 
124 }
125 
127  // Loading integer from constant pool needs two instructions (the reason why
128  // the minimum cost is 2): an address calculation instruction and a load
129  // instruction. Usually, address calculation and instructions used for
130  // building integers (addi, slli, etc.) can be done in one cycle, so here we
131  // set the default cost to (LoadLatency + 1) if no threshold is provided.
132  return RISCVMaxBuildIntsCost == 0
133  ? getSchedModel().LoadLatency + 1
134  : std::max<unsigned>(2, RISCVMaxBuildIntsCost);
135 }
136 
139  "Tried to get vector length without Zve or V extension support!");
140  if (RVVVectorBitsMax == 0)
141  return 0;
142 
143  // ZvlLen specifies the minimum required vlen. The upper bound provided by
144  // riscv-v-vector-bits-max should be no less than it.
145  if (RVVVectorBitsMax < (int)ZvlLen)
146  report_fatal_error("riscv-v-vector-bits-max specified is lower "
147  "than the Zvl*b limitation");
148 
149  // FIXME: Change to >= 32 when VLEN = 32 is supported
150  assert(
151  RVVVectorBitsMax >= 64 && RVVVectorBitsMax <= 65536 &&
153  "V or Zve* extension requires vector length to be in the range of 64 to "
154  "65536 and a power of 2!");
156  "Minimum V extension vector length should not be larger than its "
157  "maximum!");
158  unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
159  return PowerOf2Floor((Max < 64 || Max > 65536) ? 0 : Max);
160 }
161 
164  "Tried to get vector length without Zve or V extension support!");
165 
166  if (RVVVectorBitsMin == -1)
167  return ZvlLen;
168 
169  // ZvlLen specifies the minimum required vlen. The lower bound provided by
170  // riscv-v-vector-bits-min should be no less than it.
171  if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < (int)ZvlLen)
172  report_fatal_error("riscv-v-vector-bits-min specified is lower "
173  "than the Zvl*b limitation");
174 
175  // FIXME: Change to >= 32 when VLEN = 32 is supported
176  assert(
177  (RVVVectorBitsMin == 0 ||
178  (RVVVectorBitsMin >= 64 && RVVVectorBitsMin <= 65536 &&
180  "V or Zve* extension requires vector length to be in the range of 64 to "
181  "65536 and a power of 2!");
183  "Minimum V extension vector length should not be larger than its "
184  "maximum!");
185  unsigned Min = RVVVectorBitsMin;
186  if (RVVVectorBitsMax != 0)
188  return PowerOf2Floor((Min < 64 || Min > 65536) ? 0 : Min);
189 }
190 
193  "Tried to get vector length without Zve or V extension support!");
195  "V extension requires a LMUL to be at most 8 and a power of 2!");
196  return PowerOf2Floor(
197  std::max<unsigned>(std::min<unsigned>(RVVVectorLMULMax, 8), 1));
198 }
199 
201  return hasVInstructions() && getMinRVVVectorSizeInBits() != 0;
202 }
203 
206  return EnableSubRegLiveness;
207  // Enable subregister liveness for RVV to better handle LMUL>1 and segment
208  // load/store.
209  return hasVInstructions();
210 }
211 
213  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
214  Mutations.push_back(createRISCVMacroFusionDAGMutation());
215 }
RISCVMacroFusion.h
llvm::RISCVSubtarget::getPostRAMutations
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
Definition: RISCVSubtarget.cpp:212
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::ARM::PredBlockMask::TT
@ TT
llvm::RISCVSubtarget::useRVVForFixedLengthVectors
bool useRVVForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:200
llvm::RISCVSubtarget::getTargetLowering
const RISCVTargetLowering * getTargetLowering() const override
Definition: RISCVSubtarget.h:133
RISCVLegalizerInfo.h
llvm::RISCVRegisterBankInfo
This class provides the information for the target register banks.
Definition: RISCVRegisterBankInfo.h:32
RISCVDisableUsingConstantPoolForLargeInts
static cl::opt< bool > RISCVDisableUsingConstantPoolForLargeInts("riscv-disable-using-constant-pool-for-large-ints", cl::desc("Disable using constant pool for large integers."), cl::init(false), cl::Hidden)
llvm::RISCVSubtarget::hasVInstructions
bool hasVInstructions() const
Definition: RISCVSubtarget.h:223
ErrorHandling.h
llvm::RISCVSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Definition: RISCVSubtarget.cpp:204
llvm::RISCVSubtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: RISCVSubtarget.cpp:106
llvm::RISCVTargetMachine
Definition: RISCVTargetMachine.h:23
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::RISCVSubtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
Definition: RISCVSubtarget.h:238
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::RISCVFeatures::validate
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:97
llvm::RISCVSubtarget::RISCVSubtarget
RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, const TargetMachine &TM)
Definition: RISCVSubtarget.cpp:90
llvm::RISCVCallLowering
Definition: RISCVCallLowering.h:25
llvm::PowerOf2Floor
uint64_t PowerOf2Floor(uint64_t A)
Returns the power of two which is less than or equal to the given value.
Definition: MathExtras.h:722
EnableSubRegLiveness
static cl::opt< bool > EnableSubRegLiveness("riscv-enable-subreg-liveness", cl::init(false), cl::Hidden)
llvm::Legalizer
Definition: Legalizer.h:36
RVVVectorBitsMin
static cl::opt< int > RVVVectorBitsMin("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(0), cl::Hidden)
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:395
llvm::createRISCVInstructionSelector
InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &, RISCVSubtarget &, RISCVRegisterBankInfo &)
Definition: RISCVInstructionSelector.cpp:98
llvm::cl::opt< bool >
llvm::RISCVSubtarget::getMaxRVVVectorSizeInBits
unsigned getMaxRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:137
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:424
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::RISCVSubtarget::getMaxBuildIntsCost
unsigned getMaxBuildIntsCost() const
Definition: RISCVSubtarget.cpp:126
RISCVCallLowering.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::X86AS::FS
@ FS
Definition: X86.h:192
llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors
unsigned getMaxLMULForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:191
RISCV.h
llvm::RISCVSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: RISCVSubtarget.cpp:118
llvm::createRISCVMacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createRISCVMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createRISCVMacroFusionDAGMutation()); to RISCVPassConfig::...
Definition: RISCVMacroFusion.cpp:65
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition: RISCVSubtarget.h:130
RVVVectorLMULMax
static cl::opt< unsigned > RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)
RVVVectorBitsMax
static cl::opt< int > RVVVectorBitsMax("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
llvm::RISCVSubtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: RISCVSubtarget.h:239
llvm::RISCVLegalizerInfo
This class provides the information for the target register banks.
Definition: RISCVLegalizerInfo.h:23
llvm::RISCVABI::computeTargetABI
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
Definition: RISCVBaseInfo.cpp:37
llvm::RISCVSubtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: RISCVSubtarget.cpp:114
RISCVSubtarget.h
RISCVFrameLowering.h
RISCVGenSubtargetInfo
llvm::RISCVSubtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: RISCVSubtarget.h:241
llvm::RISCVSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1180
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
RISCVMaxBuildIntsCost
static cl::opt< unsigned > RISCVMaxBuildIntsCost("riscv-max-build-ints-cost", cl::desc("The maximum cost used for building integers."), cl::init(0), cl::Hidden)
llvm::RISCVSubtarget::getMinRVVVectorSizeInBits
unsigned getMinRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:162
llvm::cl::desc
Definition: CommandLine.h:405
TargetRegistry.h
llvm::CallLowering
Definition: CallLowering.h:44
llvm::RISCVSubtarget::useConstantPoolForLargeInts
bool useConstantPoolForLargeInts() const
Definition: RISCVSubtarget.cpp:122
llvm::RISCVSubtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: RISCVSubtarget.cpp:110
RISCVRegisterBankInfo.h
RISCVTargetMachine.h