LLVM 18.0.0git
RISCVSubtarget.cpp
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1//===-- RISCVSubtarget.cpp - RISC-V Subtarget Information -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISC-V specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVSubtarget.h"
17#include "RISCV.h"
18#include "RISCVFrameLowering.h"
19#include "RISCVMacroFusion.h"
20#include "RISCVTargetMachine.h"
23
24using namespace llvm;
25
26#define DEBUG_TYPE "riscv-subtarget"
27
28#define GET_SUBTARGETINFO_TARGET_DESC
29#define GET_SUBTARGETINFO_CTOR
30#include "RISCVGenSubtargetInfo.inc"
31
33
34#define GET_RISCVTuneInfoTable_IMPL
35#include "RISCVGenSearchableTables.inc"
36} // namespace llvm::RISCVTuneInfoTable
37
38static cl::opt<bool> EnableSubRegLiveness("riscv-enable-subreg-liveness",
39 cl::init(true), cl::Hidden);
40
42 "riscv-v-fixed-length-vector-lmul-max",
43 cl::desc("The maximum LMUL value to use for fixed length vectors. "
44 "Fractional LMUL values are not supported."),
46
48 "riscv-disable-using-constant-pool-for-large-ints",
49 cl::desc("Disable using constant pool for large integers."),
50 cl::init(false), cl::Hidden);
51
53 "riscv-max-build-ints-cost",
54 cl::desc("The maximum cost used for building integers."), cl::init(0),
56
57static cl::opt<bool> UseAA("riscv-use-aa", cl::init(true),
58 cl::desc("Enable the use of AA during codegen."));
59
60void RISCVSubtarget::anchor() {}
61
63RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
64 StringRef TuneCPU, StringRef FS,
65 StringRef ABIName) {
66 // Determine default and user-specified characteristics
67 bool Is64Bit = TT.isArch64Bit();
68 if (CPU.empty() || CPU == "generic")
69 CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
70
71 if (TuneCPU.empty())
72 TuneCPU = CPU;
73
74 TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo(TuneCPU);
75 // If there is no TuneInfo for this CPU, we fail back to generic.
76 if (!TuneInfo)
77 TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo("generic");
78 assert(TuneInfo && "TuneInfo shouldn't be nullptr!");
79
80 ParseSubtargetFeatures(CPU, TuneCPU, FS);
81 TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
82 RISCVFeatures::validate(TT, getFeatureBits());
83 return *this;
84}
85
87 StringRef TuneCPU, StringRef FS,
88 StringRef ABIName, unsigned RVVVectorBitsMin,
89 unsigned RVVVectorBitsMax,
90 const TargetMachine &TM)
91 : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
92 RVVVectorBitsMin(RVVVectorBitsMin), RVVVectorBitsMax(RVVVectorBitsMax),
93 FrameLowering(
94 initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
95 InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
97 Legalizer.reset(new RISCVLegalizerInfo(*this));
98
99 auto *RBI = new RISCVRegisterBankInfo(getHwMode());
100 RegBankInfo.reset(RBI);
102 *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
103}
104
106 return CallLoweringInfo.get();
107}
108
110 return InstSelector.get();
111}
112
114 return Legalizer.get();
115}
116
118 return RegBankInfo.get();
119}
120
123}
124
126 // Loading integer from constant pool needs two instructions (the reason why
127 // the minimum cost is 2): an address calculation instruction and a load
128 // instruction. Usually, address calculation and instructions used for
129 // building integers (addi, slli, etc.) can be done in one cycle, so here we
130 // set the default cost to (LoadLatency + 1) if no threshold is provided.
131 return RISCVMaxBuildIntsCost == 0
132 ? getSchedModel().LoadLatency + 1
133 : std::max<unsigned>(2, RISCVMaxBuildIntsCost);
134}
135
138 "Tried to get vector length without Zve or V extension support!");
139
140 // ZvlLen specifies the minimum required vlen. The upper bound provided by
141 // riscv-v-vector-bits-max should be no less than it.
142 if (RVVVectorBitsMax != 0 && RVVVectorBitsMax < ZvlLen)
143 report_fatal_error("riscv-v-vector-bits-max specified is lower "
144 "than the Zvl*b limitation");
145
146 return RVVVectorBitsMax;
147}
148
151 "Tried to get vector length without Zve or V extension support!");
152
153 if (RVVVectorBitsMin == -1U)
154 return ZvlLen;
155
156 // ZvlLen specifies the minimum required vlen. The lower bound provided by
157 // riscv-v-vector-bits-min should be no less than it.
158 if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
159 report_fatal_error("riscv-v-vector-bits-min specified is lower "
160 "than the Zvl*b limitation");
161
162 return RVVVectorBitsMin;
163}
164
167 "Tried to get vector length without Zve or V extension support!");
169 llvm::has_single_bit<uint32_t>(RVVVectorLMULMax) &&
170 "V extension requires a LMUL to be at most 8 and a power of 2!");
171 return llvm::bit_floor(std::clamp<unsigned>(RVVVectorLMULMax, 1, 8));
172}
173
176}
177
179 // FIXME: Enable subregister liveness by default for RVV to better handle
180 // LMUL>1 and segment load/store.
182}
183
185 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
186 Mutations.push_back(createRISCVMacroFusionDAGMutation());
187}
188
189 /// Enable use of alias analysis during code generation (during MI
190 /// scheduling, DAGCombine, etc.).
191bool RISCVSubtarget::useAA() const { return UseAA; }
static cl::opt< bool > UseAA("aarch64-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM calls to machine code calls.
return InstrInfo
This file declares the targeting of the Machinelegalizer class for RISC-V.
This file declares the targeting of the RegisterBankInfo class for RISC-V.
static cl::opt< bool > EnableSubRegLiveness("riscv-enable-subreg-liveness", cl::init(true), cl::Hidden)
static cl::opt< unsigned > RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)
static cl::opt< bool > UseAA("riscv-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))
static cl::opt< bool > RISCVDisableUsingConstantPoolForLargeInts("riscv-disable-using-constant-pool-for-large-ints", cl::desc("Disable using constant pool for large integers."), cl::init(false), cl::Hidden)
static cl::opt< unsigned > RISCVMaxBuildIntsCost("riscv-max-build-ints-cost", cl::desc("The maximum cost used for building integers."), cl::init(0), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class provides the information for the target register banks.
This class provides the information for the target register banks.
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
const LegalizerInfo * getLegalizerInfo() const override
const RegisterBankInfo * getRegBankInfo() const override
unsigned getMaxLMULForFixedLengthVectors() const
bool useRVVForFixedLengthVectors() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
unsigned getMinRVVVectorSizeInBits() const
std::unique_ptr< InstructionSelector > InstSelector
RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, unsigned RVVVectorLMULMax, const TargetMachine &TM)
const CallLowering * getCallLowering() const override
InstructionSelector * getInstructionSelector() const override
unsigned getMaxBuildIntsCost() const
bool hasVInstructions() const
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
bool useConstantPoolForLargeInts() const
unsigned getMaxRVVVectorSizeInBits() const
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
std::unique_ptr< CallLowering > CallLoweringInfo
const RISCVTargetLowering * getTargetLowering() const override
bool enableSubRegLiveness() const override
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
std::unique_ptr< ScheduleDAGMutation > createRISCVMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createRISCVMacroFusionDAGMutation()); to RISCVPassConfig::...
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
Definition: bit.h:291
InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &TM, RISCVSubtarget &Subtarget, RISCVRegisterBankInfo &RBI)