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26 #define DEBUG_TYPE "riscv-subtarget"
28 #define GET_SUBTARGETINFO_TARGET_DESC
29 #define GET_SUBTARGETINFO_CTOR
30 #include "RISCVGenSubtargetInfo.inc"
36 "riscv-v-vector-bits-max",
37 cl::desc(
"Assume V extension vector registers are at most this big, "
38 "with zero meaning no maximum size is assumed."),
42 "riscv-v-vector-bits-min",
43 cl::desc(
"Assume V extension vector registers are at least this big, "
44 "with zero meaning no minimum size is assumed. A value of -1 "
45 "means use Zvl*b extension. This is primarily used to enable "
46 "autovectorization with fixed width vectors."),
50 "riscv-v-fixed-length-vector-lmul-max",
51 cl::desc(
"The maximum LMUL value to use for fixed length vectors. "
52 "Fractional LMUL values are not supported."),
56 "riscv-disable-using-constant-pool-for-large-ints",
57 cl::desc(
"Disable using constant pool for large integers."),
61 "riscv-max-build-ints-cost",
65 void RISCVSubtarget::anchor() {}
68 RISCVSubtarget::initializeSubtargetDependencies(
const Triple &TT,
StringRef CPU,
72 bool Is64Bit =
TT.isArch64Bit();
73 if (CPU.
empty() || CPU ==
"generic")
74 CPU = Is64Bit ?
"generic-rv64" :
"generic-rv32";
94 UserReservedRegister(RISCV::NUM_TARGET_REGS),
95 FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU,
FS, ABIName)),
96 InstrInfo(*
this), RegInfo(getHwMode()), TLInfo(
TM, *
this) {
133 ? getSchedModel().LoadLatency + 1
139 "Tried to get vector length without Zve or V extension support!");
147 "than the Zvl*b limitation");
153 "V or Zve* extension requires vector length to be in the range of 64 to "
154 "65536 and a power of 2!");
156 "Minimum V extension vector length should not be larger than its "
164 "Tried to get vector length without Zve or V extension support!");
173 "than the Zvl*b limitation");
180 "V or Zve* extension requires vector length to be in the range of 64 to "
181 "65536 and a power of 2!");
183 "Minimum V extension vector length should not be larger than its "
193 "Tried to get vector length without Zve or V extension support!");
195 "V extension requires a LMUL to be at most 8 and a power of 2!");
213 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
const {
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
This is an optimization pass for GlobalISel generic memory operations.
bool useRVVForFixedLengthVectors() const
const RISCVTargetLowering * getTargetLowering() const override
This class provides the information for the target register banks.
static cl::opt< bool > RISCVDisableUsingConstantPoolForLargeInts("riscv-disable-using-constant-pool-for-large-ints", cl::desc("Disable using constant pool for large integers."), cl::init(false), cl::Hidden)
bool hasVInstructions() const
bool enableSubRegLiveness() const override
const CallLowering * getCallLowering() const override
Triple - Helper class for working with autoconf configuration names.
std::unique_ptr< CallLowering > CallLoweringInfo
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, const TargetMachine &TM)
uint64_t PowerOf2Floor(uint64_t A)
Returns the power of two which is less than or equal to the given value.
static cl::opt< bool > EnableSubRegLiveness("riscv-enable-subreg-liveness", cl::init(false), cl::Hidden)
static cl::opt< int > RVVVectorBitsMin("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(0), cl::Hidden)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
int getNumOccurrences() const
InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &, RISCVSubtarget &, RISCVRegisterBankInfo &)
unsigned getMaxRVVVectorSizeInBits() const
Holds all the information related to register banks.
Provides the logic to select generic machine instructions.
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
unsigned getMaxBuildIntsCost() const
initializer< Ty > init(const Ty &Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
unsigned getMaxLMULForFixedLengthVectors() const
const RegisterBankInfo * getRegBankInfo() const override
std::unique_ptr< ScheduleDAGMutation > createRISCVMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createRISCVMacroFusionDAGMutation()); to RISCVPassConfig::...
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
StringRef - Represent a constant reference to a string, i.e.
Analysis the ScalarEvolution expression for r is this
const RISCVRegisterInfo * getRegisterInfo() const override
static cl::opt< unsigned > RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)
static cl::opt< int > RVVVectorBitsMax("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
std::unique_ptr< InstructionSelector > InstSelector
This class provides the information for the target register banks.
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< RegisterBankInfo > RegBankInfo
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
const char LLVMTargetMachineRef TM
static cl::opt< unsigned > RISCVMaxBuildIntsCost("riscv-max-build-ints-cost", cl::desc("The maximum cost used for building integers."), cl::init(0), cl::Hidden)
unsigned getMinRVVVectorSizeInBits() const
bool useConstantPoolForLargeInts() const
InstructionSelector * getInstructionSelector() const override