26#define DEBUG_TYPE "riscv-subtarget"
28#define GET_SUBTARGETINFO_TARGET_DESC
29#define GET_SUBTARGETINFO_CTOR
30#include "RISCVGenSubtargetInfo.inc"
36 "riscv-v-fixed-length-vector-lmul-max",
37 cl::desc(
"The maximum LMUL value to use for fixed length vectors. "
38 "Fractional LMUL values are not supported."),
42 "riscv-disable-using-constant-pool-for-large-ints",
43 cl::desc(
"Disable using constant pool for large integers."),
47 "riscv-max-build-ints-cost",
51void RISCVSubtarget::anchor() {}
54RISCVSubtarget::initializeSubtargetDependencies(
const Triple &TT,
StringRef CPU,
58 bool Is64Bit =
TT.isArch64Bit();
59 if (CPU.
empty() || CPU ==
"generic")
60 CPU = Is64Bit ?
"generic-rv64" :
"generic-rv32";
78 StringRef ABIName,
unsigned RVVVectorBitsMin,
79 unsigned RVVVectorBitsMax,
82 RVVVectorBitsMin(RVVVectorBitsMin), RVVVectorBitsMax(RVVVectorBitsMax),
84 initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
85 InstrInfo(*this), RegInfo(getHwMode()), TLInfo(
TM, *this) {
122 ? getSchedModel().LoadLatency + 1
128 "Tried to get vector length without Zve or V extension support!");
132 if (RVVVectorBitsMax != 0 && RVVVectorBitsMax < ZvlLen)
134 "than the Zvl*b limitation");
136 return RVVVectorBitsMax;
141 "Tried to get vector length without Zve or V extension support!");
143 if (RVVVectorBitsMin == -1U)
148 if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
150 "than the Zvl*b limitation");
152 return RVVVectorBitsMin;
157 "Tried to get vector length without Zve or V extension support!");
159 "V extension requires a LMUL to be at most 8 and a power of 2!");
174 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
const {
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for RISCV.
This file declares the targeting of the RegisterBankInfo class for RISCV.
static cl::opt< bool > EnableSubRegLiveness("riscv-enable-subreg-liveness", cl::init(false), cl::Hidden)
static cl::opt< unsigned > RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)
static cl::opt< bool > RISCVDisableUsingConstantPoolForLargeInts("riscv-disable-using-constant-pool-for-large-ints", cl::desc("Disable using constant pool for large integers."), cl::init(false), cl::Hidden)
static cl::opt< unsigned > RISCVMaxBuildIntsCost("riscv-max-build-ints-cost", cl::desc("The maximum cost used for building integers."), cl::init(0), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Provides the logic to select generic machine instructions.
This class provides the information for the target register banks.
This class provides the information for the target register banks.
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
const LegalizerInfo * getLegalizerInfo() const override
const RegisterBankInfo * getRegBankInfo() const override
unsigned getMaxLMULForFixedLengthVectors() const
bool useRVVForFixedLengthVectors() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
unsigned getMinRVVVectorSizeInBits() const
std::unique_ptr< InstructionSelector > InstSelector
RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, unsigned RVVVectorLMULMax, const TargetMachine &TM)
const CallLowering * getCallLowering() const override
InstructionSelector * getInstructionSelector() const override
unsigned getMaxBuildIntsCost() const
bool hasVInstructions() const
bool useConstantPoolForLargeInts() const
unsigned getMaxRVVVectorSizeInBits() const
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
const RISCVRegisterInfo * getRegisterInfo() const override
std::unique_ptr< CallLowering > CallLoweringInfo
const RISCVTargetLowering * getTargetLowering() const override
bool enableSubRegLiveness() const override
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
Primary interface to the complete machine description for the target machine.
Triple - Helper class for working with autoconf configuration names.
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
std::unique_ptr< ScheduleDAGMutation > createRISCVMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createRISCVMacroFusionDAGMutation()); to RISCVPassConfig::...
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &TM, RISCVSubtarget &Subtarget, RISCVRegisterBankInfo &RBI)