LLVM 18.0.0git
RISCVLegalizerInfo.h
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1//===-- RISCVLegalizerInfo.h ------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the Machinelegalizer class for RISC-V.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINELEGALIZER_H
14#define LLVM_LIB_TARGET_RISCV_RISCVMACHINELEGALIZER_H
15
17
18namespace llvm {
19
20class RISCVSubtarget;
21
22/// This class provides the information for the target register banks.
24public:
26
27 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
28};
29} // end namespace llvm
30#endif
IRTranslator LLVM IR MI
Interface for Targets to specify which operations they can successfully select and how the others sho...
Representation of each machine instruction.
Definition: MachineInstr.h:68
This class provides the information for the target register banks.
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override
Called for instructions with the Custom LegalizationAction.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18