LLVM 17.0.0git
LegalizerHelper.h
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1//== llvm/CodeGen/GlobalISel/LegalizerHelper.h ---------------- -*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file A pass to convert the target-illegal operations created by IR -> MIR
10/// translation into ones the target expects to be able to select. This may
11/// occur in multiple phases, for example G_ADD <2 x i8> -> G_ADD <2 x i16> ->
12/// G_ADD <4 x i16>.
13///
14/// The LegalizerHelper class is where most of the work happens, and is
15/// designed to be callable from other passes that find themselves with an
16/// illegal instruction.
17//
18//===----------------------------------------------------------------------===//
19
20#ifndef LLVM_CODEGEN_GLOBALISEL_LEGALIZERHELPER_H
21#define LLVM_CODEGEN_GLOBALISEL_LEGALIZERHELPER_H
22
27
28namespace llvm {
29// Forward declarations.
30class APInt;
31class GAnyLoad;
32class GLoadStore;
33class GStore;
34class GenericMachineInstr;
35class MachineFunction;
36class MachineIRBuilder;
37class MachineInstr;
38class MachineInstrBuilder;
39struct MachinePointerInfo;
40template <typename T> class SmallVectorImpl;
41class LegalizerInfo;
42class MachineRegisterInfo;
43class GISelChangeObserver;
44class LostDebugLocObserver;
45class TargetLowering;
46
48public:
49 /// Expose MIRBuilder so clients can set their own RecordInsertInstruction
50 /// functions
52
53 /// To keep track of changes made by the LegalizerHelper.
55
56private:
58 const LegalizerInfo &LI;
59 const TargetLowering &TLI;
61
62public:
64 /// Instruction was already legal and no change was made to the
65 /// MachineFunction.
67
68 /// Instruction has been legalized and the MachineFunction changed.
70
71 /// Some kind of error has occurred and we could not legalize this
72 /// instruction.
74 };
75
76 /// Expose LegalizerInfo so the clients can re-use.
77 const LegalizerInfo &getLegalizerInfo() const { return LI; }
78 const TargetLowering &getTargetLowering() const { return TLI; }
79 GISelKnownBits *getKnownBits() const { return KB; }
80
85 GISelKnownBits *KB = nullptr);
86
87 /// Replace \p MI by a sequence of legal instructions that can implement the
88 /// same operation. Note that this means \p MI may be deleted, so any iterator
89 /// steps should be performed before calling this function. \p Helper should
90 /// be initialized to the MachineFunction containing \p MI.
91 ///
92 /// Considered as an opaque blob, the legal code will use and define the same
93 /// registers as \p MI.
95 LostDebugLocObserver &LocObserver);
96
97 /// Legalize an instruction by emiting a runtime library call instead.
99
100 /// Legalize an instruction by reducing the width of the underlying scalar
101 /// type.
102 LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
103
104 /// Legalize an instruction by performing the operation on a wider scalar type
105 /// (for example a 16-bit addition can be safely performed at 32-bits
106 /// precision, ignoring the unused bits).
107 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
108
109 /// Legalize an instruction by replacing the value type
110 LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
111
112 /// Legalize an instruction by splitting it into simpler parts, hopefully
113 /// understood by the target.
114 LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
115
116 /// Legalize a vector instruction by splitting into multiple components, each
117 /// acting on the same scalar type as the original but with fewer elements.
119 LLT NarrowTy);
120
121 /// Legalize a vector instruction by increasing the number of vector elements
122 /// involved and ignoring the added elements later.
124 LLT MoreTy);
125
126 /// Cast the given value to an LLT::scalar with an equivalent size. Returns
127 /// the register to use if an instruction was inserted. Returns the original
128 /// register if no coercion was necessary.
129 //
130 // This may also fail and return Register() if there is no legal way to cast.
132
133 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
134 /// Use by extending the operand's type to \p WideTy using the specified \p
135 /// ExtOpcode for the extension instruction, and replacing the vreg of the
136 /// operand in place.
137 void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
138 unsigned ExtOpcode);
139
140 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
141 /// Use by truncating the operand's type to \p NarrowTy using G_TRUNC, and
142 /// replacing the vreg of the operand in place.
143 void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx);
144
145 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
146 /// Def by extending the operand's type to \p WideTy and truncating it back
147 /// with the \p TruncOpcode, and replacing the vreg of the operand in place.
148 void widenScalarDst(MachineInstr &MI, LLT WideTy, unsigned OpIdx = 0,
149 unsigned TruncOpcode = TargetOpcode::G_TRUNC);
150
151 // Legalize a single operand \p OpIdx of the machine instruction \p MI as a
152 // Def by truncating the operand's type to \p NarrowTy, replacing in place and
153 // extending back with \p ExtOpcode.
154 void narrowScalarDst(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx,
155 unsigned ExtOpcode);
156 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
157 /// Def by performing it with additional vector elements and extracting the
158 /// result elements, and replacing the vreg of the operand in place.
159 void moreElementsVectorDst(MachineInstr &MI, LLT MoreTy, unsigned OpIdx);
160
161 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
162 /// Use by producing a vector with undefined high elements, extracting the
163 /// original vector type, and replacing the vreg of the operand in place.
164 void moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, unsigned OpIdx);
165
166 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
167 /// use by inserting a G_BITCAST to \p CastTy
168 void bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx);
169
170 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
171 /// def by inserting a G_BITCAST from \p CastTy
172 void bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx);
173
174private:
176 widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
178 widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
180 widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
182 widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
183 LegalizeResult widenScalarAddSubOverflow(MachineInstr &MI, unsigned TypeIdx,
184 LLT WideTy);
185 LegalizeResult widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx,
186 LLT WideTy);
187 LegalizeResult widenScalarMulo(MachineInstr &MI, unsigned TypeIdx,
188 LLT WideTy);
189
190 /// Helper function to split a wide generic register into bitwise blocks with
191 /// the given Type (which implies the number of blocks needed). The generic
192 /// registers created are appended to Ops, starting at bit 0 of Reg.
193 void extractParts(Register Reg, LLT Ty, int NumParts,
195
196 /// Version which handles irregular splits.
197 bool extractParts(Register Reg, LLT RegTy, LLT MainTy,
198 LLT &LeftoverTy,
200 SmallVectorImpl<Register> &LeftoverVRegs);
201
202 /// Version which handles irregular sub-vector splits.
203 void extractVectorParts(Register Reg, unsigned NumElst,
205
206 /// Helper function to build a wide generic register \p DstReg of type \p
207 /// RegTy from smaller parts. This will produce a G_MERGE_VALUES,
208 /// G_BUILD_VECTOR, G_CONCAT_VECTORS, or sequence of G_INSERT as appropriate
209 /// for the types.
210 ///
211 /// \p PartRegs must be registers of type \p PartTy.
212 ///
213 /// If \p ResultTy does not evenly break into \p PartTy sized pieces, the
214 /// remainder must be specified with \p LeftoverRegs of type \p LeftoverTy.
215 void insertParts(Register DstReg, LLT ResultTy,
216 LLT PartTy, ArrayRef<Register> PartRegs,
217 LLT LeftoverTy = LLT(), ArrayRef<Register> LeftoverRegs = {});
218
219 /// Merge \p PartRegs with different types into \p DstReg.
220 void mergeMixedSubvectors(Register DstReg, ArrayRef<Register> PartRegs);
221
222 void appendVectorElts(SmallVectorImpl<Register> &Elts, Register Reg);
223
224 /// Unmerge \p SrcReg into smaller sized values, and append them to \p
225 /// Parts. The elements of \p Parts will be the greatest common divisor type
226 /// of \p DstTy, \p NarrowTy and the type of \p SrcReg. This will compute and
227 /// return the GCD type.
228 LLT extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy,
229 LLT NarrowTy, Register SrcReg);
230
231 /// Unmerge \p SrcReg into \p GCDTy typed registers. This will append all of
232 /// the unpacked registers to \p Parts. This version is if the common unmerge
233 /// type is already known.
234 void extractGCDType(SmallVectorImpl<Register> &Parts, LLT GCDTy,
235 Register SrcReg);
236
237 /// Produce a merge of values in \p VRegs to define \p DstReg. Perform a merge
238 /// from the least common multiple type, and convert as appropriate to \p
239 /// DstReg.
240 ///
241 /// \p VRegs should each have type \p GCDTy. This type should be greatest
242 /// common divisor type of \p DstReg, \p NarrowTy, and an undetermined source
243 /// type.
244 ///
245 /// \p NarrowTy is the desired result merge source type. If the source value
246 /// needs to be widened to evenly cover \p DstReg, inserts high bits
247 /// corresponding to the extension opcode \p PadStrategy.
248 ///
249 /// \p VRegs will be cleared, and the the result \p NarrowTy register pieces
250 /// will replace it. Returns The complete LCMTy that \p VRegs will cover when
251 /// merged.
252 LLT buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy,
253 SmallVectorImpl<Register> &VRegs,
254 unsigned PadStrategy = TargetOpcode::G_ANYEXT);
255
256 /// Merge the values in \p RemergeRegs to an \p LCMTy typed value. Extract the
257 /// low bits into \p DstReg. This is intended to use the outputs from
258 /// buildLCMMergePieces after processing.
259 void buildWidenedRemergeToDst(Register DstReg, LLT LCMTy,
260 ArrayRef<Register> RemergeRegs);
261
262 /// Perform generic multiplication of values held in multiple registers.
263 /// Generated instructions use only types NarrowTy and i1.
264 /// Destination can be same or two times size of the source.
265 void multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
266 ArrayRef<Register> Src1Regs,
267 ArrayRef<Register> Src2Regs, LLT NarrowTy);
268
269 void changeOpcode(MachineInstr &MI, unsigned NewOpcode);
270
271 LegalizeResult tryNarrowPow2Reduction(MachineInstr &MI, Register SrcReg,
272 LLT SrcTy, LLT NarrowTy,
273 unsigned ScalarOpc);
274
275 // Memcpy family legalization helpers.
276 LegalizeResult lowerMemset(MachineInstr &MI, Register Dst, Register Val,
277 uint64_t KnownLen, Align Alignment,
278 bool IsVolatile);
279 LegalizeResult lowerMemcpyInline(MachineInstr &MI, Register Dst, Register Src,
280 uint64_t KnownLen, Align DstAlign,
281 Align SrcAlign, bool IsVolatile);
282 LegalizeResult lowerMemcpy(MachineInstr &MI, Register Dst, Register Src,
283 uint64_t KnownLen, uint64_t Limit, Align DstAlign,
284 Align SrcAlign, bool IsVolatile);
285 LegalizeResult lowerMemmove(MachineInstr &MI, Register Dst, Register Src,
286 uint64_t KnownLen, Align DstAlign, Align SrcAlign,
287 bool IsVolatile);
288
289public:
290 /// Return the alignment to use for a stack temporary object with the given
291 /// type.
292 Align getStackTemporaryAlignment(LLT Type, Align MinAlign = Align()) const;
293
294 /// Create a stack temporary based on the size in bytes and the alignment
295 MachineInstrBuilder createStackTemporary(TypeSize Bytes, Align Alignment,
296 MachinePointerInfo &PtrInfo);
297
298 /// Get a pointer to vector element \p Index located in memory for a vector of
299 /// type \p VecTy starting at a base address of \p VecPtr. If \p Index is out
300 /// of bounds the returned pointer is unspecified, but will be within the
301 /// vector bounds.
302 Register getVectorElementPointer(Register VecPtr, LLT VecTy, Register Index);
303
304 /// Handles most opcodes. Split \p MI into same instruction on sub-vectors or
305 /// scalars with \p NumElts elements (1 for scalar). Supports uneven splits:
306 /// there can be leftover sub-vector with fewer then \p NumElts or a leftover
307 /// scalar. To avoid this use moreElements first and set MI number of elements
308 /// to multiple of \p NumElts. Non-vector operands that should be used on all
309 /// sub-instructions without split are listed in \p NonVecOpIndices.
311 GenericMachineInstr &MI, unsigned NumElts,
312 std::initializer_list<unsigned> NonVecOpIndices = {});
313
314 LegalizeResult fewerElementsVectorPhi(GenericMachineInstr &MI,
315 unsigned NumElts);
316
317 LegalizeResult moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
318 LLT MoreTy);
319 LegalizeResult moreElementsVectorShuffle(MachineInstr &MI, unsigned TypeIdx,
320 LLT MoreTy);
321
323 unsigned TypeIdx,
324 LLT NarrowTy);
325 LegalizeResult fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx,
326 LLT NarrowTy);
328 unsigned TypeIdx,
329 LLT NarrowTy);
330
331 /// Equalize source and destination vector sizes of G_SHUFFLE_VECTOR.
333
334 LegalizeResult reduceLoadStoreWidth(GLoadStore &MI, unsigned TypeIdx,
335 LLT NarrowTy);
336
337 LegalizeResult narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
338 LLT HalfTy, LLT ShiftAmtTy);
339
341 unsigned TypeIdx, LLT NarrowTy);
342
343 LegalizeResult fewerElementsVectorShuffle(MachineInstr &MI, unsigned TypeIdx,
344 LLT NarrowTy);
345
346 LegalizeResult narrowScalarShift(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
347 LegalizeResult narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx,
348 LLT NarrowTy);
349 LegalizeResult narrowScalarMul(MachineInstr &MI, LLT Ty);
350 LegalizeResult narrowScalarFPTOI(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
351 LegalizeResult narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
352 LegalizeResult narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
353
354 LegalizeResult narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
355 LegalizeResult narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
356 LegalizeResult narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
357 LegalizeResult narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
358 LegalizeResult narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
359 LegalizeResult narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
360 LegalizeResult narrowScalarFLDEXP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
361
362 /// Perform Bitcast legalize action on G_EXTRACT_VECTOR_ELT.
363 LegalizeResult bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx,
364 LLT CastTy);
365
366 /// Perform Bitcast legalize action on G_INSERT_VECTOR_ELT.
367 LegalizeResult bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx,
368 LLT CastTy);
369
370 LegalizeResult lowerFConstant(MachineInstr &MI);
371 LegalizeResult lowerBitcast(MachineInstr &MI);
372 LegalizeResult lowerLoad(GAnyLoad &MI);
374 LegalizeResult lowerBitCount(MachineInstr &MI);
377 LegalizeResult lowerFunnelShift(MachineInstr &MI);
379 LegalizeResult lowerRotate(MachineInstr &MI);
380
382 LegalizeResult lowerUITOFP(MachineInstr &MI);
383 LegalizeResult lowerSITOFP(MachineInstr &MI);
384 LegalizeResult lowerFPTOUI(MachineInstr &MI);
385 LegalizeResult lowerFPTOSI(MachineInstr &MI);
386
388 LegalizeResult lowerFPTRUNC(MachineInstr &MI);
389 LegalizeResult lowerFPOWI(MachineInstr &MI);
390
391 LegalizeResult lowerISFPCLASS(MachineInstr &MI);
392
393 LegalizeResult lowerMinMax(MachineInstr &MI);
394 LegalizeResult lowerFCopySign(MachineInstr &MI);
395 LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI);
396 LegalizeResult lowerFMad(MachineInstr &MI);
398 LegalizeResult lowerFFloor(MachineInstr &MI);
399 LegalizeResult lowerMergeValues(MachineInstr &MI);
400 LegalizeResult lowerUnmergeValues(MachineInstr &MI);
402 LegalizeResult lowerShuffleVector(MachineInstr &MI);
403 LegalizeResult lowerDynStackAlloc(MachineInstr &MI);
404 LegalizeResult lowerExtract(MachineInstr &MI);
405 LegalizeResult lowerInsert(MachineInstr &MI);
406 LegalizeResult lowerSADDO_SSUBO(MachineInstr &MI);
409 LegalizeResult lowerShlSat(MachineInstr &MI);
410 LegalizeResult lowerBswap(MachineInstr &MI);
411 LegalizeResult lowerBitreverse(MachineInstr &MI);
413 LegalizeResult lowerSMULH_UMULH(MachineInstr &MI);
414 LegalizeResult lowerSelect(MachineInstr &MI);
415 LegalizeResult lowerDIVREM(MachineInstr &MI);
416 LegalizeResult lowerAbsToAddXor(MachineInstr &MI);
417 LegalizeResult lowerAbsToMaxNeg(MachineInstr &MI);
419 LegalizeResult lowerMemcpyInline(MachineInstr &MI);
420 LegalizeResult lowerMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
421};
422
423/// Helper function that creates a libcall to the given \p Name using the given
424/// calling convention \p CC.
426createLibcall(MachineIRBuilder &MIRBuilder, const char *Name,
427 const CallLowering::ArgInfo &Result,
428 ArrayRef<CallLowering::ArgInfo> Args, CallingConv::ID CC);
429
430/// Helper function that creates the given libcall.
432createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
433 const CallLowering::ArgInfo &Result,
434 ArrayRef<CallLowering::ArgInfo> Args);
435
436/// Create a libcall to memcpy et al.
438createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
439 MachineInstr &MI, LostDebugLocObserver &LocObserver);
440
441} // End namespace llvm.
442
443#endif
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
This file describes how to lower LLVM calls to machine code calls.
std::string Name
Provides analysis for querying information about KnownBits during GISel passes.
IRTranslator LLVM IR MI
unsigned Reg
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Abstract class that contains various methods for clients to notify about changes.
LegalizeResult lowerShlSat(MachineInstr &MI)
LegalizeResult narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult lowerFPTRUNC_F64_TO_F16(MachineInstr &MI)
LegalizeResult equalizeVectorShuffleLengths(MachineInstr &MI)
Equalize source and destination vector sizes of G_SHUFFLE_VECTOR.
LegalizeResult bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx, LLT CastTy)
Perform Bitcast legalize action on G_INSERT_VECTOR_ELT.
LegalizeResult lowerSITOFP(MachineInstr &MI)
LegalizeResult lowerDynStackAlloc(MachineInstr &MI)
LegalizeResult lowerBitCount(MachineInstr &MI)
LegalizeResult narrowScalarMul(MachineInstr &MI, LLT Ty)
LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI)
LegalizeResult lowerIntrinsicRound(MachineInstr &MI)
void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx, unsigned ExtOpcode)
Legalize a single operand OpIdx of the machine instruction MI as a Use by extending the operand's typ...
LegalizeResult moreElementsVectorShuffle(MachineInstr &MI, unsigned TypeIdx, LLT MoreTy)
LegalizeResult lowerSMULH_UMULH(MachineInstr &MI)
LegalizeResult lowerLoad(GAnyLoad &MI)
LegalizeResult fewerElementsVectorShuffle(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
LegalizeResult lowerAbsToAddXor(MachineInstr &MI)
void moreElementsVectorDst(MachineInstr &MI, LLT MoreTy, unsigned OpIdx)
Legalize a single operand OpIdx of the machine instruction MI as a Def by performing it with addition...
LegalizeResult lowerFConstant(MachineInstr &MI)
LegalizeResult narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult lowerBitreverse(MachineInstr &MI)
LegalizeResult narrowScalarShift(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult lowerExtractInsertVectorElt(MachineInstr &MI)
Lower a vector extract or insert by writing the vector to a stack temporary and reloading the element...
LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx, LLT MoreTy)
Legalize a vector instruction by increasing the number of vector elements involved and ignoring the a...
LegalizeResult lowerFunnelShiftWithInverse(MachineInstr &MI)
LegalizeResult lowerAbsToMaxNeg(MachineInstr &MI)
LegalizeResult lowerStore(GStore &MI)
LegalizeResult lowerSADDO_SSUBO(MachineInstr &MI)
MachineInstrBuilder createStackTemporary(TypeSize Bytes, Align Alignment, MachinePointerInfo &PtrInfo)
Create a stack temporary based on the size in bytes and the alignment.
void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx)
Legalize a single operand OpIdx of the machine instruction MI as a Use by truncating the operand's ty...
LegalizeResult fewerElementsVectorPhi(GenericMachineInstr &MI, unsigned NumElts)
LegalizeResult lowerFPTOUI(MachineInstr &MI)
const TargetLowering & getTargetLowering() const
LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
Legalize an instruction by reducing the width of the underlying scalar type.
LegalizeResult narrowScalarFPTOI(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult lowerUnmergeValues(MachineInstr &MI)
LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
Legalize an instruction by replacing the value type.
LegalizeResult lowerBitcast(MachineInstr &MI)
LegalizeResult lowerMinMax(MachineInstr &MI)
LegalizeResult lowerFunnelShiftAsShifts(MachineInstr &MI)
LegalizeResult lowerInsert(MachineInstr &MI)
LegalizeResult lowerReadWriteRegister(MachineInstr &MI)
LegalizeResult lowerExtract(MachineInstr &MI)
LegalizeResult narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt, LLT HalfTy, LLT ShiftAmtTy)
LegalizeResult lowerISFPCLASS(MachineInstr &MI)
LegalizeResult lowerAddSubSatToMinMax(MachineInstr &MI)
LegalizeResult lowerFPOWI(MachineInstr &MI)
LegalizeResult narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult lowerVectorReduction(MachineInstr &MI)
const LegalizerInfo & getLegalizerInfo() const
Expose LegalizerInfo so the clients can re-use.
LegalizeResult reduceLoadStoreWidth(GLoadStore &MI, unsigned TypeIdx, LLT NarrowTy)
LegalizeResult fewerElementsVectorMultiEltType(GenericMachineInstr &MI, unsigned NumElts, std::initializer_list< unsigned > NonVecOpIndices={})
Handles most opcodes.
LegalizeResult narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
@ Legalized
Instruction has been legalized and the MachineFunction changed.
@ AlreadyLegal
Instruction was already legal and no change was made to the MachineFunction.
@ UnableToLegalize
Some kind of error has occurred and we could not legalize this instruction.
LegalizeResult moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, LLT MoreTy)
LegalizeResult lowerU64ToF32BitOps(MachineInstr &MI)
LegalizeResult lowerFCopySign(MachineInstr &MI)
LegalizeResult lowerRotateWithReverseRotate(MachineInstr &MI)
LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
Legalize an instruction by splitting it into simpler parts, hopefully understood by the target.
LegalizeResult lowerFunnelShift(MachineInstr &MI)
LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
Legalize a vector instruction by splitting into multiple components, each acting on the same scalar t...
GISelChangeObserver & Observer
To keep track of changes made by the LegalizerHelper.
void bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx)
Legalize a single operand OpIdx of the machine instruction MI as a def by inserting a G_BITCAST from ...
LegalizeResult lowerFPTRUNC(MachineInstr &MI)
LegalizeResult lowerFMad(MachineInstr &MI)
LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy)
Legalize an instruction by performing the operation on a wider scalar type (for example a 16-bit addi...
LegalizeResult lowerAddSubSatToAddoSubo(MachineInstr &MI)
LegalizeResult narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult lowerFFloor(MachineInstr &MI)
LegalizeResult narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult lowerFPTOSI(MachineInstr &MI)
LegalizeResult lowerUITOFP(MachineInstr &MI)
LegalizeResult lowerShuffleVector(MachineInstr &MI)
LegalizeResult fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
LegalizeResult lowerMergeValues(MachineInstr &MI)
LegalizeResult fewerElementsVectorUnmergeValues(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
void moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, unsigned OpIdx)
Legalize a single operand OpIdx of the machine instruction MI as a Use by producing a vector with und...
LegalizeResult bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx, LLT CastTy)
Perform Bitcast legalize action on G_EXTRACT_VECTOR_ELT.
LegalizeResult lowerRotate(MachineInstr &MI)
LegalizeResult lowerMemCpyFamily(MachineInstr &MI, unsigned MaxLen=0)
Register coerceToScalar(Register Val)
Cast the given value to an LLT::scalar with an equivalent size.
LegalizeResult lowerDIVREM(MachineInstr &MI)
GISelKnownBits * getKnownBits() const
LegalizeResult lowerSelect(MachineInstr &MI)
LegalizeResult narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult narrowScalarFLDEXP(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
void bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx)
Legalize a single operand OpIdx of the machine instruction MI as a use by inserting a G_BITCAST to Ca...
void narrowScalarDst(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx, unsigned ExtOpcode)
LegalizeResult fewerElementsVectorReductions(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
LegalizeResult fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
LegalizeResult narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
MachineIRBuilder & MIRBuilder
Expose MIRBuilder so clients can set their own RecordInsertInstruction functions.
LegalizeResult lowerBswap(MachineInstr &MI)
Register getVectorElementPointer(Register VecPtr, LLT VecTy, Register Index)
Get a pointer to vector element Index located in memory for a vector of type VecTy starting at a base...
LegalizeResult narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
Align getStackTemporaryAlignment(LLT Type, Align MinAlign=Align()) const
Return the alignment to use for a stack temporary object with the given type.
void widenScalarDst(MachineInstr &MI, LLT WideTy, unsigned OpIdx=0, unsigned TruncOpcode=TargetOpcode::G_TRUNC)
Legalize a single operand OpIdx of the machine instruction MI as a Def by extending the operand's typ...
LegalizeResult legalizeInstrStep(MachineInstr &MI, LostDebugLocObserver &LocObserver)
Replace MI by a sequence of legal instructions that can implement the same operation.
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
LegalizerHelper::LegalizeResult createLibcall(MachineIRBuilder &MIRBuilder, const char *Name, const CallLowering::ArgInfo &Result, ArrayRef< CallLowering::ArgInfo > Args, CallingConv::ID CC)
Helper function that creates a libcall to the given Name using the given calling convention CC.
LegalizerHelper::LegalizeResult createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstr &MI, LostDebugLocObserver &LocObserver)
Create a libcall to memcpy et al.
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:407