LLVM 19.0.0git
LegalizerHelper.h
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1//== llvm/CodeGen/GlobalISel/LegalizerHelper.h ---------------- -*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file A pass to convert the target-illegal operations created by IR -> MIR
10/// translation into ones the target expects to be able to select. This may
11/// occur in multiple phases, for example G_ADD <2 x i8> -> G_ADD <2 x i16> ->
12/// G_ADD <4 x i16>.
13///
14/// The LegalizerHelper class is where most of the work happens, and is
15/// designed to be callable from other passes that find themselves with an
16/// illegal instruction.
17//
18//===----------------------------------------------------------------------===//
19
20#ifndef LLVM_CODEGEN_GLOBALISEL_LEGALIZERHELPER_H
21#define LLVM_CODEGEN_GLOBALISEL_LEGALIZERHELPER_H
22
27
28namespace llvm {
29// Forward declarations.
30class APInt;
31class GAnyLoad;
32class GLoadStore;
33class GStore;
34class GenericMachineInstr;
35class MachineFunction;
36class MachineIRBuilder;
37class MachineInstr;
38class MachineInstrBuilder;
39struct MachinePointerInfo;
40template <typename T> class SmallVectorImpl;
41class LegalizerInfo;
42class MachineRegisterInfo;
43class GISelChangeObserver;
44class LostDebugLocObserver;
45class TargetLowering;
46
48public:
49 /// Expose MIRBuilder so clients can set their own RecordInsertInstruction
50 /// functions
52
53 /// To keep track of changes made by the LegalizerHelper.
55
56private:
58 const LegalizerInfo &LI;
59 const TargetLowering &TLI;
61
62public:
64 /// Instruction was already legal and no change was made to the
65 /// MachineFunction.
67
68 /// Instruction has been legalized and the MachineFunction changed.
70
71 /// Some kind of error has occurred and we could not legalize this
72 /// instruction.
74 };
75
76 /// Expose LegalizerInfo so the clients can re-use.
77 const LegalizerInfo &getLegalizerInfo() const { return LI; }
78 const TargetLowering &getTargetLowering() const { return TLI; }
79 GISelKnownBits *getKnownBits() const { return KB; }
80
85 GISelKnownBits *KB = nullptr);
86
87 /// Replace \p MI by a sequence of legal instructions that can implement the
88 /// same operation. Note that this means \p MI may be deleted, so any iterator
89 /// steps should be performed before calling this function. \p Helper should
90 /// be initialized to the MachineFunction containing \p MI.
91 ///
92 /// Considered as an opaque blob, the legal code will use and define the same
93 /// registers as \p MI.
95 LostDebugLocObserver &LocObserver);
96
97 /// Legalize an instruction by emiting a runtime library call instead.
99
100 /// Legalize an instruction by reducing the width of the underlying scalar
101 /// type.
102 LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
103
104 /// Legalize an instruction by performing the operation on a wider scalar type
105 /// (for example a 16-bit addition can be safely performed at 32-bits
106 /// precision, ignoring the unused bits).
107 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
108
109 /// Legalize an instruction by replacing the value type
110 LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
111
112 /// Legalize an instruction by splitting it into simpler parts, hopefully
113 /// understood by the target.
114 LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
115
116 /// Legalize a vector instruction by splitting into multiple components, each
117 /// acting on the same scalar type as the original but with fewer elements.
119 LLT NarrowTy);
120
121 /// Legalize a vector instruction by increasing the number of vector elements
122 /// involved and ignoring the added elements later.
124 LLT MoreTy);
125
126 /// Cast the given value to an LLT::scalar with an equivalent size. Returns
127 /// the register to use if an instruction was inserted. Returns the original
128 /// register if no coercion was necessary.
129 //
130 // This may also fail and return Register() if there is no legal way to cast.
132
133 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
134 /// Use by extending the operand's type to \p WideTy using the specified \p
135 /// ExtOpcode for the extension instruction, and replacing the vreg of the
136 /// operand in place.
137 void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
138 unsigned ExtOpcode);
139
140 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
141 /// Use by truncating the operand's type to \p NarrowTy using G_TRUNC, and
142 /// replacing the vreg of the operand in place.
143 void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx);
144
145 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
146 /// Def by extending the operand's type to \p WideTy and truncating it back
147 /// with the \p TruncOpcode, and replacing the vreg of the operand in place.
148 void widenScalarDst(MachineInstr &MI, LLT WideTy, unsigned OpIdx = 0,
149 unsigned TruncOpcode = TargetOpcode::G_TRUNC);
150
151 // Legalize a single operand \p OpIdx of the machine instruction \p MI as a
152 // Def by truncating the operand's type to \p NarrowTy, replacing in place and
153 // extending back with \p ExtOpcode.
154 void narrowScalarDst(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx,
155 unsigned ExtOpcode);
156 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
157 /// Def by performing it with additional vector elements and extracting the
158 /// result elements, and replacing the vreg of the operand in place.
159 void moreElementsVectorDst(MachineInstr &MI, LLT MoreTy, unsigned OpIdx);
160
161 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
162 /// Use by producing a vector with undefined high elements, extracting the
163 /// original vector type, and replacing the vreg of the operand in place.
164 void moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, unsigned OpIdx);
165
166 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
167 /// use by inserting a G_BITCAST to \p CastTy
168 void bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx);
169
170 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
171 /// def by inserting a G_BITCAST from \p CastTy
172 void bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx);
173
174private:
176 widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
178 widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
180 widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
182 widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
183 LegalizeResult widenScalarAddSubOverflow(MachineInstr &MI, unsigned TypeIdx,
184 LLT WideTy);
185 LegalizeResult widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx,
186 LLT WideTy);
187 LegalizeResult widenScalarMulo(MachineInstr &MI, unsigned TypeIdx,
188 LLT WideTy);
189
190 /// Helper function to build a wide generic register \p DstReg of type \p
191 /// RegTy from smaller parts. This will produce a G_MERGE_VALUES,
192 /// G_BUILD_VECTOR, G_CONCAT_VECTORS, or sequence of G_INSERT as appropriate
193 /// for the types.
194 ///
195 /// \p PartRegs must be registers of type \p PartTy.
196 ///
197 /// If \p ResultTy does not evenly break into \p PartTy sized pieces, the
198 /// remainder must be specified with \p LeftoverRegs of type \p LeftoverTy.
199 void insertParts(Register DstReg, LLT ResultTy,
200 LLT PartTy, ArrayRef<Register> PartRegs,
201 LLT LeftoverTy = LLT(), ArrayRef<Register> LeftoverRegs = {});
202
203 /// Merge \p PartRegs with different types into \p DstReg.
204 void mergeMixedSubvectors(Register DstReg, ArrayRef<Register> PartRegs);
205
206 void appendVectorElts(SmallVectorImpl<Register> &Elts, Register Reg);
207
208 /// Unmerge \p SrcReg into smaller sized values, and append them to \p
209 /// Parts. The elements of \p Parts will be the greatest common divisor type
210 /// of \p DstTy, \p NarrowTy and the type of \p SrcReg. This will compute and
211 /// return the GCD type.
212 LLT extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy,
213 LLT NarrowTy, Register SrcReg);
214
215 /// Unmerge \p SrcReg into \p GCDTy typed registers. This will append all of
216 /// the unpacked registers to \p Parts. This version is if the common unmerge
217 /// type is already known.
218 void extractGCDType(SmallVectorImpl<Register> &Parts, LLT GCDTy,
219 Register SrcReg);
220
221 /// Produce a merge of values in \p VRegs to define \p DstReg. Perform a merge
222 /// from the least common multiple type, and convert as appropriate to \p
223 /// DstReg.
224 ///
225 /// \p VRegs should each have type \p GCDTy. This type should be greatest
226 /// common divisor type of \p DstReg, \p NarrowTy, and an undetermined source
227 /// type.
228 ///
229 /// \p NarrowTy is the desired result merge source type. If the source value
230 /// needs to be widened to evenly cover \p DstReg, inserts high bits
231 /// corresponding to the extension opcode \p PadStrategy.
232 ///
233 /// \p VRegs will be cleared, and the result \p NarrowTy register pieces
234 /// will replace it. Returns The complete LCMTy that \p VRegs will cover when
235 /// merged.
236 LLT buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy,
237 SmallVectorImpl<Register> &VRegs,
238 unsigned PadStrategy = TargetOpcode::G_ANYEXT);
239
240 /// Merge the values in \p RemergeRegs to an \p LCMTy typed value. Extract the
241 /// low bits into \p DstReg. This is intended to use the outputs from
242 /// buildLCMMergePieces after processing.
243 void buildWidenedRemergeToDst(Register DstReg, LLT LCMTy,
244 ArrayRef<Register> RemergeRegs);
245
246 /// Perform generic multiplication of values held in multiple registers.
247 /// Generated instructions use only types NarrowTy and i1.
248 /// Destination can be same or two times size of the source.
249 void multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
250 ArrayRef<Register> Src1Regs,
251 ArrayRef<Register> Src2Regs, LLT NarrowTy);
252
253 void changeOpcode(MachineInstr &MI, unsigned NewOpcode);
254
255 LegalizeResult tryNarrowPow2Reduction(MachineInstr &MI, Register SrcReg,
256 LLT SrcTy, LLT NarrowTy,
257 unsigned ScalarOpc);
258
259 // Memcpy family legalization helpers.
260 LegalizeResult lowerMemset(MachineInstr &MI, Register Dst, Register Val,
261 uint64_t KnownLen, Align Alignment,
262 bool IsVolatile);
263 LegalizeResult lowerMemcpyInline(MachineInstr &MI, Register Dst, Register Src,
264 uint64_t KnownLen, Align DstAlign,
265 Align SrcAlign, bool IsVolatile);
266 LegalizeResult lowerMemcpy(MachineInstr &MI, Register Dst, Register Src,
267 uint64_t KnownLen, uint64_t Limit, Align DstAlign,
268 Align SrcAlign, bool IsVolatile);
269 LegalizeResult lowerMemmove(MachineInstr &MI, Register Dst, Register Src,
270 uint64_t KnownLen, Align DstAlign, Align SrcAlign,
271 bool IsVolatile);
272
273 // Implements floating-point environment read/write via library function call.
274 LegalizeResult createGetStateLibcall(MachineIRBuilder &MIRBuilder,
275 MachineInstr &MI,
276 LostDebugLocObserver &LocObserver);
277 LegalizeResult createSetStateLibcall(MachineIRBuilder &MIRBuilder,
278 MachineInstr &MI,
279 LostDebugLocObserver &LocObserver);
280 LegalizeResult createResetStateLibcall(MachineIRBuilder &MIRBuilder,
281 MachineInstr &MI,
282 LostDebugLocObserver &LocObserver);
283
284public:
285 /// Return the alignment to use for a stack temporary object with the given
286 /// type.
287 Align getStackTemporaryAlignment(LLT Type, Align MinAlign = Align()) const;
288
289 /// Create a stack temporary based on the size in bytes and the alignment
290 MachineInstrBuilder createStackTemporary(TypeSize Bytes, Align Alignment,
291 MachinePointerInfo &PtrInfo);
292
293 /// Get a pointer to vector element \p Index located in memory for a vector of
294 /// type \p VecTy starting at a base address of \p VecPtr. If \p Index is out
295 /// of bounds the returned pointer is unspecified, but will be within the
296 /// vector bounds.
297 Register getVectorElementPointer(Register VecPtr, LLT VecTy, Register Index);
298
299 /// Handles most opcodes. Split \p MI into same instruction on sub-vectors or
300 /// scalars with \p NumElts elements (1 for scalar). Supports uneven splits:
301 /// there can be leftover sub-vector with fewer then \p NumElts or a leftover
302 /// scalar. To avoid this use moreElements first and set MI number of elements
303 /// to multiple of \p NumElts. Non-vector operands that should be used on all
304 /// sub-instructions without split are listed in \p NonVecOpIndices.
306 GenericMachineInstr &MI, unsigned NumElts,
307 std::initializer_list<unsigned> NonVecOpIndices = {});
308
309 LegalizeResult fewerElementsVectorPhi(GenericMachineInstr &MI,
310 unsigned NumElts);
311
312 LegalizeResult moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
313 LLT MoreTy);
314 LegalizeResult moreElementsVectorShuffle(MachineInstr &MI, unsigned TypeIdx,
315 LLT MoreTy);
316
318 unsigned TypeIdx,
319 LLT NarrowTy);
320 LegalizeResult fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx,
321 LLT NarrowTy);
323 unsigned TypeIdx,
324 LLT NarrowTy);
325
326 /// Equalize source and destination vector sizes of G_SHUFFLE_VECTOR.
328
329 LegalizeResult reduceLoadStoreWidth(GLoadStore &MI, unsigned TypeIdx,
330 LLT NarrowTy);
331
332 LegalizeResult narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
333 LLT HalfTy, LLT ShiftAmtTy);
334
336 unsigned TypeIdx, LLT NarrowTy);
338 unsigned TypeIdx,
339 LLT NarrowTy);
340
341 LegalizeResult fewerElementsVectorShuffle(MachineInstr &MI, unsigned TypeIdx,
342 LLT NarrowTy);
343
344 LegalizeResult narrowScalarShift(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
345 LegalizeResult narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx,
346 LLT NarrowTy);
347 LegalizeResult narrowScalarMul(MachineInstr &MI, LLT Ty);
348 LegalizeResult narrowScalarFPTOI(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
349 LegalizeResult narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
350 LegalizeResult narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
351
352 LegalizeResult narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
353 LegalizeResult narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
354 LegalizeResult narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
355 LegalizeResult narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
356 LegalizeResult narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
357 LegalizeResult narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
358 LegalizeResult narrowScalarFLDEXP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
359
360 /// Perform Bitcast legalize action on G_EXTRACT_VECTOR_ELT.
361 LegalizeResult bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx,
362 LLT CastTy);
363
364 /// Perform Bitcast legalize action on G_INSERT_VECTOR_ELT.
365 LegalizeResult bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx,
366 LLT CastTy);
367
368 LegalizeResult lowerConstant(MachineInstr &MI);
369 LegalizeResult lowerFConstant(MachineInstr &MI);
370 LegalizeResult lowerBitcast(MachineInstr &MI);
371 LegalizeResult lowerLoad(GAnyLoad &MI);
373 LegalizeResult lowerBitCount(MachineInstr &MI);
376 LegalizeResult lowerFunnelShift(MachineInstr &MI);
377 LegalizeResult lowerEXT(MachineInstr &MI);
378 LegalizeResult lowerTRUNC(MachineInstr &MI);
380 LegalizeResult lowerRotate(MachineInstr &MI);
381
383 LegalizeResult lowerUITOFP(MachineInstr &MI);
384 LegalizeResult lowerSITOFP(MachineInstr &MI);
385 LegalizeResult lowerFPTOUI(MachineInstr &MI);
386 LegalizeResult lowerFPTOSI(MachineInstr &MI);
387
389 LegalizeResult lowerFPTRUNC(MachineInstr &MI);
390 LegalizeResult lowerFPOWI(MachineInstr &MI);
391
392 LegalizeResult lowerISFPCLASS(MachineInstr &MI);
393
394 LegalizeResult lowerMinMax(MachineInstr &MI);
395 LegalizeResult lowerFCopySign(MachineInstr &MI);
396 LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI);
397 LegalizeResult lowerFMad(MachineInstr &MI);
399 LegalizeResult lowerFFloor(MachineInstr &MI);
400 LegalizeResult lowerMergeValues(MachineInstr &MI);
401 LegalizeResult lowerUnmergeValues(MachineInstr &MI);
403 LegalizeResult lowerShuffleVector(MachineInstr &MI);
404 Register getDynStackAllocTargetPtr(Register SPReg, Register AllocSize,
405 Align Alignment, LLT PtrTy);
406 LegalizeResult lowerDynStackAlloc(MachineInstr &MI);
407 LegalizeResult lowerStackSave(MachineInstr &MI);
408 LegalizeResult lowerStackRestore(MachineInstr &MI);
409 LegalizeResult lowerExtract(MachineInstr &MI);
410 LegalizeResult lowerInsert(MachineInstr &MI);
411 LegalizeResult lowerSADDO_SSUBO(MachineInstr &MI);
414 LegalizeResult lowerShlSat(MachineInstr &MI);
415 LegalizeResult lowerBswap(MachineInstr &MI);
416 LegalizeResult lowerBitreverse(MachineInstr &MI);
418 LegalizeResult lowerSMULH_UMULH(MachineInstr &MI);
419 LegalizeResult lowerSelect(MachineInstr &MI);
420 LegalizeResult lowerDIVREM(MachineInstr &MI);
421 LegalizeResult lowerAbsToAddXor(MachineInstr &MI);
422 LegalizeResult lowerAbsToMaxNeg(MachineInstr &MI);
424 LegalizeResult lowerMemcpyInline(MachineInstr &MI);
425 LegalizeResult lowerMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
426 LegalizeResult lowerVAArg(MachineInstr &MI);
427};
428
429/// Helper function that creates a libcall to the given \p Name using the given
430/// calling convention \p CC.
432createLibcall(MachineIRBuilder &MIRBuilder, const char *Name,
433 const CallLowering::ArgInfo &Result,
434 ArrayRef<CallLowering::ArgInfo> Args, CallingConv::ID CC,
435 LostDebugLocObserver &LocObserver, MachineInstr *MI = nullptr);
436
437/// Helper function that creates the given libcall.
439createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
440 const CallLowering::ArgInfo &Result,
441 ArrayRef<CallLowering::ArgInfo> Args,
442 LostDebugLocObserver &LocObserver, MachineInstr *MI = nullptr);
443
444/// Create a libcall to memcpy et al.
446createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
447 MachineInstr &MI, LostDebugLocObserver &LocObserver);
448
449
450} // End namespace llvm.
451
452#endif
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
This file describes how to lower LLVM calls to machine code calls.
std::string Name
Provides analysis for querying information about KnownBits during GISel passes.
IRTranslator LLVM IR MI
unsigned Reg
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Abstract class that contains various methods for clients to notify about changes.
LegalizeResult lowerShlSat(MachineInstr &MI)
LegalizeResult narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult lowerFPTRUNC_F64_TO_F16(MachineInstr &MI)
LegalizeResult equalizeVectorShuffleLengths(MachineInstr &MI)
Equalize source and destination vector sizes of G_SHUFFLE_VECTOR.
LegalizeResult bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx, LLT CastTy)
Perform Bitcast legalize action on G_INSERT_VECTOR_ELT.
LegalizeResult lowerSITOFP(MachineInstr &MI)
LegalizeResult lowerDynStackAlloc(MachineInstr &MI)
LegalizeResult lowerBitCount(MachineInstr &MI)
LegalizeResult narrowScalarMul(MachineInstr &MI, LLT Ty)
LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI)
LegalizeResult lowerIntrinsicRound(MachineInstr &MI)
void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx, unsigned ExtOpcode)
Legalize a single operand OpIdx of the machine instruction MI as a Use by extending the operand's typ...
LegalizeResult moreElementsVectorShuffle(MachineInstr &MI, unsigned TypeIdx, LLT MoreTy)
LegalizeResult lowerSMULH_UMULH(MachineInstr &MI)
LegalizeResult lowerLoad(GAnyLoad &MI)
LegalizeResult fewerElementsVectorShuffle(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
LegalizeResult lowerAbsToAddXor(MachineInstr &MI)
void moreElementsVectorDst(MachineInstr &MI, LLT MoreTy, unsigned OpIdx)
Legalize a single operand OpIdx of the machine instruction MI as a Def by performing it with addition...
LegalizeResult lowerFConstant(MachineInstr &MI)
LegalizeResult narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult lowerBitreverse(MachineInstr &MI)
LegalizeResult narrowScalarShift(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult lowerExtractInsertVectorElt(MachineInstr &MI)
Lower a vector extract or insert by writing the vector to a stack temporary and reloading the element...
LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx, LLT MoreTy)
Legalize a vector instruction by increasing the number of vector elements involved and ignoring the a...
LegalizeResult lowerFunnelShiftWithInverse(MachineInstr &MI)
LegalizeResult lowerAbsToMaxNeg(MachineInstr &MI)
LegalizeResult lowerEXT(MachineInstr &MI)
LegalizeResult lowerStore(GStore &MI)
LegalizeResult lowerSADDO_SSUBO(MachineInstr &MI)
MachineInstrBuilder createStackTemporary(TypeSize Bytes, Align Alignment, MachinePointerInfo &PtrInfo)
Create a stack temporary based on the size in bytes and the alignment.
void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx)
Legalize a single operand OpIdx of the machine instruction MI as a Use by truncating the operand's ty...
LegalizeResult fewerElementsVectorPhi(GenericMachineInstr &MI, unsigned NumElts)
LegalizeResult lowerFPTOUI(MachineInstr &MI)
const TargetLowering & getTargetLowering() const
LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
Legalize an instruction by reducing the width of the underlying scalar type.
LegalizeResult narrowScalarFPTOI(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult lowerUnmergeValues(MachineInstr &MI)
LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
Legalize an instruction by replacing the value type.
LegalizeResult lowerBitcast(MachineInstr &MI)
LegalizeResult lowerMinMax(MachineInstr &MI)
LegalizeResult lowerFunnelShiftAsShifts(MachineInstr &MI)
LegalizeResult lowerInsert(MachineInstr &MI)
LegalizeResult lowerReadWriteRegister(MachineInstr &MI)
LegalizeResult lowerExtract(MachineInstr &MI)
LegalizeResult narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt, LLT HalfTy, LLT ShiftAmtTy)
LegalizeResult lowerISFPCLASS(MachineInstr &MI)
LegalizeResult lowerAddSubSatToMinMax(MachineInstr &MI)
LegalizeResult lowerFPOWI(MachineInstr &MI)
LegalizeResult narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult lowerVectorReduction(MachineInstr &MI)
const LegalizerInfo & getLegalizerInfo() const
Expose LegalizerInfo so the clients can re-use.
LegalizeResult reduceLoadStoreWidth(GLoadStore &MI, unsigned TypeIdx, LLT NarrowTy)
LegalizeResult fewerElementsVectorMultiEltType(GenericMachineInstr &MI, unsigned NumElts, std::initializer_list< unsigned > NonVecOpIndices={})
Handles most opcodes.
LegalizeResult narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult lowerVAArg(MachineInstr &MI)
@ Legalized
Instruction has been legalized and the MachineFunction changed.
@ AlreadyLegal
Instruction was already legal and no change was made to the MachineFunction.
@ UnableToLegalize
Some kind of error has occurred and we could not legalize this instruction.
LegalizeResult moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, LLT MoreTy)
LegalizeResult lowerU64ToF32BitOps(MachineInstr &MI)
LegalizeResult lowerFCopySign(MachineInstr &MI)
LegalizeResult lowerRotateWithReverseRotate(MachineInstr &MI)
LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
Legalize an instruction by splitting it into simpler parts, hopefully understood by the target.
LegalizeResult lowerFunnelShift(MachineInstr &MI)
LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
Legalize a vector instruction by splitting into multiple components, each acting on the same scalar t...
GISelChangeObserver & Observer
To keep track of changes made by the LegalizerHelper.
void bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx)
Legalize a single operand OpIdx of the machine instruction MI as a def by inserting a G_BITCAST from ...
LegalizeResult lowerFPTRUNC(MachineInstr &MI)
LegalizeResult lowerFMad(MachineInstr &MI)
LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy)
Legalize an instruction by performing the operation on a wider scalar type (for example a 16-bit addi...
LegalizeResult lowerAddSubSatToAddoSubo(MachineInstr &MI)
LegalizeResult narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult lowerFFloor(MachineInstr &MI)
LegalizeResult narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult fewerElementsVectorSeqReductions(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
Register getDynStackAllocTargetPtr(Register SPReg, Register AllocSize, Align Alignment, LLT PtrTy)
LegalizeResult lowerFPTOSI(MachineInstr &MI)
LegalizeResult lowerUITOFP(MachineInstr &MI)
LegalizeResult lowerShuffleVector(MachineInstr &MI)
LegalizeResult fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
LegalizeResult lowerMergeValues(MachineInstr &MI)
LegalizeResult fewerElementsVectorUnmergeValues(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
void moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, unsigned OpIdx)
Legalize a single operand OpIdx of the machine instruction MI as a Use by producing a vector with und...
LegalizeResult bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx, LLT CastTy)
Perform Bitcast legalize action on G_EXTRACT_VECTOR_ELT.
LegalizeResult lowerRotate(MachineInstr &MI)
LegalizeResult lowerMemCpyFamily(MachineInstr &MI, unsigned MaxLen=0)
Register coerceToScalar(Register Val)
Cast the given value to an LLT::scalar with an equivalent size.
LegalizeResult lowerDIVREM(MachineInstr &MI)
GISelKnownBits * getKnownBits() const
LegalizeResult lowerSelect(MachineInstr &MI)
LegalizeResult narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
LegalizeResult narrowScalarFLDEXP(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
void bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx)
Legalize a single operand OpIdx of the machine instruction MI as a use by inserting a G_BITCAST to Ca...
void narrowScalarDst(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx, unsigned ExtOpcode)
LegalizeResult lowerStackRestore(MachineInstr &MI)
LegalizeResult fewerElementsVectorReductions(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
LegalizeResult lowerStackSave(MachineInstr &MI)
LegalizeResult fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
LegalizeResult narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
MachineIRBuilder & MIRBuilder
Expose MIRBuilder so clients can set their own RecordInsertInstruction functions.
LegalizeResult lowerTRUNC(MachineInstr &MI)
LegalizeResult lowerBswap(MachineInstr &MI)
Register getVectorElementPointer(Register VecPtr, LLT VecTy, Register Index)
Get a pointer to vector element Index located in memory for a vector of type VecTy starting at a base...
LegalizeResult narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
Align getStackTemporaryAlignment(LLT Type, Align MinAlign=Align()) const
Return the alignment to use for a stack temporary object with the given type.
LegalizeResult lowerConstant(MachineInstr &MI)
void widenScalarDst(MachineInstr &MI, LLT WideTy, unsigned OpIdx=0, unsigned TruncOpcode=TargetOpcode::G_TRUNC)
Legalize a single operand OpIdx of the machine instruction MI as a Def by extending the operand's typ...
LegalizeResult legalizeInstrStep(MachineInstr &MI, LostDebugLocObserver &LocObserver)
Replace MI by a sequence of legal instructions that can implement the same operation.
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
LegalizerHelper::LegalizeResult createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstr &MI, LostDebugLocObserver &LocObserver)
Create a libcall to memcpy et al.
LegalizerHelper::LegalizeResult createLibcall(MachineIRBuilder &MIRBuilder, const char *Name, const CallLowering::ArgInfo &Result, ArrayRef< CallLowering::ArgInfo > Args, CallingConv::ID CC, LostDebugLocObserver &LocObserver, MachineInstr *MI=nullptr)
Helper function that creates a libcall to the given Name using the given calling convention CC.
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:338