LLVM  16.0.0git
LoongArchISelLowering.cpp
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1 //=- LoongArchISelLowering.cpp - LoongArch DAG Lowering Implementation ---===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that LoongArch uses to lower LLVM code into
10 // a selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "LoongArchISelLowering.h"
15 #include "LoongArch.h"
17 #include "LoongArchRegisterInfo.h"
18 #include "LoongArchSubtarget.h"
19 #include "LoongArchTargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/KnownBits.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "loongarch-isel-lowering"
29 
31  "loongarch-check-zero-division", cl::Hidden,
32  cl::desc("Trap on integer division by zero."),
33  cl::init(false));
34 
36  const LoongArchSubtarget &STI)
37  : TargetLowering(TM), Subtarget(STI) {
38 
39  MVT GRLenVT = Subtarget.getGRLenVT();
40  // Set up the register classes.
41  addRegisterClass(GRLenVT, &LoongArch::GPRRegClass);
42  if (Subtarget.hasBasicF())
43  addRegisterClass(MVT::f32, &LoongArch::FPR32RegClass);
44  if (Subtarget.hasBasicD())
45  addRegisterClass(MVT::f64, &LoongArch::FPR64RegClass);
46 
48  MVT::i1, Promote);
49 
50  // TODO: add necessary setOperationAction calls later.
57 
59 
61  if (Subtarget.is64Bit())
63 
67 
68  if (Subtarget.is64Bit()) {
78  if (Subtarget.hasBasicF() && !Subtarget.hasBasicD())
80  }
81 
82  // LA32 does not have REVB.2W and REVB.D due to the 64-bit operands, and
83  // the narrower REVB.W does not exist. But LA32 does have REVB.2H, so i16
84  // and i32 could still be byte-swapped relatively cheaply.
86  if (Subtarget.is64Bit()) {
88  }
89 
90  // Expand bitreverse.i16 with native-width bitrev and shift for now, before
91  // we get to know which of sll and revb.2h is faster.
93  if (Subtarget.is64Bit()) {
96  } else {
98  }
99 
100  static const ISD::CondCode FPCCToExpand[] = {ISD::SETOGT, ISD::SETOGE,
102 
103  if (Subtarget.hasBasicF()) {
104  setCondCodeAction(FPCCToExpand, MVT::f32, Expand);
106  }
107  if (Subtarget.hasBasicD()) {
108  setCondCodeAction(FPCCToExpand, MVT::f64, Expand);
112  }
113 
118  if (!Subtarget.is64Bit())
119  setLibcallName(RTLIB::MUL_I128, nullptr);
120 
123 
124  // Compute derived properties from the register classes.
126 
128 
130 
132 
133  // Function alignments.
134  const Align FunctionAlignment(4);
135  setMinFunctionAlignment(FunctionAlignment);
136 
140 }
141 
143  const GlobalAddressSDNode *GA) const {
144  // In order to maximise the opportunity for common subexpression elimination,
145  // keep a separate ADD node for the global address offset instead of folding
146  // it in the global address node. Later peephole optimisations may choose to
147  // fold it back in when profitable.
148  return false;
149 }
150 
152  SelectionDAG &DAG) const {
153  switch (Op.getOpcode()) {
154  case ISD::EH_DWARF_CFA:
155  return lowerEH_DWARF_CFA(Op, DAG);
156  case ISD::GlobalAddress:
157  return lowerGlobalAddress(Op, DAG);
158  case ISD::SHL_PARTS:
159  return lowerShiftLeftParts(Op, DAG);
160  case ISD::SRA_PARTS:
161  return lowerShiftRightParts(Op, DAG, true);
162  case ISD::SRL_PARTS:
163  return lowerShiftRightParts(Op, DAG, false);
164  case ISD::ConstantPool:
165  return lowerConstantPool(Op, DAG);
166  case ISD::FP_TO_SINT:
167  return lowerFP_TO_SINT(Op, DAG);
168  case ISD::BITCAST:
169  return lowerBITCAST(Op, DAG);
170  case ISD::UINT_TO_FP:
171  return lowerUINT_TO_FP(Op, DAG);
172  case ISD::VASTART:
173  return lowerVASTART(Op, DAG);
174  }
175  return SDValue();
176 }
177 
178 SDValue LoongArchTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
179  SelectionDAG &DAG) const {
181  auto Size = Subtarget.getGRLen() / 8;
182  auto FI = MF.getFrameInfo().CreateFixedObject(Size, 0, false);
183  return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
184 }
185 
186 SDValue LoongArchTargetLowering::lowerVASTART(SDValue Op,
187  SelectionDAG &DAG) const {
189  auto *FuncInfo = MF.getInfo<LoongArchMachineFunctionInfo>();
190 
191  SDLoc DL(Op);
192  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
194 
195  // vastart just stores the address of the VarArgsFrameIndex slot into the
196  // memory location argument.
197  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
198  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
199  MachinePointerInfo(SV));
200 }
201 
202 SDValue LoongArchTargetLowering::lowerUINT_TO_FP(SDValue Op,
203  SelectionDAG &DAG) const {
204 
205  SDLoc DL(Op);
206  auto &TLI = DAG.getTargetLoweringInfo();
207  SDValue Tmp1, Tmp2;
208  SDValue Op1 = Op.getOperand(0);
209  if (Op1->getOpcode() == ISD::AssertZext ||
210  Op1->getOpcode() == ISD::AssertSext)
211  return Op;
212  SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op.getOperand(0));
213  SDValue Res = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f64, Trunc);
214  SDNode *N = Res.getNode();
215  TLI.expandUINT_TO_FP(N, Tmp1, Tmp2, DAG);
216  return Tmp1;
217 }
218 
219 SDValue LoongArchTargetLowering::lowerBITCAST(SDValue Op,
220  SelectionDAG &DAG) const {
221 
222  SDLoc DL(Op);
223  SDValue Op0 = Op.getOperand(0);
224 
225  if (Op.getValueType() == MVT::f32 && Op0.getValueType() == MVT::i32 &&
226  Subtarget.is64Bit() && Subtarget.hasBasicF()) {
227  SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
228  return DAG.getNode(LoongArchISD::MOVGR2FR_W_LA64, DL, MVT::f32, NewOp0);
229  }
230  return Op;
231 }
232 
233 SDValue LoongArchTargetLowering::lowerFP_TO_SINT(SDValue Op,
234  SelectionDAG &DAG) const {
235 
236  SDLoc DL(Op);
237 
238  if (Op.getValueSizeInBits() > 32 && Subtarget.hasBasicF() &&
239  !Subtarget.hasBasicD()) {
240  SDValue Dst =
241  DAG.getNode(LoongArchISD::FTINT, DL, MVT::f32, Op.getOperand(0));
243  }
244 
245  EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
246  SDValue Trunc = DAG.getNode(LoongArchISD::FTINT, DL, FPTy, Op.getOperand(0));
247  return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Trunc);
248 }
249 
250 SDValue LoongArchTargetLowering::lowerConstantPool(SDValue Op,
251  SelectionDAG &DAG) const {
252  SDLoc DL(Op);
253  EVT Ty = Op.getValueType();
254  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
255 
256  // FIXME: Only support PC-relative addressing to access the symbol.
257  // Target flags will be added later.
258  if (!isPositionIndependent()) {
259  SDValue ConstantN = DAG.getTargetConstantPool(
260  N->getConstVal(), Ty, N->getAlign(), N->getOffset());
261  SDValue AddrHi(DAG.getMachineNode(LoongArch::PCALAU12I, DL, Ty, ConstantN),
262  0);
263  SDValue Addr(DAG.getMachineNode(Subtarget.is64Bit() ? LoongArch::ADDI_D
264  : LoongArch::ADDI_W,
265  DL, Ty, AddrHi, ConstantN),
266  0);
267  return Addr;
268  }
269  report_fatal_error("Unable to lower ConstantPool");
270 }
271 
272 SDValue LoongArchTargetLowering::lowerGlobalAddress(SDValue Op,
273  SelectionDAG &DAG) const {
274  SDLoc DL(Op);
275  EVT Ty = getPointerTy(DAG.getDataLayout());
276  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
277  unsigned ADDIOp = Subtarget.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
278 
279  // TODO: Support dso_preemptable and target flags.
280  if (GV->isDSOLocal()) {
281  SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty);
282  SDValue AddrHi(DAG.getMachineNode(LoongArch::PCALAU12I, DL, Ty, GA), 0);
283  SDValue Addr(DAG.getMachineNode(ADDIOp, DL, Ty, AddrHi, GA), 0);
284  return Addr;
285  }
286  report_fatal_error("Unable to lowerGlobalAddress");
287 }
288 
289 SDValue LoongArchTargetLowering::lowerShiftLeftParts(SDValue Op,
290  SelectionDAG &DAG) const {
291  SDLoc DL(Op);
292  SDValue Lo = Op.getOperand(0);
293  SDValue Hi = Op.getOperand(1);
294  SDValue Shamt = Op.getOperand(2);
295  EVT VT = Lo.getValueType();
296 
297  // if Shamt-GRLen < 0: // Shamt < GRLen
298  // Lo = Lo << Shamt
299  // Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (GRLen-1 ^ Shamt))
300  // else:
301  // Lo = 0
302  // Hi = Lo << (Shamt-GRLen)
303 
304  SDValue Zero = DAG.getConstant(0, DL, VT);
305  SDValue One = DAG.getConstant(1, DL, VT);
306  SDValue MinusGRLen = DAG.getConstant(-(int)Subtarget.getGRLen(), DL, VT);
307  SDValue GRLenMinus1 = DAG.getConstant(Subtarget.getGRLen() - 1, DL, VT);
308  SDValue ShamtMinusGRLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusGRLen);
309  SDValue GRLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, GRLenMinus1);
310 
311  SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
312  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One);
313  SDValue ShiftRightLo =
314  DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, GRLenMinus1Shamt);
315  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
316  SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
317  SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusGRLen);
318 
319  SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusGRLen, Zero, ISD::SETLT);
320 
321  Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);
322  Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
323 
324  SDValue Parts[2] = {Lo, Hi};
325  return DAG.getMergeValues(Parts, DL);
326 }
327 
328 SDValue LoongArchTargetLowering::lowerShiftRightParts(SDValue Op,
329  SelectionDAG &DAG,
330  bool IsSRA) const {
331  SDLoc DL(Op);
332  SDValue Lo = Op.getOperand(0);
333  SDValue Hi = Op.getOperand(1);
334  SDValue Shamt = Op.getOperand(2);
335  EVT VT = Lo.getValueType();
336 
337  // SRA expansion:
338  // if Shamt-GRLen < 0: // Shamt < GRLen
339  // Lo = (Lo >>u Shamt) | ((Hi << 1) << (ShAmt ^ GRLen-1))
340  // Hi = Hi >>s Shamt
341  // else:
342  // Lo = Hi >>s (Shamt-GRLen);
343  // Hi = Hi >>s (GRLen-1)
344  //
345  // SRL expansion:
346  // if Shamt-GRLen < 0: // Shamt < GRLen
347  // Lo = (Lo >>u Shamt) | ((Hi << 1) << (ShAmt ^ GRLen-1))
348  // Hi = Hi >>u Shamt
349  // else:
350  // Lo = Hi >>u (Shamt-GRLen);
351  // Hi = 0;
352 
353  unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;
354 
355  SDValue Zero = DAG.getConstant(0, DL, VT);
356  SDValue One = DAG.getConstant(1, DL, VT);
357  SDValue MinusGRLen = DAG.getConstant(-(int)Subtarget.getGRLen(), DL, VT);
358  SDValue GRLenMinus1 = DAG.getConstant(Subtarget.getGRLen() - 1, DL, VT);
359  SDValue ShamtMinusGRLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusGRLen);
360  SDValue GRLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, GRLenMinus1);
361 
362  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
363  SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);
364  SDValue ShiftLeftHi =
365  DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, GRLenMinus1Shamt);
366  SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);
367  SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);
368  SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusGRLen);
369  SDValue HiFalse =
370  IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, GRLenMinus1) : Zero;
371 
372  SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusGRLen, Zero, ISD::SETLT);
373 
374  Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
375  Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
376 
377  SDValue Parts[2] = {Lo, Hi};
378  return DAG.getMergeValues(Parts, DL);
379 }
380 
381 // Returns the opcode of the target-specific SDNode that implements the 32-bit
382 // form of the given Opcode.
384  switch (Opcode) {
385  default:
386  llvm_unreachable("Unexpected opcode");
387  case ISD::SHL:
388  return LoongArchISD::SLL_W;
389  case ISD::SRA:
390  return LoongArchISD::SRA_W;
391  case ISD::SRL:
392  return LoongArchISD::SRL_W;
393  case ISD::ROTR:
394  return LoongArchISD::ROTR_W;
395  case ISD::ROTL:
396  return LoongArchISD::ROTL_W;
397  case ISD::CTTZ:
398  return LoongArchISD::CTZ_W;
399  case ISD::CTLZ:
400  return LoongArchISD::CLZ_W;
401  }
402 }
403 
404 // Converts the given i8/i16/i32 operation to a target-specific SelectionDAG
405 // node. Because i8/i16/i32 isn't a legal type for LA64, these operations would
406 // otherwise be promoted to i64, making it difficult to select the
407 // SLL_W/.../*W later one because the fact the operation was originally of
408 // type i8/i16/i32 is lost.
410  unsigned ExtOpc = ISD::ANY_EXTEND) {
411  SDLoc DL(N);
412  LoongArchISD::NodeType WOpcode = getLoongArchWOpcode(N->getOpcode());
413  SDValue NewOp0, NewRes;
414 
415  switch (NumOp) {
416  default:
417  llvm_unreachable("Unexpected NumOp");
418  case 1: {
419  NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0));
420  NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0);
421  break;
422  }
423  case 2: {
424  NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0));
425  SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1));
426  NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1);
427  break;
428  }
429  // TODO:Handle more NumOp.
430  }
431 
432  // ReplaceNodeResults requires we maintain the same type for the return
433  // value.
434  return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes);
435 }
436 
439  SDLoc DL(N);
440  switch (N->getOpcode()) {
441  default:
442  llvm_unreachable("Don't know how to legalize this operation");
443  case ISD::SHL:
444  case ISD::SRA:
445  case ISD::SRL:
446  case ISD::ROTR:
447  assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
448  "Unexpected custom legalisation");
449  if (N->getOperand(1).getOpcode() != ISD::Constant) {
450  Results.push_back(customLegalizeToWOp(N, DAG, 2));
451  break;
452  }
453  break;
454  case ISD::ROTL:
455  ConstantSDNode *CN;
456  if ((CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))) {
457  Results.push_back(customLegalizeToWOp(N, DAG, 2));
458  break;
459  }
460  break;
461  case ISD::FP_TO_SINT: {
462  assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
463  "Unexpected custom legalisation");
464  SDValue Src = N->getOperand(0);
465  EVT VT = EVT::getFloatingPointVT(N->getValueSizeInBits(0));
466  SDValue Dst = DAG.getNode(LoongArchISD::FTINT, DL, VT, Src);
467  Results.push_back(DAG.getNode(ISD::BITCAST, DL, N->getValueType(0), Dst));
468  break;
469  }
470  case ISD::BITCAST: {
471  EVT VT = N->getValueType(0);
472  SDValue Src = N->getOperand(0);
473  EVT SrcVT = Src.getValueType();
474  if (VT == MVT::i32 && SrcVT == MVT::f32 && Subtarget.is64Bit() &&
475  Subtarget.hasBasicF()) {
476  SDValue Dst =
478  Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Dst));
479  }
480  break;
481  }
482  case ISD::FP_TO_UINT: {
483  assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
484  "Unexpected custom legalisation");
485  auto &TLI = DAG.getTargetLoweringInfo();
486  SDValue Tmp1, Tmp2;
487  TLI.expandFP_TO_UINT(N, Tmp1, Tmp2, DAG);
488  Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Tmp1));
489  break;
490  }
491  case ISD::BSWAP: {
492  SDValue Src = N->getOperand(0);
493  EVT VT = N->getValueType(0);
494  assert((VT == MVT::i16 || VT == MVT::i32) &&
495  "Unexpected custom legalization");
496  MVT GRLenVT = Subtarget.getGRLenVT();
497  SDValue NewSrc = DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT, Src);
498  SDValue Tmp;
499  switch (VT.getSizeInBits()) {
500  default:
501  llvm_unreachable("Unexpected operand width");
502  case 16:
503  Tmp = DAG.getNode(LoongArchISD::REVB_2H, DL, GRLenVT, NewSrc);
504  break;
505  case 32:
506  // Only LA64 will get to here due to the size mismatch between VT and
507  // GRLenVT, LA32 lowering is directly defined in LoongArchInstrInfo.
508  Tmp = DAG.getNode(LoongArchISD::REVB_2W, DL, GRLenVT, NewSrc);
509  break;
510  }
511  Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Tmp));
512  break;
513  }
514  case ISD::BITREVERSE: {
515  SDValue Src = N->getOperand(0);
516  EVT VT = N->getValueType(0);
517  assert((VT == MVT::i8 || (VT == MVT::i32 && Subtarget.is64Bit())) &&
518  "Unexpected custom legalization");
519  MVT GRLenVT = Subtarget.getGRLenVT();
520  SDValue NewSrc = DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT, Src);
521  SDValue Tmp;
522  switch (VT.getSizeInBits()) {
523  default:
524  llvm_unreachable("Unexpected operand width");
525  case 8:
526  Tmp = DAG.getNode(LoongArchISD::BITREV_4B, DL, GRLenVT, NewSrc);
527  break;
528  case 32:
529  Tmp = DAG.getNode(LoongArchISD::BITREV_W, DL, GRLenVT, NewSrc);
530  break;
531  }
532  Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Tmp));
533  break;
534  }
535  case ISD::CTLZ:
536  case ISD::CTTZ: {
537  assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
538  "Unexpected custom legalisation");
539  Results.push_back(customLegalizeToWOp(N, DAG, 1));
540  break;
541  }
542  }
543 }
544 
547  const LoongArchSubtarget &Subtarget) {
548  if (DCI.isBeforeLegalizeOps())
549  return SDValue();
550 
551  SDValue FirstOperand = N->getOperand(0);
552  SDValue SecondOperand = N->getOperand(1);
553  unsigned FirstOperandOpc = FirstOperand.getOpcode();
554  EVT ValTy = N->getValueType(0);
555  SDLoc DL(N);
556  uint64_t lsb, msb;
557  unsigned SMIdx, SMLen;
558  ConstantSDNode *CN;
559  SDValue NewOperand;
560  MVT GRLenVT = Subtarget.getGRLenVT();
561 
562  // Op's second operand must be a shifted mask.
563  if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)) ||
564  !isShiftedMask_64(CN->getZExtValue(), SMIdx, SMLen))
565  return SDValue();
566 
567  if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
568  // Pattern match BSTRPICK.
569  // $dst = and ((sra or srl) $src , lsb), (2**len - 1)
570  // => BSTRPICK $dst, $src, msb, lsb
571  // where msb = lsb + len - 1
572 
573  // The second operand of the shift must be an immediate.
574  if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
575  return SDValue();
576 
577  lsb = CN->getZExtValue();
578 
579  // Return if the shifted mask does not start at bit 0 or the sum of its
580  // length and lsb exceeds the word's size.
581  if (SMIdx != 0 || lsb + SMLen > ValTy.getSizeInBits())
582  return SDValue();
583 
584  NewOperand = FirstOperand.getOperand(0);
585  } else {
586  // Pattern match BSTRPICK.
587  // $dst = and $src, (2**len- 1) , if len > 12
588  // => BSTRPICK $dst, $src, msb, lsb
589  // where lsb = 0 and msb = len - 1
590 
591  // If the mask is <= 0xfff, andi can be used instead.
592  if (CN->getZExtValue() <= 0xfff)
593  return SDValue();
594 
595  // Return if the mask doesn't start at position 0.
596  if (SMIdx)
597  return SDValue();
598 
599  lsb = 0;
600  NewOperand = FirstOperand;
601  }
602  msb = lsb + SMLen - 1;
603  return DAG.getNode(LoongArchISD::BSTRPICK, DL, ValTy, NewOperand,
604  DAG.getConstant(msb, DL, GRLenVT),
605  DAG.getConstant(lsb, DL, GRLenVT));
606 }
607 
610  const LoongArchSubtarget &Subtarget) {
611  if (DCI.isBeforeLegalizeOps())
612  return SDValue();
613 
614  // $dst = srl (and $src, Mask), Shamt
615  // =>
616  // BSTRPICK $dst, $src, MaskIdx+MaskLen-1, Shamt
617  // when Mask is a shifted mask, and MaskIdx <= Shamt <= MaskIdx+MaskLen-1
618  //
619 
620  SDValue FirstOperand = N->getOperand(0);
621  ConstantSDNode *CN;
622  EVT ValTy = N->getValueType(0);
623  SDLoc DL(N);
624  MVT GRLenVT = Subtarget.getGRLenVT();
625  unsigned MaskIdx, MaskLen;
626  uint64_t Shamt;
627 
628  // The first operand must be an AND and the second operand of the AND must be
629  // a shifted mask.
630  if (FirstOperand.getOpcode() != ISD::AND ||
631  !(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
632  !isShiftedMask_64(CN->getZExtValue(), MaskIdx, MaskLen))
633  return SDValue();
634 
635  // The second operand (shift amount) must be an immediate.
636  if (!(CN = dyn_cast<ConstantSDNode>(N->getOperand(1))))
637  return SDValue();
638 
639  Shamt = CN->getZExtValue();
640  if (MaskIdx <= Shamt && Shamt <= MaskIdx + MaskLen - 1)
641  return DAG.getNode(LoongArchISD::BSTRPICK, DL, ValTy,
642  FirstOperand->getOperand(0),
643  DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT),
644  DAG.getConstant(Shamt, DL, GRLenVT));
645 
646  return SDValue();
647 }
648 
651  const LoongArchSubtarget &Subtarget) {
652  MVT GRLenVT = Subtarget.getGRLenVT();
653  EVT ValTy = N->getValueType(0);
654  SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
655  ConstantSDNode *CN0, *CN1;
656  SDLoc DL(N);
657  unsigned ValBits = ValTy.getSizeInBits();
658  unsigned MaskIdx0, MaskLen0, MaskIdx1, MaskLen1;
659  unsigned Shamt;
660  bool SwapAndRetried = false;
661 
662  if (DCI.isBeforeLegalizeOps())
663  return SDValue();
664 
665  if (ValBits != 32 && ValBits != 64)
666  return SDValue();
667 
668 Retry:
669  // 1st pattern to match BSTRINS:
670  // R = or (and X, mask0), (and (shl Y, lsb), mask1)
671  // where mask1 = (2**size - 1) << lsb, mask0 = ~mask1
672  // =>
673  // R = BSTRINS X, Y, msb, lsb (where msb = lsb + size - 1)
674  if (N0.getOpcode() == ISD::AND &&
675  (CN0 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) &&
676  isShiftedMask_64(~CN0->getSExtValue(), MaskIdx0, MaskLen0) &&
677  N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL &&
678  (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
679  isShiftedMask_64(CN1->getZExtValue(), MaskIdx1, MaskLen1) &&
680  MaskIdx0 == MaskIdx1 && MaskLen0 == MaskLen1 &&
681  (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(1))) &&
682  (Shamt = CN1->getZExtValue()) == MaskIdx0 &&
683  (MaskIdx0 + MaskLen0 <= ValBits)) {
684  LLVM_DEBUG(dbgs() << "Perform OR combine: match pattern 1\n");
685  return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0.getOperand(0),
686  N1.getOperand(0).getOperand(0),
687  DAG.getConstant((MaskIdx0 + MaskLen0 - 1), DL, GRLenVT),
688  DAG.getConstant(MaskIdx0, DL, GRLenVT));
689  }
690 
691  // 2nd pattern to match BSTRINS:
692  // R = or (and X, mask0), (shl (and Y, mask1), lsb)
693  // where mask1 = (2**size - 1), mask0 = ~(mask1 << lsb)
694  // =>
695  // R = BSTRINS X, Y, msb, lsb (where msb = lsb + size - 1)
696  if (N0.getOpcode() == ISD::AND &&
697  (CN0 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) &&
698  isShiftedMask_64(~CN0->getSExtValue(), MaskIdx0, MaskLen0) &&
699  N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::AND &&
700  (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
701  (Shamt = CN1->getZExtValue()) == MaskIdx0 &&
702  (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(1))) &&
703  isShiftedMask_64(CN1->getZExtValue(), MaskIdx1, MaskLen1) &&
704  MaskLen0 == MaskLen1 && MaskIdx1 == 0 &&
705  (MaskIdx0 + MaskLen0 <= ValBits)) {
706  LLVM_DEBUG(dbgs() << "Perform OR combine: match pattern 2\n");
707  return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0.getOperand(0),
708  N1.getOperand(0).getOperand(0),
709  DAG.getConstant((MaskIdx0 + MaskLen0 - 1), DL, GRLenVT),
710  DAG.getConstant(MaskIdx0, DL, GRLenVT));
711  }
712 
713  // 3rd pattern to match BSTRINS:
714  // R = or (and X, mask0), (and Y, mask1)
715  // where ~mask0 = (2**size - 1) << lsb, mask0 & mask1 = 0
716  // =>
717  // R = BSTRINS X, (shr (and Y, mask1), lsb), msb, lsb
718  // where msb = lsb + size - 1
719  if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
720  (CN0 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) &&
721  isShiftedMask_64(~CN0->getSExtValue(), MaskIdx0, MaskLen0) &&
722  (MaskIdx0 + MaskLen0 <= 64) &&
723  (CN1 = dyn_cast<ConstantSDNode>(N1->getOperand(1))) &&
724  (CN1->getSExtValue() & CN0->getSExtValue()) == 0) {
725  LLVM_DEBUG(dbgs() << "Perform OR combine: match pattern 3\n");
726  return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0.getOperand(0),
727  DAG.getNode(ISD::SRL, DL, N1->getValueType(0), N1,
728  DAG.getConstant(MaskIdx0, DL, GRLenVT)),
729  DAG.getConstant(ValBits == 32
730  ? (MaskIdx0 + (MaskLen0 & 31) - 1)
731  : (MaskIdx0 + MaskLen0 - 1),
732  DL, GRLenVT),
733  DAG.getConstant(MaskIdx0, DL, GRLenVT));
734  }
735 
736  // 4th pattern to match BSTRINS:
737  // R = or (and X, mask), (shl Y, shamt)
738  // where mask = (2**shamt - 1)
739  // =>
740  // R = BSTRINS X, Y, ValBits - 1, shamt
741  // where ValBits = 32 or 64
742  if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::SHL &&
743  (CN0 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) &&
744  isShiftedMask_64(CN0->getZExtValue(), MaskIdx0, MaskLen0) &&
745  MaskIdx0 == 0 && (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
746  (Shamt = CN1->getZExtValue()) == MaskLen0 &&
747  (MaskIdx0 + MaskLen0 <= ValBits)) {
748  LLVM_DEBUG(dbgs() << "Perform OR combine: match pattern 4\n");
749  return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0.getOperand(0),
750  N1.getOperand(0),
751  DAG.getConstant((ValBits - 1), DL, GRLenVT),
752  DAG.getConstant(Shamt, DL, GRLenVT));
753  }
754 
755  // 5th pattern to match BSTRINS:
756  // R = or (and X, mask), const
757  // where ~mask = (2**size - 1) << lsb, mask & const = 0
758  // =>
759  // R = BSTRINS X, (const >> lsb), msb, lsb
760  // where msb = lsb + size - 1
761  if (N0.getOpcode() == ISD::AND &&
762  (CN0 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) &&
763  isShiftedMask_64(~CN0->getSExtValue(), MaskIdx0, MaskLen0) &&
764  (CN1 = dyn_cast<ConstantSDNode>(N1)) &&
765  (CN1->getSExtValue() & CN0->getSExtValue()) == 0) {
766  LLVM_DEBUG(dbgs() << "Perform OR combine: match pattern 5\n");
767  return DAG.getNode(
768  LoongArchISD::BSTRINS, DL, ValTy, N0.getOperand(0),
769  DAG.getConstant(CN1->getSExtValue() >> MaskIdx0, DL, ValTy),
770  DAG.getConstant((MaskIdx0 + MaskLen0 - 1), DL, GRLenVT),
771  DAG.getConstant(MaskIdx0, DL, GRLenVT));
772  }
773 
774  // 6th pattern.
775  // a = b | ((c & mask) << shamt), where all positions in b to be overwritten
776  // by the incoming bits are known to be zero.
777  // =>
778  // a = BSTRINS b, c, shamt + MaskLen - 1, shamt
779  //
780  // Note that the 1st pattern is a special situation of the 6th, i.e. the 6th
781  // pattern is more common than the 1st. So we put the 1st before the 6th in
782  // order to match as many nodes as possible.
783  ConstantSDNode *CNMask, *CNShamt;
784  unsigned MaskIdx, MaskLen;
785  if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::AND &&
786  (CNMask = dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(1))) &&
787  isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen) &&
788  MaskIdx == 0 && (CNShamt = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
789  CNShamt->getZExtValue() + MaskLen <= ValBits) {
790  Shamt = CNShamt->getZExtValue();
791  APInt ShMask(ValBits, CNMask->getZExtValue() << Shamt);
792  if (ShMask.isSubsetOf(DAG.computeKnownBits(N0).Zero)) {
793  LLVM_DEBUG(dbgs() << "Perform OR combine: match pattern 6\n");
794  return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0,
795  N1.getOperand(0).getOperand(0),
796  DAG.getConstant(Shamt + MaskLen - 1, DL, GRLenVT),
797  DAG.getConstant(Shamt, DL, GRLenVT));
798  }
799  }
800 
801  // 7th pattern.
802  // a = b | ((c << shamt) & shifted_mask), where all positions in b to be
803  // overwritten by the incoming bits are known to be zero.
804  // =>
805  // a = BSTRINS b, c, MaskIdx + MaskLen - 1, MaskIdx
806  //
807  // Similarly, the 7th pattern is more common than the 2nd. So we put the 2nd
808  // before the 7th in order to match as many nodes as possible.
809  if (N1.getOpcode() == ISD::AND &&
810  (CNMask = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
811  isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen) &&
812  N1.getOperand(0).getOpcode() == ISD::SHL &&
813  (CNShamt = dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(1))) &&
814  CNShamt->getZExtValue() == MaskIdx) {
815  APInt ShMask(ValBits, CNMask->getZExtValue());
816  if (ShMask.isSubsetOf(DAG.computeKnownBits(N0).Zero)) {
817  LLVM_DEBUG(dbgs() << "Perform OR combine: match pattern 7\n");
818  return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0,
819  N1.getOperand(0).getOperand(0),
820  DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT),
821  DAG.getConstant(MaskIdx, DL, GRLenVT));
822  }
823  }
824 
825  // (or a, b) and (or b, a) are equivalent, so swap the operands and retry.
826  if (!SwapAndRetried) {
827  std::swap(N0, N1);
828  SwapAndRetried = true;
829  goto Retry;
830  }
831 
832  SwapAndRetried = false;
833 Retry2:
834  // 8th pattern.
835  // a = b | (c & shifted_mask), where all positions in b to be overwritten by
836  // the incoming bits are known to be zero.
837  // =>
838  // a = BSTRINS b, c >> MaskIdx, MaskIdx + MaskLen - 1, MaskIdx
839  //
840  // Similarly, the 8th pattern is more common than the 4th and 5th patterns. So
841  // we put it here in order to match as many nodes as possible or generate less
842  // instructions.
843  if (N1.getOpcode() == ISD::AND &&
844  (CNMask = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
845  isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen)) {
846  APInt ShMask(ValBits, CNMask->getZExtValue());
847  if (ShMask.isSubsetOf(DAG.computeKnownBits(N0).Zero)) {
848  LLVM_DEBUG(dbgs() << "Perform OR combine: match pattern 8\n");
849  return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0,
850  DAG.getNode(ISD::SRL, DL, N1->getValueType(0),
851  N1->getOperand(0),
852  DAG.getConstant(MaskIdx, DL, GRLenVT)),
853  DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT),
854  DAG.getConstant(MaskIdx, DL, GRLenVT));
855  }
856  }
857  // Swap N0/N1 and retry.
858  if (!SwapAndRetried) {
859  std::swap(N0, N1);
860  SwapAndRetried = true;
861  goto Retry2;
862  }
863 
864  return SDValue();
865 }
866 
867 // Combine (loongarch_bitrev_w (loongarch_revb_2w X)) to loongarch_bitrev_4b.
870  const LoongArchSubtarget &Subtarget) {
871  if (DCI.isBeforeLegalizeOps())
872  return SDValue();
873 
874  SDValue Src = N->getOperand(0);
875  if (Src.getOpcode() != LoongArchISD::REVB_2W)
876  return SDValue();
877 
878  return DAG.getNode(LoongArchISD::BITREV_4B, SDLoc(N), N->getValueType(0),
879  Src.getOperand(0));
880 }
881 
883  DAGCombinerInfo &DCI) const {
884  SelectionDAG &DAG = DCI.DAG;
885  switch (N->getOpcode()) {
886  default:
887  break;
888  case ISD::AND:
889  return performANDCombine(N, DAG, DCI, Subtarget);
890  case ISD::OR:
891  return performORCombine(N, DAG, DCI, Subtarget);
892  case ISD::SRL:
893  return performSRLCombine(N, DAG, DCI, Subtarget);
895  return performBITREV_WCombine(N, DAG, DCI, Subtarget);
896  }
897  return SDValue();
898 }
899 
902  if (!ZeroDivCheck)
903  return MBB;
904 
905  // Build instructions:
906  // MBB:
907  // div(or mod) $dst, $dividend, $divisor
908  // bnez $divisor, SinkMBB
909  // BreakMBB:
910  // break 7 // BRK_DIVZERO
911  // SinkMBB:
912  // fallthrough
913  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
915  MachineFunction *MF = MBB->getParent();
916  auto BreakMBB = MF->CreateMachineBasicBlock(LLVM_BB);
917  auto SinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
918  MF->insert(It, BreakMBB);
919  MF->insert(It, SinkMBB);
920 
921  // Transfer the remainder of MBB and its successor edges to SinkMBB.
922  SinkMBB->splice(SinkMBB->end(), MBB, std::next(MI.getIterator()), MBB->end());
923  SinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
924 
925  const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
926  DebugLoc DL = MI.getDebugLoc();
927  MachineOperand &Divisor = MI.getOperand(2);
928  Register DivisorReg = Divisor.getReg();
929 
930  // MBB:
931  BuildMI(MBB, DL, TII.get(LoongArch::BNEZ))
932  .addReg(DivisorReg, getKillRegState(Divisor.isKill()))
933  .addMBB(SinkMBB);
934  MBB->addSuccessor(BreakMBB);
935  MBB->addSuccessor(SinkMBB);
936 
937  // BreakMBB:
938  // See linux header file arch/loongarch/include/uapi/asm/break.h for the
939  // definition of BRK_DIVZERO.
940  BuildMI(BreakMBB, DL, TII.get(LoongArch::BREAK)).addImm(7 /*BRK_DIVZERO*/);
941  BreakMBB->addSuccessor(SinkMBB);
942 
943  // Clear Divisor's kill flag.
944  Divisor.setIsKill(false);
945 
946  return SinkMBB;
947 }
948 
949 MachineBasicBlock *LoongArchTargetLowering::EmitInstrWithCustomInserter(
950  MachineInstr &MI, MachineBasicBlock *BB) const {
951 
952  switch (MI.getOpcode()) {
953  default:
954  llvm_unreachable("Unexpected instr type to insert");
955  case LoongArch::DIV_W:
956  case LoongArch::DIV_WU:
957  case LoongArch::MOD_W:
958  case LoongArch::MOD_WU:
959  case LoongArch::DIV_D:
960  case LoongArch::DIV_DU:
961  case LoongArch::MOD_D:
962  case LoongArch::MOD_DU:
963  return insertDivByZeroTrap(MI, BB);
964  break;
965  }
966 }
967 
968 const char *LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
969  switch ((LoongArchISD::NodeType)Opcode) {
971  break;
972 
973 #define NODE_NAME_CASE(node) \
974  case LoongArchISD::node: \
975  return "LoongArchISD::" #node;
976 
977  // TODO: Add more target-dependent nodes later.
996  }
997 #undef NODE_NAME_CASE
998  return nullptr;
999 }
1000 
1001 //===----------------------------------------------------------------------===//
1002 // Calling Convention Implementation
1003 //===----------------------------------------------------------------------===//
1004 
1005 // Eight general-purpose registers a0-a7 used for passing integer arguments,
1006 // with a0-a1 reused to return values. Generally, the GPRs are used to pass
1007 // fixed-point arguments, and floating-point arguments when no FPR is available
1008 // or with soft float ABI.
1009 const MCPhysReg ArgGPRs[] = {LoongArch::R4, LoongArch::R5, LoongArch::R6,
1010  LoongArch::R7, LoongArch::R8, LoongArch::R9,
1011  LoongArch::R10, LoongArch::R11};
1012 // Eight floating-point registers fa0-fa7 used for passing floating-point
1013 // arguments, and fa0-fa1 are also used to return values.
1014 const MCPhysReg ArgFPR32s[] = {LoongArch::F0, LoongArch::F1, LoongArch::F2,
1015  LoongArch::F3, LoongArch::F4, LoongArch::F5,
1016  LoongArch::F6, LoongArch::F7};
1017 // FPR32 and FPR64 alias each other.
1019  LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64,
1020  LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64};
1021 
1022 // Pass a 2*GRLen argument that has been split into two GRLen values through
1023 // registers or the stack as necessary.
1024 static bool CC_LoongArchAssign2GRLen(unsigned GRLen, CCState &State,
1025  CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1,
1026  unsigned ValNo2, MVT ValVT2, MVT LocVT2,
1027  ISD::ArgFlagsTy ArgFlags2) {
1028  unsigned GRLenInBytes = GRLen / 8;
1029  if (Register Reg = State.AllocateReg(ArgGPRs)) {
1030  // At least one half can be passed via register.
1031  State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg,
1032  VA1.getLocVT(), CCValAssign::Full));
1033  } else {
1034  // Both halves must be passed on the stack, with proper alignment.
1035  Align StackAlign =
1036  std::max(Align(GRLenInBytes), ArgFlags1.getNonZeroOrigAlign());
1037  State.addLoc(
1038  CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(),
1039  State.AllocateStack(GRLenInBytes, StackAlign),
1040  VA1.getLocVT(), CCValAssign::Full));
1042  ValNo2, ValVT2, State.AllocateStack(GRLenInBytes, Align(GRLenInBytes)),
1043  LocVT2, CCValAssign::Full));
1044  return false;
1045  }
1046  if (Register Reg = State.AllocateReg(ArgGPRs)) {
1047  // The second half can also be passed via register.
1048  State.addLoc(
1049  CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full));
1050  } else {
1051  // The second half is passed via the stack, without additional alignment.
1053  ValNo2, ValVT2, State.AllocateStack(GRLenInBytes, Align(GRLenInBytes)),
1054  LocVT2, CCValAssign::Full));
1055  }
1056  return false;
1057 }
1058 
1059 // Implements the LoongArch calling convention. Returns true upon failure.
1061  unsigned ValNo, MVT ValVT,
1062  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
1063  CCState &State, bool IsFixed, bool IsRet,
1064  Type *OrigTy) {
1065  unsigned GRLen = DL.getLargestLegalIntTypeSizeInBits();
1066  assert((GRLen == 32 || GRLen == 64) && "Unspport GRLen");
1067  MVT GRLenVT = GRLen == 32 ? MVT::i32 : MVT::i64;
1068  MVT LocVT = ValVT;
1069 
1070  // Any return value split into more than two values can't be returned
1071  // directly.
1072  if (IsRet && ValNo > 1)
1073  return true;
1074 
1075  // If passing a variadic argument, or if no FPR is available.
1076  bool UseGPRForFloat = true;
1077 
1078  switch (ABI) {
1079  default:
1080  llvm_unreachable("Unexpected ABI");
1085  report_fatal_error("Unimplemented ABI");
1086  break;
1089  UseGPRForFloat = !IsFixed;
1090  break;
1091  }
1092 
1093  // FPR32 and FPR64 alias each other.
1095  UseGPRForFloat = true;
1096 
1097  if (UseGPRForFloat && ValVT == MVT::f32) {
1098  LocVT = GRLenVT;
1099  LocInfo = CCValAssign::BCvt;
1100  } else if (UseGPRForFloat && GRLen == 64 && ValVT == MVT::f64) {
1101  LocVT = MVT::i64;
1102  LocInfo = CCValAssign::BCvt;
1103  } else if (UseGPRForFloat && GRLen == 32 && ValVT == MVT::f64) {
1104  // TODO: Handle passing f64 on LA32 with D feature.
1105  report_fatal_error("Passing f64 with GPR on LA32 is undefined");
1106  }
1107 
1108  // If this is a variadic argument, the LoongArch calling convention requires
1109  // that it is assigned an 'even' or 'aligned' register if it has (2*GRLen)/8
1110  // byte alignment. An aligned register should be used regardless of whether
1111  // the original argument was split during legalisation or not. The argument
1112  // will not be passed by registers if the original type is larger than
1113  // 2*GRLen, so the register alignment rule does not apply.
1114  unsigned TwoGRLenInBytes = (2 * GRLen) / 8;
1115  if (!IsFixed && ArgFlags.getNonZeroOrigAlign() == TwoGRLenInBytes &&
1116  DL.getTypeAllocSize(OrigTy) == TwoGRLenInBytes) {
1117  unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
1118  // Skip 'odd' register if necessary.
1119  if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1)
1120  State.AllocateReg(ArgGPRs);
1121  }
1122 
1123  SmallVectorImpl<CCValAssign> &PendingLocs = State.getPendingLocs();
1124  SmallVectorImpl<ISD::ArgFlagsTy> &PendingArgFlags =
1125  State.getPendingArgFlags();
1126 
1127  assert(PendingLocs.size() == PendingArgFlags.size() &&
1128  "PendingLocs and PendingArgFlags out of sync");
1129 
1130  // Split arguments might be passed indirectly, so keep track of the pending
1131  // values.
1132  if (ValVT.isScalarInteger() && (ArgFlags.isSplit() || !PendingLocs.empty())) {
1133  LocVT = GRLenVT;
1134  LocInfo = CCValAssign::Indirect;
1135  PendingLocs.push_back(
1136  CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
1137  PendingArgFlags.push_back(ArgFlags);
1138  if (!ArgFlags.isSplitEnd()) {
1139  return false;
1140  }
1141  }
1142 
1143  // If the split argument only had two elements, it should be passed directly
1144  // in registers or on the stack.
1145  if (ValVT.isScalarInteger() && ArgFlags.isSplitEnd() &&
1146  PendingLocs.size() <= 2) {
1147  assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()");
1148  // Apply the normal calling convention rules to the first half of the
1149  // split argument.
1150  CCValAssign VA = PendingLocs[0];
1151  ISD::ArgFlagsTy AF = PendingArgFlags[0];
1152  PendingLocs.clear();
1153  PendingArgFlags.clear();
1154  return CC_LoongArchAssign2GRLen(GRLen, State, VA, AF, ValNo, ValVT, LocVT,
1155  ArgFlags);
1156  }
1157 
1158  // Allocate to a register if possible, or else a stack slot.
1159  Register Reg;
1160  unsigned StoreSizeBytes = GRLen / 8;
1161  Align StackAlign = Align(GRLen / 8);
1162 
1163  if (ValVT == MVT::f32 && !UseGPRForFloat)
1164  Reg = State.AllocateReg(ArgFPR32s);
1165  else if (ValVT == MVT::f64 && !UseGPRForFloat)
1166  Reg = State.AllocateReg(ArgFPR64s);
1167  else
1168  Reg = State.AllocateReg(ArgGPRs);
1169 
1170  unsigned StackOffset =
1171  Reg ? 0 : State.AllocateStack(StoreSizeBytes, StackAlign);
1172 
1173  // If we reach this point and PendingLocs is non-empty, we must be at the
1174  // end of a split argument that must be passed indirectly.
1175  if (!PendingLocs.empty()) {
1176  assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()");
1177  assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()");
1178  for (auto &It : PendingLocs) {
1179  if (Reg)
1180  It.convertToReg(Reg);
1181  else
1182  It.convertToMem(StackOffset);
1183  State.addLoc(It);
1184  }
1185  PendingLocs.clear();
1186  PendingArgFlags.clear();
1187  return false;
1188  }
1189  assert((!UseGPRForFloat || LocVT == GRLenVT) &&
1190  "Expected an GRLenVT at this stage");
1191 
1192  if (Reg) {
1193  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1194  return false;
1195  }
1196 
1197  // When a floating-point value is passed on the stack, no bit-cast is needed.
1198  if (ValVT.isFloatingPoint()) {
1199  LocVT = ValVT;
1200  LocInfo = CCValAssign::Full;
1201  }
1202 
1203  State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
1204  return false;
1205 }
1206 
1207 void LoongArchTargetLowering::analyzeInputArgs(
1208  MachineFunction &MF, CCState &CCInfo,
1209  const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
1210  LoongArchCCAssignFn Fn) const {
1211  FunctionType *FType = MF.getFunction().getFunctionType();
1212  for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
1213  MVT ArgVT = Ins[i].VT;
1214  Type *ArgTy = nullptr;
1215  if (IsRet)
1216  ArgTy = FType->getReturnType();
1217  else if (Ins[i].isOrigArg())
1218  ArgTy = FType->getParamType(Ins[i].getOrigArgIndex());
1221  if (Fn(MF.getDataLayout(), ABI, i, ArgVT, CCValAssign::Full, Ins[i].Flags,
1222  CCInfo, /*IsFixed=*/true, IsRet, ArgTy)) {
1223  LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type "
1224  << EVT(ArgVT).getEVTString() << '\n');
1225  llvm_unreachable("");
1226  }
1227  }
1228 }
1229 
1230 void LoongArchTargetLowering::analyzeOutputArgs(
1231  MachineFunction &MF, CCState &CCInfo,
1232  const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet,
1233  CallLoweringInfo *CLI, LoongArchCCAssignFn Fn) const {
1234  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
1235  MVT ArgVT = Outs[i].VT;
1236  Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty : nullptr;
1239  if (Fn(MF.getDataLayout(), ABI, i, ArgVT, CCValAssign::Full, Outs[i].Flags,
1240  CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) {
1241  LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type "
1242  << EVT(ArgVT).getEVTString() << "\n");
1243  llvm_unreachable("");
1244  }
1245  }
1246 }
1247 
1248 // Convert Val to a ValVT. Should not be called for CCValAssign::Indirect
1249 // values.
1251  const CCValAssign &VA, const SDLoc &DL) {
1252  switch (VA.getLocInfo()) {
1253  default:
1254  llvm_unreachable("Unexpected CCValAssign::LocInfo");
1255  case CCValAssign::Full:
1256  case CCValAssign::Indirect:
1257  break;
1258  case CCValAssign::BCvt:
1259  if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32)
1261  else
1262  Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
1263  break;
1264  }
1265  return Val;
1266 }
1267 
1269  const CCValAssign &VA, const SDLoc &DL,
1270  const LoongArchTargetLowering &TLI) {
1271  MachineFunction &MF = DAG.getMachineFunction();
1272  MachineRegisterInfo &RegInfo = MF.getRegInfo();
1273  EVT LocVT = VA.getLocVT();
1274  SDValue Val;
1275  const TargetRegisterClass *RC = TLI.getRegClassFor(LocVT.getSimpleVT());
1276  Register VReg = RegInfo.createVirtualRegister(RC);
1277  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1278  Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
1279 
1280  return convertLocVTToValVT(DAG, Val, VA, DL);
1281 }
1282 
1283 // The caller is responsible for loading the full value if the argument is
1284 // passed with CCValAssign::Indirect.
1286  const CCValAssign &VA, const SDLoc &DL) {
1287  MachineFunction &MF = DAG.getMachineFunction();
1288  MachineFrameInfo &MFI = MF.getFrameInfo();
1289  EVT ValVT = VA.getValVT();
1290  int FI = MFI.CreateFixedObject(ValVT.getStoreSize(), VA.getLocMemOffset(),
1291  /*IsImmutable=*/true);
1292  SDValue FIN = DAG.getFrameIndex(
1294 
1295  ISD::LoadExtType ExtType;
1296  switch (VA.getLocInfo()) {
1297  default:
1298  llvm_unreachable("Unexpected CCValAssign::LocInfo");
1299  case CCValAssign::Full:
1300  case CCValAssign::Indirect:
1301  case CCValAssign::BCvt:
1302  ExtType = ISD::NON_EXTLOAD;
1303  break;
1304  }
1305  return DAG.getExtLoad(
1306  ExtType, DL, VA.getLocVT(), Chain, FIN,
1308 }
1309 
1311  const CCValAssign &VA, const SDLoc &DL) {
1312  EVT LocVT = VA.getLocVT();
1313 
1314  switch (VA.getLocInfo()) {
1315  default:
1316  llvm_unreachable("Unexpected CCValAssign::LocInfo");
1317  case CCValAssign::Full:
1318  break;
1319  case CCValAssign::BCvt:
1320  if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32)
1322  else
1323  Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val);
1324  break;
1325  }
1326  return Val;
1327 }
1328 
1329 // Transform physical registers into virtual registers.
1331  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
1332  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1333  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1334 
1335  MachineFunction &MF = DAG.getMachineFunction();
1336 
1337  switch (CallConv) {
1338  default:
1339  llvm_unreachable("Unsupported calling convention");
1340  case CallingConv::C:
1341  break;
1342  }
1343 
1344  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1345  MVT GRLenVT = Subtarget.getGRLenVT();
1346  unsigned GRLenInBytes = Subtarget.getGRLen() / 8;
1347  // Used with varargs to acumulate store chains.
1348  std::vector<SDValue> OutChains;
1349 
1350  // Assign locations to all of the incoming arguments.
1351  SmallVector<CCValAssign> ArgLocs;
1352  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1353 
1354  analyzeInputArgs(MF, CCInfo, Ins, /*IsRet=*/false, CC_LoongArch);
1355 
1356  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1357  CCValAssign &VA = ArgLocs[i];
1358  SDValue ArgValue;
1359  if (VA.isRegLoc())
1360  ArgValue = unpackFromRegLoc(DAG, Chain, VA, DL, *this);
1361  else
1362  ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);
1363  if (VA.getLocInfo() == CCValAssign::Indirect) {
1364  // If the original argument was split and passed by reference, we need to
1365  // load all parts of it here (using the same address).
1366  InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
1367  MachinePointerInfo()));
1368  unsigned ArgIndex = Ins[i].OrigArgIndex;
1369  unsigned ArgPartOffset = Ins[i].PartOffset;
1370  assert(ArgPartOffset == 0);
1371  while (i + 1 != e && Ins[i + 1].OrigArgIndex == ArgIndex) {
1372  CCValAssign &PartVA = ArgLocs[i + 1];
1373  unsigned PartOffset = Ins[i + 1].PartOffset - ArgPartOffset;
1374  SDValue Offset = DAG.getIntPtrConstant(PartOffset, DL);
1375  SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue, Offset);
1376  InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address,
1377  MachinePointerInfo()));
1378  ++i;
1379  }
1380  continue;
1381  }
1382  InVals.push_back(ArgValue);
1383  }
1384 
1385  if (IsVarArg) {
1387  unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
1388  const TargetRegisterClass *RC = &LoongArch::GPRRegClass;
1389  MachineFrameInfo &MFI = MF.getFrameInfo();
1390  MachineRegisterInfo &RegInfo = MF.getRegInfo();
1391  auto *LoongArchFI = MF.getInfo<LoongArchMachineFunctionInfo>();
1392 
1393  // Offset of the first variable argument from stack pointer, and size of
1394  // the vararg save area. For now, the varargs save area is either zero or
1395  // large enough to hold a0-a7.
1396  int VaArgOffset, VarArgsSaveSize;
1397 
1398  // If all registers are allocated, then all varargs must be passed on the
1399  // stack and we don't need to save any argregs.
1400  if (ArgRegs.size() == Idx) {
1401  VaArgOffset = CCInfo.getNextStackOffset();
1402  VarArgsSaveSize = 0;
1403  } else {
1404  VarArgsSaveSize = GRLenInBytes * (ArgRegs.size() - Idx);
1405  VaArgOffset = -VarArgsSaveSize;
1406  }
1407 
1408  // Record the frame index of the first variable argument
1409  // which is a value necessary to VASTART.
1410  int FI = MFI.CreateFixedObject(GRLenInBytes, VaArgOffset, true);
1411  LoongArchFI->setVarArgsFrameIndex(FI);
1412 
1413  // If saving an odd number of registers then create an extra stack slot to
1414  // ensure that the frame pointer is 2*GRLen-aligned, which in turn ensures
1415  // offsets to even-numbered registered remain 2*GRLen-aligned.
1416  if (Idx % 2) {
1417  MFI.CreateFixedObject(GRLenInBytes, VaArgOffset - (int)GRLenInBytes,
1418  true);
1419  VarArgsSaveSize += GRLenInBytes;
1420  }
1421 
1422  // Copy the integer registers that may have been used for passing varargs
1423  // to the vararg save area.
1424  for (unsigned I = Idx; I < ArgRegs.size();
1425  ++I, VaArgOffset += GRLenInBytes) {
1426  const Register Reg = RegInfo.createVirtualRegister(RC);
1427  RegInfo.addLiveIn(ArgRegs[I], Reg);
1428  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, GRLenVT);
1429  FI = MFI.CreateFixedObject(GRLenInBytes, VaArgOffset, true);
1430  SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1431  SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
1433  cast<StoreSDNode>(Store.getNode())
1434  ->getMemOperand()
1435  ->setValue((Value *)nullptr);
1436  OutChains.push_back(Store);
1437  }
1438  LoongArchFI->setVarArgsSaveSize(VarArgsSaveSize);
1439  }
1440 
1441  // All stores are grouped in one node to allow the matching between
1442  // the size of Ins and InVals. This only happens for vararg functions.
1443  if (!OutChains.empty()) {
1444  OutChains.push_back(Chain);
1445  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
1446  }
1447 
1448  return Chain;
1449 }
1450 
1452  return DAG.getDataLayout().getPrefTypeAlign(
1453  VT.getTypeForEVT(*DAG.getContext()));
1454 }
1455 
1456 // Lower a call to a callseq_start + CALL + callseq_end chain, and add input
1457 // and output parameter nodes.
1458 SDValue
1460  SmallVectorImpl<SDValue> &InVals) const {
1461  SelectionDAG &DAG = CLI.DAG;
1462  SDLoc &DL = CLI.DL;
1464  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1466  SDValue Chain = CLI.Chain;
1467  SDValue Callee = CLI.Callee;
1468  CallingConv::ID CallConv = CLI.CallConv;
1469  bool IsVarArg = CLI.IsVarArg;
1470  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1471  MVT GRLenVT = Subtarget.getGRLenVT();
1472  CLI.IsTailCall = false;
1473 
1474  MachineFunction &MF = DAG.getMachineFunction();
1475 
1476  // Analyze the operands of the call, assigning locations to each operand.
1477  SmallVector<CCValAssign> ArgLocs;
1478  CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1479 
1480  analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI, CC_LoongArch);
1481 
1482  // Get a count of how many bytes are to be pushed on the stack.
1483  unsigned NumBytes = ArgCCInfo.getNextStackOffset();
1484 
1485  // Create local copies for byval args.
1486  SmallVector<SDValue> ByValArgs;
1487  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
1488  ISD::ArgFlagsTy Flags = Outs[i].Flags;
1489  if (!Flags.isByVal())
1490  continue;
1491 
1492  SDValue Arg = OutVals[i];
1493  unsigned Size = Flags.getByValSize();
1494  Align Alignment = Flags.getNonZeroByValAlign();
1495 
1496  int FI =
1497  MF.getFrameInfo().CreateStackObject(Size, Alignment, /*isSS=*/false);
1498  SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1499  SDValue SizeNode = DAG.getConstant(Size, DL, GRLenVT);
1500 
1501  Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,
1502  /*IsVolatile=*/false,
1503  /*AlwaysInline=*/false, /*isTailCall=*/false,
1505  ByValArgs.push_back(FIPtr);
1506  }
1507 
1508  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
1509 
1510  // Copy argument values to their designated locations.
1512  SmallVector<SDValue> MemOpChains;
1513  SDValue StackPtr;
1514  for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) {
1515  CCValAssign &VA = ArgLocs[i];
1516  SDValue ArgValue = OutVals[i];
1517  ISD::ArgFlagsTy Flags = Outs[i].Flags;
1518 
1519  // Promote the value if needed.
1520  // For now, only handle fully promoted and indirect arguments.
1521  if (VA.getLocInfo() == CCValAssign::Indirect) {
1522  // Store the argument in a stack slot and pass its address.
1523  Align StackAlign =
1524  std::max(getPrefTypeAlign(Outs[i].ArgVT, DAG),
1525  getPrefTypeAlign(ArgValue.getValueType(), DAG));
1526  TypeSize StoredSize = ArgValue.getValueType().getStoreSize();
1527  // If the original argument was split and passed by reference, we need to
1528  // store the required parts of it here (and pass just one address).
1529  unsigned ArgIndex = Outs[i].OrigArgIndex;
1530  unsigned ArgPartOffset = Outs[i].PartOffset;
1531  assert(ArgPartOffset == 0);
1532  // Calculate the total size to store. We don't have access to what we're
1533  // actually storing other than performing the loop and collecting the
1534  // info.
1536  while (i + 1 != e && Outs[i + 1].OrigArgIndex == ArgIndex) {
1537  SDValue PartValue = OutVals[i + 1];
1538  unsigned PartOffset = Outs[i + 1].PartOffset - ArgPartOffset;
1539  SDValue Offset = DAG.getIntPtrConstant(PartOffset, DL);
1540  EVT PartVT = PartValue.getValueType();
1541 
1542  StoredSize += PartVT.getStoreSize();
1544  Parts.push_back(std::make_pair(PartValue, Offset));
1545  ++i;
1546  }
1547  SDValue SpillSlot = DAG.CreateStackTemporary(StoredSize, StackAlign);
1548  int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1549  MemOpChains.push_back(
1550  DAG.getStore(Chain, DL, ArgValue, SpillSlot,
1552  for (const auto &Part : Parts) {
1553  SDValue PartValue = Part.first;
1554  SDValue PartOffset = Part.second;
1555  SDValue Address =
1556  DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot, PartOffset);
1557  MemOpChains.push_back(
1558  DAG.getStore(Chain, DL, PartValue, Address,
1560  }
1561  ArgValue = SpillSlot;
1562  } else {
1563  ArgValue = convertValVTToLocVT(DAG, ArgValue, VA, DL);
1564  }
1565 
1566  // Use local copy if it is a byval arg.
1567  if (Flags.isByVal())
1568  ArgValue = ByValArgs[j++];
1569 
1570  if (VA.isRegLoc()) {
1571  // Queue up the argument copies and emit them at the end.
1572  RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
1573  } else {
1574  assert(VA.isMemLoc() && "Argument not register or memory");
1575 
1576  // Work out the address of the stack slot.
1577  if (!StackPtr.getNode())
1578  StackPtr = DAG.getCopyFromReg(Chain, DL, LoongArch::R3, PtrVT);
1579  SDValue Address =
1580  DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
1581  DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
1582 
1583  // Emit the store.
1584  MemOpChains.push_back(
1585  DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
1586  }
1587  }
1588 
1589  // Join the stores, which are independent of one another.
1590  if (!MemOpChains.empty())
1591  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1592 
1593  SDValue Glue;
1594 
1595  // Build a sequence of copy-to-reg nodes, chained and glued together.
1596  for (auto &Reg : RegsToPass) {
1597  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
1598  Glue = Chain.getValue(1);
1599  }
1600 
1601  // If the callee is a GlobalAddress/ExternalSymbol node, turn it into a
1602  // TargetGlobalAddress/TargetExternalSymbol node so that legalize won't
1603  // split it and then direct call can be matched by PseudoCALL.
1604  // FIXME: Add target flags for relocation.
1605  if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee))
1606  Callee = DAG.getTargetGlobalAddress(S->getGlobal(), DL, PtrVT);
1607  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1608  Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT);
1609 
1610  // The first call operand is the chain and the second is the target address.
1612  Ops.push_back(Chain);
1613  Ops.push_back(Callee);
1614 
1615  // Add argument registers to the end of the list so that they are
1616  // known live into the call.
1617  for (auto &Reg : RegsToPass)
1618  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1619 
1620  // Add a register mask operand representing the call-preserved registers.
1621  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1622  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
1623  assert(Mask && "Missing call preserved mask for calling convention");
1624  Ops.push_back(DAG.getRegisterMask(Mask));
1625 
1626  // Glue the call to the argument copies, if any.
1627  if (Glue.getNode())
1628  Ops.push_back(Glue);
1629 
1630  // Emit the call.
1631  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1632 
1633  Chain = DAG.getNode(LoongArchISD::CALL, DL, NodeTys, Ops);
1634  DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
1635  Glue = Chain.getValue(1);
1636 
1637  // Mark the end of the call, which is glued to the call itself.
1638  Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, DL, PtrVT, true),
1639  DAG.getConstant(0, DL, PtrVT, true), Glue, DL);
1640  Glue = Chain.getValue(1);
1641 
1642  // Assign locations to each value returned by this call.
1643  SmallVector<CCValAssign> RVLocs;
1644  CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
1645  analyzeInputArgs(MF, RetCCInfo, Ins, /*IsRet=*/true, CC_LoongArch);
1646 
1647  // Copy all of the result registers out of their specified physreg.
1648  for (auto &VA : RVLocs) {
1649  // Copy the value out.
1650  SDValue RetValue =
1651  DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue);
1652  // Glue the RetValue to the end of the call sequence.
1653  Chain = RetValue.getValue(1);
1654  Glue = RetValue.getValue(2);
1655 
1656  RetValue = convertLocVTToValVT(DAG, RetValue, VA, DL);
1657 
1658  InVals.push_back(RetValue);
1659  }
1660 
1661  return Chain;
1662 }
1663 
1665  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
1666  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1667  SmallVector<CCValAssign> RVLocs;
1668  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
1669 
1670  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
1673  if (CC_LoongArch(MF.getDataLayout(), ABI, i, Outs[i].VT, CCValAssign::Full,
1674  Outs[i].Flags, CCInfo, /*IsFixed=*/true, /*IsRet=*/true,
1675  nullptr))
1676  return false;
1677  }
1678  return true;
1679 }
1680 
1682  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
1683  const SmallVectorImpl<ISD::OutputArg> &Outs,
1684  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
1685  SelectionDAG &DAG) const {
1686  // Stores the assignment of the return value to a location.
1687  SmallVector<CCValAssign> RVLocs;
1688 
1689  // Info about the registers and stack slot.
1690  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
1691  *DAG.getContext());
1692 
1693  analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, /*IsRet=*/true,
1694  nullptr, CC_LoongArch);
1695 
1696  SDValue Glue;
1697  SmallVector<SDValue, 4> RetOps(1, Chain);
1698 
1699  // Copy the result values into the output registers.
1700  for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) {
1701  CCValAssign &VA = RVLocs[i];
1702  assert(VA.isRegLoc() && "Can only return in registers!");
1703 
1704  // Handle a 'normal' return.
1705  SDValue Val = convertValVTToLocVT(DAG, OutVals[i], VA, DL);
1706  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);
1707 
1708  // Guarantee that all emitted copies are stuck together.
1709  Glue = Chain.getValue(1);
1710  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1711  }
1712 
1713  RetOps[0] = Chain; // Update chain.
1714 
1715  // Add the glue node if we have it.
1716  if (Glue.getNode())
1717  RetOps.push_back(Glue);
1718 
1719  return DAG.getNode(LoongArchISD::RET, DL, MVT::Other, RetOps);
1720 }
1721 
1722 bool LoongArchTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
1723  bool ForCodeSize) const {
1724  assert((VT == MVT::f32 || VT == MVT::f64) && "Unexpected VT");
1725 
1726  if (VT == MVT::f32 && !Subtarget.hasBasicF())
1727  return false;
1728  if (VT == MVT::f64 && !Subtarget.hasBasicD())
1729  return false;
1730  return (Imm.isZero() || Imm.isExactlyValue(+1.0));
1731 }
1732 
1734 
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:151
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:959
llvm::SelectionDAG::getMemcpy
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
Definition: SelectionDAG.cpp:7242
llvm::LoongArchSubtarget::getRegisterInfo
const LoongArchRegisterInfo * getRegisterInfo() const override
Definition: LoongArchSubtarget.h:70
i
i
Definition: README.txt:29
getLoongArchWOpcode
static LoongArchISD::NodeType getLoongArchWOpcode(unsigned Opcode)
Definition: LoongArchISelLowering.cpp:383
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1437
llvm::LoongArchTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: LoongArchISelLowering.cpp:151
llvm::LoongArchISD::SRA_W
@ SRA_W
Definition: LoongArchISelLowering.h:35
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1576
ABI
Generic address nodes are lowered to some combination of target independent and machine specific ABI
Definition: Relocation.txt:34
llvm::RISCVAttrs::StackAlign
StackAlign
Definition: RISCVAttributes.h:37
performORCombine
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
Definition: LoongArchISelLowering.cpp:649
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:943
llvm::ISD::ArgFlagsTy::isSplit
bool isSplit() const
Definition: TargetCallingConv.h:132
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::LoongArchTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: LoongArchISelLowering.cpp:968
llvm::LoongArchABI::ABI_LP64S
@ ABI_LP64S
Definition: LoongArchBaseInfo.h:30
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1098
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:34
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:195
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:209
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:886
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::SelectionDAG::addNoMergeSiteInfo
void addNoMergeSiteInfo(const SDNode *Node, bool NoMerge)
Set NoMergeSiteInfo to be associated with Node if NoMerge is true.
Definition: SelectionDAG.h:2189
llvm::ISD::NON_EXTLOAD
@ NON_EXTLOAD
Definition: ISDOpcodes.h:1404
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:750
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:159
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:700
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:976
llvm::LoongArchTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: LoongArchISelLowering.cpp:1733
llvm::CCState::addLoc
void addLoc(const CCValAssign &V)
Definition: CallingConvLower.h:251
llvm::KnownBits::Zero
APInt Zero
Definition: KnownBits.h:24
llvm::LoongArchSubtarget::getGRLen
unsigned getGRLen() const
Definition: LoongArchSubtarget.h:84
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:509
LoongArchRegisterInfo.h
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1709
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1183
llvm::LoongArchABI::ABI_ILP32D
@ ABI_ILP32D
Definition: LoongArchBaseInfo.h:29
Statistic.h
llvm::LoongArchISD::MOVGR2FR_W_LA64
@ MOVGR2FR_W_LA64
Definition: LoongArchISelLowering.h:42
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:9290
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:462
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:819
llvm::TargetLowering::DAGCombinerInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:3818
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:270
llvm::CCValAssign::Indirect
@ Indirect
Definition: CallingConvLower.h:50
R4
#define R4(n)
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
convertValVTToLocVT
static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
Definition: LoongArchISelLowering.cpp:1310
llvm::TargetLowering::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetLowering.cpp:45
llvm::LoongArchISD::BITREV_W
@ BITREV_W
Definition: LoongArchISelLowering.h:58
llvm::LoongArchSubtarget::is64Bit
bool is64Bit() const
Definition: LoongArchSubtarget.h:76
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::LoongArchABI::ABI_LP64F
@ ABI_LP64F
Definition: LoongArchBaseInfo.h:31
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:749
llvm::LoongArchISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: LoongArchISelLowering.h:27
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:7950
llvm::LoongArchABI::ABI_ILP32F
@ ABI_ILP32F
Definition: LoongArchBaseInfo.h:28
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:872
llvm::AArch64ISD::CALL
@ CALL
Definition: AArch64ISelLowering.h:52
LoongArchSubtarget.h
llvm::CallingConv::C
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
ZeroDivCheck
static cl::opt< bool > ZeroDivCheck("loongarch-check-zero-division", cl::Hidden, cl::desc("Trap on integer division by zero."), cl::init(false))
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:44
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2463
llvm::CCValAssign::getPending
static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, LocInfo HTP, unsigned ExtraInfo=0)
Definition: CallingConvLower.h:125
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:794
llvm::LoongArchISD::SLL_W
@ SLL_W
Definition: LoongArchISelLowering.h:34
llvm::LoongArchTargetLowering::LoongArchTargetLowering
LoongArchTargetLowering(const TargetMachine &TM, const LoongArchSubtarget &STI)
Definition: LoongArchISelLowering.cpp:35
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1086
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1404
ArgFPR64s
const MCPhysReg ArgFPR64s[]
Definition: LoongArchISelLowering.cpp:1018
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:462
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
KnownBits.h
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:2091
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::MipsISD::Hi
@ Hi
Definition: MipsISelLowering.h:75
llvm::ISD::ROTL
@ ROTL
Definition: ISDOpcodes.h:694
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::TargetLoweringBase::setTargetDAGCombine
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
Definition: TargetLowering.h:2455
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:761
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1404
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1008
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7900
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::EVT::getStoreSize
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: ValueTypes.h:362
llvm::SDNode::getOpcode
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
Definition: SelectionDAGNodes.h:640
llvm::TargetLowering::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: TargetLowering.h:4028
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:728
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2224
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:96
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1133
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:702
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:713
llvm::ISD::Constant
@ Constant
Definition: ISDOpcodes.h:76
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps
bool isBeforeLegalizeOps() const
Definition: TargetLowering.h:3824
llvm::LoongArchMachineFunctionInfo
LoongArchMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private Lo...
Definition: LoongArchMachineFunctionInfo.h:25
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:148
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:754
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:781
llvm::SelectionDAG::getTargetLoweringInfo
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:458
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::LoongArchISD::REVB_2H
@ REVB_2H
Definition: LoongArchISelLowering.h:55
LoongArchISelLowering.h
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:58
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1479
llvm::isShiftedMask_64
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
Definition: MathExtras.h:481
performANDCombine
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
Definition: LoongArchISelLowering.cpp:545
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3410
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::LoongArchTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: LoongArchISelLowering.cpp:437
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3812
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:692
llvm::ISD::ArgFlagsTy::isSplitEnd
bool isSplitEnd() const
Definition: TargetCallingConv.h:135
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2300
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::LoongArchABI::getTargetABI
ABI getTargetABI(StringRef ABIName)
Definition: LoongArchBaseInfo.cpp:23
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::LoongArchSubtarget::hasBasicF
bool hasBasicF() const
Definition: LoongArchSubtarget.h:77
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:153
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::LoongArchISD::FTINT
@ FTINT
Definition: LoongArchISelLowering.h:45
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:149
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
unpackFromRegLoc
static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const LoongArchTargetLowering &TLI)
Definition: LoongArchISelLowering.cpp:1268
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLArrayExtras.h:29
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:182
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:143
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1436
NODE_NAME_CASE
#define NODE_NAME_CASE(node)
llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign
Align getNonZeroOrigAlign() const
Definition: TargetCallingConv.h:160
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:698
llvm::LoongArchTargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: LoongArchISelLowering.cpp:1459
llvm::MVT::isFloatingPoint
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: MachineValueType.h:348
llvm::APInt::isSubsetOf
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
Definition: APInt.h:1207
convertLocVTToValVT
static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
Definition: LoongArchISelLowering.cpp:1250
llvm::LoongArchTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: LoongArchISelLowering.cpp:1681
llvm::DataLayout::getPrefTypeAlign
Align getPrefTypeAlign(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
Definition: DataLayout.cpp:838
llvm::TargetLowering::CallLoweringInfo::Outs
SmallVector< ISD::OutputArg, 32 > Outs
Definition: TargetLowering.h:4051
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2317
llvm::cl::opt< bool >
llvm::LoongArchSubtarget::hasBasicD
bool hasBasicD() const
Definition: LoongArchSubtarget.h:78
llvm::APFloat
Definition: APFloat.h:701
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:33
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
getPrefTypeAlign
static Align getPrefTypeAlign(EVT VT, SelectionDAG &DAG)
Definition: LoongArchISelLowering.cpp:1451
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::ISD::FP_TO_UINT
@ FP_TO_UINT
Definition: ISDOpcodes.h:820
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::TargetLowering::CallLoweringInfo::Chain
SDValue Chain
Definition: TargetLowering.h:4024
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Definition: SelectionDAG.cpp:1602
llvm::LoongArchSubtarget
Definition: LoongArchSubtarget.h:32
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:62
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:196
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:776
llvm::TargetLowering::CallLoweringInfo::CallConv
CallingConv::ID CallConv
Definition: TargetLowering.h:4045
llvm::LoongArchTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: LoongArchISelLowering.cpp:1330
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2266
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:916
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:8984
llvm::FunctionType::getParamType
Type * getParamType(unsigned i) const
Parameter type accessors.
Definition: DerivedTypes.h:135
llvm::LoongArchTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: LoongArchISelLowering.cpp:1735
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:439
llvm::TargetLowering::CallLoweringInfo::DL
SDLoc DL
Definition: TargetLowering.h:4049
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:439
llvm::CCValAssign::getMem
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:100
llvm::LoongArchISD::ROTR_W
@ ROTR_W
Definition: LoongArchISelLowering.h:39
llvm::LoongArchISD::ROTL_W
@ ROTL_W
Definition: LoongArchISelLowering.h:38
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1404
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:179
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
llvm::ISD::SETOGT
@ SETOGT
Definition: ISDOpcodes.h:1428
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:4023
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LoongArchABI::ABI
ABI
Definition: LoongArchBaseInfo.h:26
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::LoongArchTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: LoongArchISelLowering.cpp:882
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::ConstantSDNode::getZExtValue
uint64_t getZExtValue() const
Definition: SelectionDAGNodes.h:1591
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1424
llvm::ISD::EH_DWARF_CFA
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
Definition: ISDOpcodes.h:129
llvm::SelectionDAG::getMachineNode
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
Definition: SelectionDAG.cpp:9728
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::LoongArchISD::CALL
@ CALL
Definition: LoongArchISelLowering.h:30
R6
#define R6(n)
llvm::LoongArchTargetLowering
Definition: LoongArchISelLowering.h:62
llvm::LoongArchSubtarget::getGRLenVT
MVT getGRLenVT() const
Definition: LoongArchSubtarget.h:83
llvm::SelectionDAG::CreateStackTemporary
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
Definition: SelectionDAG.cpp:2312
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:750
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1087
llvm::CCState::getPendingLocs
SmallVectorImpl< CCValAssign > & getPendingLocs()
Definition: CallingConvLower.h:496
CC_LoongArch
static bool CC_LoongArch(const DataLayout &DL, LoongArchABI::ABI ABI, unsigned ValNo, MVT ValVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy)
Definition: LoongArchISelLowering.cpp:1060
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::SelectionDAG::getCALLSEQ_END
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
Definition: SelectionDAG.h:955
llvm::TargetLowering::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 32 > Ins
Definition: TargetLowering.h:4053
llvm::ISD::ConstantPool
@ ConstantPool
Definition: ISDOpcodes.h:82
llvm::CCValAssign::getValNo
unsigned getValNo() const
Definition: CallingConvLower.h:140
llvm::TargetLowering::CallLoweringInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:4048
llvm::SelectionDAG::getTargetConstantPool
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:714
customLegalizeToWOp
static SDValue customLegalizeToWOp(SDNode *N, SelectionDAG &DAG, int NumOp, unsigned ExtOpc=ISD::ANY_EXTEND)
Definition: LoongArchISelLowering.cpp:409
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1870
LoongArch.h
llvm::CCState::AllocateReg
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
Definition: CallingConvLower.h:349
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:1141
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::ConstantSDNode::getSExtValue
int64_t getSExtValue() const
Definition: SelectionDAGNodes.h:1592
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:79
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1404
llvm::CCState::getPendingArgFlags
SmallVectorImpl< ISD::ArgFlagsTy > & getPendingArgFlags()
Definition: CallingConvLower.h:501
llvm::LoongArchISD::RET
@ RET
Definition: LoongArchISelLowering.h:31
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:186
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetLowering::CallLoweringInfo::IsTailCall
bool IsTailCall
Definition: TargetLowering.h:4039
j
return j(j<< 16)
llvm::LoongArchABI::ABI_ILP32S
@ ABI_ILP32S
Definition: LoongArchBaseInfo.h:27
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1447
llvm::CCState::getFirstUnallocated
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
Definition: CallingConvLower.h:334
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:144
llvm::ISD::ArgFlagsTy::getByValSize
unsigned getByValSize() const
Definition: TargetCallingConv.h:169
performBITREV_WCombine
static SDValue performBITREV_WCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
Definition: LoongArchISelLowering.cpp:868
llvm::LoongArchTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: LoongArchISelLowering.cpp:142
llvm::SelectionDAG::computeKnownBits
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
Definition: SelectionDAG.cpp:2878
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2334
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1746
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::LoongArchISD::NodeType
NodeType
Definition: LoongArchISelLowering.h:26
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
llvm::ARCISD::RET
@ RET
Definition: ARCISelLowering.h:52
ArgFPR32s
const MCPhysReg ArgFPR32s[]
Definition: LoongArchISelLowering.cpp:1014
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:452
ISDOpcodes.h
CC_LoongArchAssign2GRLen
static bool CC_LoongArchAssign2GRLen(unsigned GRLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
Definition: LoongArchISelLowering.cpp:1024
llvm::TypeSize
Definition: TypeSize.h:435
llvm::LoongArchISD::BSTRPICK
@ BSTRPICK
Definition: LoongArchISelLowering.h:52
llvm::LoongArchISD::CTZ_W
@ CTZ_W
Definition: LoongArchISelLowering.h:49
unpackFromMemLoc
static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
Definition: LoongArchISelLowering.cpp:1285
llvm::CCState::AllocateStack
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Definition: CallingConvLower.h:423
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:199
llvm::LoongArchABI::ABI_LP64D
@ ABI_LP64D
Definition: LoongArchBaseInfo.h:32
llvm::SelectionDAG::getTargetExternalSymbol
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:1859
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::CCState::getNextStackOffset
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Definition: CallingConvLower.h:262
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
LoongArchMachineFunctionInfo.h
llvm::Function::getFunctionType
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:175
llvm::EVT::getFloatingPointVT
static EVT getFloatingPointVT(unsigned BitWidth)
Returns the EVT that represents a floating-point type with the given number of bits.
Definition: ValueTypes.h:58
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:231
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:598
llvm::LoongArchISD::SRL_W
@ SRL_W
Definition: LoongArchISelLowering.h:36
llvm::TargetLoweringBase::setLibcallName
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
Definition: TargetLowering.h:3071
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1082
llvm::TargetLowering::CallLoweringInfo::NoMerge
bool NoMerge
Definition: TargetLowering.h:4035
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:751
llvm::ISD::UINT_TO_FP
@ UINT_TO_FP
Definition: ISDOpcodes.h:774
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
performSRLCombine
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
Definition: LoongArchISelLowering.cpp:608
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2234
llvm::ISD::SETOGE
@ SETOGE
Definition: ISDOpcodes.h:1429
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
LoongArchMCTargetDesc.h
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:691
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::ISD::ArgFlagsTy::getNonZeroByValAlign
Align getNonZeroByValAlign() const
Definition: TargetCallingConv.h:153
llvm::CCValAssign::getReg
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:77
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:197
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:141
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
LoongArchTargetMachine.h
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1277
llvm::ISD::BITREVERSE
@ BITREVERSE
Definition: ISDOpcodes.h:704
llvm::TargetLoweringBase::setMaxAtomicSizeInBitsSupported
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Definition: TargetLowering.h:2490
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:693
llvm::SelectionDAG::getRegisterMask
SDValue getRegisterMask(const uint32_t *RegMask)
Definition: SelectionDAG.cpp:2106
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::TargetLoweringBase::setCondCodeAction
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
Definition: TargetLowering.h:2417
llvm::LoongArchISD::BSTRINS
@ BSTRINS
Definition: LoongArchISelLowering.h:51
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:701
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:893
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:285
insertDivByZeroTrap
static MachineBasicBlock * insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock *MBB)
Definition: LoongArchISelLowering.cpp:900
llvm::MVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
Definition: MachineValueType.h:368
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::TargetLowering::CallLoweringInfo::OutVals
SmallVector< SDValue, 32 > OutVals
Definition: TargetLowering.h:4052
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:1129
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::TargetLowering::CallLoweringInfo::Callee
SDValue Callee
Definition: TargetLowering.h:4046
llvm::DataLayout::getPointerSizeInBits
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:412
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:47
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:449
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1077
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
ArgGPRs
const MCPhysReg ArgGPRs[]
Definition: LoongArchISelLowering.cpp:1009
llvm::cl::desc
Definition: CommandLine.h:412
llvm::LoongArchISD::REVB_2W
@ REVB_2W
Definition: LoongArchISelLowering.h:56
llvm::LoongArchISD::BITREV_4B
@ BITREV_4B
Definition: LoongArchISelLowering.h:57
llvm::GlobalValue::isDSOLocal
bool isDSOLocal() const
Definition: GlobalValue.h:287
llvm::SelectionDAG::getExtLoad
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Definition: SelectionDAG.cpp:7917
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:57
llvm::FunctionType::getReturnType
Type * getReturnType() const
Definition: DerivedTypes.h:124
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:695
Debug.h
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:480
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
llvm::LoongArchISD::MOVFR2GR_S_LA64
@ MOVFR2GR_S_LA64
Definition: LoongArchISelLowering.h:43
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:353
llvm::ISD::CTPOP
@ CTPOP
Definition: ISDOpcodes.h:703
llvm::SelectionDAG::getSetCC
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:1081
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::SelectionDAG::getMergeValues
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
Definition: SelectionDAG.cpp:7664
llvm::FunctionType
Class to represent function types.
Definition: DerivedTypes.h:103
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:288
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1193
llvm::LoongArchTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: LoongArchISelLowering.cpp:1664
llvm::LoongArchISD::CLZ_W
@ CLZ_W
Definition: LoongArchISelLowering.h:48