Go to the documentation of this file.
28 #define DEBUG_TYPE "loongarch-isel-lowering"
32 cl::desc(
"Trap on integer division by zero."),
134 const Align FunctionAlignment(4);
153 switch (
Op.getOpcode()) {
155 return lowerEH_DWARF_CFA(
Op, DAG);
157 return lowerGlobalAddress(
Op, DAG);
159 return lowerShiftLeftParts(
Op, DAG);
161 return lowerShiftRightParts(
Op, DAG,
true);
163 return lowerShiftRightParts(
Op, DAG,
false);
165 return lowerConstantPool(
Op, DAG);
167 return lowerFP_TO_SINT(
Op, DAG);
169 return lowerBITCAST(
Op, DAG);
171 return lowerUINT_TO_FP(
Op, DAG);
173 return lowerVASTART(
Op, DAG);
181 auto Size = Subtarget.
getGRLen() / 8;
197 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
215 TLI.expandUINT_TO_FP(
N, Tmp1, Tmp2, DAG);
238 if (
Op.getValueSizeInBits() > 32 && Subtarget.
hasBasicF() &&
253 EVT Ty =
Op.getValueType();
260 N->getConstVal(), Ty,
N->getAlign(),
N->getOffset());
265 DL, Ty, AddrHi, ConstantN),
276 const GlobalValue *GV = cast<GlobalAddressSDNode>(
Op)->getGlobal();
277 unsigned ADDIOp = Subtarget.
is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
295 EVT VT =
Lo.getValueType();
335 EVT VT =
Lo.getValueType();
440 switch (
N->getOpcode()) {
448 "Unexpected custom legalisation");
456 if ((CN = dyn_cast<ConstantSDNode>(
N->getOperand(1)))) {
463 "Unexpected custom legalisation");
471 EVT VT =
N->getValueType(0);
473 EVT SrcVT = Src.getValueType();
484 "Unexpected custom legalisation");
487 TLI.expandFP_TO_UINT(
N, Tmp1, Tmp2, DAG);
493 EVT VT =
N->getValueType(0);
495 "Unexpected custom legalization");
516 EVT VT =
N->getValueType(0);
518 "Unexpected custom legalization");
538 "Unexpected custom legalisation");
551 SDValue FirstOperand =
N->getOperand(0);
552 SDValue SecondOperand =
N->getOperand(1);
553 unsigned FirstOperandOpc = FirstOperand.
getOpcode();
554 EVT ValTy =
N->getValueType(0);
557 unsigned SMIdx, SMLen;
563 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)) ||
574 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))))
600 NewOperand = FirstOperand;
602 msb = lsb + SMLen - 1;
620 SDValue FirstOperand =
N->getOperand(0);
622 EVT ValTy =
N->getValueType(0);
625 unsigned MaskIdx, MaskLen;
631 !(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))) ||
636 if (!(CN = dyn_cast<ConstantSDNode>(
N->getOperand(1))))
640 if (MaskIdx <= Shamt && Shamt <= MaskIdx + MaskLen - 1)
653 EVT ValTy =
N->getValueType(0);
654 SDValue N0 =
N->getOperand(0), N1 =
N->getOperand(1);
658 unsigned MaskIdx0, MaskLen0, MaskIdx1, MaskLen1;
660 bool SwapAndRetried =
false;
665 if (ValBits != 32 && ValBits != 64)
675 (CN0 = dyn_cast<ConstantSDNode>(N0.
getOperand(1))) &&
678 (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
680 MaskIdx0 == MaskIdx1 && MaskLen0 == MaskLen1 &&
681 (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(1))) &&
683 (MaskIdx0 + MaskLen0 <= ValBits)) {
697 (CN0 = dyn_cast<ConstantSDNode>(N0.
getOperand(1))) &&
700 (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
702 (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(1))) &&
704 MaskLen0 == MaskLen1 && MaskIdx1 == 0 &&
705 (MaskIdx0 + MaskLen0 <= ValBits)) {
720 (CN0 = dyn_cast<ConstantSDNode>(N0.
getOperand(1))) &&
722 (MaskIdx0 + MaskLen0 <= 64) &&
723 (CN1 = dyn_cast<ConstantSDNode>(N1->getOperand(1))) &&
730 ? (MaskIdx0 + (MaskLen0 & 31) - 1)
731 : (MaskIdx0 + MaskLen0 - 1),
743 (CN0 = dyn_cast<ConstantSDNode>(N0.
getOperand(1))) &&
745 MaskIdx0 == 0 && (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
747 (MaskIdx0 + MaskLen0 <= ValBits)) {
762 (CN0 = dyn_cast<ConstantSDNode>(N0.
getOperand(1))) &&
764 (CN1 = dyn_cast<ConstantSDNode>(N1)) &&
784 unsigned MaskIdx, MaskLen;
785 if (N1.getOpcode() ==
ISD::SHL && N1.getOperand(0).getOpcode() ==
ISD::AND &&
786 (CNMask = dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(1))) &&
788 MaskIdx == 0 && (CNShamt = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
810 (CNMask = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
812 N1.getOperand(0).getOpcode() ==
ISD::SHL &&
813 (CNShamt = dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(1))) &&
826 if (!SwapAndRetried) {
828 SwapAndRetried =
true;
832 SwapAndRetried =
false;
844 (CNMask = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
858 if (!SwapAndRetried) {
860 SwapAndRetried =
true;
885 switch (
N->getOpcode()) {
922 SinkMBB->splice(SinkMBB->end(),
MBB, std::next(
MI.getIterator()),
MBB->
end());
923 SinkMBB->transferSuccessorsAndUpdatePHIs(
MBB);
941 BreakMBB->addSuccessor(SinkMBB);
952 switch (
MI.getOpcode()) {
955 case LoongArch::DIV_W:
956 case LoongArch::DIV_WU:
957 case LoongArch::MOD_W:
958 case LoongArch::MOD_WU:
959 case LoongArch::DIV_D:
960 case LoongArch::DIV_DU:
961 case LoongArch::MOD_D:
962 case LoongArch::MOD_DU:
973 #define NODE_NAME_CASE(node) \
974 case LoongArchISD::node: \
975 return "LoongArchISD::" #node;
997 #undef NODE_NAME_CASE
1010 LoongArch::R7, LoongArch::R8, LoongArch::R9,
1011 LoongArch::R10, LoongArch::R11};
1015 LoongArch::F3, LoongArch::F4, LoongArch::F5,
1016 LoongArch::F6, LoongArch::F7};
1019 LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64,
1020 LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64};
1026 unsigned ValNo2,
MVT ValVT2,
MVT LocVT2,
1028 unsigned GRLenInBytes = GRLen / 8;
1061 unsigned ValNo,
MVT ValVT,
1063 CCState &State,
bool IsFixed,
bool IsRet,
1065 unsigned GRLen =
DL.getLargestLegalIntTypeSizeInBits();
1066 assert((GRLen == 32 || GRLen == 64) &&
"Unspport GRLen");
1072 if (IsRet && ValNo > 1)
1076 bool UseGPRForFloat =
true;
1089 UseGPRForFloat = !IsFixed;
1095 UseGPRForFloat =
true;
1097 if (UseGPRForFloat && ValVT ==
MVT::f32) {
1100 }
else if (UseGPRForFloat && GRLen == 64 && ValVT ==
MVT::f64) {
1103 }
else if (UseGPRForFloat && GRLen == 32 && ValVT ==
MVT::f64) {
1114 unsigned TwoGRLenInBytes = (2 * GRLen) / 8;
1116 DL.getTypeAllocSize(OrigTy) == TwoGRLenInBytes) {
1127 assert(PendingLocs.size() == PendingArgFlags.size() &&
1128 "PendingLocs and PendingArgFlags out of sync");
1135 PendingLocs.push_back(
1137 PendingArgFlags.push_back(ArgFlags);
1146 PendingLocs.size() <= 2) {
1147 assert(PendingLocs.size() == 2 &&
"Unexpected PendingLocs.size()");
1152 PendingLocs.
clear();
1153 PendingArgFlags.
clear();
1160 unsigned StoreSizeBytes = GRLen / 8;
1163 if (ValVT ==
MVT::f32 && !UseGPRForFloat)
1165 else if (ValVT ==
MVT::f64 && !UseGPRForFloat)
1175 if (!PendingLocs.empty()) {
1177 assert(PendingLocs.size() > 2 &&
"Unexpected PendingLocs.size()");
1178 for (
auto &It : PendingLocs) {
1180 It.convertToReg(
Reg);
1185 PendingLocs.clear();
1186 PendingArgFlags.
clear();
1189 assert((!UseGPRForFloat || LocVT == GRLenVT) &&
1190 "Expected an GRLenVT at this stage");
1207 void LoongArchTargetLowering::analyzeInputArgs(
1210 LoongArchCCAssignFn Fn)
const {
1212 for (
unsigned i = 0,
e =
Ins.size();
i !=
e; ++
i) {
1214 Type *ArgTy =
nullptr;
1217 else if (
Ins[
i].isOrigArg())
1222 CCInfo,
true, IsRet, ArgTy)) {
1224 <<
EVT(ArgVT).getEVTString() <<
'\n');
1230 void LoongArchTargetLowering::analyzeOutputArgs(
1233 CallLoweringInfo *CLI, LoongArchCCAssignFn Fn)
const {
1234 for (
unsigned i = 0,
e = Outs.size();
i !=
e; ++
i) {
1235 MVT ArgVT = Outs[
i].VT;
1236 Type *OrigTy = CLI ? CLI->getArgs()[Outs[
i].OrigArgIndex].Ty :
nullptr;
1240 CCInfo, Outs[
i].IsFixed, IsRet, OrigTy)) {
1242 <<
EVT(ArgVT).getEVTString() <<
"\n");
1346 unsigned GRLenInBytes = Subtarget.
getGRLen() / 8;
1348 std::vector<SDValue> OutChains;
1356 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
1368 unsigned ArgIndex =
Ins[
i].OrigArgIndex;
1369 unsigned ArgPartOffset =
Ins[
i].PartOffset;
1370 assert(ArgPartOffset == 0);
1371 while (
i + 1 !=
e &&
Ins[
i + 1].OrigArgIndex == ArgIndex) {
1373 unsigned PartOffset =
Ins[
i + 1].PartOffset - ArgPartOffset;
1382 InVals.push_back(ArgValue);
1396 int VaArgOffset, VarArgsSaveSize;
1400 if (ArgRegs.
size() == Idx) {
1402 VarArgsSaveSize = 0;
1404 VarArgsSaveSize = GRLenInBytes * (ArgRegs.
size() - Idx);
1405 VaArgOffset = -VarArgsSaveSize;
1411 LoongArchFI->setVarArgsFrameIndex(FI);
1419 VarArgsSaveSize += GRLenInBytes;
1424 for (
unsigned I = Idx;
I < ArgRegs.
size();
1425 ++
I, VaArgOffset += GRLenInBytes) {
1433 cast<StoreSDNode>(
Store.getNode())
1435 ->setValue((
Value *)
nullptr);
1436 OutChains.push_back(
Store);
1438 LoongArchFI->setVarArgsSaveSize(VarArgsSaveSize);
1443 if (!OutChains.empty()) {
1444 OutChains.push_back(Chain);
1480 analyzeOutputArgs(MF, ArgCCInfo, Outs,
false, &CLI,
CC_LoongArch);
1487 for (
unsigned i = 0,
e = Outs.size();
i !=
e; ++
i) {
1501 Chain = DAG.
getMemcpy(Chain,
DL, FIPtr,
Arg, SizeNode, Alignment,
1505 ByValArgs.push_back(FIPtr);
1514 for (
unsigned i = 0,
j = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
1529 unsigned ArgIndex = Outs[
i].OrigArgIndex;
1530 unsigned ArgPartOffset = Outs[
i].PartOffset;
1531 assert(ArgPartOffset == 0);
1536 while (
i + 1 !=
e && Outs[
i + 1].OrigArgIndex == ArgIndex) {
1537 SDValue PartValue = OutVals[
i + 1];
1538 unsigned PartOffset = Outs[
i + 1].PartOffset - ArgPartOffset;
1544 Parts.push_back(std::make_pair(PartValue, Offset));
1548 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1549 MemOpChains.push_back(
1552 for (
const auto &Part : Parts) {
1553 SDValue PartValue = Part.first;
1554 SDValue PartOffset = Part.second;
1557 MemOpChains.push_back(
1561 ArgValue = SpillSlot;
1568 ArgValue = ByValArgs[
j++];
1572 RegsToPass.push_back(std::make_pair(VA.
getLocReg(), ArgValue));
1577 if (!StackPtr.getNode())
1584 MemOpChains.push_back(
1590 if (!MemOpChains.empty())
1596 for (
auto &
Reg : RegsToPass) {
1612 Ops.push_back(Chain);
1617 for (
auto &
Reg : RegsToPass)
1623 assert(
Mask &&
"Missing call preserved mask for calling convention");
1628 Ops.push_back(Glue);
1648 for (
auto &VA : RVLocs) {
1658 InVals.push_back(RetValue);
1670 for (
unsigned i = 0,
e = Outs.size();
i !=
e; ++
i) {
1674 Outs[
i].Flags, CCInfo,
true,
true,
1700 for (
unsigned i = 0,
e = RVLocs.size();
i <
e; ++
i) {
1717 RetOps.push_back(Glue);
1722 bool LoongArchTargetLowering::isFPImmLegal(
const APFloat &
Imm,
EVT VT,
1723 bool ForCodeSize)
const {
1730 return (
Imm.isZero() ||
Imm.isExactlyValue(+1.0));
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
const LoongArchRegisterInfo * getRegisterInfo() const override
static LoongArchISD::NodeType getLoongArchWOpcode(unsigned Opcode)
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Generic address nodes are lowered to some combination of target independent and machine specific ABI
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addNoMergeSiteInfo(const SDNode *Node, bool NoMerge)
Set NoMergeSiteInfo to be associated with Node if NoMerge is true.
CCState - This class holds information needed while lowering arguments and return values.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
SDNode * getNode() const
get the SDNode which holds the desired result
@ BSWAP
Byte Swap and Counting operators.
virtual const TargetInstrInfo * getInstrInfo() const
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
void addLoc(const CCValAssign &V)
unsigned getGRLen() const
void setIsKill(bool Val=true)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Reg
All possible values of the reg field in the ModR/M byte.
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Represents one node in the SelectionDAG.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
bool isPositionIndependent() const
The instances of the Type class are immutable: once they are created, they are never changed.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void insert(iterator MBBI, MachineBasicBlock *MBB)
@ C
The default llvm calling convention, compatible with C.
static cl::opt< bool > ZeroDivCheck("loongarch-check-zero-division", cl::Hidden, cl::desc("Trap on integer division by zero."), cl::init(false))
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, LocInfo HTP, unsigned ExtraInfo=0)
Function Alias Analysis Results
LoongArchTargetLowering(const TargetMachine &TM, const LoongArchSubtarget &STI)
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
const MCPhysReg ArgFPR64s[]
unsigned const TargetRegisterInfo * TRI
LLVMContext * getContext() const
SDValue getRegister(unsigned Reg, EVT VT)
LLVM Basic Block Representation.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
@ BR_CC
BR_CC - Conditional branch.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
TargetInstrInfo - Interface to description of machine instruction set.
EVT getValueType() const
Return the ValueType of the referenced return value.
CCValAssign - Represent assignment of one arg/retval to a location.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
bool isBeforeLegalizeOps() const
LoongArchMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private Lo...
Register getLocReg() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
const TargetLowering & getTargetLoweringInfo() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
const HexagonInstrInfo * TII
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
MachineOperand class - Representation of each machine instruction operand.
ABI getTargetABI(StringRef ABIName)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
@ AND
Bitwise operators - logical and, logical or, logical xor.
LocInfo getLocInfo() const
unsigned getLocMemOffset() const
This struct is a compact representation of a valid (non-zero power of two) alignment.
static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const LoongArchTargetLowering &TLI)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
#define NODE_NAME_CASE(node)
Align getNonZeroOrigAlign() const
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Align getPrefTypeAlign(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
SmallVector< ISD::OutputArg, 32 > Outs
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
static Align getPrefTypeAlign(EVT VT, SelectionDAG &DAG)
Representation of each machine instruction.
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
This class contains a discriminated union of information about pointers in memory operands,...
This is an important class for using LLVM in a threaded context.
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
const SDValue & getOperand(unsigned Num) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Type * getParamType(unsigned i) const
Parameter type accessors.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
initializer< Ty > init(const Ty &Val)
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
SDValue getValue(unsigned R) const
This structure contains all information that is necessary for lowering calls.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
uint64_t getZExtValue() const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SmallVectorImpl< CCValAssign > & getPendingLocs()
static bool CC_LoongArch(const DataLayout &DL, LoongArchABI::ABI ABI, unsigned ValNo, MVT ValVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy)
Class for arbitrary precision integers.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SmallVector< ISD::InputArg, 32 > Ins
unsigned getValNo() const
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0)
static SDValue customLegalizeToWOp(SDNode *N, SelectionDAG &DAG, int NumOp, unsigned ExtOpc=ISD::ANY_EXTEND)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
const SDValue & getOperand(unsigned i) const
self_iterator getIterator()
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
int64_t getSExtValue() const
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SmallVectorImpl< ISD::ArgFlagsTy > & getPendingArgFlags()
Wrapper class representing virtual and physical registers.
amdgpu Simplify well known AMD library false FunctionCallee Callee
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
unsigned getByValSize() const
static SDValue performBITREV_WCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Function & getFunction()
Return the LLVM function that this machine code represents.
Iterator for intrusive lists based on ilist_node.
const MCPhysReg ArgFPR32s[]
const DataLayout & getDataLayout() const
static bool CC_LoongArchAssign2GRLen(unsigned GRLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
FunctionType * getFunctionType() const
Returns the FunctionType for me.
static EVT getFloatingPointVT(unsigned BitWidth)
Returns the EVT that represents a floating-point type with the given number of bits.
@ ZeroOrOneBooleanContent
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ ADD
Simple integer binary arithmetic operators.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
unsigned getKillRegState(bool B)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
@ SHL
Shift and rotation operations.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Align getNonZeroByValAlign() const
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
SDValue getRegisterMask(const uint32_t *RegMask)
size_t size() const
size - Get the array size.
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
static MachineBasicBlock * insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock *MBB)
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
SmallVector< SDValue, 32 > OutVals
unsigned getOpcode() const
const char LLVMTargetMachineRef TM
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
MachineFunction & getMachineFunction() const
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
const MCPhysReg ArgGPRs[]
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Type * getReturnType() const
LLVM Value Representation.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
Class to represent function types.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static MVT getIntegerVT(unsigned BitWidth)
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...