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LoongArchISelLowering.h
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1//=- LoongArchISelLowering.h - LoongArch DAG Lowering Interface -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that LoongArch uses to lower LLVM code into
10// a selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H
15#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H
16
17#include "LoongArch.h"
21
22namespace llvm {
23class LoongArchSubtarget;
24namespace LoongArchISD {
25enum NodeType : unsigned {
27
28 // TODO: add more LoongArchISDs
36
37 // 32-bit shifts, directly matching the semantics of the named LoongArch
38 // instructions.
42
45
46 // FPR<->GPR transfer operations
51
53
54 // Bit counting operations
57
60
61 // Byte-swapping and bit-reversal
66
67 // Intrinsic operations start ============================================
74
75 // CRC check operations
84
86
87 // Write new value to CSR and return old value.
88 // Operand 0: A chain pointer.
89 // Operand 1: The new value to write.
90 // Operand 2: The address of the required CSR.
91 // Result 0: The old value of the CSR.
92 // Result 1: The new chain pointer.
94
95 // Similar to CSRWR but with a write mask.
96 // Operand 0: A chain pointer.
97 // Operand 1: The new value to write.
98 // Operand 2: The write mask.
99 // Operand 3: The address of the required CSR.
100 // Result 0: The old value of the CSR.
101 // Result 1: The new chain pointer.
103
104 // IOCSR access operations
113
114 // Read CPU configuration information operation
116
117 // Vector Shuffle
119
120 // Extended vector element extraction
123
124 // Vector comparisons
129
130 // Intrinsic operations end =============================================
131};
132} // end namespace LoongArchISD
133
135 const LoongArchSubtarget &Subtarget;
136
137public:
139 const LoongArchSubtarget &STI);
140
141 const LoongArchSubtarget &getSubtarget() const { return Subtarget; }
142
143 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
144
145 // Provide custom lowering hooks for some operations.
146 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
148 SelectionDAG &DAG) const override;
149
150 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
151
152 // This method returns the name of a target specific DAG node.
153 const char *getTargetNodeName(unsigned Opcode) const override;
154
155 // Lower incoming arguments, copy physregs into vregs.
157 bool IsVarArg,
159 const SDLoc &DL, SelectionDAG &DAG,
160 SmallVectorImpl<SDValue> &InVals) const override;
162 bool IsVarArg,
164 LLVMContext &Context) const override;
165 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
167 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
168 SelectionDAG &DAG) const override;
170 SmallVectorImpl<SDValue> &InVals) const override;
171 bool isCheapToSpeculateCttz(Type *Ty) const override;
172 bool isCheapToSpeculateCtlz(Type *Ty) const override;
173 bool hasAndNot(SDValue Y) const override;
175 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
176
178 Value *AlignedAddr, Value *Incr,
179 Value *Mask, Value *ShiftAmt,
180 AtomicOrdering Ord) const override;
181
183 EVT VT) const override;
188 Value *AlignedAddr, Value *CmpVal,
189 Value *NewVal, Value *Mask,
190 AtomicOrdering Ord) const override;
191
192 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
193 MachineFunction &MF,
194 unsigned Intrinsic) const override;
195
197 EVT VT) const override;
198
200 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
201
203 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
204
206 return ISD::SIGN_EXTEND;
207 }
208
209 Register getRegisterByName(const char *RegName, LLT VT,
210 const MachineFunction &MF) const override;
211 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
212
213 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
214 SDValue C) const override;
215
216 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
217
218 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
219 unsigned AS,
220 Instruction *I = nullptr) const override;
221
222 bool isLegalICmpImmediate(int64_t Imm) const override;
223 bool isLegalAddImmediate(int64_t Imm) const override;
224 bool isZExtFree(SDValue Val, EVT VT2) const override;
225 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
226
227 bool hasAndNotCompare(SDValue Y) const override;
228
229 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
230
232 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
234 unsigned *Fast = nullptr) const override;
235
236 bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override {
237 return false;
238 }
239
240private:
241 /// Target-specific function used to lower LoongArch calling conventions.
242 typedef bool LoongArchCCAssignFn(const DataLayout &DL, LoongArchABI::ABI ABI,
243 unsigned ValNo, MVT ValVT,
244 CCValAssign::LocInfo LocInfo,
245 ISD::ArgFlagsTy ArgFlags, CCState &State,
246 bool IsFixed, bool IsReg, Type *OrigTy);
247
248 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
249 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
250 LoongArchCCAssignFn Fn) const;
251 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
253 bool IsRet, CallLoweringInfo *CLI,
254 LoongArchCCAssignFn Fn) const;
255
256 template <class NodeTy>
257 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, CodeModel::Model M,
258 bool IsLocal = true) const;
259 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
260 unsigned Opc, bool Large = false) const;
261 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
262 unsigned Opc, bool Large = false) const;
263 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
264 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
265 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
266 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
267 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
268 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
269
271 EmitInstrWithCustomInserter(MachineInstr &MI,
272 MachineBasicBlock *BB) const override;
273 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
274 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
275 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
276 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
277 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
278 SDValue lowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
279 SDValue lowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
280 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
281 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
282 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
283 SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
284 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
285 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
286 SDValue lowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) const;
287 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
288 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
289 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
290 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
291
292 bool isFPImmLegal(const APFloat &Imm, EVT VT,
293 bool ForCodeSize) const override;
294
295 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
296
297 ConstraintType getConstraintType(StringRef Constraint) const override;
298
300 getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
301
302 std::pair<unsigned, const TargetRegisterClass *>
303 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
304 StringRef Constraint, MVT VT) const override;
305
306 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
307 std::vector<SDValue> &Ops,
308 SelectionDAG &DAG) const override;
309
310 bool isEligibleForTailCallOptimization(
311 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
312 const SmallVectorImpl<CCValAssign> &ArgLocs) const;
313};
314
315} // end namespace llvm
316
317#endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
IRTranslator LLVM IR MI
#define RegName(no)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:539
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:748
CCState - This class holds information needed while lowering arguments and return values.
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override
Return true if result of the specified node is used by a return node only.
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
const LoongArchSubtarget & getSubtarget() const
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:69
Flags
Flags values. These may be or'd together.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1389
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:774
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
AtomicOrdering
Atomic ordering for LLVM's memory model.
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
This structure contains all information that is necessary for lowering calls.