LLVM 18.0.0git
LoongArchISelLowering.h
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1//=- LoongArchISelLowering.h - LoongArch DAG Lowering Interface -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that LoongArch uses to lower LLVM code into
10// a selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H
15#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H
16
17#include "LoongArch.h"
21
22namespace llvm {
23class LoongArchSubtarget;
24struct LoongArchRegisterInfo;
25namespace LoongArchISD {
26enum NodeType : unsigned {
28
29 // TODO: add more LoongArchISDs
33
34 // 32-bit shifts, directly matching the semantics of the named LoongArch
35 // instructions.
39
42
43 // FPR<->GPR transfer operations
48
50
51 // Bit counting operations
54
57
58 // Byte-swapping and bit-reversal
63
64 // Intrinsic operations start ============================================
71
72 // CRC check operations
81
83
84 // Write new value to CSR and return old value.
85 // Operand 0: A chain pointer.
86 // Operand 1: The new value to write.
87 // Operand 2: The address of the required CSR.
88 // Result 0: The old value of the CSR.
89 // Result 1: The new chain pointer.
91
92 // Similar to CSRWR but with a write mask.
93 // Operand 0: A chain pointer.
94 // Operand 1: The new value to write.
95 // Operand 2: The write mask.
96 // Operand 3: The address of the required CSR.
97 // Result 0: The old value of the CSR.
98 // Result 1: The new chain pointer.
100
101 // IOCSR access operations
110
111 // Read CPU configuration information operation
113
114 // Vector Shuffle
116
117 // Extended vector element extraction
120
121 // Vector comparisons
126
127 // Intrinsic operations end =============================================
128};
129} // end namespace LoongArchISD
130
132 const LoongArchSubtarget &Subtarget;
133
134public:
136 const LoongArchSubtarget &STI);
137
138 const LoongArchSubtarget &getSubtarget() const { return Subtarget; }
139
140 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
141
142 // Provide custom lowering hooks for some operations.
143 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
145 SelectionDAG &DAG) const override;
146
147 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
148
149 // This method returns the name of a target specific DAG node.
150 const char *getTargetNodeName(unsigned Opcode) const override;
151
152 // Lower incoming arguments, copy physregs into vregs.
154 bool IsVarArg,
156 const SDLoc &DL, SelectionDAG &DAG,
157 SmallVectorImpl<SDValue> &InVals) const override;
159 bool IsVarArg,
161 LLVMContext &Context) const override;
162 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
164 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
165 SelectionDAG &DAG) const override;
167 SmallVectorImpl<SDValue> &InVals) const override;
168 bool isCheapToSpeculateCttz(Type *Ty) const override;
169 bool isCheapToSpeculateCtlz(Type *Ty) const override;
170 bool hasAndNot(SDValue Y) const override;
172 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
173
175 Value *AlignedAddr, Value *Incr,
176 Value *Mask, Value *ShiftAmt,
177 AtomicOrdering Ord) const override;
178
180 EVT VT) const override;
185 Value *AlignedAddr, Value *CmpVal,
186 Value *NewVal, Value *Mask,
187 AtomicOrdering Ord) const override;
188
189 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
190 MachineFunction &MF,
191 unsigned Intrinsic) const override;
192
194 EVT VT) const override;
195
197 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
198
200 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
201
203 return ISD::SIGN_EXTEND;
204 }
205
206 Register getRegisterByName(const char *RegName, LLT VT,
207 const MachineFunction &MF) const override;
208 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
209
210 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
211 SDValue C) const override;
212
213 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
214
215 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
216 unsigned AS,
217 Instruction *I = nullptr) const override;
218
219 bool isLegalICmpImmediate(int64_t Imm) const override;
220 bool isLegalAddImmediate(int64_t Imm) const override;
221 bool isZExtFree(SDValue Val, EVT VT2) const override;
222 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
223
224 bool hasAndNotCompare(SDValue Y) const override;
225
226 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
227
229 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
231 unsigned *Fast = nullptr) const override;
232
233private:
234 /// Target-specific function used to lower LoongArch calling conventions.
235 typedef bool LoongArchCCAssignFn(const DataLayout &DL, LoongArchABI::ABI ABI,
236 unsigned ValNo, MVT ValVT,
237 CCValAssign::LocInfo LocInfo,
238 ISD::ArgFlagsTy ArgFlags, CCState &State,
239 bool IsFixed, bool IsReg, Type *OrigTy);
240
241 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
242 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
243 LoongArchCCAssignFn Fn) const;
244 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
246 bool IsRet, CallLoweringInfo *CLI,
247 LoongArchCCAssignFn Fn) const;
248
249 template <class NodeTy>
250 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
251 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
252 unsigned Opc, bool Large = false) const;
253 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
254 unsigned Opc, bool Large = false) const;
255 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
256 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
257 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
258 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
259 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
260 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
261
263 EmitInstrWithCustomInserter(MachineInstr &MI,
264 MachineBasicBlock *BB) const override;
265 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
266 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
267 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
268 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
269 SDValue lowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
270 SDValue lowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
271 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
272 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
273 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
274 SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
275 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
276 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
277 SDValue lowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) const;
278
279 bool isFPImmLegal(const APFloat &Imm, EVT VT,
280 bool ForCodeSize) const override;
281
282 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
283
284 ConstraintType getConstraintType(StringRef Constraint) const override;
285
287 getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
288
289 std::pair<unsigned, const TargetRegisterClass *>
290 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
291 StringRef Constraint, MVT VT) const override;
292
293 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
294 std::vector<SDValue> &Ops,
295 SelectionDAG &DAG) const override;
296
297 bool isEligibleForTailCallOptimization(
298 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
299 const SmallVectorImpl<CCValAssign> &ArgLocs) const;
300};
301
302} // end namespace llvm
303
304#endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
IRTranslator LLVM IR MI
#define RegName(no)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:513
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
CCState - This class holds information needed while lowering arguments and return values.
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override
Return true if result of the specified node is used by a return node only.
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
const LoongArchSubtarget & getSubtarget() const
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags
Flags values. These may be or'd together.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1380
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:774
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
AtomicOrdering
Atomic ordering for LLVM's memory model.
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
This structure contains all information that is necessary for lowering calls.