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1//=- LoongArchISelLowering.h - LoongArch DAG Lowering Interface -*- C++ -*-===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9// This file defines the interfaces that LoongArch uses to lower LLVM code into
10// a selection DAG.
17#include "LoongArch.h"
22namespace llvm {
23class LoongArchSubtarget;
24struct LoongArchRegisterInfo;
25namespace LoongArchISD {
26enum NodeType : unsigned {
29 // TODO: add more LoongArchISDs
34 // 32-bit shifts, directly matching the semantics of the named LoongArch
35 // instructions.
43 // FPR<->GPR transfer operations
51 // Bit counting operations
58 // Byte-swapping and bit-reversal
64 // Intrinsic operations start ============================================
72 // CRC check operations
86 // IOCSR access operations
96 // Read CPU configuration information operation
98 // Intrinsic operations end =============================================
100} // end namespace LoongArchISD
103 const LoongArchSubtarget &Subtarget;
107 const LoongArchSubtarget &STI);
109 const LoongArchSubtarget &getSubtarget() const { return Subtarget; }
111 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
113 // Provide custom lowering hooks for some operations.
114 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
116 SelectionDAG &DAG) const override;
118 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
120 // This method returns the name of a target specific DAG node.
121 const char *getTargetNodeName(unsigned Opcode) const override;
123 // Lower incoming arguments, copy physregs into vregs.
125 bool IsVarArg,
127 const SDLoc &DL, SelectionDAG &DAG,
128 SmallVectorImpl<SDValue> &InVals) const override;
130 bool IsVarArg,
132 LLVMContext &Context) const override;
133 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
135 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
136 SelectionDAG &DAG) const override;
138 SmallVectorImpl<SDValue> &InVals) const override;
139 bool isCheapToSpeculateCttz(Type *Ty) const override;
140 bool isCheapToSpeculateCtlz(Type *Ty) const override;
141 bool hasAndNot(SDValue Y) const override;
143 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
146 Value *AlignedAddr, Value *Incr,
147 Value *Mask, Value *ShiftAmt,
148 AtomicOrdering Ord) const override;
151 EVT VT) const override;
156 Value *AlignedAddr, Value *CmpVal,
157 Value *NewVal, Value *Mask,
158 AtomicOrdering Ord) const override;
160 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
161 MachineFunction &MF,
162 unsigned Intrinsic) const override;
165 EVT VT) const override;
168 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
171 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
174 return ISD::SIGN_EXTEND;
175 }
177 Register getRegisterByName(const char *RegName, LLT VT,
178 const MachineFunction &MF) const override;
179 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
181 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
182 SDValue C) const override;
184 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
186 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
187 unsigned AS,
188 Instruction *I = nullptr) const override;
190 bool hasAndNotCompare(SDValue Y) const override;
192 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
195 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
197 unsigned *Fast = nullptr) const override;
200 /// Target-specific function used to lower LoongArch calling conventions.
201 typedef bool LoongArchCCAssignFn(const DataLayout &DL, LoongArchABI::ABI ABI,
202 unsigned ValNo, MVT ValVT,
203 CCValAssign::LocInfo LocInfo,
204 ISD::ArgFlagsTy ArgFlags, CCState &State,
205 bool IsFixed, bool IsReg, Type *OrigTy);
207 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
208 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
209 LoongArchCCAssignFn Fn) const;
210 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
212 bool IsRet, CallLoweringInfo *CLI,
213 LoongArchCCAssignFn Fn) const;
215 template <class NodeTy>
216 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
217 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
218 unsigned Opc) const;
219 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
220 unsigned Opc) const;
221 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
222 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
223 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
224 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
225 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
226 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
229 EmitInstrWithCustomInserter(MachineInstr &MI,
230 MachineBasicBlock *BB) const override;
231 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
232 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
233 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
234 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
235 SDValue lowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
236 SDValue lowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
237 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
238 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
239 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
240 SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
241 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
242 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
243 SDValue lowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) const;
245 bool isFPImmLegal(const APFloat &Imm, EVT VT,
246 bool ForCodeSize) const override;
248 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
250 ConstraintType getConstraintType(StringRef Constraint) const override;
252 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
254 std::pair<unsigned, const TargetRegisterClass *>
255 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
256 StringRef Constraint, MVT VT) const override;
258 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
259 std::vector<SDValue> &Ops,
260 SelectionDAG &DAG) const override;
262 bool isEligibleForTailCallOptimization(
263 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
264 const SmallVectorImpl<CCValAssign> &ArgLocs) const;
267} // end namespace llvm
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
IRTranslator LLVM IR MI
#define RegName(no)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
@ Flags
Definition: TextStubV5.cpp:93
Definition: TextStubV5.cpp:100
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:513
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
CCState - This class holds information needed while lowering arguments and return values.
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override
Return true if result of the specified node is used by a return node only.
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
const LoongArchSubtarget & getSubtarget() const
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags values. These may be or'd together.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1351
Conversion operators.
Definition: ISDOpcodes.h:774
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Atomic ordering for LLVM's memory model.
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
This structure contains all information that is necessary for lowering calls.