LLVM 19.0.0git
LoongArchRegisterInfo.cpp
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1//===- LoongArchRegisterInfo.cpp - LoongArch Register Information -*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the LoongArch implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
15#include "LoongArch.h"
16#include "LoongArchInstrInfo.h"
17#include "LoongArchSubtarget.h"
27
28using namespace llvm;
29
30#define GET_REGINFO_TARGET_DESC
31#include "LoongArchGenRegisterInfo.inc"
32
34 : LoongArchGenRegisterInfo(LoongArch::R1, /*DwarfFlavour*/ 0,
35 /*EHFlavor*/ 0,
36 /*PC*/ 0, HwMode) {}
37
38const MCPhysReg *
40 auto &Subtarget = MF->getSubtarget<LoongArchSubtarget>();
41
43 return CSR_NoRegs_SaveList;
44 switch (Subtarget.getTargetABI()) {
45 default:
46 llvm_unreachable("Unrecognized ABI");
49 return CSR_ILP32S_LP64S_SaveList;
52 return CSR_ILP32F_LP64F_SaveList;
55 return CSR_ILP32D_LP64D_SaveList;
56 }
57}
58
59const uint32_t *
61 CallingConv::ID CC) const {
62 auto &Subtarget = MF.getSubtarget<LoongArchSubtarget>();
63
64 if (CC == CallingConv::GHC)
65 return CSR_NoRegs_RegMask;
66 switch (Subtarget.getTargetABI()) {
67 default:
68 llvm_unreachable("Unrecognized ABI");
71 return CSR_ILP32S_LP64S_RegMask;
74 return CSR_ILP32F_LP64F_RegMask;
77 return CSR_ILP32D_LP64D_RegMask;
78 }
79}
80
82 return CSR_NoRegs_RegMask;
83}
84
87 const LoongArchFrameLowering *TFI = getFrameLowering(MF);
88 BitVector Reserved(getNumRegs());
89
90 // Use markSuperRegs to ensure any register aliases are also reserved
91 markSuperRegs(Reserved, LoongArch::R0); // zero
92 markSuperRegs(Reserved, LoongArch::R2); // tp
93 markSuperRegs(Reserved, LoongArch::R3); // sp
94 markSuperRegs(Reserved, LoongArch::R21); // non-allocatable
95 if (TFI->hasFP(MF))
96 markSuperRegs(Reserved, LoongArch::R22); // fp
97 // Reserve the base register if we need to realign the stack and allocate
98 // variable-sized objects at runtime.
99 if (TFI->hasBP(MF))
100 markSuperRegs(Reserved, LoongArchABI::getBPReg()); // bp
101
102 assert(checkAllSuperRegsMarked(Reserved));
103 return Reserved;
104}
105
108 const TargetFrameLowering *TFI = getFrameLowering(MF);
109 return TFI->hasFP(MF) ? LoongArch::R22 : LoongArch::R3;
110}
111
113 int SPAdj,
114 unsigned FIOperandNum,
115 RegScavenger *RS) const {
116 // TODO: this implementation is a temporary placeholder which does just
117 // enough to allow other aspects of code generation to be tested.
118
119 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
120
121 MachineInstr &MI = *II;
122 assert(MI.getOperand(FIOperandNum + 1).isImm() &&
123 "Unexpected FI-consuming insn");
124
125 MachineBasicBlock &MBB = *MI.getParent();
126 MachineFunction &MF = *MI.getParent()->getParent();
129 const LoongArchInstrInfo *TII = STI.getInstrInfo();
131 DebugLoc DL = MI.getDebugLoc();
132 bool IsLA64 = STI.is64Bit();
133 unsigned MIOpc = MI.getOpcode();
134
135 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
136 Register FrameReg;
138 TFI->getFrameIndexReference(MF, FrameIndex, FrameReg) +
139 StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
140
141 bool FrameRegIsKill = false;
142
143 if (!isInt<12>(Offset.getFixed())) {
144 unsigned Addi = IsLA64 ? LoongArch::ADDI_D : LoongArch::ADDI_W;
145 unsigned Add = IsLA64 ? LoongArch::ADD_D : LoongArch::ADD_W;
146
147 // The offset won't fit in an immediate, so use a scratch register instead.
148 // Modify Offset and FrameReg appropriately.
149 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass);
150 TII->movImm(MBB, II, DL, ScratchReg, Offset.getFixed());
151 if (MIOpc == Addi) {
152 BuildMI(MBB, II, DL, TII->get(Add), MI.getOperand(0).getReg())
153 .addReg(FrameReg)
154 .addReg(ScratchReg, RegState::Kill);
155 MI.eraseFromParent();
156 return true;
157 }
158 BuildMI(MBB, II, DL, TII->get(Add), ScratchReg)
159 .addReg(FrameReg)
160 .addReg(ScratchReg, RegState::Kill);
162 FrameReg = ScratchReg;
163 FrameRegIsKill = true;
164 }
165
166 // Spill CFRs.
167 if (MIOpc == LoongArch::PseudoST_CFR) {
168 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass);
169 BuildMI(MBB, II, DL, TII->get(LoongArch::MOVCF2GR), ScratchReg)
170 .add(MI.getOperand(0));
171 BuildMI(MBB, II, DL, TII->get(IsLA64 ? LoongArch::ST_D : LoongArch::ST_W))
172 .addReg(ScratchReg, RegState::Kill)
173 .addReg(FrameReg)
174 .addImm(Offset.getFixed());
175 MI.eraseFromParent();
176 return true;
177 }
178
179 // Reload CFRs.
180 if (MIOpc == LoongArch::PseudoLD_CFR) {
181 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass);
182 BuildMI(MBB, II, DL, TII->get(IsLA64 ? LoongArch::LD_D : LoongArch::LD_W),
183 ScratchReg)
184 .addReg(FrameReg)
185 .addImm(Offset.getFixed());
186 BuildMI(MBB, II, DL, TII->get(LoongArch::MOVGR2CF))
187 .add(MI.getOperand(0))
188 .addReg(ScratchReg, RegState::Kill);
189 MI.eraseFromParent();
190 return true;
191 }
192
193 MI.getOperand(FIOperandNum)
194 .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
195 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
196 return false;
197}
198
201 return false;
202
203 const MachineRegisterInfo *MRI = &MF.getRegInfo();
204 const LoongArchFrameLowering *TFI = getFrameLowering(MF);
205
206 // Stack realignment requires a frame pointer. If we already started
207 // register allocation with frame pointer elimination, it is too late now.
208 if (!MRI->canReserveReg(LoongArch::R22))
209 return false;
210
211 // We may also need a base pointer if there are dynamic allocas or stack
212 // pointer adjustments around calls.
213 if (TFI->hasReservedCallFrame(MF))
214 return true;
215
216 // A base pointer is required and allowed. Check that it isn't too late to
217 // reserve it.
218 return MRI->canReserveReg(LoongArchABI::getBPReg());
219}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A debug info location.
Definition: DebugLoc.h:33
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:262
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
bool hasBP(const MachineFunction &MF) const
const LoongArchInstrInfo * getInstrInfo() const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
int64_t getFixed() const
Returns the fixed component of the stack.
Definition: TypeSize.h:49
Information about stack frame layout on the target.
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
virtual StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const
getFrameIndexReference - This method should return the base register and offset used to reference a f...
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
virtual const TargetFrameLowering * getFrameLowering() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
Definition: CallingConv.h:50
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
@ Add
Sum of integers.
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Register getFrameRegister(const MachineFunction &MF) const override
const uint32_t * getNoPreservedMask() const override
BitVector getReservedRegs(const MachineFunction &MF) const override
bool canRealignStack(const MachineFunction &MF) const override