LLVM 19.0.0git
LoongArchInstrInfo.h
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1//=- LoongArchInstrInfo.h - LoongArch Instruction Information ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the LoongArch implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
14#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
15
18
19#define GET_INSTRINFO_HEADER
20#include "LoongArchGenInstrInfo.inc"
21
22namespace llvm {
23
24class LoongArchSubtarget;
25
27public:
29
30 MCInst getNop() const override;
31
33 const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
34 bool KillSrc) const override;
35
38 bool IsKill, int FrameIndex,
39 const TargetRegisterClass *RC,
41 Register VReg) const override;
44 int FrameIndex, const TargetRegisterClass *RC,
46 Register VReg) const override;
47
48 // Materializes the given integer Val into DstReg.
50 const DebugLoc &DL, Register DstReg, uint64_t Val,
52
53 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
54
56
60 bool AllowModify) const override;
61
62 bool isBranchOffsetInRange(unsigned BranchOpc,
63 int64_t BrOffset) const override;
64
66 int *BytesRemoved = nullptr) const override;
67
70 const DebugLoc &dl,
71 int *BytesAdded = nullptr) const override;
72
74 MachineBasicBlock &NewDestBB,
75 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
76 int64_t BrOffset, RegScavenger *RS) const override;
77
78 bool
80
81 std::pair<unsigned, unsigned>
82 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
83
86
87protected:
89};
90
91namespace LoongArch {
92
93// Mask assignments for floating-point.
94static constexpr unsigned FClassMaskSignalingNaN = 0x001;
95static constexpr unsigned FClassMaskQuietNaN = 0x002;
96static constexpr unsigned FClassMaskNegativeInfinity = 0x004;
97static constexpr unsigned FClassMaskNegativeNormal = 0x008;
98static constexpr unsigned FClassMaskNegativeSubnormal = 0x010;
99static constexpr unsigned FClassMaskNegativeZero = 0x020;
100static constexpr unsigned FClassMaskPositiveInfinity = 0x040;
101static constexpr unsigned FClassMaskPositiveNormal = 0x080;
102static constexpr unsigned FClassMaskPositiveSubnormal = 0x100;
103static constexpr unsigned FClassMaskPositiveZero = 0x200;
104} // namespace LoongArch
105
106} // end namespace llvm
107#endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
const LoongArchSubtarget & STI
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
MCInst getNop() const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:69
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static constexpr unsigned FClassMaskSignalingNaN
static constexpr unsigned FClassMaskNegativeSubnormal
static constexpr unsigned FClassMaskPositiveInfinity
static constexpr unsigned FClassMaskNegativeZero
static constexpr unsigned FClassMaskNegativeNormal
static constexpr unsigned FClassMaskQuietNaN
static constexpr unsigned FClassMaskNegativeInfinity
static constexpr unsigned FClassMaskPositiveNormal
static constexpr unsigned FClassMaskPositiveZero
static constexpr unsigned FClassMaskPositiveSubnormal
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18