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LoongArchInstrInfo.cpp
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1 //=- LoongArchInstrInfo.cpp - LoongArch Instruction Information -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the LoongArch implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "LoongArchInstrInfo.h"
14 #include "LoongArch.h"
16 #include "LoongArchRegisterInfo.h"
20 
21 using namespace llvm;
22 
23 #define GET_INSTRINFO_CTOR_DTOR
24 #include "LoongArchGenInstrInfo.inc"
25 
27  : LoongArchGenInstrInfo(LoongArch::ADJCALLSTACKDOWN,
28  LoongArch::ADJCALLSTACKUP),
29  STI(STI) {}
30 
33  const DebugLoc &DL, MCRegister DstReg,
34  MCRegister SrcReg, bool KillSrc) const {
35  if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {
36  BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg)
37  .addReg(SrcReg, getKillRegState(KillSrc))
38  .addReg(LoongArch::R0);
39  return;
40  }
41 
42  // GPR->CFR copy.
43  if (LoongArch::CFRRegClass.contains(DstReg) &&
44  LoongArch::GPRRegClass.contains(SrcReg)) {
45  BuildMI(MBB, MBBI, DL, get(LoongArch::MOVGR2CF), DstReg)
46  .addReg(SrcReg, getKillRegState(KillSrc));
47  return;
48  }
49  // CFR->GPR copy.
50  if (LoongArch::GPRRegClass.contains(DstReg) &&
51  LoongArch::CFRRegClass.contains(SrcReg)) {
52  BuildMI(MBB, MBBI, DL, get(LoongArch::MOVCF2GR), DstReg)
53  .addReg(SrcReg, getKillRegState(KillSrc));
54  return;
55  }
56 
57  // FPR->FPR copies.
58  unsigned Opc;
59  if (LoongArch::FPR32RegClass.contains(DstReg, SrcReg)) {
60  Opc = LoongArch::FMOV_S;
61  } else if (LoongArch::FPR64RegClass.contains(DstReg, SrcReg)) {
62  Opc = LoongArch::FMOV_D;
63  } else {
64  // TODO: support other copies.
65  llvm_unreachable("Impossible reg-to-reg copy");
66  }
67 
68  BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
69  .addReg(SrcReg, getKillRegState(KillSrc));
70 }
71 
74  bool IsKill, int FI, const TargetRegisterClass *RC,
75  const TargetRegisterInfo *TRI) const {
76  DebugLoc DL;
77  if (I != MBB.end())
78  DL = I->getDebugLoc();
80  MachineFrameInfo &MFI = MF->getFrameInfo();
81 
82  unsigned Opcode;
83  if (LoongArch::GPRRegClass.hasSubClassEq(RC))
84  Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
85  ? LoongArch::ST_W
86  : LoongArch::ST_D;
87  else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
88  Opcode = LoongArch::FST_S;
89  else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
90  Opcode = LoongArch::FST_D;
91  else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
92  Opcode = LoongArch::PseudoST_CFR;
93  else
94  llvm_unreachable("Can't store this register to stack slot");
95 
98  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
99 
100  BuildMI(MBB, I, DL, get(Opcode))
101  .addReg(SrcReg, getKillRegState(IsKill))
102  .addFrameIndex(FI)
103  .addImm(0)
104  .addMemOperand(MMO);
105 }
106 
109  int FI, const TargetRegisterClass *RC,
110  const TargetRegisterInfo *TRI) const {
111  DebugLoc DL;
112  if (I != MBB.end())
113  DL = I->getDebugLoc();
114  MachineFunction *MF = MBB.getParent();
115  MachineFrameInfo &MFI = MF->getFrameInfo();
116 
117  unsigned Opcode;
118  if (LoongArch::GPRRegClass.hasSubClassEq(RC))
119  Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
120  ? LoongArch::LD_W
121  : LoongArch::LD_D;
122  else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
123  Opcode = LoongArch::FLD_S;
124  else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
125  Opcode = LoongArch::FLD_D;
126  else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
127  Opcode = LoongArch::PseudoLD_CFR;
128  else
129  llvm_unreachable("Can't load this register from stack slot");
130 
133  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
134 
135  BuildMI(MBB, I, DL, get(Opcode), DstReg)
136  .addFrameIndex(FI)
137  .addImm(0)
138  .addMemOperand(MMO);
139 }
140 
143  const DebugLoc &DL, Register DstReg,
144  uint64_t Val, MachineInstr::MIFlag Flag) const {
145  Register SrcReg = LoongArch::R0;
146 
147  if (!STI.is64Bit() && !isInt<32>(Val))
148  report_fatal_error("Should only materialize 32-bit constants for LA32");
149 
150  auto Seq = LoongArchMatInt::generateInstSeq(Val);
151  assert(!Seq.empty());
152 
153  for (auto &Inst : Seq) {
154  switch (Inst.Opc) {
155  case LoongArch::LU12I_W:
156  BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
157  .addImm(Inst.Imm)
158  .setMIFlag(Flag);
159  break;
160  case LoongArch::ADDI_W:
161  case LoongArch::ORI:
162  case LoongArch::LU32I_D: // "rj" is needed due to InstrInfo pattern
163  case LoongArch::LU52I_D:
164  BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
165  .addReg(SrcReg, RegState::Kill)
166  .addImm(Inst.Imm)
167  .setMIFlag(Flag);
168  break;
169  default:
170  assert(false && "Unknown insn emitted by LoongArchMatInt");
171  }
172 
173  // Only the first instruction has $zero as its source.
174  SrcReg = DstReg;
175  }
176 }
177 
179  if (MI.getOpcode() == TargetOpcode::INLINEASM) {
180  const MachineFunction *MF = MI.getParent()->getParent();
181  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
182  return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
183  }
184  return MI.getDesc().getSize();
185 }
186 
189  assert(MI.getDesc().isBranch() && "Unexpected opcode!");
190  // The branch target is always the last operand.
191  return MI.getOperand(MI.getNumExplicitOperands() - 1).getMBB();
192 }
193 
196  // Block ends with fall-through condbranch.
197  assert(LastInst.getDesc().isConditionalBranch() &&
198  "Unknown conditional branch");
199  int NumOp = LastInst.getNumExplicitOperands();
200  Target = LastInst.getOperand(NumOp - 1).getMBB();
201 
202  Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
203  for (int i = 0; i < NumOp - 1; i++)
204  Cond.push_back(LastInst.getOperand(i));
205 }
206 
209  MachineBasicBlock *&FBB,
211  bool AllowModify) const {
212  TBB = FBB = nullptr;
213  Cond.clear();
214 
215  // If the block has no terminators, it just falls into the block after it.
217  if (I == MBB.end() || !isUnpredicatedTerminator(*I))
218  return false;
219 
220  // Count the number of terminators and find the first unconditional or
221  // indirect branch.
222  MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
223  int NumTerminators = 0;
224  for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
225  J++) {
226  NumTerminators++;
227  if (J->getDesc().isUnconditionalBranch() ||
228  J->getDesc().isIndirectBranch()) {
229  FirstUncondOrIndirectBr = J.getReverse();
230  }
231  }
232 
233  // If AllowModify is true, we can erase any terminators after
234  // FirstUncondOrIndirectBR.
235  if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
236  while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
237  std::next(FirstUncondOrIndirectBr)->eraseFromParent();
238  NumTerminators--;
239  }
240  I = FirstUncondOrIndirectBr;
241  }
242 
243  // Handle a single unconditional branch.
244  if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
246  return false;
247  }
248 
249  // Handle a single conditional branch.
250  if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
252  return false;
253  }
254 
255  // Handle a conditional branch followed by an unconditional branch.
256  if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
257  I->getDesc().isUnconditionalBranch()) {
258  parseCondBranch(*std::prev(I), TBB, Cond);
259  FBB = getBranchDestBlock(*I);
260  return false;
261  }
262 
263  // Otherwise, we can't handle this.
264  return true;
265 }
266 
268  int64_t BrOffset) const {
269  switch (BranchOp) {
270  default:
271  llvm_unreachable("Unknown branch instruction!");
272  case LoongArch::BEQ:
273  case LoongArch::BNE:
274  case LoongArch::BLT:
275  case LoongArch::BGE:
276  case LoongArch::BLTU:
277  case LoongArch::BGEU:
278  return isInt<18>(BrOffset);
279  case LoongArch::BEQZ:
280  case LoongArch::BNEZ:
281  case LoongArch::BCEQZ:
282  case LoongArch::BCNEZ:
283  return isInt<23>(BrOffset);
284  case LoongArch::B:
285  case LoongArch::PseudoBR:
286  return isInt<28>(BrOffset);
287  }
288 }
289 
291  int *BytesRemoved) const {
292  if (BytesRemoved)
293  *BytesRemoved = 0;
295  if (I == MBB.end())
296  return 0;
297 
298  if (!I->getDesc().isBranch())
299  return 0;
300 
301  // Remove the branch.
302  if (BytesRemoved)
303  *BytesRemoved += getInstSizeInBytes(*I);
304  I->eraseFromParent();
305 
306  I = MBB.end();
307 
308  if (I == MBB.begin())
309  return 1;
310  --I;
311  if (!I->getDesc().isConditionalBranch())
312  return 1;
313 
314  // Remove the branch.
315  if (BytesRemoved)
316  *BytesRemoved += getInstSizeInBytes(*I);
317  I->eraseFromParent();
318  return 2;
319 }
320 
321 // Inserts a branch into the end of the specific MachineBasicBlock, returning
322 // the number of instructions inserted.
325  ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
326  if (BytesAdded)
327  *BytesAdded = 0;
328 
329  // Shouldn't be a fall through.
330  assert(TBB && "insertBranch must not be told to insert a fallthrough");
331  assert(Cond.size() <= 3 && Cond.size() != 1 &&
332  "LoongArch branch conditions have at most two components!");
333 
334  // Unconditional branch.
335  if (Cond.empty()) {
336  MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(TBB);
337  if (BytesAdded)
338  *BytesAdded += getInstSizeInBytes(MI);
339  return 1;
340  }
341 
342  // Either a one or two-way conditional branch.
343  MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
344  for (unsigned i = 1; i < Cond.size(); ++i)
345  MIB.add(Cond[i]);
346  MIB.addMBB(TBB);
347  if (BytesAdded)
348  *BytesAdded += getInstSizeInBytes(*MIB);
349 
350  // One-way conditional branch.
351  if (!FBB)
352  return 1;
353 
354  // Two-way conditional branch.
355  MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(FBB);
356  if (BytesAdded)
357  *BytesAdded += getInstSizeInBytes(MI);
358  return 2;
359 }
360 
362  MachineBasicBlock &DestBB,
363  MachineBasicBlock &RestoreBB,
364  const DebugLoc &DL,
365  int64_t BrOffset,
366  RegScavenger *RS) const {
367  assert(RS && "RegScavenger required for long branching");
368  assert(MBB.empty() &&
369  "new block should be inserted for expanding unconditional branch");
370  assert(MBB.pred_size() == 1);
371 
372  MachineFunction *MF = MBB.getParent();
377 
378  if (!isInt<32>(BrOffset))
380  "Branch offsets outside of the signed 32-bit range not supported");
381 
382  Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass);
383  auto II = MBB.end();
384 
385  MachineInstr &PCALAU12I =
386  *BuildMI(MBB, II, DL, get(LoongArch::PCALAU12I), ScratchReg)
387  .addMBB(&DestBB, LoongArchII::MO_PCREL_HI);
388  MachineInstr &ADDI =
389  *BuildMI(MBB, II, DL,
390  get(STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W),
391  ScratchReg)
392  .addReg(ScratchReg)
393  .addMBB(&DestBB, LoongArchII::MO_PCREL_LO);
394  BuildMI(MBB, II, DL, get(LoongArch::PseudoBRIND))
395  .addReg(ScratchReg, RegState::Kill)
396  .addImm(0);
397 
398  RS->enterBasicBlockEnd(MBB);
400  LoongArch::GPRRegClass, PCALAU12I.getIterator(), /*RestoreAfter=*/false,
401  /*SPAdj=*/0, /*AllowSpill=*/false);
402  if (Scav != LoongArch::NoRegister)
403  RS->setRegUsed(Scav);
404  else {
405  // When there is no scavenged register, it needs to specify a register.
406  // Specify t8 register because it won't be used too often.
407  Scav = LoongArch::R20;
409  if (FrameIndex == -1)
410  report_fatal_error("The function size is incorrectly estimated.");
411  storeRegToStackSlot(MBB, PCALAU12I, Scav, /*IsKill=*/true, FrameIndex,
412  &LoongArch::GPRRegClass, TRI);
413  TRI->eliminateFrameIndex(std::prev(PCALAU12I.getIterator()),
414  /*SpAdj=*/0, /*FIOperandNum=*/1);
415  PCALAU12I.getOperand(1).setMBB(&RestoreBB);
416  ADDI.getOperand(2).setMBB(&RestoreBB);
417  loadRegFromStackSlot(RestoreBB, RestoreBB.end(), Scav, FrameIndex,
418  &LoongArch::GPRRegClass, TRI);
419  TRI->eliminateFrameIndex(RestoreBB.back(),
420  /*SpAdj=*/0, /*FIOperandNum=*/1);
421  }
422  MRI.replaceRegWith(ScratchReg, Scav);
423  MRI.clearVirtRegs();
424 }
425 
426 static unsigned getOppositeBranchOpc(unsigned Opc) {
427  switch (Opc) {
428  default:
429  llvm_unreachable("Unrecognized conditional branch");
430  case LoongArch::BEQ:
431  return LoongArch::BNE;
432  case LoongArch::BNE:
433  return LoongArch::BEQ;
434  case LoongArch::BEQZ:
435  return LoongArch::BNEZ;
436  case LoongArch::BNEZ:
437  return LoongArch::BEQZ;
438  case LoongArch::BCEQZ:
439  return LoongArch::BCNEZ;
440  case LoongArch::BCNEZ:
441  return LoongArch::BCEQZ;
442  case LoongArch::BLT:
443  return LoongArch::BGE;
444  case LoongArch::BGE:
445  return LoongArch::BLT;
446  case LoongArch::BLTU:
447  return LoongArch::BGEU;
448  case LoongArch::BGEU:
449  return LoongArch::BLTU;
450  }
451 }
452 
455  assert((Cond.size() && Cond.size() <= 3) && "Invalid branch condition!");
456  Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
457  return false;
458 }
459 
460 std::pair<unsigned, unsigned>
462  return std::make_pair(TF, 0u);
463 }
464 
467  using namespace LoongArchII;
468  // TODO: Add more target flags.
469  static const std::pair<unsigned, const char *> TargetFlags[] = {
470  {MO_CALL, "loongarch-call"},
471  {MO_CALL_PLT, "loongarch-call-plt"},
472  {MO_PCREL_HI, "loongarch-pcrel-hi"},
473  {MO_PCREL_LO, "loongarch-pcrel-lo"},
474  {MO_GOT_PC_HI, "loongarch-got-pc-hi"},
475  {MO_GOT_PC_LO, "loongarch-got-pc-lo"},
476  {MO_LE_HI, "loongarch-le-hi"},
477  {MO_LE_LO, "loongarch-le-lo"},
478  {MO_IE_PC_HI, "loongarch-ie-pc-hi"},
479  {MO_IE_PC_LO, "loongarch-ie-pc-lo"},
480  {MO_LD_PC_HI, "loongarch-ld-pc-hi"},
481  {MO_GD_PC_HI, "loongarch-gd-pc-hi"}};
482  return makeArrayRef(TargetFlags);
483 }
i
i
Definition: README.txt:29
llvm::LoongArchInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: LoongArchInstrInfo.cpp:290
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
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const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
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const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:255
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std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: LoongArchInstrInfo.cpp:461
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@ OR
Definition: ISDOpcodes.h:667
llvm::LoongArchII::MO_GOT_PC_LO
@ MO_GOT_PC_LO
Definition: LoongArchBaseInfo.h:35
llvm::LoongArchII::MO_LE_LO
@ MO_LE_LO
Definition: LoongArchBaseInfo.h:37
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Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
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Definition: MachineRegisterInfo.h:50
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ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: LoongArchInstrInfo.cpp:466
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unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Definition: MachineInstr.cpp:721
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const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
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Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
Definition: RegisterScavenging.cpp:592
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:150
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This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
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getMachineMemOperand - Allocate a new MachineMemOperand.
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MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Definition: LoongArchInstrInfo.cpp:188
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virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:127
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bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Definition: LoongArchInstrInfo.cpp:267
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Definition: TargetRegisterInfo.h:236
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bool is64Bit() const
Definition: LoongArchSubtarget.h:83
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const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:513
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::LoongArchII::MO_IE_PC_LO
@ MO_IE_PC_LO
Definition: LoongArchBaseInfo.h:39
llvm::LoongArchInstrInfo::insertIndirectBranch
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
Definition: LoongArchInstrInfo.cpp:361
llvm::LoongArchII::MO_LD_PC_HI
@ MO_LD_PC_HI
Definition: LoongArchBaseInfo.h:40
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MachineInstr & back()
Definition: MachineBasicBlock.h:285
llvm::LoongArchInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: LoongArchInstrInfo.cpp:107
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1025
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Definition: PointerIntPair.h:234
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unsigned pred_size() const
Definition: MachineBasicBlock.h:365
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getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
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const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
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Definition: MachineOperand.h:782
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Definition: LoongArchMachineFunctionInfo.h:25
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const LoongArchSubtarget & STI
Definition: LoongArchInstrInfo.h:84
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Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
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bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: LoongArchInstrInfo.cpp:453
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const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
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Definition: LoongArchInstrInfo.cpp:141
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Definition: TargetRegisterInfo.h:45
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MCID::Flag
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Definition: MCInstrDesc.h:147
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@ MO_PCREL_LO
Definition: LoongArchBaseInfo.h:33
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reverse_iterator rend()
Definition: MachineBasicBlock.h:315
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::RegScavenger::enterBasicBlockEnd
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
Definition: RegisterScavenging.cpp:87
llvm::LoongArchII::MO_GOT_PC_HI
@ MO_GOT_PC_HI
Definition: LoongArchBaseInfo.h:34
llvm::LoongArchII::MO_IE_PC_HI
@ MO_IE_PC_HI
Definition: LoongArchBaseInfo.h:38
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::TargetRegisterInfo::eliminateFrameIndex
virtual bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
llvm::LoongArchInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: LoongArchInstrInfo.cpp:207
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
llvm::MachineInstrBundleIterator::getReverse
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Definition: MachineInstrBundleIterator.h:283
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:470
llvm::LoongArchSubtarget
Definition: LoongArchSubtarget.h:32
llvm::LoongArchMatInt::generateInstSeq
InstSeq generateInstSeq(int64_t Val)
Definition: LoongArchMatInt.cpp:15
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:484
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:264
llvm::LoongArchII::MO_PCREL_HI
@ MO_PCREL_HI
Definition: LoongArchBaseInfo.h:32
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LoongArchInstrInfo::LoongArchInstrInfo
LoongArchInstrInfo(LoongArchSubtarget &STI)
Definition: LoongArchInstrInfo.cpp:26
llvm::LoongArchII::MO_CALL
@ MO_CALL
Definition: LoongArchBaseInfo.h:30
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:82
llvm::LoongArchII::MO_GD_PC_HI
@ MO_GD_PC_HI
Definition: LoongArchBaseInfo.h:41
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:204
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
LoongArch.h
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:138
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:516
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::LoongArchII::MO_LE_HI
@ MO_LE_HI
Definition: LoongArchBaseInfo.h:36
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::LoongArchMachineFunctionInfo::getBranchRelaxationSpillFrameIndex
int getBranchRelaxationSpillFrameIndex()
Definition: LoongArchMachineFunctionInfo.h:58
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::MachineRegisterInfo::replaceRegWith
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
Definition: MachineRegisterInfo.cpp:378
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LoongArchInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
Definition: LoongArchInstrInfo.cpp:31
LoongArchMatInt.h
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:279
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:653
llvm::RegScavenger::setRegUsed
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Definition: RegisterScavenging.cpp:51
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
LoongArchInstrInfo.h
LoongArchMachineFunctionInfo.h
llvm::LoongArchInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Definition: LoongArchInstrInfo.cpp:178
llvm::MachineRegisterInfo::clearVirtRegs
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
Definition: MachineRegisterInfo.cpp:200
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:546
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
LoongArchMCTargetDesc.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1019
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
llvm::LoongArchInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: LoongArchInstrInfo.cpp:72
llvm::MachineOperand::setMBB
void setMBB(MachineBasicBlock *MBB)
Definition: MachineOperand.h:698
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:277
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
RegisterScavenging.h
llvm::LoongArchII::MO_CALL_PLT
@ MO_CALL_PLT
Definition: LoongArchBaseInfo.h:31
getOppositeBranchOpc
static unsigned getOppositeBranchOpc(unsigned Opc)
Definition: LoongArchInstrInfo.cpp:426
llvm::LoongArchInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
Definition: LoongArchInstrInfo.cpp:323
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
llvm::MCInstrDesc::isConditionalBranch
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:314
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
parseCondBranch
static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
Definition: LoongArchInstrInfo.cpp:194