LLVM  15.0.0git
LoongArchInstrInfo.cpp
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1 //=- LoongArchInstrInfo.cpp - LoongArch Instruction Information -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the LoongArch implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "LoongArchInstrInfo.h"
14 #include "LoongArch.h"
15 
16 using namespace llvm;
17 
18 #define GET_INSTRINFO_CTOR_DTOR
19 #include "LoongArchGenInstrInfo.inc"
20 
22  // FIXME: add CFSetup and CFDestroy Inst when we implement function call.
24 
27  const DebugLoc &DL, MCRegister DstReg,
28  MCRegister SrcReg, bool KillSrc) const {
29  if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {
30  BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg)
31  .addReg(SrcReg, getKillRegState(KillSrc))
32  .addReg(LoongArch::R0);
33  return;
34  }
35 
36  // FPR->FPR copies.
37  unsigned Opc;
38  if (LoongArch::FPR32RegClass.contains(DstReg, SrcReg)) {
39  Opc = LoongArch::FMOV_S;
40  } else if (LoongArch::FPR64RegClass.contains(DstReg, SrcReg)) {
41  Opc = LoongArch::FMOV_D;
42  } else {
43  // TODO: support other copies.
44  llvm_unreachable("Impossible reg-to-reg copy");
45  }
46 
47  BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
48  .addReg(SrcReg, getKillRegState(KillSrc));
49 }
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
contains
return AArch64::GPR64RegClass contains(Reg)
LoongArchGenInstrInfo
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::LoongArchSubtarget
Definition: LoongArchSubtarget.h:32
llvm::LoongArchInstrInfo::LoongArchInstrInfo
LoongArchInstrInfo(LoongArchSubtarget &STI)
Definition: LoongArchInstrInfo.cpp:21
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
LoongArch.h
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LoongArchInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
Definition: LoongArchInstrInfo.cpp:25
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
LoongArchInstrInfo.h
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24