AMDGPUInstructionSelector.cpp File Reference

This file implements the targeting of the InstructionSelector class for AMDGPU. More...

#include "AMDGPUInstructionSelector.h"
#include "AMDGPU.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPURegisterBankInfo.h"
#include "AMDGPUTargetMachine.h"
#include "SIMachineFunctionInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include <optional>
#include "AMDGPUGenGlobalISel.inc"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "amdgpu-isel"
#define	GET_GLOBALISEL_IMPL
#define	AMDGPUSubtarget   GCNSubtarget
#define	GET_GLOBALISEL_PREDICATES_INIT
#define	GET_GLOBALISEL_TEMPORARIES_INIT

Functions
static unsigned	getLogicalBitOpcode (unsigned Opc, bool Is64)
static int	getV_CMPOpcode (CmpInst::Predicate P, unsigned Size, const GCNSubtarget &ST)
static unsigned	gwsIntrinToOpcode (unsigned IntrID)
static bool	parseTexFail (uint64_t TexFailCtrl, bool &TFE, bool &LWE, bool &IsTexFail)
static int	sizeToSubRegIndex (unsigned Size)
static bool	shouldUseAndMask (unsigned Size, unsigned &Mask)
static bool	isConstant (const MachineInstr &MI)
static bool	isVCmpResult (Register Reg, MachineRegisterInfo &MRI)
static std::pair< Register, unsigned >	computeIndirectRegIndex (MachineRegisterInfo &MRI, const SIRegisterInfo &TRI, const TargetRegisterClass *SuperRC, Register IdxReg, unsigned EltSize, GISelKnownBits &KnownBits)
	Return the register to use for the index value, and the subregister to use for the indirectly accessed register.
static Register	matchZeroExtendFromS32 (MachineRegisterInfo &MRI, Register Reg)
	Match a zero extend from a 32-bit value to 64-bits.
static Register	getWaveAddress (const MachineInstr *Def)
static void	addZeroImm (MachineInstrBuilder &MIB)
static Register	buildRSRC (MachineIRBuilder &B, MachineRegisterInfo &MRI, uint32_t FormatLo, uint32_t FormatHi, Register BasePtr)
	Return a resource descriptor for use with an arbitrary 64-bit pointer.
static Register	buildAddr64RSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)
static Register	buildOffsetSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)
static std::optional< uint64_t >	getConstantZext32Val (Register Reg, const MachineRegisterInfo &MRI)
	Get an immediate that must be 32-bits, and treated as zero extended.
static MachineInstr *	stripBitCast (MachineInstr *MI, MachineRegisterInfo &MRI)
static MachineInstr *	isExtractHiElt (MachineInstr *Inst, MachineRegisterInfo &MRI)

Variables
static cl::opt< bool >	AllowRiskySelect ("amdgpu-global-isel-risky-select", cl::desc("Allow GlobalISel to select cases that are likely to not work yet"), cl::init(false), cl::ReallyHidden)

Detailed Description

This file implements the targeting of the InstructionSelector class for AMDGPU.

Todo:

This should be generated by TableGen.

Definition in file AMDGPUInstructionSelector.cpp.

Macro Definition Documentation

AMDGPUSubtarget

#define AMDGPUSubtarget   GCNSubtarget

Definition at line 43 of file AMDGPUInstructionSelector.cpp.

DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-isel"

Definition at line 31 of file AMDGPUInstructionSelector.cpp.

GET_GLOBALISEL_IMPL

#define GET_GLOBALISEL_IMPL

Definition at line 42 of file AMDGPUInstructionSelector.cpp.

GET_GLOBALISEL_PREDICATES_INIT

#define GET_GLOBALISEL_PREDICATES_INIT

GET_GLOBALISEL_TEMPORARIES_INIT

#define GET_GLOBALISEL_TEMPORARIES_INIT

Function Documentation

addZeroImm()

static void addZeroImm ( MachineInstrBuilder &  MIB )

static

Definition at line 4463 of file AMDGPUInstructionSelector.cpp.

References llvm::MachineInstrBuilder::addImm().

buildAddr64RSrc()

static Register buildAddr64RSrc ( MachineIRBuilder &  B, MachineRegisterInfo &  MRI, const SIInstrInfo &  TII, Register  BasePtr  )

static

Definition at line 4512 of file AMDGPUInstructionSelector.cpp.

References B, buildRSRC(), llvm::Hi_32(), MRI, and TII.

buildOffsetSrc()

static Register buildOffsetSrc ( MachineIRBuilder &  B, MachineRegisterInfo &  MRI, const SIInstrInfo &  TII, Register  BasePtr  )

static

Definition at line 4521 of file AMDGPUInstructionSelector.cpp.

References B, buildRSRC(), llvm::Hi_32(), MRI, and TII.

buildRSRC()

static Register buildRSRC ( MachineIRBuilder &  B, MachineRegisterInfo &  MRI, uint32_t  FormatLo, uint32_t  FormatHi, Register  BasePtr  )

static

Return a resource descriptor for use with an arbitrary 64-bit pointer.

If BasePtr is not valid, a null base pointer will be used.

Definition at line 4469 of file AMDGPUInstructionSelector.cpp.

References B, and MRI.

Referenced by buildAddr64RSrc(), and buildOffsetSrc().

computeIndirectRegIndex()

static std::pair< Register, unsigned > computeIndirectRegIndex ( MachineRegisterInfo &  MRI, const SIRegisterInfo &  TRI, const TargetRegisterClass *  SuperRC, Register  IdxReg, unsigned  EltSize, GISelKnownBits &  KnownBits  )

static

Return the register to use for the index value, and the subregister to use for the indirectly accessed register.

Definition at line 2859 of file AMDGPUInstructionSelector.cpp.

References assert(), llvm::AMDGPU::getBaseWithConstantOffset(), MRI, llvm::Offset, llvm::ArrayRef< T >::size(), and TRI.

getConstantZext32Val()

static std::optional< uint64_t > getConstantZext32Val ( Register  Reg, const MachineRegisterInfo &  MRI  )

static

Get an immediate that must be 32-bits, and treated as zero extended.

Definition at line 4726 of file AMDGPUInstructionSelector.cpp.

References llvm::getIConstantVRegSExtVal(), llvm::Lo_32(), and MRI.

getLogicalBitOpcode()

static unsigned getLogicalBitOpcode ( unsigned  Opc, bool  Is64  )

static

Definition at line 271 of file AMDGPUInstructionSelector.cpp.

References llvm_unreachable.

getV_CMPOpcode()

static int getV_CMPOpcode ( CmpInst::Predicate  P, unsigned  Size, const GCNSubtarget &  ST  )

static

Definition at line 1077 of file AMDGPUInstructionSelector.cpp.

References llvm::CmpInst::FCMP_FALSE, llvm::CmpInst::FCMP_OEQ, llvm::CmpInst::FCMP_OGE, llvm::CmpInst::FCMP_OGT, llvm::CmpInst::FCMP_OLE, llvm::CmpInst::FCMP_OLT, llvm::CmpInst::FCMP_ONE, llvm::CmpInst::FCMP_ORD, llvm::CmpInst::FCMP_TRUE, llvm::CmpInst::FCMP_UEQ, llvm::CmpInst::FCMP_UGE, llvm::CmpInst::FCMP_UGT, llvm::CmpInst::FCMP_ULE, llvm::CmpInst::FCMP_ULT, llvm::CmpInst::FCMP_UNE, llvm::CmpInst::FCMP_UNO, llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::CmpInst::ICMP_SGE, llvm::CmpInst::ICMP_SGT, llvm::CmpInst::ICMP_SLE, llvm::CmpInst::ICMP_SLT, llvm::CmpInst::ICMP_UGE, llvm::CmpInst::ICMP_UGT, llvm::CmpInst::ICMP_ULE, llvm::CmpInst::ICMP_ULT, llvm_unreachable, P, Select, and Size.

getWaveAddress()

static Register getWaveAddress ( const MachineInstr *  Def )

static

Definition at line 4285 of file AMDGPUInstructionSelector.cpp.

gwsIntrinToOpcode()

static unsigned gwsIntrinToOpcode ( unsigned  IntrID )

static

Definition at line 1534 of file AMDGPUInstructionSelector.cpp.

References llvm_unreachable.

isConstant()

static bool isConstant ( const MachineInstr &  MI )

static

Definition at line 2567 of file AMDGPUInstructionSelector.cpp.

References MI.

Referenced by arePointersCompatible(), llvm::buildModuleSummaryIndex(), llvm::MDBuilder::createTBAANode(), llvm::HexagonInstrInfo::expandPostRAPseudo(), getMemcpyLoadsAndStores(), and llvm::slpvectorizer::BoUpSLP::getTreeCost().

isExtractHiElt()

static MachineInstr * isExtractHiElt ( MachineInstr *  Inst, MachineRegisterInfo &  MRI  )

static

Definition at line 4795 of file AMDGPUInstructionSelector.cpp.

References assert(), llvm::LLT::fixed_vector(), llvm::getDefIgnoringCopies(), llvm::getIConstantVRegValWithLookThrough(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getShuffleMask(), LHS, MRI, and stripBitCast().

isVCmpResult()

static bool isVCmpResult ( Register  Reg, MachineRegisterInfo &  MRI  )

static

Definition at line 2658 of file AMDGPUInstructionSelector.cpp.

References isVCmpResult(), MI, and MRI.

Referenced by isVCmpResult().

matchZeroExtendFromS32()

static Register matchZeroExtendFromS32 ( MachineRegisterInfo &  MRI, Register  Reg  )

static

Match a zero extend from a 32-bit value to 64-bits.

Definition at line 3126 of file AMDGPUInstructionSelector.cpp.

References assert(), llvm::getDefIgnoringCopies(), llvm::MIPatternMatch::m_GZExt(), llvm::MIPatternMatch::m_Reg(), llvm::PatternMatch::m_ZeroInt(), llvm::MIPatternMatch::mi_match(), MRI, and llvm::LLT::scalar().

parseTexFail()

static bool parseTexFail ( uint64_t  TexFailCtrl, bool &  TFE, bool &  LWE, bool &  IsTexFail  )

static

Definition at line 1689 of file AMDGPUInstructionSelector.cpp.

shouldUseAndMask()

static bool shouldUseAndMask ( unsigned  Size, unsigned &  Mask  )

static

Returns

true if a bitmask for Size bits will be an inline immediate.

Definition at line 2227 of file AMDGPUInstructionSelector.cpp.

References Size.

sizeToSubRegIndex()

static int sizeToSubRegIndex ( unsigned  Size )

static

Definition at line 2085 of file AMDGPUInstructionSelector.cpp.

References llvm::bit_ceil(), Size, and sizeToSubRegIndex().

Referenced by sizeToSubRegIndex().

stripBitCast()

static MachineInstr * stripBitCast ( MachineInstr *  MI, MachineRegisterInfo &  MRI  )

static

Definition at line 4787 of file AMDGPUInstructionSelector.cpp.

References llvm::getDefIgnoringCopies(), MI, and MRI.

Referenced by isExtractHiElt().

Variable Documentation

AllowRiskySelect

cl::opt< bool > AllowRiskySelect("amdgpu-global-isel-risky-select", cl::desc("Allow GlobalISel to select cases that are likely to not work yet"), cl::init(false), cl::ReallyHidden) ( "amdgpu-global-isel-risky-select"  , cl::desc("Allow GlobalISel to select cases that are likely to not work yet")  , cl::init(false)  , cl::ReallyHidden    )

static