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GenericMachineInstrs.h
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1 //===- llvm/CodeGen/GlobalISel/GenericMachineInstrs.h -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// Declares convenience wrapper classes for interpreting MachineInstr instances
10 /// as specific generic operations.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
15 #define LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
16 
17 #include "llvm/IR/Instructions.h"
21 #include "llvm/Support/Casting.h"
22 
23 namespace llvm {
24 
25 /// A base class for all GenericMachineInstrs.
27 public:
28  GenericMachineInstr() = delete;
29 
30  /// Access the Idx'th operand as a register and return it.
31  /// This assumes that the Idx'th operand is a Register type.
32  Register getReg(unsigned Idx) const { return getOperand(Idx).getReg(); }
33 
34  static bool classof(const MachineInstr *MI) {
35  return isPreISelGenericOpcode(MI->getOpcode());
36  }
37 };
38 
39 /// Represents any type of generic load or store.
40 /// G_LOAD, G_STORE, G_ZEXTLOAD, G_SEXTLOAD.
42 public:
43  /// Get the source register of the pointer value.
44  Register getPointerReg() const { return getOperand(1).getReg(); }
45 
46  /// Get the MachineMemOperand on this instruction.
47  MachineMemOperand &getMMO() const { return **memoperands_begin(); }
48 
49  /// Returns true if the attached MachineMemOperand has the atomic flag set.
50  bool isAtomic() const { return getMMO().isAtomic(); }
51  /// Returns true if the attached MachineMemOpeand as the volatile flag set.
52  bool isVolatile() const { return getMMO().isVolatile(); }
53  /// Returns true if the memory operation is neither atomic or volatile.
54  bool isSimple() const { return !isAtomic() && !isVolatile(); }
55  /// Returns true if this memory operation doesn't have any ordering
56  /// constraints other than normal aliasing. Volatile and (ordered) atomic
57  /// memory operations can't be reordered.
58  bool isUnordered() const { return getMMO().isUnordered(); }
59 
60  /// Returns the size in bytes of the memory access.
61  uint64_t getMemSize() const { return getMMO().getSize();
62  } /// Returns the size in bits of the memory access.
64 
65  static bool classof(const MachineInstr *MI) {
66  switch (MI->getOpcode()) {
67  case TargetOpcode::G_LOAD:
68  case TargetOpcode::G_STORE:
69  case TargetOpcode::G_ZEXTLOAD:
70  case TargetOpcode::G_SEXTLOAD:
71  return true;
72  default:
73  return false;
74  }
75  }
76 };
77 
78 /// Represents any generic load, including sign/zero extending variants.
79 class GAnyLoad : public GLoadStore {
80 public:
81  /// Get the definition register of the loaded value.
82  Register getDstReg() const { return getOperand(0).getReg(); }
83 
84  static bool classof(const MachineInstr *MI) {
85  switch (MI->getOpcode()) {
86  case TargetOpcode::G_LOAD:
87  case TargetOpcode::G_ZEXTLOAD:
88  case TargetOpcode::G_SEXTLOAD:
89  return true;
90  default:
91  return false;
92  }
93  }
94 };
95 
96 /// Represents a G_LOAD.
97 class GLoad : public GAnyLoad {
98 public:
99  static bool classof(const MachineInstr *MI) {
100  return MI->getOpcode() == TargetOpcode::G_LOAD;
101  }
102 };
103 
104 /// Represents either a G_SEXTLOAD or G_ZEXTLOAD.
105 class GExtLoad : public GAnyLoad {
106 public:
107  static bool classof(const MachineInstr *MI) {
108  return MI->getOpcode() == TargetOpcode::G_SEXTLOAD ||
109  MI->getOpcode() == TargetOpcode::G_ZEXTLOAD;
110  }
111 };
112 
113 /// Represents a G_SEXTLOAD.
114 class GSExtLoad : public GExtLoad {
115 public:
116  static bool classof(const MachineInstr *MI) {
117  return MI->getOpcode() == TargetOpcode::G_SEXTLOAD;
118  }
119 };
120 
121 /// Represents a G_ZEXTLOAD.
122 class GZExtLoad : public GExtLoad {
123 public:
124  static bool classof(const MachineInstr *MI) {
125  return MI->getOpcode() == TargetOpcode::G_ZEXTLOAD;
126  }
127 };
128 
129 /// Represents a G_STORE.
130 class GStore : public GLoadStore {
131 public:
132  /// Get the stored value register.
133  Register getValueReg() const { return getOperand(0).getReg(); }
134 
135  static bool classof(const MachineInstr *MI) {
136  return MI->getOpcode() == TargetOpcode::G_STORE;
137  }
138 };
139 
140 /// Represents a G_UNMERGE_VALUES.
142 public:
143  /// Returns the number of def registers.
144  unsigned getNumDefs() const { return getNumOperands() - 1; }
145  /// Get the unmerge source register.
147 
148  static bool classof(const MachineInstr *MI) {
149  return MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES;
150  }
151 };
152 
153 /// Represents G_BUILD_VECTOR, G_CONCAT_VECTORS or G_MERGE_VALUES.
154 /// All these have the common property of generating a single value from
155 /// multiple sources.
157 public:
158  /// Returns the number of source registers.
159  unsigned getNumSources() const { return getNumOperands() - 1; }
160  /// Returns the I'th source register.
161  Register getSourceReg(unsigned I) const { return getReg(I + 1); }
162 
163  static bool classof(const MachineInstr *MI) {
164  switch (MI->getOpcode()) {
165  case TargetOpcode::G_MERGE_VALUES:
166  case TargetOpcode::G_CONCAT_VECTORS:
167  case TargetOpcode::G_BUILD_VECTOR:
168  return true;
169  default:
170  return false;
171  }
172  }
173 };
174 
175 /// Represents a G_MERGE_VALUES.
176 class GMerge : public GMergeLikeOp {
177 public:
178  static bool classof(const MachineInstr *MI) {
179  return MI->getOpcode() == TargetOpcode::G_MERGE_VALUES;
180  }
181 };
182 
183 /// Represents a G_CONCAT_VECTORS.
184 class GConcatVectors : public GMergeLikeOp {
185 public:
186  static bool classof(const MachineInstr *MI) {
187  return MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS;
188  }
189 };
190 
191 /// Represents a G_BUILD_VECTOR.
192 class GBuildVector : public GMergeLikeOp {
193 public:
194  static bool classof(const MachineInstr *MI) {
195  return MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR;
196  }
197 };
198 
199 /// Represents a G_PTR_ADD.
200 class GPtrAdd : public GenericMachineInstr {
201 public:
202  Register getBaseReg() const { return getReg(1); }
203  Register getOffsetReg() const { return getReg(2); }
204 
205  static bool classof(const MachineInstr *MI) {
206  return MI->getOpcode() == TargetOpcode::G_PTR_ADD;
207  }
208 };
209 
210 /// Represents a G_IMPLICIT_DEF.
212 public:
213  static bool classof(const MachineInstr *MI) {
214  return MI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF;
215  }
216 };
217 
218 /// Represents a G_SELECT.
219 class GSelect : public GenericMachineInstr {
220 public:
221  Register getCondReg() const { return getReg(1); }
222  Register getTrueReg() const { return getReg(2); }
223  Register getFalseReg() const { return getReg(3); }
224 
225  static bool classof(const MachineInstr *MI) {
226  return MI->getOpcode() == TargetOpcode::G_SELECT;
227  }
228 };
229 
230 /// Represent a G_ICMP or G_FCMP.
231 class GAnyCmp : public GenericMachineInstr {
232 public:
234  return static_cast<CmpInst::Predicate>(getOperand(1).getPredicate());
235  }
236  Register getLHSReg() const { return getReg(2); }
237  Register getRHSReg() const { return getReg(3); }
238 
239  static bool classof(const MachineInstr *MI) {
240  return MI->getOpcode() == TargetOpcode::G_ICMP ||
241  MI->getOpcode() == TargetOpcode::G_FCMP;
242  }
243 };
244 
245 /// Represent a G_ICMP.
246 class GICmp : public GAnyCmp {
247 public:
248  static bool classof(const MachineInstr *MI) {
249  return MI->getOpcode() == TargetOpcode::G_ICMP;
250  }
251 };
252 
253 /// Represent a G_FCMP.
254 class GFCmp : public GAnyCmp {
255 public:
256  static bool classof(const MachineInstr *MI) {
257  return MI->getOpcode() == TargetOpcode::G_FCMP;
258  }
259 };
260 
261 } // namespace llvm
262 
263 #endif // LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
llvm::GExtLoad
Represents either a G_SEXTLOAD or G_ZEXTLOAD.
Definition: GenericMachineInstrs.h:105
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::GBuildVector
Represents a G_BUILD_VECTOR.
Definition: GenericMachineInstrs.h:192
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::GLoad
Represents a G_LOAD.
Definition: GenericMachineInstrs.h:97
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::GLoadStore::isVolatile
bool isVolatile() const
Returns true if the attached MachineMemOpeand as the volatile flag set.
Definition: GenericMachineInstrs.h:52
llvm::GMergeLikeOp::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:163
llvm::GAnyCmp::getRHSReg
Register getRHSReg() const
Definition: GenericMachineInstrs.h:237
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:731
llvm::GAnyCmp::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:239
llvm::GSelect
Represents a G_SELECT.
Definition: GenericMachineInstrs.h:219
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
llvm::GStore::getValueReg
Register getValueReg() const
Get the stored value register.
Definition: GenericMachineInstrs.h:133
llvm::GImplicitDef::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:213
llvm::MachineMemOperand::getSizeInBits
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
Definition: MachineMemOperand.h:240
llvm::GICmp::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:248
llvm::GLoadStore::getMemSizeInBits
uint64_t getMemSizeInBits() const
Returns the size in bits of the memory access.
Definition: GenericMachineInstrs.h:63
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::GMerge::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:178
llvm::GUnmerge::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:148
llvm::GSelect::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:225
llvm::MachineMemOperand::isUnordered
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
Definition: MachineMemOperand.h:303
llvm::GZExtLoad::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:124
llvm::GSelect::getCondReg
Register getCondReg() const
Definition: GenericMachineInstrs.h:221
llvm::GLoadStore::isAtomic
bool isAtomic() const
Returns true if the attached MachineMemOperand has the atomic flag set.
Definition: GenericMachineInstrs.h:50
llvm::GFCmp::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:256
llvm::GAnyLoad::getDstReg
Register getDstReg() const
Get the definition register of the loaded value.
Definition: GenericMachineInstrs.h:82
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::GSExtLoad
Represents a G_SEXTLOAD.
Definition: GenericMachineInstrs.h:114
llvm::GLoadStore::isSimple
bool isSimple() const
Returns true if the memory operation is neither atomic or volatile.
Definition: GenericMachineInstrs.h:54
TargetOpcodes.h
llvm::GExtLoad::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:107
llvm::GZExtLoad
Represents a G_ZEXTLOAD.
Definition: GenericMachineInstrs.h:122
llvm::GLoadStore::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:65
llvm::GLoadStore::getPointerReg
Register getPointerReg() const
Get the source register of the pointer value.
Definition: GenericMachineInstrs.h:44
llvm::GUnmerge::getSourceReg
Register getSourceReg() const
Get the unmerge source register.
Definition: GenericMachineInstrs.h:146
llvm::GStore
Represents a G_STORE.
Definition: GenericMachineInstrs.h:130
llvm::GPtrAdd
Represents a G_PTR_ADD.
Definition: GenericMachineInstrs.h:200
llvm::GStore::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:135
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::GAnyLoad
Represents any generic load, including sign/zero extending variants.
Definition: GenericMachineInstrs.h:79
llvm::GPtrAdd::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:205
llvm::GMergeLikeOp::getSourceReg
Register getSourceReg(unsigned I) const
Returns the I'th source register.
Definition: GenericMachineInstrs.h:161
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::GLoadStore::getMemSize
uint64_t getMemSize() const
Returns the size in bytes of the memory access.
Definition: GenericMachineInstrs.h:61
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition: MachineOperand.h:597
llvm::GPtrAdd::getBaseReg
Register getBaseReg() const
Definition: GenericMachineInstrs.h:202
llvm::GPtrAdd::getOffsetReg
Register getOffsetReg() const
Definition: GenericMachineInstrs.h:203
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::GAnyCmp
Represent a G_ICMP or G_FCMP.
Definition: GenericMachineInstrs.h:231
llvm::GSExtLoad::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:116
llvm::GConcatVectors
Represents a G_CONCAT_VECTORS.
Definition: GenericMachineInstrs.h:184
llvm::GenericMachineInstr::getReg
Register getReg(unsigned Idx) const
Access the Idx'th operand as a register and return it.
Definition: GenericMachineInstrs.h:32
llvm::GAnyCmp::getCond
CmpInst::Predicate getCond() const
Definition: GenericMachineInstrs.h:233
llvm::GMergeLikeOp
Represents G_BUILD_VECTOR, G_CONCAT_VECTORS or G_MERGE_VALUES.
Definition: GenericMachineInstrs.h:156
llvm::GUnmerge
Represents a G_UNMERGE_VALUES.
Definition: GenericMachineInstrs.h:141
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::GMerge
Represents a G_MERGE_VALUES.
Definition: GenericMachineInstrs.h:176
llvm::GLoadStore::isUnordered
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
Definition: GenericMachineInstrs.h:58
llvm::GAnyCmp::getLHSReg
Register getLHSReg() const
Definition: GenericMachineInstrs.h:236
llvm::GSelect::getTrueReg
Register getTrueReg() const
Definition: GenericMachineInstrs.h:222
llvm::MachineMemOperand::isVolatile
bool isVolatile() const
Definition: MachineMemOperand.h:289
llvm::GenericMachineInstr
A base class for all GenericMachineInstrs.
Definition: GenericMachineInstrs.h:26
llvm::GImplicitDef
Represents a G_IMPLICIT_DEF.
Definition: GenericMachineInstrs.h:211
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:235
Casting.h
llvm::GBuildVector::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:194
llvm::GenericMachineInstr::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:34
llvm::GLoad::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:99
llvm::GLoadStore
Represents any type of generic load or store.
Definition: GenericMachineInstrs.h:41
llvm::MachineMemOperand::isAtomic
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
Definition: MachineMemOperand.h:296
llvm::GMergeLikeOp::getNumSources
unsigned getNumSources() const
Returns the number of source registers.
Definition: GenericMachineInstrs.h:159
Instructions.h
llvm::GConcatVectors::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:186
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:519
llvm::GLoadStore::getMMO
MachineMemOperand & getMMO() const
Get the MachineMemOperand on this instruction.
Definition: GenericMachineInstrs.h:47
MachineMemOperand.h
llvm::GAnyLoad::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:84
llvm::GenericMachineInstr::GenericMachineInstr
GenericMachineInstr()=delete
llvm::GFCmp
Represent a G_FCMP.
Definition: GenericMachineInstrs.h:254
llvm::GSelect::getFalseReg
Register getFalseReg() const
Definition: GenericMachineInstrs.h:223
llvm::GICmp
Represent a G_ICMP.
Definition: GenericMachineInstrs.h:246
llvm::GUnmerge::getNumDefs
unsigned getNumDefs() const
Returns the number of def registers.
Definition: GenericMachineInstrs.h:144