LLVM  14.0.0git
GenericMachineInstrs.h
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1 //===- llvm/CodeGen/GlobalISel/GenericMachineInstrs.h -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// Declares convenience wrapper classes for interpreting MachineInstr instances
10 /// as specific generic operations.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
15 #define LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
16 
20 #include "llvm/Support/Casting.h"
21 
22 namespace llvm {
23 
24 /// A base class for all GenericMachineInstrs.
26 public:
27  GenericMachineInstr() = delete;
28 
29  /// Access the Idx'th operand as a register and return it.
30  /// This assumes that the Idx'th operand is a Register type.
31  Register getReg(unsigned Idx) const { return getOperand(Idx).getReg(); }
32 
33  static bool classof(const MachineInstr *MI) {
34  return isPreISelGenericOpcode(MI->getOpcode());
35  }
36 };
37 
38 /// Represents any type of generic load or store.
39 /// G_LOAD, G_STORE, G_ZEXTLOAD, G_SEXTLOAD.
41 public:
42  /// Get the source register of the pointer value.
43  Register getPointerReg() const { return getOperand(1).getReg(); }
44 
45  /// Get the MachineMemOperand on this instruction.
46  MachineMemOperand &getMMO() const { return **memoperands_begin(); }
47 
48  /// Returns true if the attached MachineMemOperand has the atomic flag set.
49  bool isAtomic() const { return getMMO().isAtomic(); }
50  /// Returns true if the attached MachineMemOpeand as the volatile flag set.
51  bool isVolatile() const { return getMMO().isVolatile(); }
52  /// Returns true if the memory operation is neither atomic or volatile.
53  bool isSimple() const { return !isAtomic() && !isVolatile(); }
54  /// Returns true if this memory operation doesn't have any ordering
55  /// constraints other than normal aliasing. Volatile and (ordered) atomic
56  /// memory operations can't be reordered.
57  bool isUnordered() const { return getMMO().isUnordered(); }
58 
59  /// Returns the size in bytes of the memory access.
60  uint64_t getMemSize() const { return getMMO().getSize();
61  } /// Returns the size in bits of the memory access.
63 
64  static bool classof(const MachineInstr *MI) {
65  switch (MI->getOpcode()) {
66  case TargetOpcode::G_LOAD:
67  case TargetOpcode::G_STORE:
68  case TargetOpcode::G_ZEXTLOAD:
69  case TargetOpcode::G_SEXTLOAD:
70  return true;
71  default:
72  return false;
73  }
74  }
75 };
76 
77 /// Represents any generic load, including sign/zero extending variants.
78 class GAnyLoad : public GLoadStore {
79 public:
80  /// Get the definition register of the loaded value.
81  Register getDstReg() const { return getOperand(0).getReg(); }
82 
83  static bool classof(const MachineInstr *MI) {
84  switch (MI->getOpcode()) {
85  case TargetOpcode::G_LOAD:
86  case TargetOpcode::G_ZEXTLOAD:
87  case TargetOpcode::G_SEXTLOAD:
88  return true;
89  default:
90  return false;
91  }
92  }
93 };
94 
95 /// Represents a G_LOAD.
96 class GLoad : public GAnyLoad {
97 public:
98  static bool classof(const MachineInstr *MI) {
99  return MI->getOpcode() == TargetOpcode::G_LOAD;
100  }
101 };
102 
103 /// Represents either a G_SEXTLOAD or G_ZEXTLOAD.
104 class GExtLoad : public GAnyLoad {
105 public:
106  static bool classof(const MachineInstr *MI) {
107  return MI->getOpcode() == TargetOpcode::G_SEXTLOAD ||
108  MI->getOpcode() == TargetOpcode::G_ZEXTLOAD;
109  }
110 };
111 
112 /// Represents a G_SEXTLOAD.
113 class GSExtLoad : public GExtLoad {
114 public:
115  static bool classof(const MachineInstr *MI) {
116  return MI->getOpcode() == TargetOpcode::G_SEXTLOAD;
117  }
118 };
119 
120 /// Represents a G_ZEXTLOAD.
121 class GZExtLoad : public GExtLoad {
122 public:
123  static bool classof(const MachineInstr *MI) {
124  return MI->getOpcode() == TargetOpcode::G_ZEXTLOAD;
125  }
126 };
127 
128 /// Represents a G_STORE.
129 class GStore : public GLoadStore {
130 public:
131  /// Get the stored value register.
132  Register getValueReg() const { return getOperand(0).getReg(); }
133 
134  static bool classof(const MachineInstr *MI) {
135  return MI->getOpcode() == TargetOpcode::G_STORE;
136  }
137 };
138 
139 /// Represents a G_UNMERGE_VALUES.
141 public:
142  /// Returns the number of def registers.
143  unsigned getNumDefs() const { return getNumOperands() - 1; }
144  /// Get the unmerge source register.
146 
147  static bool classof(const MachineInstr *MI) {
148  return MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES;
149  }
150 };
151 
152 /// Represents G_BUILD_VECTOR, G_CONCAT_VECTORS or G_MERGE_VALUES.
153 /// All these have the common property of generating a single value from
154 /// multiple sources.
156 public:
157  /// Returns the number of source registers.
158  unsigned getNumSources() const { return getNumOperands() - 1; }
159  /// Returns the I'th source register.
160  Register getSourceReg(unsigned I) const { return getReg(I + 1); }
161 
162  static bool classof(const MachineInstr *MI) {
163  switch (MI->getOpcode()) {
164  case TargetOpcode::G_MERGE_VALUES:
165  case TargetOpcode::G_CONCAT_VECTORS:
166  case TargetOpcode::G_BUILD_VECTOR:
167  return true;
168  default:
169  return false;
170  }
171  }
172 };
173 
174 /// Represents a G_MERGE_VALUES.
175 class GMerge : public GMergeLikeOp {
176 public:
177  static bool classof(const MachineInstr *MI) {
178  return MI->getOpcode() == TargetOpcode::G_MERGE_VALUES;
179  }
180 };
181 
182 /// Represents a G_CONCAT_VECTORS.
183 class GConcatVectors : public GMergeLikeOp {
184 public:
185  static bool classof(const MachineInstr *MI) {
186  return MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS;
187  }
188 };
189 
190 /// Represents a G_BUILD_VECTOR.
191 class GBuildVector : public GMergeLikeOp {
192 public:
193  static bool classof(const MachineInstr *MI) {
194  return MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR;
195  }
196 };
197 
198 /// Represents a G_PTR_ADD.
199 class GPtrAdd : public GenericMachineInstr {
200 public:
201  Register getBaseReg() const { return getReg(1); }
202  Register getOffsetReg() const { return getReg(2); }
203 
204  static bool classof(const MachineInstr *MI) {
205  return MI->getOpcode() == TargetOpcode::G_PTR_ADD;
206  }
207 };
208 
209 /// Represents a G_IMPLICIT_DEF.
211 public:
212  static bool classof(const MachineInstr *MI) {
213  return MI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF;
214  }
215 };
216 
217 /// Represents a G_SELECT.
218 class GSelect : public GenericMachineInstr {
219 public:
220  Register getCondReg() const { return getReg(1); }
221  Register getTrueReg() const { return getReg(2); }
222  Register getFalseReg() const { return getReg(3); }
223 
224  static bool classof(const MachineInstr *MI) {
225  return MI->getOpcode() == TargetOpcode::G_SELECT;
226  }
227 };
228 
229 } // namespace llvm
230 
231 #endif // LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
llvm::GExtLoad
Represents either a G_SEXTLOAD or G_ZEXTLOAD.
Definition: GenericMachineInstrs.h:104
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::GBuildVector
Represents a G_BUILD_VECTOR.
Definition: GenericMachineInstrs.h:191
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::GLoad
Represents a G_LOAD.
Definition: GenericMachineInstrs.h:96
llvm::GLoadStore::isVolatile
bool isVolatile() const
Returns true if the attached MachineMemOpeand as the volatile flag set.
Definition: GenericMachineInstrs.h:51
llvm::GMergeLikeOp::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:162
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:708
llvm::GSelect
Represents a G_SELECT.
Definition: GenericMachineInstrs.h:218
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
llvm::GStore::getValueReg
Register getValueReg() const
Get the stored value register.
Definition: GenericMachineInstrs.h:132
llvm::GImplicitDef::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:212
llvm::MachineMemOperand::getSizeInBits
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
Definition: MachineMemOperand.h:241
llvm::GLoadStore::getMemSizeInBits
uint64_t getMemSizeInBits() const
Returns the size in bits of the memory access.
Definition: GenericMachineInstrs.h:62
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::GMerge::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:177
llvm::GUnmerge::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:147
llvm::GSelect::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:224
llvm::MachineMemOperand::isUnordered
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
Definition: MachineMemOperand.h:304
llvm::GZExtLoad::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:123
llvm::GSelect::getCondReg
Register getCondReg() const
Definition: GenericMachineInstrs.h:220
llvm::GLoadStore::isAtomic
bool isAtomic() const
Returns true if the attached MachineMemOperand has the atomic flag set.
Definition: GenericMachineInstrs.h:49
llvm::GAnyLoad::getDstReg
Register getDstReg() const
Get the definition register of the loaded value.
Definition: GenericMachineInstrs.h:81
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::GSExtLoad
Represents a G_SEXTLOAD.
Definition: GenericMachineInstrs.h:113
llvm::GLoadStore::isSimple
bool isSimple() const
Returns true if the memory operation is neither atomic or volatile.
Definition: GenericMachineInstrs.h:53
TargetOpcodes.h
llvm::GExtLoad::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:106
llvm::GZExtLoad
Represents a G_ZEXTLOAD.
Definition: GenericMachineInstrs.h:121
llvm::GLoadStore::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:64
llvm::GLoadStore::getPointerReg
Register getPointerReg() const
Get the source register of the pointer value.
Definition: GenericMachineInstrs.h:43
llvm::GUnmerge::getSourceReg
Register getSourceReg() const
Get the unmerge source register.
Definition: GenericMachineInstrs.h:145
llvm::GStore
Represents a G_STORE.
Definition: GenericMachineInstrs.h:129
llvm::GPtrAdd
Represents a G_PTR_ADD.
Definition: GenericMachineInstrs.h:199
llvm::GStore::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:134
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::GAnyLoad
Represents any generic load, including sign/zero extending variants.
Definition: GenericMachineInstrs.h:78
llvm::GPtrAdd::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:204
llvm::GMergeLikeOp::getSourceReg
Register getSourceReg(unsigned I) const
Returns the I'th source register.
Definition: GenericMachineInstrs.h:160
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::GLoadStore::getMemSize
uint64_t getMemSize() const
Returns the size in bytes of the memory access.
Definition: GenericMachineInstrs.h:60
llvm::GPtrAdd::getBaseReg
Register getBaseReg() const
Definition: GenericMachineInstrs.h:201
llvm::GPtrAdd::getOffsetReg
Register getOffsetReg() const
Definition: GenericMachineInstrs.h:202
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::GSExtLoad::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:115
llvm::GConcatVectors
Represents a G_CONCAT_VECTORS.
Definition: GenericMachineInstrs.h:183
llvm::GenericMachineInstr::getReg
Register getReg(unsigned Idx) const
Access the Idx'th operand as a register and return it.
Definition: GenericMachineInstrs.h:31
llvm::GMergeLikeOp
Represents G_BUILD_VECTOR, G_CONCAT_VECTORS or G_MERGE_VALUES.
Definition: GenericMachineInstrs.h:155
llvm::GUnmerge
Represents a G_UNMERGE_VALUES.
Definition: GenericMachineInstrs.h:140
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::GMerge
Represents a G_MERGE_VALUES.
Definition: GenericMachineInstrs.h:175
llvm::GLoadStore::isUnordered
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
Definition: GenericMachineInstrs.h:57
llvm::GSelect::getTrueReg
Register getTrueReg() const
Definition: GenericMachineInstrs.h:221
llvm::MachineMemOperand::isVolatile
bool isVolatile() const
Definition: MachineMemOperand.h:290
llvm::GenericMachineInstr
A base class for all GenericMachineInstrs.
Definition: GenericMachineInstrs.h:25
llvm::GImplicitDef
Represents a G_IMPLICIT_DEF.
Definition: GenericMachineInstrs.h:210
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:236
Casting.h
llvm::GBuildVector::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:193
llvm::GenericMachineInstr::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:33
llvm::GLoad::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:98
llvm::GLoadStore
Represents any type of generic load or store.
Definition: GenericMachineInstrs.h:40
llvm::MachineMemOperand::isAtomic
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
Definition: MachineMemOperand.h:297
llvm::GMergeLikeOp::getNumSources
unsigned getNumSources() const
Returns the number of source registers.
Definition: GenericMachineInstrs.h:158
llvm::GConcatVectors::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:185
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
llvm::GLoadStore::getMMO
MachineMemOperand & getMMO() const
Get the MachineMemOperand on this instruction.
Definition: GenericMachineInstrs.h:46
MachineMemOperand.h
llvm::GAnyLoad::classof
static bool classof(const MachineInstr *MI)
Definition: GenericMachineInstrs.h:83
llvm::GenericMachineInstr::GenericMachineInstr
GenericMachineInstr()=delete
llvm::GSelect::getFalseReg
Register getFalseReg() const
Definition: GenericMachineInstrs.h:222
llvm::GUnmerge::getNumDefs
unsigned getNumDefs() const
Returns the number of def registers.
Definition: GenericMachineInstrs.h:143