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14 #ifndef LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
15 #define LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
66 switch (
MI->getOpcode()) {
67 case TargetOpcode::G_LOAD:
68 case TargetOpcode::G_STORE:
69 case TargetOpcode::G_ZEXTLOAD:
70 case TargetOpcode::G_SEXTLOAD:
85 switch (
MI->getOpcode()) {
86 case TargetOpcode::G_LOAD:
87 case TargetOpcode::G_ZEXTLOAD:
88 case TargetOpcode::G_SEXTLOAD:
100 return MI->getOpcode() == TargetOpcode::G_LOAD;
108 return MI->getOpcode() == TargetOpcode::G_SEXTLOAD ||
109 MI->getOpcode() == TargetOpcode::G_ZEXTLOAD;
117 return MI->getOpcode() == TargetOpcode::G_SEXTLOAD;
125 return MI->getOpcode() == TargetOpcode::G_ZEXTLOAD;
136 return MI->getOpcode() == TargetOpcode::G_STORE;
149 return MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES;
164 switch (
MI->getOpcode()) {
165 case TargetOpcode::G_MERGE_VALUES:
166 case TargetOpcode::G_CONCAT_VECTORS:
167 case TargetOpcode::G_BUILD_VECTOR:
179 return MI->getOpcode() == TargetOpcode::G_MERGE_VALUES;
187 return MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS;
195 return MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR;
206 return MI->getOpcode() == TargetOpcode::G_PTR_ADD;
214 return MI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF;
226 return MI->getOpcode() == TargetOpcode::G_SELECT;
240 return MI->getOpcode() == TargetOpcode::G_ICMP ||
241 MI->getOpcode() == TargetOpcode::G_FCMP;
249 return MI->getOpcode() == TargetOpcode::G_ICMP;
257 return MI->getOpcode() == TargetOpcode::G_FCMP;
263 #endif // LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
Represents either a G_SEXTLOAD or G_ZEXTLOAD.
Represents a G_BUILD_VECTOR.
This is an optimization pass for GlobalISel generic memory operations.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
bool isVolatile() const
Returns true if the attached MachineMemOpeand as the volatile flag set.
static bool classof(const MachineInstr *MI)
Register getRHSReg() const
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
static bool classof(const MachineInstr *MI)
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Register getValueReg() const
Get the stored value register.
static bool classof(const MachineInstr *MI)
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
static bool classof(const MachineInstr *MI)
uint64_t getMemSizeInBits() const
Returns the size in bits of the memory access.
A description of a memory reference used in the backend.
static bool classof(const MachineInstr *MI)
static bool classof(const MachineInstr *MI)
static bool classof(const MachineInstr *MI)
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
static bool classof(const MachineInstr *MI)
Register getCondReg() const
bool isAtomic() const
Returns true if the attached MachineMemOperand has the atomic flag set.
static bool classof(const MachineInstr *MI)
Register getDstReg() const
Get the definition register of the loaded value.
const MachineOperand & getOperand(unsigned i) const
bool isSimple() const
Returns true if the memory operation is neither atomic or volatile.
static bool classof(const MachineInstr *MI)
static bool classof(const MachineInstr *MI)
Register getPointerReg() const
Get the source register of the pointer value.
Register getSourceReg() const
Get the unmerge source register.
static bool classof(const MachineInstr *MI)
Representation of each machine instruction.
Represents any generic load, including sign/zero extending variants.
static bool classof(const MachineInstr *MI)
Register getSourceReg(unsigned I) const
Returns the I'th source register.
uint64_t getMemSize() const
Returns the size in bytes of the memory access.
unsigned getPredicate() const
Register getBaseReg() const
Register getOffsetReg() const
Register getReg() const
getReg - Returns the register number.
Represent a G_ICMP or G_FCMP.
static bool classof(const MachineInstr *MI)
Represents a G_CONCAT_VECTORS.
Register getReg(unsigned Idx) const
Access the Idx'th operand as a register and return it.
CmpInst::Predicate getCond() const
Represents G_BUILD_VECTOR, G_CONCAT_VECTORS or G_MERGE_VALUES.
Represents a G_UNMERGE_VALUES.
Wrapper class representing virtual and physical registers.
Represents a G_MERGE_VALUES.
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
Register getLHSReg() const
Register getTrueReg() const
A base class for all GenericMachineInstrs.
Represents a G_IMPLICIT_DEF.
uint64_t getSize() const
Return the size in bytes of the memory reference.
static bool classof(const MachineInstr *MI)
static bool classof(const MachineInstr *MI)
static bool classof(const MachineInstr *MI)
Represents any type of generic load or store.
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
unsigned getNumSources() const
Returns the number of source registers.
static bool classof(const MachineInstr *MI)
unsigned getNumOperands() const
Retuns the total number of operands.
MachineMemOperand & getMMO() const
Get the MachineMemOperand on this instruction.
static bool classof(const MachineInstr *MI)
GenericMachineInstr()=delete
Register getFalseReg() const
unsigned getNumDefs() const
Returns the number of def registers.