LLVM 17.0.0git
AMDGPURegisterBankInfo.h
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1//===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
15
16#include "llvm/ADT/SmallSet.h"
20
21#define GET_REGBANK_DECLARATIONS
22#include "AMDGPUGenRegisterBank.inc"
23
24namespace llvm {
25
26class LLT;
27class GCNSubtarget;
28class MachineIRBuilder;
29class SIInstrInfo;
30class SIRegisterInfo;
31class TargetRegisterInfo;
32
33/// This class provides the information for the target register banks.
35
36protected:
37
38#define GET_TARGET_REGBANK_CLASS
39#include "AMDGPUGenRegisterBank.inc"
40};
41
43public:
47
48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const;
49
51 SmallSet<Register, 4> &SGPROperandRegs,
54 ArrayRef<unsigned> OpIndices) const;
55
59 SmallSet<Register, 4> &SGPROperandRegs,
61
63 Register Src) const;
64
68 ArrayRef<unsigned> OpIndices) const;
71 ArrayRef<unsigned> OpIndices) const;
72
74 unsigned OpIdx) const;
76 const OperandsMapper &OpdMapper,
79 const OperandsMapper &OpdMapper,
81 bool
83 const OperandsMapper &OpdMapper,
84 MachineRegisterInfo &MRI, int RSrcIdx) const;
85 unsigned setBufferOffsets(MachineIRBuilder &B, Register CombinedOffset,
86 Register &VOffsetReg, Register &SOffsetReg,
87 int64_t &InstOffsetVal, Align Alignment) const;
88 bool applyMappingSBufferLoad(const OperandsMapper &OpdMapper) const;
89
90 bool applyMappingBFE(const OperandsMapper &OpdMapper, bool Signed) const;
91
92 bool applyMappingMAD_64_32(const OperandsMapper &OpdMapper) const;
93
95 Register Reg) const;
96
97 std::pair<Register, unsigned>
99
100 /// See RegisterBankInfo::applyMapping.
101 void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
102
104 Register Ptr) const;
105
108
110 unsigned Default = AMDGPU::VGPRRegBankID) const;
111
112 // Return a value mapping for an operand that is required to be an SGPR.
115 const TargetRegisterInfo &TRI) const;
116
117 // Return a value mapping for an operand that is required to be a VGPR.
120 const TargetRegisterInfo &TRI) const;
121
122 // Return a value mapping for an operand that is required to be a AGPR.
125 const TargetRegisterInfo &TRI) const;
126
127 /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p
128 /// Regs. This appropriately sets the regbank of the new registers.
131 LLT HalfTy,
132 Register Reg) const;
133
134 template <unsigned NumOps>
136 int8_t RegBanks[NumOps];
137 int16_t Cost;
138 };
139
140 template <unsigned NumOps>
143 const std::array<unsigned, NumOps> RegSrcOpIdx,
144 ArrayRef<OpRegBankEntry<NumOps>> Table) const;
145
148 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
149
152 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
153
154 unsigned getMappingType(const MachineRegisterInfo &MRI,
155 const MachineInstr &MI) const;
156
157 bool isSALUMapping(const MachineInstr &MI) const;
158
162 const MachineInstr &MI) const;
163
165 const MachineInstr &MI,
166 int RsrcIdx) const;
167
168public:
170
171 bool isDivergentRegBank(const RegisterBank *RB) const override;
172
173 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
174 unsigned Size) const override;
175
176 unsigned getBreakDownCost(const ValueMapping &ValMapping,
177 const RegisterBank *CurBank = nullptr) const override;
178
180 LLT) const override;
181
183 getInstrAlternativeMappings(const MachineInstr &MI) const override;
184
185 const InstructionMapping &
186 getInstrMapping(const MachineInstr &MI) const override;
187
188private:
189
190 bool foldExtractEltToCmpSelect(MachineInstr &MI,
192 const OperandsMapper &OpdMapper) const;
193 bool foldInsertEltToCmpSelect(MachineInstr &MI,
195 const OperandsMapper &OpdMapper) const;
196};
197} // End llvm namespace.
198#endif
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
uint64_t Size
IRTranslator LLVM IR MI
unsigned Reg
This file defines the SmallSet class.
This class provides the information for the target register banks.
bool applyMappingLoad(MachineInstr &MI, const OperandsMapper &OpdMapper, MachineRegisterInfo &MRI) const
unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const override
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
std::pair< Register, unsigned > splitBufferOffsets(MachineIRBuilder &B, Register Offset) const
bool collectWaterfallOperands(SmallSet< Register, 4 > &SGPROperandRegs, MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef< unsigned > OpIndices) const
const InstructionMapping & getImageMapping(const MachineRegisterInfo &MRI, const MachineInstr &MI, int RsrcIdx) const
InstructionMappings addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps > > Table) const
bool applyMappingMAD_64_32(const OperandsMapper &OpdMapper) const
RegisterBankInfo::InstructionMappings getInstrAlternativeMappingsIntrinsicWSideEffects(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const
bool applyMappingImage(MachineInstr &MI, const OperandsMapper &OpdMapper, MachineRegisterInfo &MRI, int RSrcIdx) const
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
bool executeInWaterfallLoop(MachineIRBuilder &B, iterator_range< MachineBasicBlock::iterator > Range, SmallSet< Register, 4 > &SGPROperandRegs, MachineRegisterInfo &MRI) const
Legalize instruction MI where operands in OpIndices must be SGPRs.
unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI, unsigned Default=AMDGPU::VGPRRegBankID) const
Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg) const
Handle register layout difference for f16 images for some subtargets.
const RegisterBankInfo::InstructionMapping & getInstrMappingForLoad(const MachineInstr &MI) const
const ValueMapping * getVGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
void applyMappingImpl(const OperandsMapper &OpdMapper) const override
See RegisterBankInfo::applyMapping.
unsigned setBufferOffsets(MachineIRBuilder &B, Register CombinedOffset, Register &VOffsetReg, Register &SOffsetReg, int64_t &InstOffsetVal, Align Alignment) const
const ValueMapping * getSGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
void split64BitValueForMapping(MachineIRBuilder &B, SmallVector< Register, 2 > &Regs, LLT HalfTy, Register Reg) const
Split 64-bit value Reg into two 32-bit halves and populate them into Regs.
const ValueMapping * getValueMappingForPtr(const MachineRegisterInfo &MRI, Register Ptr) const
Return the mapping for a pointer argument.
unsigned getMappingType(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
RegisterBankInfo::InstructionMappings getInstrAlternativeMappingsIntrinsic(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
bool isDivergentRegBank(const RegisterBank *RB) const override
Returns true if the register bank is considered divergent.
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
const InstructionMapping & getDefaultMappingSOP(const MachineInstr &MI) const
const InstructionMapping & getDefaultMappingAllVGPR(const MachineInstr &MI) const
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
This function must return a legal mapping, because AMDGPURegisterBankInfo::getInstrAlternativeMapping...
bool applyMappingDynStackAlloc(MachineInstr &MI, const OperandsMapper &OpdMapper, MachineRegisterInfo &MRI) const
bool applyMappingSBufferLoad(const OperandsMapper &OpdMapper) const
void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI, unsigned OpIdx) const
unsigned getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const override
Get the cost of using ValMapping to decompose a register.
const ValueMapping * getAGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
const InstructionMapping & getDefaultMappingVOP(const MachineInstr &MI) const
bool applyMappingBFE(const OperandsMapper &OpdMapper, bool Signed) const
bool isSALUMapping(const MachineInstr &MI) const
Register buildReadFirstLane(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Src) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Helper class that represents how the value of an instruction may be mapped and what is the related co...
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
Holds all the information related to register banks.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A range adaptor for a pair of iterators.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
@ Default
The result values are uniform if and only if all operands are uniform.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Helper struct that represents how a value is mapped through different register banks.