LLVM  10.0.0svn
AMDGPURegisterBankInfo.h
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1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
15 
16 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/CodeGen/Register.h"
20 
21 #define GET_REGBANK_DECLARATIONS
22 #include "AMDGPUGenRegisterBank.inc"
23 #undef GET_REGBANK_DECLARATIONS
24 
25 namespace llvm {
26 
27 class LLT;
28 class GCNSubtarget;
29 class MachineIRBuilder;
30 class SIInstrInfo;
31 class SIRegisterInfo;
32 class TargetRegisterInfo;
33 
34 /// This class provides the information for the target register banks.
36 
37 protected:
38 
39 #define GET_TARGET_REGBANK_CLASS
40 #include "AMDGPUGenRegisterBank.inc"
41 };
43  const GCNSubtarget &Subtarget;
44  const SIRegisterInfo *TRI;
45  const SIInstrInfo *TII;
46 
47  bool collectWaterfallOperands(
48  SmallSet<Register, 4> &SGPROperandRegs,
51  ArrayRef<unsigned> OpIndices) const;
52 
53  bool executeInWaterfallLoop(
56  SmallSet<Register, 4> &SGPROperandRegs,
57  MachineRegisterInfo &MRI) const;
58 
59  bool executeInWaterfallLoop(MachineIRBuilder &B,
60  MachineInstr &MI,
62  ArrayRef<unsigned> OpIndices) const;
63  bool executeInWaterfallLoop(MachineInstr &MI,
65  ArrayRef<unsigned> OpIndices) const;
66 
67  void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI,
68  unsigned OpIdx) const;
69  bool applyMappingWideLoad(MachineInstr &MI,
71  MachineRegisterInfo &MRI) const;
72  bool
73  applyMappingImage(MachineInstr &MI,
75  MachineRegisterInfo &MRI, int RSrcIdx) const;
76 
77  Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
78  Register Reg) const;
79 
80  std::pair<Register, unsigned>
81  splitBufferOffsets(MachineIRBuilder &B, Register Offset) const;
82 
83  MachineInstr *selectStoreIntrinsic(MachineIRBuilder &B,
84  MachineInstr &MI) const;
85 
86  /// See RegisterBankInfo::applyMapping.
87  void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
88 
90  getInstrMappingForLoad(const MachineInstr &MI) const;
91 
92  unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
93  const TargetRegisterInfo &TRI,
94  unsigned Default = AMDGPU::VGPRRegBankID) const;
95 
96  // Return a value mapping for an operand that is required to be an SGPR.
97  const ValueMapping *getSGPROpMapping(Register Reg,
98  const MachineRegisterInfo &MRI,
99  const TargetRegisterInfo &TRI) const;
100 
101  // Return a value mapping for an operand that is required to be a VGPR.
102  const ValueMapping *getVGPROpMapping(Register Reg,
103  const MachineRegisterInfo &MRI,
104  const TargetRegisterInfo &TRI) const;
105 
106  /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p
107  /// Regs. This appropriately sets the regbank of the new registers.
108  void split64BitValueForMapping(MachineIRBuilder &B,
110  LLT HalfTy,
111  Register Reg) const;
112 
113  template <unsigned NumOps>
114  struct OpRegBankEntry {
115  int8_t RegBanks[NumOps];
116  int16_t Cost;
117  };
118 
119  template <unsigned NumOps>
121  addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI,
122  const std::array<unsigned, NumOps> RegSrcOpIdx,
123  ArrayRef<OpRegBankEntry<NumOps>> Table) const;
124 
126  getInstrAlternativeMappingsIntrinsic(
127  const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
128 
130  getInstrAlternativeMappingsIntrinsicWSideEffects(
131  const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
132 
133  bool isSALUMapping(const MachineInstr &MI) const;
134  const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
135  const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const;
136  const InstructionMapping &getDefaultMappingAllVGPR(
137  const MachineInstr &MI) const;
138 
139  const InstructionMapping &getImageMapping(const MachineRegisterInfo &MRI,
140  const MachineInstr &MI,
141  int RsrcIdx) const;
142 
143 public:
145 
146  unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
147  unsigned Size) const override;
148 
149  unsigned getBreakDownCost(const ValueMapping &ValMapping,
150  const RegisterBank *CurBank = nullptr) const override;
151 
152  const RegisterBank &
153  getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
154 
156  getInstrAlternativeMappings(const MachineInstr &MI) const override;
157 
158  const InstructionMapping &
159  getInstrMapping(const MachineInstr &MI) const override;
160 };
161 } // End llvm namespace.
162 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned Reg
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
unsigned const TargetRegisterInfo * TRI
Holds all the information related to register banks.
const HexagonInstrInfo * TII
virtual unsigned getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const
Get the cost of using ValMapping to decompose a register.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
Helper class to build MachineInstr.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
This class implements the register bank concept.
Definition: RegisterBank.h:28
Helper struct that represents how a value is mapped through different register banks.
A range adaptor for a pair of iterators.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const
See applyMapping.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
uint32_t Size
Definition: Profile.cpp:46
This class provides the information for the target register banks.
IRTranslator LLVM IR MI
RegisterBank ** RegBanks
Hold the set of supported register banks.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const
Get a register bank that covers RC.