LLVM  15.0.0git
AMDGPURegisterBankInfo.h
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1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
15 
16 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/CodeGen/Register.h"
20 
21 #define GET_REGBANK_DECLARATIONS
22 #include "AMDGPUGenRegisterBank.inc"
23 
24 namespace llvm {
25 
26 class LLT;
27 class GCNSubtarget;
28 class MachineIRBuilder;
29 class SIInstrInfo;
30 class SIRegisterInfo;
31 class TargetRegisterInfo;
32 
33 /// This class provides the information for the target register banks.
35 
36 protected:
37 
38 #define GET_TARGET_REGBANK_CLASS
39 #include "AMDGPUGenRegisterBank.inc"
40 };
41 
43 public:
46  const SIInstrInfo *TII;
47 
48  bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const;
49 
51  SmallSet<Register, 4> &SGPROperandRegs,
54  ArrayRef<unsigned> OpIndices) const;
55 
59  SmallSet<Register, 4> &SGPROperandRegs,
60  MachineRegisterInfo &MRI) const;
61 
63  Register Src) const;
64 
68  ArrayRef<unsigned> OpIndices) const;
71  ArrayRef<unsigned> OpIndices) const;
72 
74  unsigned OpIdx) const;
76  const OperandsMapper &OpdMapper,
77  MachineRegisterInfo &MRI) const;
79  const OperandsMapper &OpdMapper,
80  MachineRegisterInfo &MRI) const;
81  bool
83  const OperandsMapper &OpdMapper,
84  MachineRegisterInfo &MRI, int RSrcIdx) const;
85  bool applyMappingSBufferLoad(const OperandsMapper &OpdMapper) const;
86 
87  bool applyMappingBFE(const OperandsMapper &OpdMapper, bool Signed) const;
88 
89  bool applyMappingMAD_64_32(const OperandsMapper &OpdMapper) const;
90 
92  Register Reg) const;
93 
94  std::pair<Register, unsigned>
96 
97  /// See RegisterBankInfo::applyMapping.
98  void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
99 
101  Register Ptr) const;
102 
104  getInstrMappingForLoad(const MachineInstr &MI) const;
105 
107  unsigned Default = AMDGPU::VGPRRegBankID) const;
108 
109  // Return a value mapping for an operand that is required to be an SGPR.
111  const MachineRegisterInfo &MRI,
112  const TargetRegisterInfo &TRI) const;
113 
114  // Return a value mapping for an operand that is required to be a VGPR.
116  const MachineRegisterInfo &MRI,
117  const TargetRegisterInfo &TRI) const;
118 
119  // Return a value mapping for an operand that is required to be a AGPR.
121  const MachineRegisterInfo &MRI,
122  const TargetRegisterInfo &TRI) const;
123 
124  /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p
125  /// Regs. This appropriately sets the regbank of the new registers.
128  LLT HalfTy,
129  Register Reg) const;
130 
131  template <unsigned NumOps>
132  struct OpRegBankEntry {
133  int8_t RegBanks[NumOps];
134  int16_t Cost;
135  };
136 
137  template <unsigned NumOps>
140  const std::array<unsigned, NumOps> RegSrcOpIdx,
141  ArrayRef<OpRegBankEntry<NumOps>> Table) const;
142 
145  const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
146 
149  const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
150 
151  unsigned getMappingType(const MachineRegisterInfo &MRI,
152  const MachineInstr &MI) const;
153 
154  bool isSALUMapping(const MachineInstr &MI) const;
155 
159  const MachineInstr &MI) const;
160 
162  const MachineInstr &MI,
163  int RsrcIdx) const;
164 
165 public:
167 
168  unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
169  unsigned Size) const override;
170 
171  unsigned getBreakDownCost(const ValueMapping &ValMapping,
172  const RegisterBank *CurBank = nullptr) const override;
173 
175  LLT) const override;
176 
178  getInstrAlternativeMappings(const MachineInstr &MI) const override;
179 
180  const InstructionMapping &
181  getInstrMapping(const MachineInstr &MI) const override;
182 
183 private:
184 
185  bool foldExtractEltToCmpSelect(MachineInstr &MI,
187  const OperandsMapper &OpdMapper) const;
188  bool foldInsertEltToCmpSelect(MachineInstr &MI,
190  const OperandsMapper &OpdMapper) const;
191 };
192 } // End llvm namespace.
193 #endif
llvm::AMDGPURegisterBankInfo::getSGPROpMapping
const ValueMapping * getSGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Definition: AMDGPURegisterBankInfo.cpp:3519
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4637
llvm::AMDGPURegisterBankInfo
Definition: AMDGPURegisterBankInfo.h:42
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::AMDGPURegisterBankInfo::getDefaultMappingAllVGPR
const InstructionMapping & getDefaultMappingAllVGPR(const MachineInstr &MI) const
Definition: AMDGPURegisterBankInfo.cpp:3386
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
RegisterBankInfo.h
llvm::AMDGPURegisterBankInfo::applyMappingImpl
void applyMappingImpl(const OperandsMapper &OpdMapper) const override
See RegisterBankInfo::applyMapping.
Definition: AMDGPURegisterBankInfo.cpp:2112
llvm::AMDGPURegisterBankInfo::AMDGPURegisterBankInfo
AMDGPURegisterBankInfo(const GCNSubtarget &STI)
Definition: AMDGPURegisterBankInfo.cpp:196
MachineBasicBlock.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::AMDGPURegisterBankInfo::getInstrMapping
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
This function must return a legal mapping, because AMDGPURegisterBankInfo::getInstrAlternativeMapping...
Definition: AMDGPURegisterBankInfo.cpp:3555
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::AMDGPURegisterBankInfo::getVGPROpMapping
const ValueMapping * getVGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Definition: AMDGPURegisterBankInfo.cpp:3530
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::AMDGPURegisterBankInfo::TII
const SIInstrInfo * TII
Definition: AMDGPURegisterBankInfo.h:46
llvm::AMDGPURegisterBankInfo::applyMappingSBufferLoad
bool applyMappingSBufferLoad(const OperandsMapper &OpdMapper) const
Definition: AMDGPURegisterBankInfo.cpp:1332
llvm::AMDGPURegisterBankInfo::TRI
const SIRegisterInfo * TRI
Definition: AMDGPURegisterBankInfo.h:45
llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsic
RegisterBankInfo::InstructionMappings getInstrAlternativeMappingsIntrinsic(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
Definition: AMDGPURegisterBankInfo.cpp:334
llvm::AMDGPURegisterBankInfo::OpRegBankEntry::Cost
int16_t Cost
Definition: AMDGPURegisterBankInfo.h:134
llvm::AMDGPURegisterBankInfo::copyCost
unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const override
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
Definition: AMDGPURegisterBankInfo.cpp:218
llvm::AMDGPURegisterBankInfo::OpRegBankEntry::RegBanks
int8_t RegBanks[NumOps]
Definition: AMDGPURegisterBankInfo.h:133
llvm::AMDGPURegisterBankInfo::buildReadFirstLane
Register buildReadFirstLane(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Src) const
Definition: AMDGPURegisterBankInfo.cpp:683
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::AMDGPURegisterBankInfo::applyMappingLoad
bool applyMappingLoad(MachineInstr &MI, const OperandsMapper &OpdMapper, MachineRegisterInfo &MRI) const
Definition: AMDGPURegisterBankInfo.cpp:1049
llvm::AMDGPURegisterBankInfo::getAGPROpMapping
const ValueMapping * getAGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Definition: AMDGPURegisterBankInfo.cpp:3538
llvm::AMDGPURegisterBankInfo::addMappingFromTable
InstructionMappings addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps >> Table) const
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::AMDGPURegisterBankInfo::getValueMappingForPtr
const ValueMapping * getValueMappingForPtr(const MachineRegisterInfo &MRI, Register Ptr) const
Return the mapping for a pointer argument.
Definition: AMDGPURegisterBankInfo.cpp:3449
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::AMDGPURegisterBankInfo::OpRegBankEntry
Definition: AMDGPURegisterBankInfo.h:132
llvm::AMDGPURegisterBankInfo::applyMappingMAD_64_32
bool applyMappingMAD_64_32(const OperandsMapper &OpdMapper) const
Definition: AMDGPURegisterBankInfo.cpp:1558
llvm::AMDGPURegisterBankInfo::constrainOpWithReadfirstlane
void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI, unsigned OpIdx) const
Definition: AMDGPURegisterBankInfo.cpp:1009
llvm::AMDGPURegisterBankInfo::collectWaterfallOperands
bool collectWaterfallOperands(SmallSet< Register, 4 > &SGPROperandRegs, MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef< unsigned > OpIndices) const
Definition: AMDGPURegisterBankInfo.cpp:971
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsicWSideEffects
RegisterBankInfo::InstructionMappings getInstrAlternativeMappingsIntrinsicWSideEffects(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
Definition: AMDGPURegisterBankInfo.cpp:374
llvm::RegisterBankInfo::OperandsMapper
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
Definition: RegisterBankInfo.h:279
llvm::AMDGPURegisterBankInfo::splitBufferOffsets
std::pair< Register, unsigned > splitBufferOffsets(MachineIRBuilder &B, Register Offset) const
Definition: AMDGPURegisterBankInfo.cpp:1802
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::AMDGPURegisterBankInfo::getRegBankFromRegClass
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
Definition: AMDGPURegisterBankInfo.cpp:275
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:219
llvm::AMDGPURegisterBankInfo::Subtarget
const GCNSubtarget & Subtarget
Definition: AMDGPURegisterBankInfo.h:44
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::AMDGPURegisterBankInfo::getBreakDownCost
unsigned getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const override
Get the cost of using ValMapping to decompose a register.
Definition: AMDGPURegisterBankInfo.cpp:249
llvm::RegisterBankInfo::InstructionMapping
Helper class that represents how the value of an instruction may be mapped and what is the related co...
Definition: RegisterBankInfo.h:189
llvm::AMDGPURegisterBankInfo::getMappingType
unsigned getMappingType(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
Definition: AMDGPURegisterBankInfo.cpp:3310
llvm::AMDGPURegisterBankInfo::split64BitValueForMapping
void split64BitValueForMapping(MachineIRBuilder &B, SmallVector< Register, 2 > &Regs, LLT HalfTy, Register Reg) const
Split 64-bit value Reg into two 32-bit halves and populate them into Regs.
Definition: AMDGPURegisterBankInfo.cpp:639
llvm::AMDGPURegisterBankInfo::getDefaultMappingSOP
const InstructionMapping & getDefaultMappingSOP(const MachineInstr &MI) const
Definition: AMDGPURegisterBankInfo.cpp:3344
llvm::AMDGPURegisterBankInfo::applyMappingImage
bool applyMappingImage(MachineInstr &MI, const OperandsMapper &OpdMapper, MachineRegisterInfo &MRI, int RSrcIdx) const
Definition: AMDGPURegisterBankInfo.cpp:1208
llvm::RegisterBankInfo::ValueMapping
Helper struct that represents how a value is mapped through different register banks.
Definition: RegisterBankInfo.h:145
llvm::ArrayRef< unsigned >
llvm::AMDGPURegisterBankInfo::applyMappingDynStackAlloc
bool applyMappingDynStackAlloc(MachineInstr &MI, const OperandsMapper &OpdMapper, MachineRegisterInfo &MRI) const
Definition: AMDGPURegisterBankInfo.cpp:1161
llvm::AMDGPURegisterBankInfo::buildVCopy
bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const
Definition: AMDGPURegisterBankInfo.cpp:1845
llvm::AMDGPUGenRegisterBankInfo
This class provides the information for the target register banks.
Definition: AMDGPURegisterBankInfo.h:34
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPURegisterBankInfo::handleD16VData
Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg) const
Handle register layout difference for f16 images for some subtargets.
Definition: AMDGPURegisterBankInfo.cpp:1763
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop
bool executeInWaterfallLoop(MachineIRBuilder &B, iterator_range< MachineBasicBlock::iterator > Range, SmallSet< Register, 4 > &SGPROperandRegs, MachineRegisterInfo &MRI) const
Legalize instruction MI where operands in OpIndices must be SGPRs.
Definition: AMDGPURegisterBankInfo.cpp:755
llvm::AMDGPURegisterBankInfo::applyMappingBFE
bool applyMappingBFE(const OperandsMapper &OpdMapper, bool Signed) const
Definition: AMDGPURegisterBankInfo.cpp:1451
llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad
const RegisterBankInfo::InstructionMapping & getInstrMappingForLoad(const MachineInstr &MI) const
Definition: AMDGPURegisterBankInfo.cpp:3464
llvm::AMDGPURegisterBankInfo::getDefaultMappingVOP
const InstructionMapping & getDefaultMappingVOP(const MachineInstr &MI) const
Definition: AMDGPURegisterBankInfo.cpp:3362
llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
Definition: AMDGPURegisterBankInfo.cpp:453
llvm::SIInstrInfo
Definition: SIInstrInfo.h:44
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::AMDGPURegisterBankInfo::isSALUMapping
bool isSALUMapping(const MachineInstr &MI) const
Definition: AMDGPURegisterBankInfo.cpp:3328
llvm::AMDGPURegisterBankInfo::getImageMapping
const InstructionMapping & getImageMapping(const MachineRegisterInfo &MRI, const MachineInstr &MI, int RsrcIdx) const
Definition: AMDGPURegisterBankInfo.cpp:3405
Register.h
llvm::AMDGPURegisterBankInfo::getRegBankID
unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI, unsigned Default=AMDGPU::VGPRRegBankID) const
Definition: AMDGPURegisterBankInfo.cpp:3511
SmallSet.h
llvm::LLT
Definition: LowLevelTypeImpl.h:39