LLVM 19.0.0git
AMDGPUInstructionSelector.h
Go to the documentation of this file.
1//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the InstructionSelector class for
10/// AMDGPU.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15
16#include "SIDefines.h"
18#include "llvm/IR/InstrTypes.h"
19
20namespace {
21#define GET_GLOBALISEL_PREDICATE_BITSET
22#define AMDGPUSubtarget GCNSubtarget
23#include "AMDGPUGenGlobalISel.inc"
24#undef GET_GLOBALISEL_PREDICATE_BITSET
25#undef AMDGPUSubtarget
26}
27
28namespace llvm {
29
30namespace AMDGPU {
31struct ImageDimIntrinsicInfo;
32}
33
34class AMDGPURegisterBankInfo;
35class AMDGPUTargetMachine;
36class BlockFrequencyInfo;
37class ProfileSummaryInfo;
38class GCNSubtarget;
39class MachineInstr;
40class MachineIRBuilder;
41class MachineOperand;
42class MachineRegisterInfo;
43class RegisterBank;
44class SIInstrInfo;
45class SIRegisterInfo;
46class TargetRegisterClass;
47
49private:
51 const GCNSubtarget *Subtarget;
52
53public:
55 const AMDGPURegisterBankInfo &RBI,
56 const AMDGPUTargetMachine &TM);
57
58 bool select(MachineInstr &I) override;
59 static const char *getName();
60
63 BlockFrequencyInfo *BFI) override;
64
65private:
66 struct GEPInfo {
69 int64_t Imm = 0;
70 };
71
72 bool isSGPR(Register Reg) const;
73
74 bool isInstrUniform(const MachineInstr &MI) const;
75 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
76
77 const RegisterBank *getArtifactRegBank(
79 const TargetRegisterInfo &TRI) const;
80
81 /// tblgen-erated 'select' implementation.
82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
83
84 MachineOperand getSubOperand64(MachineOperand &MO,
85 const TargetRegisterClass &SubRC,
86 unsigned SubIdx) const;
87
88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89 bool selectCOPY(MachineInstr &I) const;
90 bool selectPHI(MachineInstr &I) const;
91 bool selectG_TRUNC(MachineInstr &I) const;
92 bool selectG_SZA_EXT(MachineInstr &I) const;
93 bool selectG_FPEXT(MachineInstr &I) const;
94 bool selectG_CONSTANT(MachineInstr &I) const;
95 bool selectG_FNEG(MachineInstr &I) const;
96 bool selectG_FABS(MachineInstr &I) const;
97 bool selectG_AND_OR_XOR(MachineInstr &I) const;
98 bool selectG_ADD_SUB(MachineInstr &I) const;
99 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
100 bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
101 bool selectG_EXTRACT(MachineInstr &I) const;
102 bool selectG_FMA_FMAD(MachineInstr &I) const;
103 bool selectG_MERGE_VALUES(MachineInstr &I) const;
104 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
105 bool selectG_BUILD_VECTOR(MachineInstr &I) const;
106 bool selectG_PTR_ADD(MachineInstr &I) const;
107 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
108 bool selectG_INSERT(MachineInstr &I) const;
109 bool selectG_SBFX_UBFX(MachineInstr &I) const;
110
111 bool selectInterpP1F16(MachineInstr &MI) const;
112 bool selectWritelane(MachineInstr &MI) const;
113 bool selectDivScale(MachineInstr &MI) const;
114 bool selectIntrinsicCmp(MachineInstr &MI) const;
115 bool selectBallot(MachineInstr &I) const;
116 bool selectInverseBallot(MachineInstr &I) const;
117 bool selectRelocConstant(MachineInstr &I) const;
118 bool selectGroupStaticSize(MachineInstr &I) const;
119 bool selectReturnAddress(MachineInstr &I) const;
120 bool selectG_INTRINSIC(MachineInstr &I) const;
121
122 bool selectEndCfIntrinsic(MachineInstr &MI) const;
123 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
124 bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
125 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
126 bool selectSBarrier(MachineInstr &MI) const;
127 bool selectDSBvhStackIntrinsic(MachineInstr &MI) const;
128
129 bool selectImageIntrinsic(MachineInstr &MI,
131 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
132 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
133 bool selectG_ICMP_or_FCMP(MachineInstr &I) const;
134 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
135 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
136 SmallVectorImpl<GEPInfo> &AddrInfo) const;
137
138 void initM0(MachineInstr &I) const;
139 bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
140 bool selectG_SELECT(MachineInstr &I) const;
141 bool selectG_BRCOND(MachineInstr &I) const;
142 bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
143 bool selectG_PTRMASK(MachineInstr &I) const;
144 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
145 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
146 bool selectBufferLoadLds(MachineInstr &MI) const;
147 bool selectGlobalLoadLds(MachineInstr &MI) const;
148 bool selectBVHIntrinsic(MachineInstr &I) const;
149 bool selectSMFMACIntrin(MachineInstr &I) const;
150 bool selectWaveAddress(MachineInstr &I) const;
151 bool selectStackRestore(MachineInstr &MI) const;
152 bool selectNamedBarrierInst(MachineInstr &I, Intrinsic::ID IID) const;
153 bool selectSBarrierSignalIsfirst(MachineInstr &I, Intrinsic::ID IID) const;
154 bool selectSBarrierLeave(MachineInstr &I) const;
155
156 std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root,
157 bool IsCanonicalizing = true,
158 bool AllowAbs = true,
159 bool OpSel = false) const;
160
161 Register copyToVGPRIfSrcFolded(Register Src, unsigned Mods,
162 MachineOperand Root, MachineInstr *InsertPt,
163 bool ForceVGPR = false) const;
164
166 selectVCSRC(MachineOperand &Root) const;
167
169 selectVSRC0(MachineOperand &Root) const;
170
172 selectVOP3Mods0(MachineOperand &Root) const;
174 selectVOP3BMods0(MachineOperand &Root) const;
176 selectVOP3OMods(MachineOperand &Root) const;
178 selectVOP3Mods(MachineOperand &Root) const;
180 selectVOP3ModsNonCanonicalizing(MachineOperand &Root) const;
182 selectVOP3BMods(MachineOperand &Root) const;
183
184 ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
185
186 std::pair<Register, unsigned>
187 selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI,
188 bool IsDOT = false) const;
189
191 selectVOP3PMods(MachineOperand &Root) const;
192
194 selectVOP3PModsDOT(MachineOperand &Root) const;
195
197 selectVOP3PModsNeg(MachineOperand &Root) const;
198
200 selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;
201
203 selectWMMAModsF32NegAbs(MachineOperand &Root) const;
205 selectWMMAModsF16Neg(MachineOperand &Root) const;
207 selectWMMAModsF16NegAbs(MachineOperand &Root) const;
209 selectWMMAVISrc(MachineOperand &Root) const;
211 selectSWMMACIndex8(MachineOperand &Root) const;
213 selectSWMMACIndex16(MachineOperand &Root) const;
214
216 selectVOP3OpSelMods(MachineOperand &Root) const;
217
219 selectVINTERPMods(MachineOperand &Root) const;
221 selectVINTERPModsHi(MachineOperand &Root) const;
222
223 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
224 int64_t *Offset) const;
226 selectSmrdImm(MachineOperand &Root) const;
228 selectSmrdImm32(MachineOperand &Root) const;
230 selectSmrdSgpr(MachineOperand &Root) const;
232 selectSmrdSgprImm(MachineOperand &Root) const;
233
234 std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
235 uint64_t FlatVariant) const;
236
238 selectFlatOffset(MachineOperand &Root) const;
240 selectGlobalOffset(MachineOperand &Root) const;
242 selectScratchOffset(MachineOperand &Root) const;
243
245 selectGlobalSAddr(MachineOperand &Root) const;
246
248 selectScratchSAddr(MachineOperand &Root) const;
249 bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
250 uint64_t ImmOffset) const;
252 selectScratchSVAddr(MachineOperand &Root) const;
253
255 selectMUBUFScratchOffen(MachineOperand &Root) const;
257 selectMUBUFScratchOffset(MachineOperand &Root) const;
258
259 bool isDSOffsetLegal(Register Base, int64_t Offset) const;
260 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
261 unsigned Size) const;
262 bool isFlatScratchBaseLegal(Register Addr) const;
263 bool isFlatScratchBaseLegalSV(Register Addr) const;
264 bool isFlatScratchBaseLegalSVImm(Register Addr) const;
265
266 std::pair<Register, unsigned>
267 selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
269 selectDS1Addr1Offset(MachineOperand &Root) const;
270
272 selectDS64Bit4ByteAligned(MachineOperand &Root) const;
273
275 selectDS128Bit8ByteAligned(MachineOperand &Root) const;
276
277 std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
278 unsigned size) const;
280 selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
281
282 std::pair<Register, int64_t>
283 getPtrBaseWithConstantOffset(Register Root,
284 const MachineRegisterInfo &MRI) const;
285
286 // Parse out a chain of up to two g_ptr_add instructions.
287 // g_ptr_add (n0, _)
288 // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
289 struct MUBUFAddressData {
290 Register N0, N2, N3;
291 int64_t Offset = 0;
292 };
293
294 bool shouldUseAddr64(MUBUFAddressData AddrData) const;
295
296 void splitIllegalMUBUFOffset(MachineIRBuilder &B,
297 Register &SOffset, int64_t &ImmOffset) const;
298
299 MUBUFAddressData parseMUBUFAddress(Register Src) const;
300
301 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
302 Register &RSrcReg, Register &SOffset,
303 int64_t &Offset) const;
304
305 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
306 Register &SOffset, int64_t &Offset) const;
307
309 selectBUFSOffset(MachineOperand &Root) const;
310
312 selectMUBUFAddr64(MachineOperand &Root) const;
313
315 selectMUBUFOffset(MachineOperand &Root) const;
316
317 ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
318 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
319 ComplexRendererFns selectSMRDBufferSgprImm(MachineOperand &Root) const;
320
321 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
322 bool &Matched) const;
323 ComplexRendererFns selectVOP3PMadMixModsExt(MachineOperand &Root) const;
324 ComplexRendererFns selectVOP3PMadMixMods(MachineOperand &Root) const;
325
326 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
327 int OpIdx = -1) const;
328
329 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
330 int OpIdx) const;
331
332 void renderOpSelTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
333 int OpIdx) const;
334
335 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
336 int OpIdx) const;
337
338 void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
339 int OpIdx) const;
340
341 void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
342 int OpIdx) const;
343 void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
344 int OpIdx) const;
345 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
346 int OpIdx) const;
347 void renderExtractCpolSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
348 int OpIdx) const;
349
350 void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
351 int OpIdx) const;
352
353 void renderFPPow2ToExponent(MachineInstrBuilder &MIB, const MachineInstr &MI,
354 int OpIdx) const;
355
356 bool isInlineImmediate(const APInt &Imm) const;
357 bool isInlineImmediate(const APFloat &Imm) const;
358
359 // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
360 // shift amount operand's `ShAmtBits` bits is unneeded.
361 bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
362
363 const SIInstrInfo &TII;
364 const SIRegisterInfo &TRI;
365 const AMDGPURegisterBankInfo &RBI;
366 const AMDGPUTargetMachine &TM;
367 const GCNSubtarget &STI;
368 bool EnableLateStructurizeCFG;
369#define GET_GLOBALISEL_PREDICATES_DECL
370#define AMDGPUSubtarget GCNSubtarget
371#include "AMDGPUGenGlobalISel.inc"
372#undef GET_GLOBALISEL_PREDICATES_DECL
373#undef AMDGPUSubtarget
374
375#define GET_GLOBALISEL_TEMPORARIES_DECL
376#include "AMDGPUGenGlobalISel.inc"
377#undef GET_GLOBALISEL_TEMPORARIES_DECL
378};
379
380} // End llvm namespace.
381#endif
unsigned Intr
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
uint64_t Addr
uint64_t Size
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned Reg
#define P(N)
const char LLVMTargetMachineRef TM
static const char * getName()
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
void setupMF(MachineFunction &MF, GISelKnownBits *KB, CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF executor state.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:966
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Analysis providing profile information.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456