LLVM  15.0.0git
AMDGPUInstructionSelector.h
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1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
17 #include "llvm/IR/InstrTypes.h"
18 
19 namespace {
20 #define GET_GLOBALISEL_PREDICATE_BITSET
21 #define AMDGPUSubtarget GCNSubtarget
22 #include "AMDGPUGenGlobalISel.inc"
23 #undef GET_GLOBALISEL_PREDICATE_BITSET
24 #undef AMDGPUSubtarget
25 }
26 
27 namespace llvm {
28 
29 namespace AMDGPU {
30 struct ImageDimIntrinsicInfo;
31 }
32 
33 class AMDGPURegisterBankInfo;
34 class AMDGPUTargetMachine;
35 class BlockFrequencyInfo;
36 class ProfileSummaryInfo;
37 class GCNSubtarget;
38 class MachineInstr;
39 class MachineIRBuilder;
40 class MachineOperand;
41 class MachineRegisterInfo;
42 class RegisterBank;
43 class SIInstrInfo;
44 class SIRegisterInfo;
45 class TargetRegisterClass;
46 
48 private:
50  const GCNSubtarget *Subtarget;
51 
52 public:
54  const AMDGPURegisterBankInfo &RBI,
55  const AMDGPUTargetMachine &TM);
56 
57  bool select(MachineInstr &I) override;
58  static const char *getName();
59 
62  BlockFrequencyInfo *BFI) override;
63 
64 private:
65  struct GEPInfo {
66  const MachineInstr &GEP;
67  SmallVector<unsigned, 2> SgprParts;
68  SmallVector<unsigned, 2> VgprParts;
69  int64_t Imm;
70  GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
71  };
72 
73  bool isSGPR(Register Reg) const;
74 
75  bool isInstrUniform(const MachineInstr &MI) const;
76  bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
77 
78  const RegisterBank *getArtifactRegBank(
80  const TargetRegisterInfo &TRI) const;
81 
82  /// tblgen-erated 'select' implementation.
83  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
84 
85  MachineOperand getSubOperand64(MachineOperand &MO,
86  const TargetRegisterClass &SubRC,
87  unsigned SubIdx) const;
88 
89  bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
90  bool selectCOPY(MachineInstr &I) const;
91  bool selectPHI(MachineInstr &I) const;
92  bool selectG_TRUNC(MachineInstr &I) const;
93  bool selectG_SZA_EXT(MachineInstr &I) const;
94  bool selectG_CONSTANT(MachineInstr &I) const;
95  bool selectG_FNEG(MachineInstr &I) const;
96  bool selectG_FABS(MachineInstr &I) const;
97  bool selectG_AND_OR_XOR(MachineInstr &I) const;
98  bool selectG_ADD_SUB(MachineInstr &I) const;
99  bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
100  bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
101  bool selectG_EXTRACT(MachineInstr &I) const;
102  bool selectG_MERGE_VALUES(MachineInstr &I) const;
103  bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
104  bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const;
105  bool selectG_PTR_ADD(MachineInstr &I) const;
106  bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
107  bool selectG_INSERT(MachineInstr &I) const;
108  bool selectG_SBFX_UBFX(MachineInstr &I) const;
109 
110  bool selectInterpP1F16(MachineInstr &MI) const;
111  bool selectWritelane(MachineInstr &MI) const;
112  bool selectDivScale(MachineInstr &MI) const;
113  bool selectIntrinsicIcmp(MachineInstr &MI) const;
114  bool selectBallot(MachineInstr &I) const;
115  bool selectRelocConstant(MachineInstr &I) const;
116  bool selectGroupStaticSize(MachineInstr &I) const;
117  bool selectReturnAddress(MachineInstr &I) const;
118  bool selectG_INTRINSIC(MachineInstr &I) const;
119 
120  bool selectEndCfIntrinsic(MachineInstr &MI) const;
121  bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
122  bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
123  bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
124  bool selectSBarrier(MachineInstr &MI) const;
125 
126  bool selectImageIntrinsic(MachineInstr &MI,
127  const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
128  bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
129  int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
130  bool selectG_ICMP(MachineInstr &I) const;
131  bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
132  void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
133  SmallVectorImpl<GEPInfo> &AddrInfo) const;
134 
135  void initM0(MachineInstr &I) const;
136  bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
137  bool selectG_SELECT(MachineInstr &I) const;
138  bool selectG_BRCOND(MachineInstr &I) const;
139  bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
140  bool selectG_PTRMASK(MachineInstr &I) const;
141  bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
142  bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
143  bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const;
144  bool selectAMDGPU_BUFFER_ATOMIC_FADD(MachineInstr &I) const;
145  bool selectGlobalAtomicFadd(MachineInstr &I, MachineOperand &AddrOp,
146  MachineOperand &DataOp) const;
147  bool selectBufferLoadLds(MachineInstr &MI) const;
148  bool selectGlobalLoadLds(MachineInstr &MI) const;
149  bool selectBVHIntrinsic(MachineInstr &I) const;
150  bool selectSMFMACIntrin(MachineInstr &I) const;
151  bool selectWaveAddress(MachineInstr &I) const;
152 
153  std::pair<Register, unsigned>
154  selectVOP3ModsImpl(MachineOperand &Root, bool AllowAbs = true,
155  bool OpSel = false, bool ForceVGPR = false) const;
156 
158  selectVCSRC(MachineOperand &Root) const;
159 
161  selectVSRC0(MachineOperand &Root) const;
162 
164  selectVOP3Mods0(MachineOperand &Root) const;
166  selectVOP3BMods0(MachineOperand &Root) const;
168  selectVOP3OMods(MachineOperand &Root) const;
170  selectVOP3Mods(MachineOperand &Root) const;
172  selectVOP3BMods(MachineOperand &Root) const;
173 
174  ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
175 
177  selectVOP3Mods_nnan(MachineOperand &Root) const;
178 
179  std::pair<Register, unsigned>
180  selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI,
181  bool IsDOT = false) const;
182 
184  selectVOP3PMods(MachineOperand &Root) const;
185 
187  selectVOP3PModsDOT(MachineOperand &Root) const;
188 
190  selectDotIUVOP3PMods(MachineOperand &Root) const;
191 
193  selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;
194 
196  selectVOP3OpSelMods(MachineOperand &Root) const;
197 
199  selectVINTERPMods(MachineOperand &Root) const;
201  selectVINTERPModsHi(MachineOperand &Root) const;
202 
204  selectSmrdImm(MachineOperand &Root) const;
206  selectSmrdImm32(MachineOperand &Root) const;
208  selectSmrdSgpr(MachineOperand &Root) const;
209 
210  std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
211  uint64_t FlatVariant) const;
212 
214  selectFlatOffset(MachineOperand &Root) const;
216  selectGlobalOffset(MachineOperand &Root) const;
218  selectScratchOffset(MachineOperand &Root) const;
219 
221  selectGlobalSAddr(MachineOperand &Root) const;
222 
224  selectScratchSAddr(MachineOperand &Root) const;
225  bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
226  uint64_t ImmOffset) const;
228  selectScratchSVAddr(MachineOperand &Root) const;
229 
231  selectMUBUFScratchOffen(MachineOperand &Root) const;
233  selectMUBUFScratchOffset(MachineOperand &Root) const;
234 
235  bool isDSOffsetLegal(Register Base, int64_t Offset) const;
236  bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
237  unsigned Size) const;
238 
239  std::pair<Register, unsigned>
240  selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
242  selectDS1Addr1Offset(MachineOperand &Root) const;
243 
245  selectDS64Bit4ByteAligned(MachineOperand &Root) const;
246 
248  selectDS128Bit8ByteAligned(MachineOperand &Root) const;
249 
250  std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
251  unsigned size) const;
253  selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
254 
255  std::pair<Register, int64_t>
256  getPtrBaseWithConstantOffset(Register Root,
257  const MachineRegisterInfo &MRI) const;
258 
259  // Parse out a chain of up to two g_ptr_add instructions.
260  // g_ptr_add (n0, _)
261  // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
262  struct MUBUFAddressData {
263  Register N0, N2, N3;
264  int64_t Offset = 0;
265  };
266 
267  bool shouldUseAddr64(MUBUFAddressData AddrData) const;
268 
269  void splitIllegalMUBUFOffset(MachineIRBuilder &B,
270  Register &SOffset, int64_t &ImmOffset) const;
271 
272  MUBUFAddressData parseMUBUFAddress(Register Src) const;
273 
274  bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
275  Register &RSrcReg, Register &SOffset,
276  int64_t &Offset) const;
277 
278  bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
279  Register &SOffset, int64_t &Offset) const;
280 
282  selectMUBUFAddr64(MachineOperand &Root) const;
283 
285  selectMUBUFOffset(MachineOperand &Root) const;
286 
288  selectMUBUFOffsetAtomic(MachineOperand &Root) const;
289 
291  selectMUBUFAddr64Atomic(MachineOperand &Root) const;
292 
293  ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
294  ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
295 
296  void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
297  int OpIdx = -1) const;
298 
299  void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
300  int OpIdx) const;
301 
302  void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
303  int OpIdx) const;
304 
305  void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
306  int OpIdx) const;
307 
308  void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
309  int OpIdx) const;
310  void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
311  int OpIdx) const;
312  void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
313  int OpIdx) const;
314  void renderSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
315  int OpIdx) const;
316 
317  void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
318  int OpIdx) const;
319 
320  bool isInlineImmediate16(int64_t Imm) const;
321  bool isInlineImmediate32(int64_t Imm) const;
322  bool isInlineImmediate64(int64_t Imm) const;
323  bool isInlineImmediate(const APFloat &Imm) const;
324 
325  // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
326  // shift amount operand's `ShAmtBits` bits is unneeded.
327  bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
328 
329  const SIInstrInfo &TII;
330  const SIRegisterInfo &TRI;
331  const AMDGPURegisterBankInfo &RBI;
332  const AMDGPUTargetMachine &TM;
333  const GCNSubtarget &STI;
334  bool EnableLateStructurizeCFG;
335 #define GET_GLOBALISEL_PREDICATES_DECL
336 #define AMDGPUSubtarget GCNSubtarget
337 #include "AMDGPUGenGlobalISel.inc"
338 #undef GET_GLOBALISEL_PREDICATES_DECL
339 #undef AMDGPUSubtarget
340 
341 #define GET_GLOBALISEL_TEMPORARIES_DECL
342 #include "AMDGPUGenGlobalISel.inc"
343 #undef GET_GLOBALISEL_TEMPORARIES_DECL
344 };
345 
346 } // End llvm namespace.
347 #endif
llvm::AMDGPURegisterBankInfo
Definition: AMDGPURegisterBankInfo.h:42
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::SmallVector< unsigned, 2 >
llvm::AMDGPU::ImageDimIntrinsicInfo
Definition: AMDGPUInstrInfo.h:47
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::AMDGPU::VOP3PEncoding::OpSel
OpSel
Definition: SIDefines.h:888
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::Optional
Definition: APInt.h:33
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::AMDGPUTargetMachine
Definition: AMDGPUTargetMachine.h:28
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::AMDGPUInstructionSelector::select
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
Definition: AMDGPUInstructionSelector.cpp:3398
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:2341
InstrTypes.h
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::InstructionSelector::CoverageInfo
CodeGenCoverage * CoverageInfo
Definition: InstructionSelector.h:440
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
InstructionSelector.h
llvm::InstructionSelector::MF
MachineFunction * MF
Definition: InstructionSelector.h:442
llvm::APFloat
Definition: APFloat.h:701
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:424
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:219
llvm::CodeGenCoverage
Definition: CodeGenCoverage.h:19
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::AMDGPUInstructionSelector
Definition: AMDGPUInstructionSelector.h:47
llvm::AMDGPUInstructionSelector::getName
static const char * getName()
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1598
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::InstructionSelector::BFI
BlockFrequencyInfo * BFI
Definition: InstructionSelector.h:444
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::InstructionSelector::PSI
ProfileSummaryInfo * PSI
Definition: InstructionSelector.h:443
llvm::AMDGPUInstructionSelector::setupMF
void setupMF(MachineFunction &MF, GISelKnownBits *KB, CodeGenCoverage &CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF selector state.
Definition: AMDGPUInstructionSelector.cpp:64
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::SIInstrInfo
Definition: SIInstrInfo.h:44
llvm::SIInstrFlags::IsDOT
@ IsDOT
Definition: SIDefines.h:120
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector
AMDGPUInstructionSelector(const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, const AMDGPUTargetMachine &TM)
Definition: AMDGPUInstructionSelector.cpp:47
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:171
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38