13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
21#define GET_GLOBALISEL_PREDICATE_BITSET
22#define AMDGPUSubtarget GCNSubtarget
23#include "AMDGPUGenGlobalISel.inc"
24#undef GET_GLOBALISEL_PREDICATE_BITSET
31struct ImageDimIntrinsicInfo;
34class AMDGPURegisterBankInfo;
35class AMDGPUTargetMachine;
36class BlockFrequencyInfo;
37class ProfileSummaryInfo;
40class MachineIRBuilder;
42class MachineRegisterInfo;
46class TargetRegisterClass;
86 unsigned SubIdx)
const;
88 bool constrainCopyLikeIntrin(
MachineInstr &
MI,
unsigned NewOpc)
const;
124 bool selectDSAppendConsume(
MachineInstr &
MI,
bool IsAppend)
const;
130 bool selectG_INTRINSIC_W_SIDE_EFFECTS(
MachineInstr &
I)
const;
155 std::pair<Register, unsigned> selectVOP3ModsImpl(
MachineOperand &Root,
156 bool IsCanonicalizing =
true,
157 bool AllowAbs =
true,
158 bool OpSel =
false)
const;
162 bool ForceVGPR =
false)
const;
185 std::pair<Register, unsigned>
187 bool IsDOT =
false)
const;
233 std::pair<Register, int> selectFlatOffsetImpl(
MachineOperand &Root,
259 bool isDSOffset2Legal(
Register Base, int64_t Offset0, int64_t Offset1,
260 unsigned Size)
const;
265 std::pair<Register, unsigned>
276 std::pair<Register, unsigned> selectDSReadWrite2Impl(
MachineOperand &Root,
277 unsigned size)
const;
281 std::pair<Register, int64_t>
282 getPtrBaseWithConstantOffset(
Register Root,
288 struct MUBUFAddressData {
293 bool shouldUseAddr64(MUBUFAddressData AddrData)
const;
295 void splitIllegalMUBUFOffset(MachineIRBuilder &
B,
296 Register &SOffset, int64_t &ImmOffset)
const;
298 MUBUFAddressData parseMUBUFAddress(Register Src)
const;
300 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
301 Register &RSrcReg, Register &SOffset,
304 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
305 Register &SOffset, int64_t &
Offset)
const;
308 selectBUFSOffset(MachineOperand &Root)
const;
311 selectMUBUFAddr64(MachineOperand &Root)
const;
314 selectMUBUFOffset(MachineOperand &Root)
const;
320 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
321 bool &Matched)
const;
325 void renderTruncImm32(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
326 int OpIdx = -1)
const;
328 void renderTruncTImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
331 void renderOpSelTImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
334 void renderNegateImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
337 void renderBitcastImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
340 void renderPopcntImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
342 void renderExtractCPol(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
344 void renderExtractSWZ(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
346 void renderExtractCpolSetGLC(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
349 void renderFrameIndex(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
352 void renderFPPow2ToExponent(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
355 bool isInlineImmediate(
const APInt &Imm)
const;
356 bool isInlineImmediate(
const APFloat &Imm)
const;
360 bool isUnneededShiftMask(
const MachineInstr &
MI,
unsigned ShAmtBits)
const;
362 const SIInstrInfo &TII;
363 const SIRegisterInfo &TRI;
364 const AMDGPURegisterBankInfo &RBI;
365 const AMDGPUTargetMachine &
TM;
366 const GCNSubtarget &STI;
367 bool EnableLateStructurizeCFG;
368#define GET_GLOBALISEL_PREDICATES_DECL
369#define AMDGPUSubtarget GCNSubtarget
370#include "AMDGPUGenGlobalISel.inc"
371#undef GET_GLOBALISEL_PREDICATES_DECL
372#undef AMDGPUSubtarget
374#define GET_GLOBALISEL_TEMPORARIES_DECL
375#include "AMDGPUGenGlobalISel.inc"
376#undef GET_GLOBALISEL_TEMPORARIES_DECL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const char LLVMTargetMachineRef TM
static const char * getName()
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
void setupMF(MachineFunction &MF, GISelKnownBits *KB, CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF executor state.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
CodeGenCoverage * CoverageInfo
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Analysis providing profile information.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.