LLVM  14.0.0git
AMDGPUInstructionSelector.h
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1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
17 #include "llvm/IR/InstrTypes.h"
18 
19 namespace {
20 #define GET_GLOBALISEL_PREDICATE_BITSET
21 #define AMDGPUSubtarget GCNSubtarget
22 #include "AMDGPUGenGlobalISel.inc"
23 #undef GET_GLOBALISEL_PREDICATE_BITSET
24 #undef AMDGPUSubtarget
25 }
26 
27 namespace llvm {
28 
29 namespace AMDGPU {
30 struct ImageDimIntrinsicInfo;
31 }
32 
33 class AMDGPUInstrInfo;
34 class AMDGPURegisterBankInfo;
35 class AMDGPUTargetMachine;
36 class BlockFrequencyInfo;
37 class ProfileSummaryInfo;
38 class GCNSubtarget;
39 class MachineInstr;
40 class MachineIRBuilder;
41 class MachineOperand;
42 class MachineRegisterInfo;
43 class RegisterBank;
44 class SIInstrInfo;
45 class SIMachineFunctionInfo;
46 class SIRegisterInfo;
47 class TargetRegisterClass;
48 
50 private:
52  const GCNSubtarget *Subtarget;
53 
54 public:
56  const AMDGPURegisterBankInfo &RBI,
57  const AMDGPUTargetMachine &TM);
58 
59  bool select(MachineInstr &I) override;
60  static const char *getName();
61 
64  BlockFrequencyInfo *BFI) override;
65 
66 private:
67  struct GEPInfo {
68  const MachineInstr &GEP;
69  SmallVector<unsigned, 2> SgprParts;
70  SmallVector<unsigned, 2> VgprParts;
71  int64_t Imm;
72  GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
73  };
74 
75  bool isSGPR(Register Reg) const;
76 
77  bool isInstrUniform(const MachineInstr &MI) const;
78  bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
79 
80  const RegisterBank *getArtifactRegBank(
82  const TargetRegisterInfo &TRI) const;
83 
84  /// tblgen-erated 'select' implementation.
85  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
86 
87  MachineOperand getSubOperand64(MachineOperand &MO,
88  const TargetRegisterClass &SubRC,
89  unsigned SubIdx) const;
90 
91  bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
92  bool selectCOPY(MachineInstr &I) const;
93  bool selectPHI(MachineInstr &I) const;
94  bool selectG_TRUNC(MachineInstr &I) const;
95  bool selectG_SZA_EXT(MachineInstr &I) const;
96  bool selectG_CONSTANT(MachineInstr &I) const;
97  bool selectG_FNEG(MachineInstr &I) const;
98  bool selectG_FABS(MachineInstr &I) const;
99  bool selectG_AND_OR_XOR(MachineInstr &I) const;
100  bool selectG_ADD_SUB(MachineInstr &I) const;
101  bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
102  bool selectG_EXTRACT(MachineInstr &I) const;
103  bool selectG_MERGE_VALUES(MachineInstr &I) const;
104  bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
105  bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const;
106  bool selectG_PTR_ADD(MachineInstr &I) const;
107  bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
108  bool selectG_INSERT(MachineInstr &I) const;
109  bool selectG_SBFX_UBFX(MachineInstr &I) const;
110 
111  bool selectInterpP1F16(MachineInstr &MI) const;
112  bool selectWritelane(MachineInstr &MI) const;
113  bool selectDivScale(MachineInstr &MI) const;
114  bool selectIntrinsicIcmp(MachineInstr &MI) const;
115  bool selectBallot(MachineInstr &I) const;
116  bool selectRelocConstant(MachineInstr &I) const;
117  bool selectGroupStaticSize(MachineInstr &I) const;
118  bool selectReturnAddress(MachineInstr &I) const;
119  bool selectG_INTRINSIC(MachineInstr &I) const;
120 
121  bool selectEndCfIntrinsic(MachineInstr &MI) const;
122  bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
123  bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
124  bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
125  bool selectSBarrier(MachineInstr &MI) const;
126 
127  bool selectImageIntrinsic(MachineInstr &MI,
128  const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
129  bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
130  int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
131  bool selectG_ICMP(MachineInstr &I) const;
132  bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
133  void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
134  SmallVectorImpl<GEPInfo> &AddrInfo) const;
135  bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
136 
137  void initM0(MachineInstr &I) const;
138  bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
139  bool selectG_AMDGPU_ATOMIC_CMPXCHG(MachineInstr &I) const;
140  bool selectG_SELECT(MachineInstr &I) const;
141  bool selectG_BRCOND(MachineInstr &I) const;
142  bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
143  bool selectG_PTRMASK(MachineInstr &I) const;
144  bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
145  bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
146  bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const;
147  bool selectAMDGPU_BUFFER_ATOMIC_FADD(MachineInstr &I) const;
148  bool selectGlobalAtomicFadd(MachineInstr &I, MachineOperand &AddrOp,
149  MachineOperand &DataOp) const;
150  bool selectBVHIntrinsic(MachineInstr &I) const;
151 
152  std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root,
153  bool AllowAbs = true) const;
154 
156  selectVCSRC(MachineOperand &Root) const;
157 
159  selectVSRC0(MachineOperand &Root) const;
160 
162  selectVOP3Mods0(MachineOperand &Root) const;
164  selectVOP3BMods0(MachineOperand &Root) const;
166  selectVOP3OMods(MachineOperand &Root) const;
168  selectVOP3Mods(MachineOperand &Root) const;
170  selectVOP3BMods(MachineOperand &Root) const;
171 
172  ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
173 
175  selectVOP3Mods_nnan(MachineOperand &Root) const;
176 
177  std::pair<Register, unsigned>
178  selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI) const;
179 
181  selectVOP3PMods(MachineOperand &Root) const;
182 
184  selectVOP3OpSelMods(MachineOperand &Root) const;
185 
187  selectSmrdImm(MachineOperand &Root) const;
189  selectSmrdImm32(MachineOperand &Root) const;
191  selectSmrdSgpr(MachineOperand &Root) const;
192 
193  std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
194  uint64_t FlatVariant) const;
195 
197  selectFlatOffset(MachineOperand &Root) const;
199  selectGlobalOffset(MachineOperand &Root) const;
201  selectScratchOffset(MachineOperand &Root) const;
202 
204  selectGlobalSAddr(MachineOperand &Root) const;
205 
207  selectScratchSAddr(MachineOperand &Root) const;
208 
210  selectMUBUFScratchOffen(MachineOperand &Root) const;
212  selectMUBUFScratchOffset(MachineOperand &Root) const;
213 
214  bool isDSOffsetLegal(Register Base, int64_t Offset) const;
215  bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
216  unsigned Size) const;
217 
218  std::pair<Register, unsigned>
219  selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
221  selectDS1Addr1Offset(MachineOperand &Root) const;
222 
224  selectDS64Bit4ByteAligned(MachineOperand &Root) const;
225 
227  selectDS128Bit8ByteAligned(MachineOperand &Root) const;
228 
229  std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
230  unsigned size) const;
232  selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
233 
234  std::pair<Register, int64_t>
235  getPtrBaseWithConstantOffset(Register Root,
236  const MachineRegisterInfo &MRI) const;
237 
238  // Parse out a chain of up to two g_ptr_add instructions.
239  // g_ptr_add (n0, _)
240  // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
241  struct MUBUFAddressData {
242  Register N0, N2, N3;
243  int64_t Offset = 0;
244  };
245 
246  bool shouldUseAddr64(MUBUFAddressData AddrData) const;
247 
248  void splitIllegalMUBUFOffset(MachineIRBuilder &B,
249  Register &SOffset, int64_t &ImmOffset) const;
250 
251  MUBUFAddressData parseMUBUFAddress(Register Src) const;
252 
253  bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
254  Register &RSrcReg, Register &SOffset,
255  int64_t &Offset) const;
256 
257  bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
258  Register &SOffset, int64_t &Offset) const;
259 
261  selectMUBUFAddr64(MachineOperand &Root) const;
262 
264  selectMUBUFOffset(MachineOperand &Root) const;
265 
267  selectMUBUFOffsetAtomic(MachineOperand &Root) const;
268 
270  selectMUBUFAddr64Atomic(MachineOperand &Root) const;
271 
272  ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
273  ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
274 
275  void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
276  int OpIdx = -1) const;
277 
278  void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
279  int OpIdx) const;
280 
281  void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
282  int OpIdx) const;
283 
284  void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
285  int OpIdx) const;
286 
287  void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
288  int OpIdx) const;
289  void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
290  int OpIdx) const;
291  void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
292  int OpIdx) const;
293  void renderSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
294  int OpIdx) const;
295 
296  void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
297  int OpIdx) const;
298 
299  bool isInlineImmediate16(int64_t Imm) const;
300  bool isInlineImmediate32(int64_t Imm) const;
301  bool isInlineImmediate64(int64_t Imm) const;
302  bool isInlineImmediate(const APFloat &Imm) const;
303 
304  const SIInstrInfo &TII;
305  const SIRegisterInfo &TRI;
306  const AMDGPURegisterBankInfo &RBI;
307  const AMDGPUTargetMachine &TM;
308  const GCNSubtarget &STI;
309  bool EnableLateStructurizeCFG;
310 #define GET_GLOBALISEL_PREDICATES_DECL
311 #define AMDGPUSubtarget GCNSubtarget
312 #include "AMDGPUGenGlobalISel.inc"
313 #undef GET_GLOBALISEL_PREDICATES_DECL
314 #undef AMDGPUSubtarget
315 
316 #define GET_GLOBALISEL_TEMPORARIES_DECL
317 #include "AMDGPUGenGlobalISel.inc"
318 #undef GET_GLOBALISEL_TEMPORARIES_DECL
319 };
320 
321 } // End llvm namespace.
322 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::AMDGPURegisterBankInfo
Definition: AMDGPURegisterBankInfo.h:42
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::SmallVector< unsigned, 2 >
llvm::AMDGPU::ImageDimIntrinsicInfo
Definition: AMDGPUInstrInfo.h:50
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Optional
Definition: APInt.h:33
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::AMDGPUTargetMachine
Definition: AMDGPUTargetMachine.h:29
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::AMDGPUInstructionSelector::select
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
Definition: AMDGPUInstructionSelector.cpp:3126
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:1991
InstrTypes.h
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::InstructionSelector::CoverageInfo
CodeGenCoverage * CoverageInfo
Definition: InstructionSelector.h:439
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
InstructionSelector.h
llvm::InstructionSelector::MF
MachineFunction * MF
Definition: InstructionSelector.h:441
llvm::APFloat
Definition: APFloat.h:701
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:212
llvm::CodeGenCoverage
Definition: CodeGenCoverage.h:20
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::AMDGPUInstructionSelector
Definition: AMDGPUInstructionSelector.h:49
llvm::AMDGPUInstructionSelector::getName
static const char * getName()
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1532
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::InstructionSelector::BFI
BlockFrequencyInfo * BFI
Definition: InstructionSelector.h:443
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::InstructionSelector::PSI
ProfileSummaryInfo * PSI
Definition: InstructionSelector.h:442
llvm::AMDGPUInstructionSelector::setupMF
void setupMF(MachineFunction &MF, GISelKnownBits *KB, CodeGenCoverage &CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF selector state.
Definition: AMDGPUInstructionSelector.cpp:64
llvm::SIInstrInfo
Definition: SIInstrInfo.h:38
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector
AMDGPUInstructionSelector(const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, const AMDGPUTargetMachine &TM)
Definition: AMDGPUInstructionSelector.cpp:46
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:172
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37