LLVM 24.0.0git
AMDGPUInstructionSelector.h
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1//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the InstructionSelector class for
10/// AMDGPU.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15
16#include "SIDefines.h"
17#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
18#include "llvm/IR/InstrTypes.h"
19
20namespace {
21#define GET_GLOBALISEL_PREDICATE_BITSET
22#define AMDGPUSubtarget GCNSubtarget
23#include "AMDGPUGenGlobalISel.inc"
24#undef GET_GLOBALISEL_PREDICATE_BITSET
25#undef AMDGPUSubtarget
26}
27
28namespace llvm {
29
30namespace AMDGPU {
31struct ImageDimIntrinsicInfo;
32}
33
34class AMDGPURegisterBankInfo;
35class AMDGPUTargetMachine;
36class BlockFrequencyInfo;
37class ProfileSummaryInfo;
38class GCNSubtarget;
39class MachineInstr;
40class MachineIRBuilder;
41class MachineOperand;
42class MachineRegisterInfo;
43class RegisterBank;
44class SIInstrInfo;
45class SIRegisterInfo;
46class MCRegisterClass;
47using TargetRegisterClass = MCRegisterClass;
48
49class AMDGPUInstructionSelector final : public InstructionSelector {
50private:
51 MachineRegisterInfo *MRI;
52 const GCNSubtarget *Subtarget;
53
54public:
55 AMDGPUInstructionSelector(const GCNSubtarget &STI,
56 const AMDGPURegisterBankInfo &RBI);
57
58 bool select(MachineInstr &I) override;
59 static const char *getName();
60
61 void setupMF(MachineFunction &MF, GISelValueTracking *VT,
62 CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI,
63 BlockFrequencyInfo *BFI) override;
64
65private:
66 struct GEPInfo {
67 SmallVector<unsigned, 2> SgprParts;
68 SmallVector<unsigned, 2> VgprParts;
69 int64_t Imm = 0;
70 };
71
72 bool isSGPR(Register Reg) const;
73
74 bool isInstrUniform(const MachineInstr &MI) const;
75 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
76
77 const RegisterBank *getArtifactRegBank(
78 Register Reg, const MachineRegisterInfo &MRI,
79 const TargetRegisterInfo &TRI) const;
80
81 /// tblgen-erated 'select' implementation.
82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
83
84 MachineOperand getSubOperand64(MachineOperand &MO,
85 const TargetRegisterClass &SubRC,
86 unsigned SubIdx) const;
87
88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89 bool selectCOPY(MachineInstr &I) const;
90 bool selectCOPY_SCC_VCC(MachineInstr &I) const;
91 bool selectCOPY_VCC_SCC(MachineInstr &I) const;
92 bool selectReadAnyLane(MachineInstr &I) const;
93 bool selectPHI(MachineInstr &I) const;
94 bool selectG_TRUNC(MachineInstr &I) const;
95 bool selectG_SZA_EXT(MachineInstr &I) const;
96 bool selectG_FPEXT(MachineInstr &I) const;
97 bool selectG_FNEG(MachineInstr &I) const;
98 bool selectG_FABS(MachineInstr &I) const;
99 bool selectG_AND_OR_XOR(MachineInstr &I) const;
100 bool selectG_ADD_SUB(MachineInstr &I) const;
101 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
102 bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
103 bool selectG_EXTRACT(MachineInstr &I) const;
104 bool selectS16MergeToS32(MachineInstr &MI) const;
105 bool selectS16MergeToWide(MachineInstr &MI) const;
106 bool selectG_MERGE_VALUES(MachineInstr &I) const;
107 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
108 bool selectG_BUILD_VECTOR(MachineInstr &I) const;
109 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
110 bool selectG_INSERT(MachineInstr &I) const;
111 bool selectG_SBFX_UBFX(MachineInstr &I) const;
112
113 bool selectInterpP1F16(MachineInstr &MI) const;
114 bool selectWritelane(MachineInstr &MI) const;
115 bool selectDivScale(MachineInstr &MI) const;
116 bool selectIntrinsicCmp(MachineInstr &MI) const;
117 bool selectBallot(MachineInstr &I) const;
118 bool selectRelocConstant(MachineInstr &I) const;
119 bool selectGroupStaticSize(MachineInstr &I) const;
120 bool selectReturnAddress(MachineInstr &I) const;
121 bool selectG_INTRINSIC(MachineInstr &I) const;
122
123 bool selectEndCfIntrinsic(MachineInstr &MI) const;
124 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
125 bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
126 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
127 bool selectInitWholeWave(MachineInstr &MI) const;
128 bool selectDSBvhStackIntrinsic(MachineInstr &MI) const;
129
130 bool selectImageIntrinsic(MachineInstr &MI,
131 const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
132 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
133 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
134 bool selectG_ICMP_or_FCMP(MachineInstr &I) const;
135 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
136 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
137 SmallVectorImpl<GEPInfo> &AddrInfo) const;
138
139 void initM0(MachineInstr &I) const;
140 bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
141 bool selectG_SELECT(MachineInstr &I) const;
142 bool selectG_BRCOND(MachineInstr &I) const;
143 bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
144 bool selectG_PTRMASK(MachineInstr &I) const;
145 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
146 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
147 bool selectBufferLoadLds(MachineInstr &MI) const;
148 bool selectGlobalLoadLds(MachineInstr &MI) const;
149 bool selectTensorLoadStore(MachineInstr &MI, Intrinsic::ID IID) const;
150 bool selectBVHIntersectRayIntrinsic(MachineInstr &I) const;
151 bool selectSMFMACIntrin(MachineInstr &I) const;
152 bool selectPermlaneSwapIntrin(MachineInstr &I, Intrinsic::ID IntrID) const;
153 bool selectWaveAddress(MachineInstr &I) const;
154 bool selectBITOP3(MachineInstr &I) const;
155 bool selectStackRestore(MachineInstr &MI) const;
156 bool selectNamedBarrierInit(MachineInstr &I, Intrinsic::ID IID) const;
157 bool selectNamedBarrierInst(MachineInstr &I, Intrinsic::ID IID) const;
158 bool selectSBarrierSignalIsfirst(MachineInstr &I, Intrinsic::ID IID) const;
159 bool selectSGetBarrierState(MachineInstr &I, Intrinsic::ID IID) const;
160 bool selectWaveShuffleIntrin(MachineInstr &I) const;
161
162 std::pair<Register, unsigned> selectVOP3ModsImpl(Register Src,
163 bool IsCanonicalizing = true,
164 bool AllowAbs = true,
165 bool OpSel = false) const;
166 std::pair<Register, unsigned> selectVOP3PModsF32Impl(Register Src) const;
167
168 Register copyToVGPRIfSrcFolded(Register Src, unsigned Mods,
169 MachineOperand Root, MachineInstr *InsertPt,
170 bool ForceVGPR = false) const;
171
172 InstructionSelector::ComplexRendererFns
173 selectVCSRC(MachineOperand &Root) const;
174
175 InstructionSelector::ComplexRendererFns
176 selectVSRC0(MachineOperand &Root) const;
177
178 InstructionSelector::ComplexRendererFns
179 selectVOP3Mods0(MachineOperand &Root) const;
180 InstructionSelector::ComplexRendererFns
181 selectVOP3BMods0(MachineOperand &Root) const;
182 InstructionSelector::ComplexRendererFns
183 selectVOP3OMods(MachineOperand &Root) const;
184 InstructionSelector::ComplexRendererFns
185 selectVOP3Mods(MachineOperand &Root) const;
186 InstructionSelector::ComplexRendererFns
187 selectVOP3ModsNonCanonicalizing(MachineOperand &Root) const;
188 InstructionSelector::ComplexRendererFns
189 selectVOP3BMods(MachineOperand &Root) const;
190
191 ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
192
193 std::pair<Register, unsigned>
194 selectVOP3PModsImpl(Register RootReg, const MachineRegisterInfo &MRI,
195 bool IsDOT = false) const;
196 InstructionSelector::ComplexRendererFns
197 selectVOP3PRetHelper(MachineOperand &Root, bool IsDOT = false) const;
198
199 InstructionSelector::ComplexRendererFns
200 selectVOP3PMods(MachineOperand &Root) const;
201
202 InstructionSelector::ComplexRendererFns
203 selectVOP3PModsDOT(MachineOperand &Root) const;
204 InstructionSelector::ComplexRendererFns
205 selectVOP3PNoModsDOT(MachineOperand &Root) const;
206 InstructionSelector::ComplexRendererFns
207 selectVOP3PModsF32(MachineOperand &Root) const;
208 InstructionSelector::ComplexRendererFns
209 selectVOP3PNoModsF32(MachineOperand &Root) const;
210
211 InstructionSelector::ComplexRendererFns
212 selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;
213
214 InstructionSelector::ComplexRendererFns
215 selectWMMAModsF32NegAbs(MachineOperand &Root) const;
216 InstructionSelector::ComplexRendererFns
217 selectWMMAModsF16Neg(MachineOperand &Root) const;
218 InstructionSelector::ComplexRendererFns
219 selectWMMAModsF16NegAbs(MachineOperand &Root) const;
220 InstructionSelector::ComplexRendererFns
221 selectWMMAVISrc(MachineOperand &Root) const;
222 InstructionSelector::ComplexRendererFns
223 selectSWMMACIndex8(MachineOperand &Root) const;
224 InstructionSelector::ComplexRendererFns
225 selectSWMMACIndex16(MachineOperand &Root) const;
226 InstructionSelector::ComplexRendererFns
227 selectSWMMACIndex32(MachineOperand &Root) const;
228
229 InstructionSelector::ComplexRendererFns
230 selectVOP3OpSelMods(MachineOperand &Root) const;
231
232 InstructionSelector::ComplexRendererFns
233 selectVINTERPMods(MachineOperand &Root) const;
234 InstructionSelector::ComplexRendererFns
235 selectVINTERPModsHi(MachineOperand &Root) const;
236
237 bool selectScaleOffset(MachineOperand &Root, Register &Offset,
238 bool IsSigned) const;
239 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
240 int64_t *Offset, bool *ScaleOffset) const;
241 InstructionSelector::ComplexRendererFns
242 selectSmrdImm(MachineOperand &Root) const;
243 InstructionSelector::ComplexRendererFns
244 selectSmrdImm32(MachineOperand &Root) const;
245 InstructionSelector::ComplexRendererFns
246 selectSmrdSgpr(MachineOperand &Root) const;
247 InstructionSelector::ComplexRendererFns
248 selectSmrdSgprImm(MachineOperand &Root) const;
249
250 std::pair<Register, int>
251 selectFlatOffsetImpl(MachineOperand &Root,
252 AMDGPU::FlatAddrSpace FlatVariant) const;
253
254 InstructionSelector::ComplexRendererFns
255 selectFlatOffset(MachineOperand &Root) const;
256 InstructionSelector::ComplexRendererFns
257 selectGlobalOffset(MachineOperand &Root) const;
258 InstructionSelector::ComplexRendererFns
259 selectScratchOffset(MachineOperand &Root) const;
260
261 InstructionSelector::ComplexRendererFns
262 selectGlobalSAddr(MachineOperand &Root, unsigned CPolBits,
263 bool NeedIOffset = true) const;
264 InstructionSelector::ComplexRendererFns
265 selectGlobalSAddr(MachineOperand &Root) const;
266 InstructionSelector::ComplexRendererFns
267 selectGlobalSAddrCPol(MachineOperand &Root) const;
268 InstructionSelector::ComplexRendererFns
269 selectGlobalSAddrCPolM0(MachineOperand &Root) const;
270 InstructionSelector::ComplexRendererFns
271 selectGlobalSAddrGLC(MachineOperand &Root) const;
272 InstructionSelector::ComplexRendererFns
273 selectGlobalSAddrNoIOffset(MachineOperand &Root) const;
274 InstructionSelector::ComplexRendererFns
275 selectGlobalSAddrNoIOffsetM0(MachineOperand &Root) const;
276
277 InstructionSelector::ComplexRendererFns
278 selectScratchSAddr(MachineOperand &Root) const;
279 bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
280 uint64_t ImmOffset) const;
281 InstructionSelector::ComplexRendererFns
282 selectScratchSVAddr(MachineOperand &Root) const;
283
284 InstructionSelector::ComplexRendererFns
285 selectMUBUFScratchOffen(MachineOperand &Root) const;
286 InstructionSelector::ComplexRendererFns
287 selectMUBUFScratchOffset(MachineOperand &Root) const;
288
289 bool isDSOffsetLegal(Register Base, int64_t Offset) const;
290 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
291 unsigned Size) const;
292 bool isFlatScratchBaseLegal(Register Addr) const;
293 bool isFlatScratchBaseLegalSV(Register Addr) const;
294 bool isFlatScratchBaseLegalSVImm(Register Addr) const;
295
296 std::pair<Register, unsigned>
297 selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
298 InstructionSelector::ComplexRendererFns
299 selectDS1Addr1Offset(MachineOperand &Root) const;
300
301 InstructionSelector::ComplexRendererFns
302 selectDS64Bit4ByteAligned(MachineOperand &Root) const;
303
304 InstructionSelector::ComplexRendererFns
305 selectDS128Bit8ByteAligned(MachineOperand &Root) const;
306
307 std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
308 unsigned size) const;
309 InstructionSelector::ComplexRendererFns
310 selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
311
312 std::tuple<Register, int64_t, bool>
313 getPtrBaseWithConstantOffset(Register Root,
314 const MachineRegisterInfo &MRI) const;
315
316 // Parse out a chain of up to two g_ptr_add instructions.
317 // g_ptr_add (n0, _)
318 // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
319 struct MUBUFAddressData {
320 Register N0, N2, N3;
321 int64_t Offset = 0;
322 };
323
324 bool shouldUseAddr64(MUBUFAddressData AddrData) const;
325
326 void splitIllegalMUBUFOffset(MachineIRBuilder &B,
327 Register &SOffset, int64_t &ImmOffset) const;
328
329 MUBUFAddressData parseMUBUFAddress(Register Src) const;
330
331 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
332 Register &RSrcReg, Register &SOffset,
333 int64_t &Offset) const;
334
335 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
336 Register &SOffset, int64_t &Offset) const;
337
338 InstructionSelector::ComplexRendererFns
339 selectBUFSOffset(MachineOperand &Root) const;
340
341 InstructionSelector::ComplexRendererFns
342 selectMUBUFAddr64(MachineOperand &Root) const;
343
344 InstructionSelector::ComplexRendererFns
345 selectMUBUFOffset(MachineOperand &Root) const;
346
347 ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
348 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
349 ComplexRendererFns selectSMRDBufferSgprImm(MachineOperand &Root) const;
350
351 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
352 bool &Matched) const;
353 ComplexRendererFns selectVOP3PMadMixModsExt(MachineOperand &Root) const;
354 ComplexRendererFns selectVOP3PMadMixMods(MachineOperand &Root) const;
355 ComplexRendererFns selectVOP3PMadMixModsExtNeg(MachineOperand &Root) const;
356 ComplexRendererFns selectVOP3PMadMixModsNeg(MachineOperand &Root) const;
357
358 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
359 int OpIdx = -1) const;
360
361 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
362 int OpIdx) const;
363 void renderZextBoolTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
364 int OpIdx) const;
365
366 void renderOpSelTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
367 int OpIdx) const;
368
369 void renderSrcAndDstSelToOpSelXForm_0_0(MachineInstrBuilder &MIB,
370 const MachineInstr &MI,
371 int OpIdx) const;
372
373 void renderSrcAndDstSelToOpSelXForm_0_1(MachineInstrBuilder &MIB,
374 const MachineInstr &MI,
375 int OpIdx) const;
376
377 void renderSrcAndDstSelToOpSelXForm_1_0(MachineInstrBuilder &MIB,
378 const MachineInstr &MI,
379 int OpIdx) const;
380
381 void renderSrcAndDstSelToOpSelXForm_1_1(MachineInstrBuilder &MIB,
382 const MachineInstr &MI,
383 int OpIdx) const;
384
385 void renderDstSelToOpSelXForm(MachineInstrBuilder &MIB,
386 const MachineInstr &MI, int OpIdx) const;
387
388 void renderSrcSelToOpSelXForm(MachineInstrBuilder &MIB,
389 const MachineInstr &MI, int OpIdx) const;
390
391 void renderSrcAndDstSelToOpSelXForm_2_0(MachineInstrBuilder &MIB,
392 const MachineInstr &MI,
393 int OpIdx) const;
394
395 void renderDstSelToOpSel3XFormXForm(MachineInstrBuilder &MIB,
396 const MachineInstr &MI, int OpIdx) const;
397
398 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
399 int OpIdx) const;
400
401 void renderBitcastFPImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
402 int OpIdx) const;
403
404 void renderBitcastFPImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
405 int OpIdx) const {
406 renderBitcastFPImm(MIB, MI, OpIdx);
407 }
408 void renderBitcastFPImm64(MachineInstrBuilder &MIB, const MachineInstr &MI,
409 int OpIdx) const {
410 renderBitcastFPImm(MIB, MI, OpIdx);
411 }
412
413 void renderCountTrailingOnesImm(MachineInstrBuilder &MIB,
414 const MachineInstr &MI, int OpIdx) const;
415 void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
416 int OpIdx) const;
417 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
418 int OpIdx) const;
419 void renderExtractCpolSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
420 int OpIdx) const;
421
422 void renderFPPow2ToExponent(MachineInstrBuilder &MIB, const MachineInstr &MI,
423 int OpIdx) const;
424
425 void renderRoundMode(MachineInstrBuilder &MIB, const MachineInstr &MI,
426 int OpIdx) const;
427
428 void renderVOP3PModsNeg(MachineInstrBuilder &MIB, const MachineInstr &MI,
429 int OpIdx) const;
430 void renderVOP3PModsNegs(MachineInstrBuilder &MIB, const MachineInstr &MI,
431 int OpIdx) const;
432 void renderVOP3PModsNegAbs(MachineInstrBuilder &MIB, const MachineInstr &MI,
433 int OpIdx) const;
434
435 void renderPrefetchLoc(MachineInstrBuilder &MIB, const MachineInstr &MI,
436 int OpIdx) const;
437
438 void renderScaledMAIIntrinsicOperand(MachineInstrBuilder &MIB,
439 const MachineInstr &MI, int OpIdx) const;
440
441 bool isInlineImmediate(const APInt &Imm) const;
442 bool isInlineImmediate(const APFloat &Imm) const;
443
444 // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
445 // shift amount operand's `ShAmtBits` bits is unneeded.
446 bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
447
448 /// Match a zero extend from a 32-bit value to 64-bits.
449 Register matchZeroExtendFromS32(Register Reg) const;
450 /// Match a sign extend from a 32-bit value to 64-bits.
451 Register matchSignExtendFromS32(Register Reg) const;
452 /// Match a zero extend from a 32-bit value to 64-bits, or \p Reg itself if it
453 /// is 32-bit.
454 Register matchZeroExtendFromS32OrS32(Register Reg) const;
455 /// Match a sign extend from a 32-bit value to 64-bits, or \p Reg itself if it
456 /// is 32-bit.
457 Register matchSignExtendFromS32OrS32(Register Reg) const;
458 /// Match either sign or zero extend depending on the \p IsSigned from a
459 /// 32-bit value to 64-bits, or \p Reg itself if it is 32-bit.
460 Register matchExtendFromS32OrS32(Register Reg, bool IsSigned) const;
461 /// Match an any extend from a 32-bit value to 64-bit.
462 Register matchAnyExtendFromS32(Register Reg) const;
463
464 const SIInstrInfo &TII;
465 const SIRegisterInfo &TRI;
466 const AMDGPURegisterBankInfo &RBI;
467 const GCNSubtarget &STI;
468#define GET_GLOBALISEL_PREDICATES_DECL
469#define AMDGPUSubtarget GCNSubtarget
470#include "AMDGPUGenGlobalISel.inc"
471#undef GET_GLOBALISEL_PREDICATES_DECL
472#undef AMDGPUSubtarget
473
474#define GET_GLOBALISEL_TEMPORARIES_DECL
475#include "AMDGPUGenGlobalISel.inc"
476#undef GET_GLOBALISEL_TEMPORARIES_DECL
477};
478
479} // End llvm namespace.
480#endif
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
I
#define I(x, y, z)
Definition MD5.cpp:57
Reg
Register Reg
Definition MachineSink.cpp:2131
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2132
Register
Promote Memory to Register
Definition Mem2Reg.cpp:110
OpIdx
MachineInstr unsigned OpIdx
Definition NVPTXPrologEpilogPass.cpp:56
P
#define P(N)
llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector
AMDGPUInstructionSelector(const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI)
Definition AMDGPUInstructionSelector.cpp:43
llvm::AMDGPUInstructionSelector::getName
static const char * getName()
llvm::AMDGPUInstructionSelector::select
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
Definition AMDGPUInstructionSelector.cpp:4559
llvm::AMDGPUInstructionSelector::setupMF
void setupMF(MachineFunction &MF, GISelValueTracking *VT, CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF executor state.
Definition AMDGPUInstructionSelector.cpp:57
llvm::ArrayRef
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition BlockFrequencyInfo.h:38
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition InstrTypes.h:740
llvm::GIMatchTableExecutor::ComplexRendererFns
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
Definition GIMatchTableExecutor.h:633
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition MCRegisterInfo.h:37
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition MachineIRBuilder.h:238
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:74
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition MachineOperand.h:49
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition MachineRegisterInfo.h:53
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition ProfileSummaryInfo.h:42
llvm::RegisterBank
This class implements the register bank concept.
Definition RegisterBank.h:30
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition SmallVector.h:592
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1236
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition TargetRegisterInfo.h:72
uint64_t
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::Offset
@ Offset
Definition DWP.cpp:578
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition STLExtras.h:1669
llvm::VectorInstrContext::Load
@ Load
The value being inserted comes from a load (InsertElement only).
Definition TargetTransformInfo.h:191
llvm::TargetRegisterClass
MCRegisterClass TargetRegisterClass
Definition FastISel.h:58
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