LLVM 18.0.0git
GIMatchTableExecutor.h
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1//===- llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file declares the GIMatchTableExecutor API, the opcodes supported
10/// by the match table, and some associated data structures used by the
11/// executor's implementation (see `GIMatchTableExecutorImpl.h`).
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
16#define LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
17
18#include "llvm/ADT/Bitset.h"
19#include "llvm/ADT/DenseMap.h"
24#include "llvm/IR/Function.h"
25#include <bitset>
26#include <cstddef>
27#include <cstdint>
28#include <functional>
29#include <initializer_list>
30#include <optional>
31#include <vector>
32
33namespace llvm {
34
35class BlockFrequencyInfo;
36class CodeGenCoverage;
37class MachineBasicBlock;
38class ProfileSummaryInfo;
39class APInt;
40class APFloat;
41class GISelKnownBits;
42class MachineInstr;
43class MachineIRBuilder;
44class MachineInstrBuilder;
45class MachineFunction;
46class MachineOperand;
47class MachineRegisterInfo;
48class RegisterBankInfo;
49class TargetInstrInfo;
50class TargetRegisterInfo;
51
52enum {
55};
56
57enum {
58 /// Begin a try-block to attempt a match and jump to OnFail if it is
59 /// unsuccessful.
60 /// - OnFail - The MatchTable entry at which to resume if the match fails.
61 ///
62 /// FIXME: This ought to take an argument indicating the number of try-blocks
63 /// to exit on failure. It's usually one but the last match attempt of
64 /// a block will need more. The (implemented) alternative is to tack a
65 /// GIM_Reject on the end of each try-block which is simpler but
66 /// requires an extra opcode and iteration in the interpreter on each
67 /// failed match.
69
70 /// Switch over the opcode on the specified instruction
71 /// - InsnID - Instruction ID
72 /// - LowerBound - numerically minimum opcode supported
73 /// - UpperBound - numerically maximum + 1 opcode supported
74 /// - Default - failure jump target
75 /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
77
78 /// Switch over the LLT on the specified instruction operand
79 /// - InsnID - Instruction ID
80 /// - OpIdx - Operand index
81 /// - LowerBound - numerically minimum Type ID supported
82 /// - UpperBound - numerically maximum + 1 Type ID supported
83 /// - Default - failure jump target
84 /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
86
87 /// Record the specified instruction.
88 /// The IgnoreCopies variant ignores COPY instructions.
89 /// - NewInsnID - Instruction ID to define
90 /// - InsnID - Instruction ID
91 /// - OpIdx - Operand index
94
95 /// Check the feature bits
96 /// - Expected features
98
99 /// Check the opcode on the specified instruction
100 /// - InsnID - Instruction ID
101 /// - Expected opcode
103
104 /// Check the opcode on the specified instruction, checking 2 acceptable
105 /// alternatives.
106 /// - InsnID - Instruction ID
107 /// - Expected opcode
108 /// - Alternative expected opcode
110
111 /// Check the instruction has the right number of operands
112 /// - InsnID - Instruction ID
113 /// - Expected number of operands
115 /// Check an immediate predicate on the specified instruction
116 /// - InsnID - Instruction ID
117 /// - The predicate to test
119 /// Check an immediate predicate on the specified instruction via an APInt.
120 /// - InsnID - Instruction ID
121 /// - The predicate to test
123 /// Check a floating point immediate predicate on the specified instruction.
124 /// - InsnID - Instruction ID
125 /// - The predicate to test
127 /// Check an immediate predicate on the specified instruction
128 /// - InsnID - Instruction ID
129 /// - OpIdx - Operand index
130 /// - The predicate to test
132 /// Check a memory operation has the specified atomic ordering.
133 /// - InsnID - Instruction ID
134 /// - Ordering - The AtomicOrdering value
138 /// Check the size of the memory access for the given machine memory operand.
139 /// - InsnID - Instruction ID
140 /// - MMOIdx - MMO index
141 /// - Size - The size in bytes of the memory access
143
144 /// Check the address space of the memory access for the given machine memory
145 /// operand.
146 /// - InsnID - Instruction ID
147 /// - MMOIdx - MMO index
148 /// - NumAddrSpace - Number of valid address spaces
149 /// - AddrSpaceN - An allowed space of the memory access
150 /// - AddrSpaceN+1 ...
152
153 /// Check the minimum alignment of the memory access for the given machine
154 /// memory operand.
155 /// - InsnID - Instruction ID
156 /// - MMOIdx - MMO index
157 /// - MinAlign - Minimum acceptable alignment
159
160 /// Check the size of the memory access for the given machine memory operand
161 /// against the size of an operand.
162 /// - InsnID - Instruction ID
163 /// - MMOIdx - MMO index
164 /// - OpIdx - The operand index to compare the MMO against
168
169 /// Check if this is a vector that can be treated as a vector splat
170 /// constant. This is valid for both G_BUILD_VECTOR as well as
171 /// G_BUILD_VECTOR_TRUNC. For AllOnes refers to individual bits, so a -1
172 /// element.
173 /// - InsnID - Instruction ID
176
177 /// Check a trivial predicate which takes no arguments.
178 /// This can be used by executors to implement custom flags that don't fit in
179 /// target features.
181
182 /// Check a generic C++ instruction predicate
183 /// - InsnID - Instruction ID
184 /// - PredicateID - The ID of the predicate function to call
186
187 /// Check if there's no use of the first result.
188 /// - InsnID - Instruction ID
190
191 /// Check the type for the specified operand
192 /// - InsnID - Instruction ID
193 /// - OpIdx - Operand index
194 /// - Expected type
196 /// Check the type of a pointer to any address space.
197 /// - InsnID - Instruction ID
198 /// - OpIdx - Operand index
199 /// - SizeInBits - The size of the pointer value in bits.
201 /// Check the register bank for the specified operand
202 /// - InsnID - Instruction ID
203 /// - OpIdx - Operand index
204 /// - Expected register bank (specified as a register class)
206
207 /// Check the operand matches a complex predicate
208 /// - InsnID - Instruction ID
209 /// - OpIdx - Operand index
210 /// - RendererID - The renderer to hold the result
211 /// - Complex predicate ID
213
214 /// Check the operand is a specific integer
215 /// - InsnID - Instruction ID
216 /// - OpIdx - Operand index
217 /// - Expected integer
219 /// Check the operand is a specific literal integer (i.e. MO.isImm() or
220 /// MO.isCImm() is true).
221 /// - InsnID - Instruction ID
222 /// - OpIdx - Operand index
223 /// - Expected integer
225 /// Check the operand is a specific intrinsic ID
226 /// - InsnID - Instruction ID
227 /// - OpIdx - Operand index
228 /// - Expected Intrinsic ID
230
231 /// Check the operand is a specific predicate
232 /// - InsnID - Instruction ID
233 /// - OpIdx - Operand index
234 /// - Expected predicate
236
237 /// Check the specified operand is an MBB
238 /// - InsnID - Instruction ID
239 /// - OpIdx - Operand index
241
242 /// Check the specified operand is an Imm
243 /// - InsnID - Instruction ID
244 /// - OpIdx - Operand index
246
247 /// Check if the specified operand is safe to fold into the current
248 /// instruction.
249 /// - InsnID - Instruction ID
251
252 /// Check the specified operands are identical.
253 /// The IgnoreCopies variant looks through COPY instructions before
254 /// comparing the operands.
255 /// - InsnID - Instruction ID
256 /// - OpIdx - Operand index
257 /// - OtherInsnID - Other instruction ID
258 /// - OtherOpIdx - Other operand index
261
262 /// Check we can replace all uses of a register with another.
263 /// - OldInsnID
264 /// - OldOpIdx
265 /// - NewInsnID
266 /// - NewOpIdx
268
269 /// Check that a matched instruction has, or doesn't have a MIFlag.
270 ///
271 /// - InsnID - Instruction to check.
272 /// - Flag(s) - (can be one or more flags OR'd together)
275
276 /// Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some
277 /// named operands that will be recorded in RecordedOperands. Names of these
278 /// operands are referenced in predicate argument list. Emitter determines
279 /// StoreIdx(corresponds to the order in which names appear in argument list).
280 /// - InsnID - Instruction ID
281 /// - OpIdx - Operand index
282 /// - StoreIdx - Store location in RecordedOperands.
284
285 /// Records an operand's register type into the set of temporary types.
286 /// - InsnID - Instruction ID
287 /// - OpIdx - Operand index
288 /// - TempTypeIdx - Temp Type Index, always negative.
290
291 /// Fail the current try-block, or completely fail to match if there is no
292 /// current try-block.
294
295 //=== Renderers ===
296
297 /// Mutate an instruction
298 /// - NewInsnID - Instruction ID to define
299 /// - OldInsnID - Instruction ID to mutate
300 /// - NewOpcode - The new opcode to use
302
303 /// Build a new instruction
304 /// - InsnID - Instruction ID to define
305 /// - Opcode - The new opcode to use
307
308 /// Builds a constant and stores its result in a TempReg.
309 /// - TempRegID - Temp Register to define.
310 /// - Imm - The immediate to add
312
313 /// Copy an operand to the specified instruction
314 /// - NewInsnID - Instruction ID to modify
315 /// - OldInsnID - Instruction ID to copy from
316 /// - OpIdx - The operand to copy
318
319 /// Copy an operand to the specified instruction or add a zero register if the
320 /// operand is a zero immediate.
321 /// - NewInsnID - Instruction ID to modify
322 /// - OldInsnID - Instruction ID to copy from
323 /// - OpIdx - The operand to copy
324 /// - ZeroReg - The zero register to use
326 /// Copy an operand to the specified instruction
327 /// - NewInsnID - Instruction ID to modify
328 /// - OldInsnID - Instruction ID to copy from
329 /// - OpIdx - The operand to copy
330 /// - SubRegIdx - The subregister to copy
332
333 /// Add an implicit register def to the specified instruction
334 /// - InsnID - Instruction ID to modify
335 /// - RegNum - The register to add
336 /// - Flags - Register Flags
338 /// Add an implicit register use to the specified instruction
339 /// - InsnID - Instruction ID to modify
340 /// - RegNum - The register to add
342 /// Add an register to the specified instruction
343 /// - InsnID - Instruction ID to modify
344 /// - RegNum - The register to add
346
347 /// Marks the implicit def of a register as dead.
348 /// - InsnID - Instruction ID to modify
349 /// - OpIdx - The implicit def operand index
350 ///
351 /// OpIdx starts at 0 for the first implicit def.
353
354 /// Set or unset a MIFlag on an instruction.
355 ///
356 /// - InsnID - Instruction to modify.
357 /// - Flag(s) - (can be one or more flags OR'd together)
360
361 /// Copy the MIFlags of a matched instruction into an
362 /// output instruction. The flags are OR'd together.
363 ///
364 /// - InsnID - Instruction to modify.
365 /// - OldInsnID - Matched instruction to copy flags from.
367
368 /// Add a temporary register to the specified instruction
369 /// - InsnID - Instruction ID to modify
370 /// - TempRegID - The temporary register ID to add
371 /// - TempRegFlags - The register flags to set
373
374 /// Add a temporary register to the specified instruction
375 /// - InsnID - Instruction ID to modify
376 /// - TempRegID - The temporary register ID to add
377 /// - TempRegFlags - The register flags to set
378 /// - SubRegIndex - The subregister index to set
380
381 /// Add an immediate to the specified instruction
382 /// - InsnID - Instruction ID to modify
383 /// - Imm - The immediate to add
385
386 /// Add an CImm to the specified instruction
387 /// - InsnID - Instruction ID to modify
388 /// - Ty - Type of the constant immediate.
389 /// - Imm - The immediate to add
391
392 /// Render complex operands to the specified instruction
393 /// - InsnID - Instruction ID to modify
394 /// - RendererID - The renderer to call
396 /// Render sub-operands of complex operands to the specified instruction
397 /// - InsnID - Instruction ID to modify
398 /// - RendererID - The renderer to call
399 /// - RenderOpID - The suboperand to render.
401 /// Render subregisters of suboperands of complex operands to the
402 /// specified instruction
403 /// - InsnID - Instruction ID to modify
404 /// - RendererID - The renderer to call
405 /// - RenderOpID - The suboperand to render
406 /// - SubRegIdx - The subregister to extract
408
409 /// Render operands to the specified instruction using a custom function
410 /// - InsnID - Instruction ID to modify
411 /// - OldInsnID - Instruction ID to get the matched operand from
412 /// - RendererFnID - Custom renderer function to call
414
415 /// Calls a C++ function to perform an action when a match is complete.
416 /// The MatcherState is passed to the function to allow it to modify
417 /// instructions.
418 /// This is less constrained than a custom renderer and can update
419 /// instructions
420 /// in the state.
421 /// - FnID - The function to call.
422 /// TODO: Remove this at some point when combiners aren't reliant on it. It's
423 /// a bit of a hack.
425
426 /// Render operands to the specified instruction using a custom function,
427 /// reading from a specific operand.
428 /// - InsnID - Instruction ID to modify
429 /// - OldInsnID - Instruction ID to get the matched operand from
430 /// - OpIdx - Operand index in OldInsnID the render function should read
431 /// from..
432 /// - RendererFnID - Custom renderer function to call
434
435 /// Render a G_CONSTANT operator as a sign-extended immediate.
436 /// - NewInsnID - Instruction ID to modify
437 /// - OldInsnID - Instruction ID to copy from
438 /// The operand index is implicitly 1.
440
441 /// Render a G_FCONSTANT operator as a sign-extended immediate.
442 /// - NewInsnID - Instruction ID to modify
443 /// - OldInsnID - Instruction ID to copy from
444 /// The operand index is implicitly 1.
446
447 /// Constrain an instruction operand to a register class.
448 /// - InsnID - Instruction ID to modify
449 /// - OpIdx - Operand index
450 /// - RCEnum - Register class enumeration value
452
453 /// Constrain an instructions operands according to the instruction
454 /// description.
455 /// - InsnID - Instruction ID to modify
457
458 /// Merge all memory operands into instruction.
459 /// - InsnID - Instruction ID to modify
460 /// - MergeInsnID... - One or more Instruction ID to merge into the result.
461 /// - GIU_MergeMemOperands_EndOfList - Terminates the list of instructions to
462 /// merge.
464
465 /// Erase from parent.
466 /// - InsnID - Instruction ID to erase
468
469 /// Create a new temporary register that's not constrained.
470 /// - TempRegID - The temporary register ID to initialize.
471 /// - Expected type
473
474 /// Replaces all references to a register from an instruction
475 /// with another register from another instruction.
476 /// - OldInsnID
477 /// - OldOpIdx
478 /// - NewInsnID
479 /// - NewOpIdx
481
482 /// Replaces all references to a register with a temporary register.
483 /// - OldInsnID
484 /// - OldOpIdx
485 /// - TempRegIdx
487
488 /// A successful emission
490
491 /// Increment the rule coverage counter.
492 /// - RuleID - The ID of the rule that was covered.
494
495 /// Keeping track of the number of the GI opcodes. Must be the last entry.
497};
498
499enum {
500 /// Indicates the end of the variable-length MergeInsnID list in a
501 /// GIR_MergeMemOperands opcode.
503};
504
505/// Provides the logic to execute GlobalISel match tables, which are used by the
506/// instruction selector and instruction combiners as their engine to match and
507/// apply MIR patterns.
509public:
510 virtual ~GIMatchTableExecutor() = default;
511
513 GISelKnownBits *KB = nullptr;
514 MachineFunction *MF = nullptr;
517 // For some predicates, we need to track the current MBB.
519
521
522 /// Setup per-MF executor state.
524 CodeGenCoverage *covinfo = nullptr,
525 ProfileSummaryInfo *psi = nullptr,
526 BlockFrequencyInfo *bfi = nullptr) {
527 CoverageInfo = covinfo;
528 KB = kb;
529 MF = &mf;
530 PSI = psi;
531 BFI = bfi;
532 CurMBB = nullptr;
534 }
535
536protected:
538 std::optional<SmallVector<std::function<void(MachineInstrBuilder &)>, 4>>;
541
543 std::vector<ComplexRendererFns::value_type> Renderers;
546 /// Named operands that predicate with 'let PredicateCodeUsesOperands = 1'
547 /// referenced in its argument list. Operands are inserted at index set by
548 /// emitter, it corresponds to the order in which names appear in argument
549 /// list. Currently such predicates don't have more then 3 arguments.
550 std::array<const MachineOperand *, 3> RecordedOperands;
551
552 /// Types extracted from an instruction's operand.
553 /// Whenever a type index is negative, we look here instead.
555
556 MatcherState(unsigned MaxRenderers);
557 };
558
560 const auto &F = MF->getFunction();
561 return F.hasOptSize() || F.hasMinSize() ||
563 }
564
565public:
566 template <class PredicateBitset, class ComplexMatcherMemFn,
567 class CustomRendererFn>
568 struct ExecInfoTy {
569 ExecInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
570 const PredicateBitset *FeatureBitsets,
571 const ComplexMatcherMemFn *ComplexPredicates,
572 const CustomRendererFn *CustomRenderers)
576
577 for (size_t I = 0; I < NumTypeObjects; ++I)
579 }
581 const PredicateBitset *FeatureBitsets;
582 const ComplexMatcherMemFn *ComplexPredicates;
583 const CustomRendererFn *CustomRenderers;
584
586 };
587
588protected:
590
591 /// Execute a given matcher table and return true if the match was successful
592 /// and false otherwise.
593 template <class TgtExecutor, class PredicateBitset, class ComplexMatcherMemFn,
594 class CustomRendererFn>
595 bool executeMatchTable(TgtExecutor &Exec, MatcherState &State,
596 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn,
597 CustomRendererFn> &ExecInfo,
598 MachineIRBuilder &Builder, const int64_t *MatchTable,
600 const TargetRegisterInfo &TRI,
601 const RegisterBankInfo &RBI,
602 const PredicateBitset &AvailableFeatures,
604
605 virtual const int64_t *getMatchTable() const {
606 llvm_unreachable("Should have been overridden by tablegen if used");
607 }
608
609 virtual bool testImmPredicate_I64(unsigned, int64_t) const {
611 "Subclasses must override this with a tablegen-erated function");
612 }
613 virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
615 "Subclasses must override this with a tablegen-erated function");
616 }
617 virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
619 "Subclasses must override this with a tablegen-erated function");
620 }
621 virtual bool testMIPredicate_MI(unsigned, const MachineInstr &,
622 const MatcherState &State) const {
624 "Subclasses must override this with a tablegen-erated function");
625 }
626
627 virtual bool testSimplePredicate(unsigned) const {
628 llvm_unreachable("Subclass does not implement testSimplePredicate!");
629 }
630
631 virtual void runCustomAction(unsigned, const MatcherState &State,
632 NewMIVector &OutMIs) const {
633 llvm_unreachable("Subclass does not implement runCustomAction!");
634 }
635
636 bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
638 bool Splat = false) const;
639
640 /// Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on
641 /// the right-hand side. GlobalISel's separation of pointer and integer types
642 /// means that we don't need to worry about G_OR with equivalent semantics.
644 const MachineRegisterInfo &MRI) const;
645
646 /// Return true if MI can obviously be folded into IntoMI.
647 /// MI and IntoMI do not need to be in the same basic blocks, but MI must
648 /// preceed IntoMI.
650};
651
652} // end namespace llvm
653
654#endif // LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
unsigned const MachineRegisterInfo * MRI
This file defines the DenseMap class.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Implement a low-level type suitable for MachineInstr level instruction selection.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
This file defines the SmallVector class.
Class for arbitrary precision integers.
Definition: APInt.h:76
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Provides the logic to execute GlobalISel match tables, which are used by the instruction selector and...
virtual bool testSimplePredicate(unsigned) const
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &, const MatcherState &State) const
bool isBaseWithConstantOffset(const MachineOperand &Root, const MachineRegisterInfo &MRI) const
Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the right-hand side.
virtual bool testImmPredicate_I64(unsigned, int64_t) const
virtual const int64_t * getMatchTable() const
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
bool executeMatchTable(TgtExecutor &Exec, MatcherState &State, const ExecInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ExecInfo, MachineIRBuilder &Builder, const int64_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage *CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise.
bool shouldOptForSize(const MachineFunction *MF) const
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI, bool Splat=false) const
virtual void runCustomAction(unsigned, const MatcherState &State, NewMIVector &OutMIs) const
virtual ~GIMatchTableExecutor()=default
virtual void setupMF(MachineFunction &mf, GISelKnownBits *kb, CodeGenCoverage *covinfo=nullptr, ProfileSummaryInfo *psi=nullptr, BlockFrequencyInfo *bfi=nullptr)
Setup per-MF executor state.
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
virtual void setupGeneratedPerFunctionState(MachineFunction &MF)=0
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Analysis providing profile information.
Holds all the information related to register banks.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ GIU_MergeMemOperands_EndOfList
Indicates the end of the variable-length MergeInsnID list in a GIR_MergeMemOperands opcode.
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1353
@ GIR_ComplexRenderer
Render complex operands to the specified instruction.
@ GIR_ReplaceRegWithTempReg
Replaces all references to a register with a temporary register.
@ GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
@ GIR_MakeTempReg
Create a new temporary register that's not constrained.
@ GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
@ GIR_Done
A successful emission.
@ GIM_RecordNamedOperand
Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some named operands that will be ...
@ GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
@ GIM_CheckIsBuildVectorAllOnes
Check if this is a vector that can be treated as a vector splat constant.
@ GIM_CheckNumOperands
Check the instruction has the right number of operands.
@ GIR_AddCImm
Add an CImm to the specified instruction.
@ GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
@ GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
@ GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
@ GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
@ GIM_CheckHasNoUse
Check if there's no use of the first result.
@ GIM_CheckPointerToAny
Check the type of a pointer to any address space.
@ GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
@ GIM_CheckComplexPattern
Check the operand matches a complex predicate.
@ GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
@ GIR_EraseFromParent
Erase from parent.
@ GIR_CustomAction
Calls a C++ function to perform an action when a match is complete.
@ GIM_SwitchType
Switch over the LLT on the specified instruction operand.
@ GIR_CopySubReg
Copy an operand to the specified instruction.
@ GIR_MutateOpcode
Mutate an instruction.
@ GIM_CheckIsBuildVectorAllZeros
@ GIM_CheckAtomicOrderingOrStrongerThan
@ GIR_AddRegister
Add an register to the specified instruction.
@ GIR_AddTempSubRegister
Add a temporary register to the specified instruction.
@ GIM_CheckIsSafeToFold
Check if the specified operand is safe to fold into the current instruction.
@ GIM_CheckOpcode
Check the opcode on the specified instruction.
@ GIR_ReplaceReg
Replaces all references to a register from an instruction with another register from another instruct...
@ GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
@ GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
@ GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
@ GIR_AddTempRegister
Add a temporary register to the specified instruction.
@ GIR_Copy
Copy an operand to the specified instruction.
@ GIR_AddImm
Add an immediate to the specified instruction.
@ GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
@ GIU_NumOpcodes
Keeping track of the number of the GI opcodes. Must be the last entry.
@ GIM_MIFlags
Check that a matched instruction has, or doesn't have a MIFlag.
@ GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
@ GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
@ GIM_CheckIsSameOperand
Check the specified operands are identical.
@ GIM_CheckIsSameOperandIgnoreCopies
@ GIM_CheckIsMBB
Check the specified operand is an MBB.
@ GIM_CheckMemorySizeGreaterThanLLT
@ GIM_CheckRegBankForClass
Check the register bank for the specified operand.
@ GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
@ GIM_CheckMemorySizeLessThanLLT
@ GIM_RecordRegType
Records an operand's register type into the set of temporary types.
@ GIR_CopyMIFlags
Copy the MIFlags of a matched instruction into an output instruction.
@ GIR_BuildMI
Build a new instruction.
@ GIM_RecordInsn
Record the specified instruction.
@ GIM_CheckIsImm
Check the specified operand is an Imm.
@ GIM_CheckFeatures
Check the feature bits.
@ GIM_CheckCanReplaceReg
Check we can replace all uses of a register with another.
@ GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
@ GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
@ GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
@ GIM_CheckType
Check the type for the specified operand.
@ GIM_CheckCmpPredicate
Check the operand is a specific predicate.
@ GIM_CheckOpcodeIsEither
Check the opcode on the specified instruction, checking 2 acceptable alternatives.
@ GIR_SetImplicitDefDead
Marks the implicit def of a register as dead.
@ GIR_BuildConstant
Builds a constant and stores its result in a TempReg.
@ GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
@ GIR_Coverage
Increment the rule coverage counter.
@ GIR_MergeMemOperands
Merge all memory operands into instruction.
@ GIM_CheckImmOperandPredicate
Check an immediate predicate on the specified instruction.
@ GIM_CheckAtomicOrderingWeakerThan
@ GIR_SetMIFlags
Set or unset a MIFlag on an instruction.
@ GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
@ GIM_CheckConstantInt
Check the operand is a specific integer.
@ GIR_ComplexSubOperandSubRegRenderer
Render subregisters of suboperands of complex operands to the specified instruction.
@ GIM_RecordInsnIgnoreCopies
@ GIR_CustomOperandRenderer
Render operands to the specified instruction using a custom function, reading from a specific operand...
@ GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
@ GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
@ GIM_CheckSimplePredicate
Check a trivial predicate which takes no arguments.
@ GICXXCustomAction_Invalid
ExecInfoTy(const LLT *TypeObjects, size_t NumTypeObjects, const PredicateBitset *FeatureBitsets, const ComplexMatcherMemFn *ComplexPredicates, const CustomRendererFn *CustomRenderers)
SmallDenseMap< LLT, unsigned, 64 > TypeIDMap
const ComplexMatcherMemFn * ComplexPredicates
std::array< const MachineOperand *, 3 > RecordedOperands
Named operands that predicate with 'let PredicateCodeUsesOperands = 1' referenced in its argument lis...
SmallVector< LLT, 4 > RecordedTypes
Types extracted from an instruction's operand.
DenseMap< unsigned, unsigned > TempRegisters
std::vector< ComplexRendererFns::value_type > Renderers