LLVM 19.0.0git
GIMatchTableExecutor.h
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1//===- llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file declares the GIMatchTableExecutor API, the opcodes supported
10/// by the match table, and some associated data structures used by the
11/// executor's implementation (see `GIMatchTableExecutorImpl.h`).
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
16#define LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
17
18#include "llvm/ADT/Bitset.h"
19#include "llvm/ADT/DenseMap.h"
24#include "llvm/IR/Function.h"
25#include <bitset>
26#include <cstddef>
27#include <cstdint>
28#include <functional>
29#include <initializer_list>
30#include <optional>
31#include <vector>
32
33namespace llvm {
34
35class BlockFrequencyInfo;
36class CodeGenCoverage;
37class MachineBasicBlock;
38class ProfileSummaryInfo;
39class APInt;
40class APFloat;
41class GISelKnownBits;
42class MachineInstr;
43class MachineIRBuilder;
44class MachineInstrBuilder;
45class MachineFunction;
46class MachineOperand;
47class MachineRegisterInfo;
48class RegisterBankInfo;
49class TargetInstrInfo;
50class TargetRegisterInfo;
51
52enum {
55};
56
57/// The MatchTable is encoded as an array of bytes.
58/// Thus, opcodes are expected to be <255.
59///
60/// Operands can be variable-sized, their size is always after their name
61/// in the docs, e.g. "Foo(4)" means that "Foo" takes 4 entries in the table,
62/// so 4 bytes. "Foo()"
63///
64/// As a general rule of thumb:
65/// - Instruction & Operand IDs are ULEB128
66/// - LLT IDs are 1 byte
67/// - Predicates and target opcodes, register and register class IDs are 2
68/// bytes.
69/// - Indexes into the table are 4 bytes.
70/// - Inline constants are 8 bytes
71///
72/// Design notes:
73/// - Inst/Op IDs have to be LEB128 because some targets generate
74/// extremely long patterns which need more than 255 temporaries.
75/// We could just use 2 bytes everytime, but then some targets like
76/// X86/AMDGPU that have no need for it will pay the price all the time.
77enum {
78 /// Begin a try-block to attempt a match and jump to OnFail if it is
79 /// unsuccessful.
80 /// - OnFail(4) - The MatchTable entry at which to resume if the match fails.
81 ///
82 /// FIXME: This ought to take an argument indicating the number of try-blocks
83 /// to exit on failure. It's usually one but the last match attempt of
84 /// a block will need more. The (implemented) alternative is to tack a
85 /// GIM_Reject on the end of each try-block which is simpler but
86 /// requires an extra opcode and iteration in the interpreter on each
87 /// failed match.
89
90 /// Switch over the opcode on the specified instruction
91 /// - InsnID(ULEB128) - Instruction ID
92 /// - LowerBound(2) - numerically minimum opcode supported
93 /// - UpperBound(2) - numerically maximum + 1 opcode supported
94 /// - Default(4) - failure jump target
95 /// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets
97
98 /// Switch over the LLT on the specified instruction operand
99 /// - InsnID(ULEB128) - Instruction ID
100 /// - OpIdx(ULEB128) - Operand index
101 /// - LowerBound(2) - numerically minimum Type ID supported
102 /// - UpperBound(2) - numerically maximum + 1 Type ID supported
103 /// - Default(4) - failure jump target
104 /// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets
106
107 /// Record the specified instruction.
108 /// The IgnoreCopies variant ignores COPY instructions.
109 /// - NewInsnID(ULEB128) - Instruction ID to define
110 /// - InsnID(ULEB128) - Instruction ID
111 /// - OpIdx(ULEB128) - Operand index
114
115 /// Check the feature bits
116 /// Feature(2) - Expected features
118
119 /// Check the opcode on the specified instruction
120 /// - InsnID(ULEB128) - Instruction ID
121 /// - Opc(2) - Expected opcode
123
124 /// Check the opcode on the specified instruction, checking 2 acceptable
125 /// alternatives.
126 /// - InsnID(ULEB128) - Instruction ID
127 /// - Opc(2) - Expected opcode
128 /// - Opc(2) - Alternative expected opcode
130
131 /// Check the instruction has the right number of operands
132 /// - InsnID(ULEB128) - Instruction ID
133 /// - Ops(ULEB128) - Expected number of operands
135
136 /// Check an immediate predicate on the specified instruction
137 /// - InsnID(ULEB128) - Instruction ID
138 /// - Pred(2) - The predicate to test
140 /// Check an immediate predicate on the specified instruction via an APInt.
141 /// - InsnID(ULEB128) - Instruction ID
142 /// - Pred(2) - The predicate to test
144 /// Check a floating point immediate predicate on the specified instruction.
145 /// - InsnID(ULEB128) - Instruction ID
146 /// - Pred(2) - The predicate to test
148 /// Check an immediate predicate on the specified instruction
149 /// - InsnID(ULEB128) - Instruction ID
150 /// - OpIdx(ULEB128) - Operand index
151 /// - Pred(2) - The predicate to test
153
154 /// Check a memory operation has the specified atomic ordering.
155 /// - InsnID(ULEB128) - Instruction ID
156 /// - Ordering(ULEB128) - The AtomicOrdering value
160
161 /// Check the size of the memory access for the given machine memory operand.
162 /// - InsnID(ULEB128) - Instruction ID
163 /// - MMOIdx(ULEB128) - MMO index
164 /// - Size(4) - The size in bytes of the memory access
166
167 /// Check the address space of the memory access for the given machine memory
168 /// operand.
169 /// - InsnID(ULEB128) - Instruction ID
170 /// - MMOIdx(ULEB128) - MMO index
171 /// - NumAddrSpace(1) - Number of valid address spaces
172 /// - AddrSpaceN(ULEB128) - An allowed space of the memory access
173 /// - AddrSpaceN+1 ...
175
176 /// Check the minimum alignment of the memory access for the given machine
177 /// memory operand.
178 /// - InsnID(ULEB128) - Instruction ID
179 /// - MMOIdx(ULEB128) - MMO index
180 /// - MinAlign(1) - Minimum acceptable alignment
182
183 /// Check the size of the memory access for the given machine memory operand
184 /// against the size of an operand.
185 /// - InsnID(ULEB128) - Instruction ID
186 /// - MMOIdx(ULEB128) - MMO index
187 /// - OpIdx(ULEB128) - The operand index to compare the MMO against
191
192 /// Check if this is a vector that can be treated as a vector splat
193 /// constant. This is valid for both G_BUILD_VECTOR as well as
194 /// G_BUILD_VECTOR_TRUNC. For AllOnes refers to individual bits, so a -1
195 /// element.
196 /// - InsnID(ULEB128) - Instruction ID
199
200 /// Check a trivial predicate which takes no arguments.
201 /// This can be used by executors to implement custom flags that don't fit in
202 /// target features.
203 /// - Pred(2) - Predicate ID to check.
205
206 /// Check a generic C++ instruction predicate
207 /// - InsnID(ULEB128) - Instruction ID
208 /// - PredicateID(2) - The ID of the predicate function to call
210
211 /// Check if there's no use of the first result.
212 /// - InsnID(ULEB128) - Instruction ID
214
215 /// Check the type for the specified operand
216 /// - InsnID(ULEB128) - Instruction ID
217 /// - OpIdx(ULEB128) - Operand index
218 /// - Ty(1) - Expected type
220 /// GIM_CheckType but InsnID is omitted and defaults to zero.
222
223 /// Check the type of a pointer to any address space.
224 /// - InsnID(ULEB128) - Instruction ID
225 /// - OpIdx(ULEB128) - Operand index
226 /// - SizeInBits(ULEB128) - The size of the pointer value in bits.
228
229 /// Check the register bank for the specified operand
230 /// - InsnID(ULEB128) - Instruction ID
231 /// - OpIdx(ULEB128) - Operand index
232 /// - RC(2) - Expected register bank (specified as a register class)
234 /// GIM_CheckRegBankForClass but InsnID is omitted and defaults to zero.
236
237 /// Check the operand matches a complex predicate
238 /// - InsnID(ULEB128) - Instruction ID
239 /// - OpIdx(ULEB128) - Operand index
240 /// - RendererID(2) - The renderer to hold the result
241 /// - Pred(2) - Complex predicate ID
243
244 /// Check the operand is a specific integer
245 /// - InsnID(ULEB128) - Instruction ID
246 /// - OpIdx(ULEB128) - Operand index
247 /// - Val(8) Expected integer
249
250 /// Check the operand is a specific 8-bit signed integer
251 /// - InsnID(ULEB128) - Instruction ID
252 /// - OpIdx(ULEB128) - Operand index
253 /// - Val(1) Expected integer
255
256 /// Check the operand is a specific literal integer (i.e. MO.isImm() or
257 /// MO.isCImm() is true).
258 /// - InsnID(ULEB128) - Instruction ID
259 /// - OpIdx(ULEB128) - Operand index
260 /// - Val(8) - Expected integer
262
263 /// Check the operand is a specific intrinsic ID
264 /// - InsnID(ULEB128) - Instruction ID
265 /// - OpIdx(ULEB128) - Operand index
266 /// - IID(2) - Expected Intrinsic ID
268
269 /// Check the operand is a specific predicate
270 /// - InsnID(ULEB128) - Instruction ID
271 /// - OpIdx(ULEB128) - Operand index
272 /// - Pred(2) - Expected predicate
274
275 /// Check the specified operand is an MBB
276 /// - InsnID(ULEB128) - Instruction ID
277 /// - OpIdx(ULEB128) - Operand index
279
280 /// Check the specified operand is an Imm
281 /// - InsnID(ULEB128) - Instruction ID
282 /// - OpIdx(ULEB128) - Operand index
284
285 /// Checks if the matched instructions numbered [1, 1+N) can
286 /// be folded into the root (inst 0).
287 /// - Num(1)
289
290 /// Check the specified operands are identical.
291 /// The IgnoreCopies variant looks through COPY instructions before
292 /// comparing the operands.
293 /// - InsnID(ULEB128) - Instruction ID
294 /// - OpIdx(ULEB128) - Operand index
295 /// - OtherInsnID(ULEB128) - Other instruction ID
296 /// - OtherOpIdx(ULEB128) - Other operand index
299
300 /// Check we can replace all uses of a register with another.
301 /// - OldInsnID(ULEB128)
302 /// - OldOpIdx(ULEB128)
303 /// - NewInsnID(ULEB128)
304 /// - NewOpIdx(ULEB128)
306
307 /// Check that a matched instruction has, or doesn't have a MIFlag.
308 ///
309 /// - InsnID(ULEB128) - Instruction to check.
310 /// - Flags(4) - (can be one or more flags OR'd together)
313
314 /// Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some
315 /// named operands that will be recorded in RecordedOperands. Names of these
316 /// operands are referenced in predicate argument list. Emitter determines
317 /// StoreIdx(corresponds to the order in which names appear in argument list).
318 /// - InsnID(ULEB128) - Instruction ID
319 /// - OpIdx(ULEB128) - Operand index
320 /// - StoreIdx(ULEB128) - Store location in RecordedOperands.
322
323 /// Records an operand's register type into the set of temporary types.
324 /// - InsnID(ULEB128) - Instruction ID
325 /// - OpIdx(ULEB128) - Operand index
326 /// - TempTypeIdx(1) - Temp Type Index, always negative.
328
329 /// Fail the current try-block, or completely fail to match if there is no
330 /// current try-block.
332
333 //=== Renderers ===
334
335 /// Mutate an instruction
336 /// - NewInsnID(ULEB128) - Instruction ID to define
337 /// - OldInsnID(ULEB128) - Instruction ID to mutate
338 /// - NewOpcode(2) - The new opcode to use
340
341 /// Build a new instruction
342 /// - InsnID(ULEB128) - Instruction ID to define
343 /// - Opcode(2) - The new opcode to use
345 /// GIR_BuildMI but InsnID is omitted and defaults to zero.
347
348 /// Builds a constant and stores its result in a TempReg.
349 /// - TempRegID(ULEB128) - Temp Register to define.
350 /// - Imm(8) - The immediate to add
352
353 /// Copy an operand to the specified instruction
354 /// - NewInsnID(ULEB128) - Instruction ID to modify
355 /// - OldInsnID(ULEB128) - Instruction ID to copy from
356 /// - OpIdx(ULEB128) - The operand to copy
358 /// GIR_Copy but with both New/OldInsnIDs omitted and defaulting to zero.
360
361 /// Copy an operand to the specified instruction or add a zero register if the
362 /// operand is a zero immediate.
363 /// - NewInsnID(ULEB128) - Instruction ID to modify
364 /// - OldInsnID(ULEB128) - Instruction ID to copy from
365 /// - OpIdx(ULEB128) - The operand to copy
366 /// - ZeroReg(2) - The zero register to use
368 /// Copy an operand to the specified instruction
369 /// - NewInsnID(ULEB128) - Instruction ID to modify
370 /// - OldInsnID(ULEB128) - Instruction ID to copy from
371 /// - OpIdx(ULEB128) - The operand to copy
372 /// - SubRegIdx(2) - The subregister to copy
374
375 /// Add an implicit register def to the specified instruction
376 /// - InsnID(ULEB128) - Instruction ID to modify
377 /// - RegNum(2) - The register to add
378 /// - Flags(2) - Register Flags
380 /// Add an implicit register use to the specified instruction
381 /// - InsnID(ULEB128) - Instruction ID to modify
382 /// - RegNum(2) - The register to add
384 /// Add an register to the specified instruction
385 /// - InsnID(ULEB128) - Instruction ID to modify
386 /// - RegNum(2) - The register to add
387 /// - Flags(2) - Register Flags
389
390 /// Adds an intrinsic ID to the specified instruction.
391 /// - InsnID(ULEB128) - Instruction ID to modify
392 /// - IID(2) - Intrinsic ID
394
395 /// Marks the implicit def of a register as dead.
396 /// - InsnID(ULEB128) - Instruction ID to modify
397 /// - OpIdx(ULEB128) - The implicit def operand index
398 ///
399 /// OpIdx starts at 0 for the first implicit def.
401
402 /// Set or unset a MIFlag on an instruction.
403 ///
404 /// - InsnID(ULEB128) - Instruction to modify.
405 /// - Flags(4) - (can be one or more flags OR'd together)
408
409 /// Copy the MIFlags of a matched instruction into an
410 /// output instruction. The flags are OR'd together.
411 ///
412 /// - InsnID(ULEB128) - Instruction to modify.
413 /// - OldInsnID(ULEB128) - Matched instruction to copy flags from.
415
416 /// Add a temporary register to the specified instruction
417 /// - InsnID(ULEB128) - Instruction ID to modify
418 /// - TempRegID(ULEB128) - The temporary register ID to add
419 /// - TempRegFlags(2) - The register flags to set
421
422 /// Add a temporary register to the specified instruction without
423 /// setting any flags.
424 /// - InsnID(ULEB128) - Instruction ID to modify
425 /// - TempRegID(ULEB128) - The temporary register ID to add
427
428 /// Add a temporary register to the specified instruction
429 /// - InsnID(ULEB128) - Instruction ID to modify
430 /// - TempRegID(ULEB128) - The temporary register ID to add
431 /// - TempRegFlags(2) - The register flags to set
432 /// - SubRegIndex(2) - The subregister index to set
434
435 /// Add an immediate to the specified instruction
436 /// - InsnID(ULEB128) - Instruction ID to modify
437 /// - Imm(8) - The immediate to add
439
440 /// Add signed 8 bit immediate to the specified instruction
441 /// - InsnID(ULEB128) - Instruction ID to modify
442 /// - Imm(1) - The immediate to add
444
445 /// Add an CImm to the specified instruction
446 /// - InsnID(ULEB128) - Instruction ID to modify
447 /// - Ty(1) - Type of the constant immediate.
448 /// - Imm(8) - The immediate to add
450
451 /// Render complex operands to the specified instruction
452 /// - InsnID(ULEB128) - Instruction ID to modify
453 /// - RendererID(2) - The renderer to call
455 /// Render sub-operands of complex operands to the specified instruction
456 /// - InsnID(ULEB128) - Instruction ID to modify
457 /// - RendererID(2) - The renderer to call
458 /// - RenderOpID(ULEB128) - The suboperand to render.
460 /// Render subregisters of suboperands of complex operands to the
461 /// specified instruction
462 /// - InsnID(ULEB128) - Instruction ID to modify
463 /// - RendererID(2) - The renderer to call
464 /// - RenderOpID(ULEB128) - The suboperand to render
465 /// - SubRegIdx(2) - The subregister to extract
467
468 /// Render operands to the specified instruction using a custom function
469 /// - InsnID(ULEB128) - Instruction ID to modify
470 /// - OldInsnID(ULEB128) - Instruction ID to get the matched operand from
471 /// - RendererFnID(2) - Custom renderer function to call
473
474 /// Calls a C++ function that concludes the current match.
475 /// The C++ function is free to return false and reject the match, or
476 /// return true and mutate the instruction(s) (or do nothing, even).
477 /// - FnID(2) - The function to call.
479
480 /// Render operands to the specified instruction using a custom function,
481 /// reading from a specific operand.
482 /// - InsnID(ULEB128) - Instruction ID to modify
483 /// - OldInsnID(ULEB128) - Instruction ID to get the matched operand from
484 /// - OpIdx(ULEB128) - Operand index in OldInsnID the render function should
485 /// read
486 /// from..
487 /// - RendererFnID(2) - Custom renderer function to call
489
490 /// Render a G_CONSTANT operator as a sign-extended immediate.
491 /// - NewInsnID(ULEB128) - Instruction ID to modify
492 /// - OldInsnID(ULEB128) - Instruction ID to copy from
493 /// The operand index is implicitly 1.
495
496 /// Render a G_FCONSTANT operator as a sign-extended immediate.
497 /// - NewInsnID(ULEB128) - Instruction ID to modify
498 /// - OldInsnID(ULEB128) - Instruction ID to copy from
499 /// The operand index is implicitly 1.
501
502 /// Constrain an instruction operand to a register class.
503 /// - InsnID(ULEB128) - Instruction ID to modify
504 /// - OpIdx(ULEB128) - Operand index
505 /// - RCEnum(2) - Register class enumeration value
507
508 /// Constrain an instructions operands according to the instruction
509 /// description.
510 /// - InsnID(ULEB128) - Instruction ID to modify
512 /// GIR_ConstrainSelectedInstOperands but InsnID is omitted and defaults to
513 /// zero.
515
516 /// Merge all memory operands into instruction.
517 /// - InsnID(ULEB128) - Instruction ID to modify
518 /// - NumInsnID(1) - Number of instruction IDs following this argument
519 /// - MergeInsnID(ULEB128)... - One or more Instruction ID to merge into the
520 /// result.
522
523 /// Erase from parent.
524 /// - InsnID(ULEB128) - Instruction ID to erase
526
527 /// Combines both a GIR_EraseFromParent 0 + GIR_Done
529
530 /// Create a new temporary register that's not constrained.
531 /// - TempRegID(ULEB128) - The temporary register ID to initialize.
532 /// - Ty(1) - Expected type
534
535 /// Replaces all references to a register from an instruction
536 /// with another register from another instruction.
537 /// - OldInsnID(ULEB128)
538 /// - OldOpIdx(ULEB128)
539 /// - NewInsnID(ULEB128)
540 /// - NewOpIdx(ULEB128)
542
543 /// Replaces all references to a register with a temporary register.
544 /// - OldInsnID(ULEB128)
545 /// - OldOpIdx(ULEB128)
546 /// - TempRegIdx(ULEB128)
548
549 /// A successful emission
551
552 /// Increment the rule coverage counter.
553 /// - RuleID(4) - The ID of the rule that was covered.
555
556 /// Keeping track of the number of the GI opcodes. Must be the last entry.
558};
559
560/// Provides the logic to execute GlobalISel match tables, which are used by the
561/// instruction selector and instruction combiners as their engine to match and
562/// apply MIR patterns.
564public:
565 virtual ~GIMatchTableExecutor() = default;
566
568 GISelKnownBits *KB = nullptr;
569 MachineFunction *MF = nullptr;
572 // For some predicates, we need to track the current MBB.
574
576
577 /// Setup per-MF executor state.
579 CodeGenCoverage *covinfo = nullptr,
580 ProfileSummaryInfo *psi = nullptr,
581 BlockFrequencyInfo *bfi = nullptr) {
582 CoverageInfo = covinfo;
583 KB = kb;
584 MF = &mf;
585 PSI = psi;
586 BFI = bfi;
587 CurMBB = nullptr;
589 }
590
591protected:
593 std::optional<SmallVector<std::function<void(MachineInstrBuilder &)>, 4>>;
596
598 std::vector<ComplexRendererFns::value_type> Renderers;
601 /// Named operands that predicate with 'let PredicateCodeUsesOperands = 1'
602 /// referenced in its argument list. Operands are inserted at index set by
603 /// emitter, it corresponds to the order in which names appear in argument
604 /// list. Currently such predicates don't have more then 3 arguments.
605 std::array<const MachineOperand *, 3> RecordedOperands;
606
607 /// Types extracted from an instruction's operand.
608 /// Whenever a type index is negative, we look here instead.
610
611 MatcherState(unsigned MaxRenderers);
612 };
613
615 const auto &F = MF->getFunction();
616 return F.hasOptSize() || F.hasMinSize() ||
618 }
619
620public:
621 template <class PredicateBitset, class ComplexMatcherMemFn,
622 class CustomRendererFn>
623 struct ExecInfoTy {
624 ExecInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
625 const PredicateBitset *FeatureBitsets,
626 const ComplexMatcherMemFn *ComplexPredicates,
627 const CustomRendererFn *CustomRenderers)
631
632 for (size_t I = 0; I < NumTypeObjects; ++I)
634 }
636 const PredicateBitset *FeatureBitsets;
637 const ComplexMatcherMemFn *ComplexPredicates;
638 const CustomRendererFn *CustomRenderers;
639
641 };
642
643protected:
645
646 /// Execute a given matcher table and return true if the match was successful
647 /// and false otherwise.
648 template <class TgtExecutor, class PredicateBitset, class ComplexMatcherMemFn,
649 class CustomRendererFn>
650 bool executeMatchTable(TgtExecutor &Exec, MatcherState &State,
651 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn,
652 CustomRendererFn> &ExecInfo,
653 MachineIRBuilder &Builder, const uint8_t *MatchTable,
655 const TargetRegisterInfo &TRI,
656 const RegisterBankInfo &RBI,
657 const PredicateBitset &AvailableFeatures,
659
660 virtual const uint8_t *getMatchTable() const {
661 llvm_unreachable("Should have been overridden by tablegen if used");
662 }
663
664 virtual bool testImmPredicate_I64(unsigned, int64_t) const {
666 "Subclasses must override this with a tablegen-erated function");
667 }
668 virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
670 "Subclasses must override this with a tablegen-erated function");
671 }
672 virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
674 "Subclasses must override this with a tablegen-erated function");
675 }
676 virtual bool testMIPredicate_MI(unsigned, const MachineInstr &,
677 const MatcherState &State) const {
679 "Subclasses must override this with a tablegen-erated function");
680 }
681
682 virtual bool testSimplePredicate(unsigned) const {
683 llvm_unreachable("Subclass does not implement testSimplePredicate!");
684 }
685
686 virtual bool runCustomAction(unsigned, const MatcherState &State,
687 NewMIVector &OutMIs) const {
688 llvm_unreachable("Subclass does not implement runCustomAction!");
689 }
690
691 bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
693 bool Splat = false) const;
694
695 /// Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on
696 /// the right-hand side. GlobalISel's separation of pointer and integer types
697 /// means that we don't need to worry about G_OR with equivalent semantics.
699 const MachineRegisterInfo &MRI) const;
700
701 /// Return true if MI can obviously be folded into IntoMI.
702 /// MI and IntoMI do not need to be in the same basic blocks, but MI must
703 /// preceed IntoMI.
705
706 template <typename Ty> static Ty readBytesAs(const uint8_t *MatchTable) {
707 Ty Ret;
708 memcpy(&Ret, MatchTable, sizeof(Ret));
709 return Ret;
710 }
711
712public:
713 // Faster ULEB128 decoder tailored for the Match Table Executor.
714 //
715 // - Arguments are fixed to avoid mid-function checks.
716 // - Unchecked execution, assumes no error.
717 // - Fast common case handling (1 byte values).
720 uint64_t &CurrentIdx) {
721 uint64_t Value = MatchTable[CurrentIdx++];
722 if (LLVM_UNLIKELY(Value >= 128)) {
723 Value &= 0x7f;
724 unsigned Shift = 7;
725 do {
726 uint64_t Slice = MatchTable[CurrentIdx] & 0x7f;
727 Value += Slice << Shift;
728 Shift += 7;
729 } while (MatchTable[CurrentIdx++] >= 128);
730 }
731 return Value;
732 }
733};
734
735} // end namespace llvm
736
737#endif // LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
unsigned const MachineRegisterInfo * MRI
#define LLVM_UNLIKELY(EXPR)
Definition: Compiler.h:241
#define LLVM_ATTRIBUTE_ALWAYS_INLINE
LLVM_ATTRIBUTE_ALWAYS_INLINE - On compilers where we have a directive to do so, mark a method "always...
Definition: Compiler.h:261
#define LLVM_ATTRIBUTE_RESTRICT
LLVM_ATTRIBUTE_RESTRICT - Annotates a pointer to tell the compiler that it is not aliased in the curr...
Definition: Compiler.h:286
This file defines the DenseMap class.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Implement a low-level type suitable for MachineInstr level instruction selection.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
This file defines the SmallVector class.
Class for arbitrary precision integers.
Definition: APInt.h:76
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Provides the logic to execute GlobalISel match tables, which are used by the instruction selector and...
virtual bool testSimplePredicate(unsigned) const
bool executeMatchTable(TgtExecutor &Exec, MatcherState &State, const ExecInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ExecInfo, MachineIRBuilder &Builder, const uint8_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage *CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise.
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
virtual const uint8_t * getMatchTable() const
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &, const MatcherState &State) const
bool isBaseWithConstantOffset(const MachineOperand &Root, const MachineRegisterInfo &MRI) const
Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the right-hand side.
virtual bool testImmPredicate_I64(unsigned, int64_t) const
static Ty readBytesAs(const uint8_t *MatchTable)
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
bool shouldOptForSize(const MachineFunction *MF) const
static LLVM_ATTRIBUTE_ALWAYS_INLINE uint64_t fastDecodeULEB128(const uint8_t *LLVM_ATTRIBUTE_RESTRICT MatchTable, uint64_t &CurrentIdx)
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI, bool Splat=false) const
virtual ~GIMatchTableExecutor()=default
virtual void setupMF(MachineFunction &mf, GISelKnownBits *kb, CodeGenCoverage *covinfo=nullptr, ProfileSummaryInfo *psi=nullptr, BlockFrequencyInfo *bfi=nullptr)
Setup per-MF executor state.
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
virtual bool runCustomAction(unsigned, const MatcherState &State, NewMIVector &OutMIs) const
virtual void setupGeneratedPerFunctionState(MachineFunction &MF)=0
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Analysis providing profile information.
Holds all the information related to register banks.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ GICXXCustomAction_Invalid
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1623
@ GIR_AddIntrinsicID
Adds an intrinsic ID to the specified instruction.
@ GIR_ComplexRenderer
Render complex operands to the specified instruction.
@ GIR_ReplaceRegWithTempReg
Replaces all references to a register with a temporary register.
@ GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
@ GIR_MakeTempReg
Create a new temporary register that's not constrained.
@ GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
@ GIM_RootCheckType
GIM_CheckType but InsnID is omitted and defaults to zero.
@ GIM_RootCheckRegBankForClass
GIM_CheckRegBankForClass but InsnID is omitted and defaults to zero.
@ GIR_Done
A successful emission.
@ GIM_RecordNamedOperand
Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some named operands that will be ...
@ GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
@ GIR_RootConstrainSelectedInstOperands
GIR_ConstrainSelectedInstOperands but InsnID is omitted and defaults to zero.
@ GIM_CheckIsBuildVectorAllOnes
Check if this is a vector that can be treated as a vector splat constant.
@ GIM_CheckNumOperands
Check the instruction has the right number of operands.
@ GIR_AddCImm
Add an CImm to the specified instruction.
@ GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
@ GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
@ GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
@ GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
@ GIM_CheckHasNoUse
Check if there's no use of the first result.
@ GIM_CheckPointerToAny
Check the type of a pointer to any address space.
@ GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
@ GIM_CheckComplexPattern
Check the operand matches a complex predicate.
@ GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
@ GIR_EraseFromParent
Erase from parent.
@ GIM_SwitchType
Switch over the LLT on the specified instruction operand.
@ GIR_CopySubReg
Copy an operand to the specified instruction.
@ GIR_MutateOpcode
Mutate an instruction.
@ GIM_CheckIsBuildVectorAllZeros
@ GIM_CheckAtomicOrderingOrStrongerThan
@ GIR_AddRegister
Add an register to the specified instruction.
@ GIR_AddTempSubRegister
Add a temporary register to the specified instruction.
@ GIM_CheckIsSafeToFold
Checks if the matched instructions numbered [1, 1+N) can be folded into the root (inst 0).
@ GIM_CheckOpcode
Check the opcode on the specified instruction.
@ GIR_ReplaceReg
Replaces all references to a register from an instruction with another register from another instruct...
@ GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
@ GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
@ GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
@ GIR_AddSimpleTempRegister
Add a temporary register to the specified instruction without setting any flags.
@ GIR_AddTempRegister
Add a temporary register to the specified instruction.
@ GIR_Copy
Copy an operand to the specified instruction.
@ GIR_AddImm
Add an immediate to the specified instruction.
@ GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
@ GIU_NumOpcodes
Keeping track of the number of the GI opcodes. Must be the last entry.
@ GIM_MIFlags
Check that a matched instruction has, or doesn't have a MIFlag.
@ GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
@ GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
@ GIM_CheckIsSameOperand
Check the specified operands are identical.
@ GIR_AddImm8
Add signed 8 bit immediate to the specified instruction.
@ GIM_CheckIsSameOperandIgnoreCopies
@ GIM_CheckIsMBB
Check the specified operand is an MBB.
@ GIM_CheckMemorySizeGreaterThanLLT
@ GIM_CheckRegBankForClass
Check the register bank for the specified operand.
@ GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
@ GIM_CheckMemorySizeLessThanLLT
@ GIM_RecordRegType
Records an operand's register type into the set of temporary types.
@ GIR_EraseRootFromParent_Done
Combines both a GIR_EraseFromParent 0 + GIR_Done.
@ GIR_CopyMIFlags
Copy the MIFlags of a matched instruction into an output instruction.
@ GIR_DoneWithCustomAction
Calls a C++ function that concludes the current match.
@ GIR_BuildMI
Build a new instruction.
@ GIM_RecordInsn
Record the specified instruction.
@ GIM_CheckIsImm
Check the specified operand is an Imm.
@ GIR_BuildRootMI
GIR_BuildMI but InsnID is omitted and defaults to zero.
@ GIM_CheckFeatures
Check the feature bits Feature(2) - Expected features.
@ GIM_CheckCanReplaceReg
Check we can replace all uses of a register with another.
@ GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
@ GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
@ GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
@ GIM_CheckType
Check the type for the specified operand.
@ GIM_CheckConstantInt8
Check the operand is a specific 8-bit signed integer.
@ GIM_CheckCmpPredicate
Check the operand is a specific predicate.
@ GIM_CheckOpcodeIsEither
Check the opcode on the specified instruction, checking 2 acceptable alternatives.
@ GIR_SetImplicitDefDead
Marks the implicit def of a register as dead.
@ GIR_BuildConstant
Builds a constant and stores its result in a TempReg.
@ GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
@ GIR_Coverage
Increment the rule coverage counter.
@ GIR_MergeMemOperands
Merge all memory operands into instruction.
@ GIM_CheckImmOperandPredicate
Check an immediate predicate on the specified instruction.
@ GIM_CheckAtomicOrderingWeakerThan
@ GIR_SetMIFlags
Set or unset a MIFlag on an instruction.
@ GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
@ GIM_CheckConstantInt
Check the operand is a specific integer.
@ GIR_RootToRootCopy
GIR_Copy but with both New/OldInsnIDs omitted and defaulting to zero.
@ GIR_ComplexSubOperandSubRegRenderer
Render subregisters of suboperands of complex operands to the specified instruction.
@ GIM_RecordInsnIgnoreCopies
@ GIR_CustomOperandRenderer
Render operands to the specified instruction using a custom function, reading from a specific operand...
@ GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
@ GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
@ GIM_CheckSimplePredicate
Check a trivial predicate which takes no arguments.
ExecInfoTy(const LLT *TypeObjects, size_t NumTypeObjects, const PredicateBitset *FeatureBitsets, const ComplexMatcherMemFn *ComplexPredicates, const CustomRendererFn *CustomRenderers)
SmallDenseMap< LLT, unsigned, 64 > TypeIDMap
const ComplexMatcherMemFn * ComplexPredicates
std::array< const MachineOperand *, 3 > RecordedOperands
Named operands that predicate with 'let PredicateCodeUsesOperands = 1' referenced in its argument lis...
SmallVector< LLT, 4 > RecordedTypes
Types extracted from an instruction's operand.
DenseMap< unsigned, unsigned > TempRegisters
std::vector< ComplexRendererFns::value_type > Renderers