LLVM  10.0.0svn
Classes | Public Member Functions | Static Public Member Functions | List of all members
llvm::AMDGPUInstructionSelector Class Reference

#include "Target/AMDGPU/AMDGPUInstructionSelector.h"

Inheritance diagram for llvm::AMDGPUInstructionSelector:
Inheritance graph
Collaboration diagram for llvm::AMDGPUInstructionSelector:
Collaboration graph

Public Member Functions

 AMDGPUInstructionSelector (const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, const AMDGPUTargetMachine &TM)
bool select (MachineInstr &I) override
 Select the (possibly generic) instruction I to only use target-specific opcodes. More...
- Public Member Functions inherited from llvm::InstructionSelector
virtual ~InstructionSelector ()=default
virtual void setupMF (MachineFunction &mf, GISelKnownBits &KB, CodeGenCoverage &covinfo)
 Setup per-MF selector state. More...

Static Public Member Functions

static const chargetName ()

Additional Inherited Members

- Public Attributes inherited from llvm::InstructionSelector
CodeGenCoverageCoverageInfo = nullptr
GISelKnownBitsKnownBits = nullptr
MachineFunctionMF = nullptr
- Protected Types inherited from llvm::InstructionSelector
using ComplexRendererFns = Optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > >
using RecordedMIVector = SmallVector< MachineInstr *, 4 >
using NewMIVector = SmallVector< MachineInstrBuilder, 4 >
- Protected Member Functions inherited from llvm::InstructionSelector
 InstructionSelector ()
template<class TgtInstructionSelector , class PredicateBitset , class ComplexMatcherMemFn , class CustomRendererFn >
bool executeMatchTable (TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, const ISelInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ISelInfo, const int64_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage &CoverageInfo) const
 Execute a given matcher table and return true if the match was successful and false otherwise. More...
virtual const int64_t * getMatchTable () const
virtual bool testImmPredicate_I64 (unsigned, int64_t) const
virtual bool testImmPredicate_APInt (unsigned, const APInt &) const
virtual bool testImmPredicate_APFloat (unsigned, const APFloat &) const
virtual bool testMIPredicate_MI (unsigned, const MachineInstr &) const
bool constrainOperandRegToRegClass (MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
 Constrain a register operand of an instruction I to a specified register class. More...
bool isOperandImmEqual (const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
bool isBaseWithConstantOffset (const MachineOperand &Root, const MachineRegisterInfo &MRI) const
 Return true if the specified operand is a G_GEP with a G_CONSTANT on the right-hand side. More...
bool isObviouslySafeToFold (MachineInstr &MI, MachineInstr &IntoMI) const
 Return true if MI can obviously be folded into IntoMI. More...

Detailed Description

Definition at line 45 of file AMDGPUInstructionSelector.h.

Constructor & Destructor Documentation

◆ AMDGPUInstructionSelector()

AMDGPUInstructionSelector::AMDGPUInstructionSelector ( const GCNSubtarget STI,
const AMDGPURegisterBankInfo RBI,
const AMDGPUTargetMachine TM 

Definition at line 48 of file AMDGPUInstructionSelector.cpp.

References DEBUG_TYPE, and getName().

Member Function Documentation

◆ getName()

static const char* llvm::AMDGPUInstructionSelector::getName ( )

◆ select()

bool AMDGPUInstructionSelector::select ( MachineInstr I)

Select the (possibly generic) instruction I to only use target-specific opcodes.

It is OK to insert multiple instructions, but they cannot be generic pre-isel instructions.

whether selection succeeded.
I.getParent() && I.getParent()->getParent()
if returns true: for I in all mutated/inserted instructions: !isPreISelGenericOpcode(I.getOpcode())

Implements llvm::InstructionSelector.

Definition at line 1604 of file AMDGPUInstructionSelector.cpp.

References llvm::SISrcMods::ABS, llvm::ISD::ATOMIC_FENCE, llvm::BuildMI(), llvm::InstructionSelector::CoverageInfo, llvm::MachineRegisterInfo::createVirtualRegister(), llvm::Default, llvm::SmallVectorBase::empty(), getAddrSpace(), llvm::getConstantVRegVal(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::AMDGPU::getSMRDEncodedOffset(), llvm::Optional< T >::getValue(), llvm::MachineRegisterInfo::getVRegDef(), llvm::GCNSubtarget::hasFlatInstOffsets(), llvm::Optional< T >::hasValue(), llvm::MachineInstr::isCopy(), llvm::SIInstrInfo::isLegalFLATOffset(), llvm::AMDGPU::isLegalSMRDImmOffset(), llvm::MachineInstr::isPHI(), llvm::isPreISelGenericOpcode(), llvm::isUInt< 32 >(), llvm::MachineInstr::memoperands_begin(), MRI, llvm::SISrcMods::NEG, llvm::None, llvm::MachineInstr::setDesc(), Signed, and llvm::SmallVectorBase::size().

The documentation for this class was generated from the following files: