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SystemZISelLowering.h
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1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 
17 #include "SystemZ.h"
18 #include "SystemZInstrInfo.h"
22 #include <optional>
23 
24 namespace llvm {
25 namespace SystemZISD {
26 enum NodeType : unsigned {
28 
29  // Return with a flag operand. Operand 0 is the chain operand.
31 
32  // Calls a function. Operand 0 is the chain operand and operand 1
33  // is the target address. The arguments start at operand 2.
34  // There is an optional glue operand at the end.
37 
38  // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
39  // (The call target is implicitly __tls_get_offset.)
42 
43  // Wraps a TargetGlobalAddress that should be loaded using PC-relative
44  // accesses (LARL). Operand 0 is the address.
46 
47  // Used in cases where an offset is applied to a TargetGlobalAddress.
48  // Operand 0 is the full TargetGlobalAddress and operand 1 is a
49  // PCREL_WRAPPER for an anchor point. This is used so that we can
50  // cheaply refer to either the full address or the anchor point
51  // as a register base.
53 
54  // Integer comparisons. There are three operands: the two values
55  // to compare, and an integer of type SystemZICMP.
57 
58  // Floating-point comparisons. The two operands are the values to compare.
60 
61  // Test under mask. The first operand is ANDed with the second operand
62  // and the condition codes are set on the result. The third operand is
63  // a boolean that is true if the condition codes need to distinguish
64  // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
65  // register forms do but the memory forms don't).
66  TM,
67 
68  // Branches if a condition is true. Operand 0 is the chain operand;
69  // operand 1 is the 4-bit condition-code mask, with bit N in
70  // big-endian order meaning "branch if CC=N"; operand 2 is the
71  // target block and operand 3 is the flag operand.
73 
74  // Selects between operand 0 and operand 1. Operand 2 is the
75  // mask of condition-code values for which operand 0 should be
76  // chosen over operand 1; it has the same form as BR_CCMASK.
77  // Operand 3 is the flag operand.
79 
80  // Evaluates to the gap between the stack pointer and the
81  // base of the dynamically-allocatable area.
83 
84  // For allocating stack space when using stack clash protector.
85  // Allocation is performed by block, and each block is probed.
87 
88  // Count number of bits set in operand 0 per byte.
90 
91  // Wrappers around the ISD opcodes of the same name. The output is GR128.
92  // Input operands may be GR64 or GR32, depending on the instruction.
97 
98  // Add/subtract with overflow/carry. These have the same operands as
99  // the corresponding standard operations, except with the carry flag
100  // replaced by a condition code value.
102 
103  // Set the condition code from a boolean value in operand 0.
104  // Operand 1 is a mask of all condition-code values that may result of this
105  // operation, operand 2 is a mask of condition-code values that may result
106  // if the boolean is true.
107  // Note that this operation is always optimized away, we will never
108  // generate any code for it.
110 
111  // Use a series of MVCs to copy bytes from one memory location to another.
112  // The operands are:
113  // - the target address
114  // - the source address
115  // - the constant length
116  //
117  // This isn't a memory opcode because we'd need to attach two
118  // MachineMemOperands rather than one.
120 
121  // Similar to MVC, but for logic operations (AND, OR, XOR).
122  NC,
123  OC,
124  XC,
125 
126  // Use CLC to compare two blocks of memory, with the same comments
127  // as for MVC.
129 
130  // Use MVC to set a block of memory after storing the first byte.
132 
133  // Use an MVST-based sequence to implement stpcpy().
135 
136  // Use a CLST-based sequence to implement strcmp(). The two input operands
137  // are the addresses of the strings to compare.
139 
140  // Use an SRST-based sequence to search a block of memory. The first
141  // operand is the end address, the second is the start, and the third
142  // is the character to search for. CC is set to 1 on success and 2
143  // on failure.
145 
146  // Store the CC value in bits 29 and 28 of an integer.
148 
149  // Compiler barrier only; generate a no-op.
151 
152  // Transaction begin. The first operand is the chain, the second
153  // the TDB pointer, and the third the immediate control field.
154  // Returns CC value and chain.
157 
158  // Transaction end. Just the chain operand. Returns CC value and chain.
160 
161  // Create a vector constant by filling byte N of the result with bit
162  // 15-N of the single operand.
164 
165  // Create a vector constant by replicating an element-sized RISBG-style mask.
166  // The first operand specifies the starting set bit and the second operand
167  // specifies the ending set bit. Both operands count from the MSB of the
168  // element.
170 
171  // Replicate a GPR scalar value into all elements of a vector.
173 
174  // Create a vector from two i64 GPRs.
176 
177  // Replicate one element of a vector into all elements. The first operand
178  // is the vector and the second is the index of the element to replicate.
180 
181  // Interleave elements from the high half of operand 0 and the high half
182  // of operand 1.
184 
185  // Likewise for the low halves.
187 
188  // Concatenate the vectors in the first two operands, shift them left
189  // by the third operand, and take the first half of the result.
191 
192  // Take one element of the first v2i64 operand and the one element of
193  // the second v2i64 operand and concatenate them to form a v2i64 result.
194  // The third operand is a 4-bit value of the form 0A0B, where A and B
195  // are the element selectors for the first operand and second operands
196  // respectively.
198 
199  // Perform a general vector permute on vector operands 0 and 1.
200  // Each byte of operand 2 controls the corresponding byte of the result,
201  // in the same way as a byte-level VECTOR_SHUFFLE mask.
203 
204  // Pack vector operands 0 and 1 into a single vector with half-sized elements.
206 
207  // Likewise, but saturate the result and set CC. PACKS_CC does signed
208  // saturation and PACKLS_CC does unsigned saturation.
211 
212  // Unpack the first half of vector operand 0 into double-sized elements.
213  // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
216 
217  // Likewise for the second half.
220 
221  // Shift each element of vector operand 0 by the number of bits specified
222  // by scalar operand 1.
226 
227  // For each element of the output type, sum across all sub-elements of
228  // operand 0 belonging to the corresponding element, and add in the
229  // rightmost sub-element of the corresponding element of operand 1.
231 
232  // Compare integer vector operands 0 and 1 to produce the usual 0/-1
233  // vector result. VICMPE is for equality, VICMPH for "signed greater than"
234  // and VICMPHL for "unsigned greater than".
238 
239  // Likewise, but also set the condition codes on the result.
243 
244  // Compare floating-point vector operands 0 and 1 to produce the usual 0/-1
245  // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
246  // greater than" and VFCMPHE for "ordered and greater than or equal to".
250 
251  // Likewise, but also set the condition codes on the result.
255 
256  // Test floating-point data class for vectors.
258 
259  // Extend the even f32 elements of vector operand 0 to produce a vector
260  // of f64 elements.
262 
263  // Round the f64 elements of vector operand 0 to f32s and store them in the
264  // even elements of the result.
266 
267  // AND the two vector operands together and set CC based on the result.
269 
270  // String operations that set CC as a side-effect.
282 
283  // Test Data Class.
284  //
285  // Operand 0: the value to test
286  // Operand 1: the bit mask
288 
289  // Strict variants of scalar floating-point comparisons.
290  // Quiet and signaling versions.
293 
294  // Strict variants of vector floating-point comparisons.
295  // Quiet and signaling versions.
302 
303  // Strict variants of VEXTEND and VROUND.
306 
307  // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
308  // ATOMIC_LOAD_<op>.
309  //
310  // Operand 0: the address of the containing 32-bit-aligned field
311  // Operand 1: the second operand of <op>, in the high bits of an i32
312  // for everything except ATOMIC_SWAPW
313  // Operand 2: how many bits to rotate the i32 left to bring the first
314  // operand into the high bits
315  // Operand 3: the negative of operand 2, for rotating the other way
316  // Operand 4: the width of the field in bits (8 or 16)
328 
329  // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
330  //
331  // Operand 0: the address of the containing 32-bit-aligned field
332  // Operand 1: the compare value, in the low bits of an i32
333  // Operand 2: the swap value, in the low bits of an i32
334  // Operand 3: how many bits to rotate the i32 left to bring the first
335  // operand into the high bits
336  // Operand 4: the negative of operand 2, for rotating the other way
337  // Operand 5: the width of the field in bits (8 or 16)
339 
340  // Atomic compare-and-swap returning CC value.
341  // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
343 
344  // 128-bit atomic load.
345  // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr)
347 
348  // 128-bit atomic store.
349  // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr)
351 
352  // 128-bit atomic compare-and-swap.
353  // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
355 
356  // Byte swapping load/store. Same operands as regular load/store.
358 
359  // Element swapping load/store. Same operands as regular load/store.
361 
362  // Prefetch from the second operand using the 4-bit control code in
363  // the first operand. The code is 1 for a load prefetch and 2 for
364  // a store prefetch.
366 };
367 
368 // Return true if OPCODE is some kind of PC-relative address.
369 inline bool isPCREL(unsigned Opcode) {
370  return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
371 }
372 } // end namespace SystemZISD
373 
374 namespace SystemZICMP {
375 // Describes whether an integer comparison needs to be signed or unsigned,
376 // or whether either type is OK.
377 enum {
381 };
382 } // end namespace SystemZICMP
383 
384 class SystemZSubtarget;
385 
387 public:
388  explicit SystemZTargetLowering(const TargetMachine &TM,
389  const SystemZSubtarget &STI);
390 
391  bool useSoftFloat() const override;
392 
393  // Override TargetLowering.
394  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
395  return MVT::i32;
396  }
397  MVT getVectorIdxTy(const DataLayout &DL) const override {
398  // Only the lower 12 bits of an element index are used, so we don't
399  // want to clobber the upper 32 bits of a GPR unnecessarily.
400  return MVT::i32;
401  }
403  const override {
404  // Widen subvectors to the full width rather than promoting integer
405  // elements. This is better because:
406  //
407  // (a) it means that we can handle the ABI for passing and returning
408  // sub-128 vectors without having to handle them as legal types.
409  //
410  // (b) we don't have instructions to extend on load and truncate on store,
411  // so promoting the integers is less efficient.
412  //
413  // (c) there are no multiplication instructions for the widest integer
414  // type (v2i64).
415  if (VT.getScalarSizeInBits() % 8 == 0)
416  return TypeWidenVector;
418  }
419  unsigned
421  std::optional<MVT> RegisterVT) const override {
422  // i128 inline assembly operand.
423  if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped)
424  return 1;
426  }
427  bool isCheapToSpeculateCtlz(Type *) const override { return true; }
428  bool preferZeroCompareBranch() const override { return true; }
429  bool hasBitPreservingFPLogic(EVT VT) const override {
430  EVT ScVT = VT.getScalarType();
431  return ScVT == MVT::f32 || ScVT == MVT::f64 || ScVT == MVT::f128;
432  }
433  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override {
434  ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1));
435  return Mask && Mask->getValue().isIntN(16);
436  }
437  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
438  return VT.isScalarInteger();
439  }
441  EVT) const override;
443  EVT VT) const override;
444  bool isFPImmLegal(const APFloat &Imm, EVT VT,
445  bool ForCodeSize) const override;
446  bool ShouldShrinkFPConstant(EVT VT) const override {
447  // Do not shrink 64-bit FP constpool entries since LDEB is slower than
448  // LD, and having the full constant in memory enables reg/mem opcodes.
449  return VT != MVT::f64;
450  }
451  bool hasInlineStackProbe(const MachineFunction &MF) const override;
452  bool isLegalICmpImmediate(int64_t Imm) const override;
453  bool isLegalAddImmediate(int64_t Imm) const override;
454  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
455  unsigned AS,
456  Instruction *I = nullptr) const override;
457  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
459  unsigned *Fast) const override;
460  bool
461  findOptimalMemOpLowering(std::vector<EVT> &MemOps, unsigned Limit,
462  const MemOp &Op, unsigned DstAS, unsigned SrcAS,
463  const AttributeList &FuncAttributes) const override;
465  const AttributeList &FuncAttributes) const override;
466  bool isTruncateFree(Type *, Type *) const override;
467  bool isTruncateFree(EVT, EVT) const override;
468 
469  bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
470  bool MathUsed) const override {
471  // Form add and sub with overflow intrinsics regardless of any extra
472  // users of the math result.
473  return VT == MVT::i32 || VT == MVT::i64;
474  }
475 
476  bool shouldConsiderGEPOffsetSplit() const override { return true; }
477 
478  const char *getTargetNodeName(unsigned Opcode) const override;
479  std::pair<unsigned, const TargetRegisterClass *>
481  StringRef Constraint, MVT VT) const override;
483  getConstraintType(StringRef Constraint) const override;
485  getSingleConstraintMatchWeight(AsmOperandInfo &info,
486  const char *constraint) const override;
488  std::string &Constraint,
489  std::vector<SDValue> &Ops,
490  SelectionDAG &DAG) const override;
491 
492  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
493  if (ConstraintCode.size() == 1) {
494  switch(ConstraintCode[0]) {
495  default:
496  break;
497  case 'o':
499  case 'Q':
501  case 'R':
503  case 'S':
505  case 'T':
507  }
508  } else if (ConstraintCode.size() == 2 && ConstraintCode[0] == 'Z') {
509  switch (ConstraintCode[1]) {
510  default:
511  break;
512  case 'Q':
514  case 'R':
516  case 'S':
518  case 'T':
520  }
521  }
522  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
523  }
524 
525  Register getRegisterByName(const char *RegName, LLT VT,
526  const MachineFunction &MF) const override;
527 
528  /// If a physical register, this returns the register that receives the
529  /// exception address on entry to an EH pad.
530  Register
531  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
532  return SystemZ::R6D;
533  }
534 
535  /// If a physical register, this returns the register that receives the
536  /// exception typeid on entry to a landing pad.
537  Register
538  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
539  return SystemZ::R7D;
540  }
541 
542  /// Override to support customized stack guard loading.
543  bool useLoadStackGuardNode() const override {
544  return true;
545  }
546  void insertSSPDeclarations(Module &M) const override {
547  }
548 
551  MachineBasicBlock *BB) const override;
552  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
554  SelectionDAG &DAG) const override;
556  SelectionDAG &DAG) const override;
557  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
558  bool allowTruncateForTailCall(Type *, Type *) const override;
559  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
561  SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
562  unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
563  const override;
565  SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
566  unsigned NumParts, MVT PartVT, EVT ValueVT,
567  std::optional<CallingConv::ID> CC) const override;
569  bool isVarArg,
571  const SDLoc &DL, SelectionDAG &DAG,
572  SmallVectorImpl<SDValue> &InVals) const override;
573  SDValue LowerCall(CallLoweringInfo &CLI,
574  SmallVectorImpl<SDValue> &InVals) const override;
575 
576  std::pair<SDValue, SDValue>
577  makeExternalCall(SDValue Chain, SelectionDAG &DAG, const char *CalleeName,
578  EVT RetVT, ArrayRef<SDValue> Ops, CallingConv::ID CallConv,
579  bool IsSigned, SDLoc DL, bool DoesNotReturn,
580  bool IsReturnValueUsed) const;
581 
583  bool isVarArg,
585  LLVMContext &Context) const override;
586  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
588  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
589  SelectionDAG &DAG) const override;
590  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
591 
592  /// Determine which of the bits specified in Mask are known to be either
593  /// zero or one and return them in the KnownZero/KnownOne bitsets.
595  KnownBits &Known,
596  const APInt &DemandedElts,
597  const SelectionDAG &DAG,
598  unsigned Depth = 0) const override;
599 
600  /// Determine the number of bits in the operation that are sign bits.
602  const APInt &DemandedElts,
603  const SelectionDAG &DAG,
604  unsigned Depth) const override;
605 
607  return ISD::ANY_EXTEND;
608  }
610  return ISD::ZERO_EXTEND;
611  }
612 
613  bool supportSwiftError() const override {
614  return true;
615  }
616 
617  unsigned getStackProbeSize(const MachineFunction &MF) const;
618 
619 private:
620  const SystemZSubtarget &Subtarget;
621 
622  // Implement LowerOperation for individual opcodes.
623  SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
624  const SDLoc &DL, EVT VT,
625  SDValue CmpOp0, SDValue CmpOp1, SDValue Chain) const;
626  SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL,
627  EVT VT, ISD::CondCode CC,
628  SDValue CmpOp0, SDValue CmpOp1,
629  SDValue Chain = SDValue(),
630  bool IsSignaling = false) const;
631  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
632  SDValue lowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG,
633  bool IsSignaling) const;
634  SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
635  SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
636  SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
637  SelectionDAG &DAG) const;
638  SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
639  SelectionDAG &DAG, unsigned Opcode,
640  SDValue GOTOffset) const;
641  SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
642  SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
643  SelectionDAG &DAG) const;
644  SDValue lowerBlockAddress(BlockAddressSDNode *Node,
645  SelectionDAG &DAG) const;
646  SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
647  SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
648  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
649  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
650  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
651  SDValue lowerVASTART_ELF(SDValue Op, SelectionDAG &DAG) const;
652  SDValue lowerVASTART_XPLINK(SDValue Op, SelectionDAG &DAG) const;
653  SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
654  SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
655  SDValue lowerDYNAMIC_STACKALLOC_ELF(SDValue Op, SelectionDAG &DAG) const;
656  SDValue lowerDYNAMIC_STACKALLOC_XPLINK(SDValue Op, SelectionDAG &DAG) const;
657  SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
658  SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
659  SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
660  SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
661  SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
662  SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const;
663  SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) const;
664  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
665  SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
666  SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
667  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
668  SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
669  SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
670  SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
671  unsigned Opcode) const;
672  SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
673  SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
674  SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
675  SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
676  SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
677  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
678  SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
679  bool isVectorElementLoad(SDValue Op) const;
680  SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
681  SmallVectorImpl<SDValue> &Elems) const;
682  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
683  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
684  SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
685  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
686  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
687  SDValue lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
688  SDValue lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
689  SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
690  SDValue lowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
691 
692  bool canTreatAsByteVector(EVT VT) const;
693  SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
694  unsigned Index, DAGCombinerInfo &DCI,
695  bool Force) const;
696  SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
697  DAGCombinerInfo &DCI) const;
698  SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
699  SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
700  SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;
701  SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
702  bool canLoadStoreByteSwapped(EVT VT) const;
703  SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const;
704  SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
705  SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const;
706  SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
707  SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
708  SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
709  SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
710  SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const;
711  SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
712  SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
713  SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
714  SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
715  SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const;
716  SDValue combineINTRINSIC(SDNode *N, DAGCombinerInfo &DCI) const;
717 
718  SDValue unwrapAddress(SDValue N) const override;
719 
720  // If the last instruction before MBBI in MBB was some form of COMPARE,
721  // try to replace it with a COMPARE AND BRANCH just before MBBI.
722  // CCMask and Target are the BRC-like operands for the branch.
723  // Return true if the change was made.
724  bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
726  unsigned CCMask,
727  MachineBasicBlock *Target) const;
728 
729  // Implement EmitInstrWithCustomInserter for individual operation types.
730  MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
732  unsigned StoreOpcode, unsigned STOCOpcode,
733  bool Invert) const;
734  MachineBasicBlock *emitPair128(MachineInstr &MI,
735  MachineBasicBlock *MBB) const;
737  bool ClearEven) const;
738  MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
740  unsigned BinOpcode, unsigned BitSize,
741  bool Invert = false) const;
742  MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
744  unsigned CompareOpcode,
745  unsigned KeepOldMask,
746  unsigned BitSize) const;
747  MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
748  MachineBasicBlock *BB) const;
749  MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
750  unsigned Opcode,
751  bool IsMemset = false) const;
752  MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
753  unsigned Opcode) const;
754  MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
756  unsigned Opcode, bool NoFloat) const;
757  MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
759  unsigned Opcode) const;
760  MachineBasicBlock *emitProbedAlloca(MachineInstr &MI,
761  MachineBasicBlock *MBB) const;
762 
763  SDValue getBackchainAddress(SDValue SP, SelectionDAG &DAG) const;
764 
766  getTargetMMOFlags(const Instruction &I) const override;
767  const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
768 };
769 
771 private:
772  APInt IntBits; // The 128 bits as an integer.
773  APInt SplatBits; // Smallest splat value.
774  APInt SplatUndef; // Bits correspoding to undef operands of the BVN.
775  unsigned SplatBitSize = 0;
776  bool isFP128 = false;
777 public:
778  unsigned Opcode = 0;
783  : SystemZVectorConstantInfo(FPImm.bitcastToAPInt()) {
784  isFP128 = (&FPImm.getSemantics() == &APFloat::IEEEquad());
785  }
787  bool isVectorConstantLegal(const SystemZSubtarget &Subtarget);
788 };
789 
790 } // end namespace llvm
791 
792 #endif
llvm::TargetLoweringBase::getPreferredVectorAction
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Definition: TargetLowering.h:462
llvm::SystemZTargetLowering::getStackProbeSize
unsigned getStackProbeSize(const MachineFunction &MF) const
Definition: SystemZISelLowering.cpp:7445
llvm::SystemZTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: SystemZISelLowering.cpp:5899
llvm::SystemZISD::UADDO
@ UADDO
Definition: SystemZISelLowering.h:101
llvm::SystemZISD::SELECT_CCMASK
@ SELECT_CCMASK
Definition: SystemZISelLowering.h:78
llvm::SystemZTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: SystemZISelLowering.cpp:1280
llvm::SystemZISD::SDIVREM
@ SDIVREM
Definition: SystemZISelLowering.h:95
llvm::SystemZISD::ATOMIC_LOADW_SUB
@ ATOMIC_LOADW_SUB
Definition: SystemZISelLowering.h:319
llvm::SystemZISD::SUBCARRY
@ SUBCARRY
Definition: SystemZISelLowering.h:101
llvm::SystemZTargetLowering::makeExternalCall
std::pair< SDValue, SDValue > makeExternalCall(SDValue Chain, SelectionDAG &DAG, const char *CalleeName, EVT RetVT, ArrayRef< SDValue > Ops, CallingConv::ID CallConv, bool IsSigned, SDLoc DL, bool DoesNotReturn, bool IsReturnValueUsed) const
Definition: SystemZISelLowering.cpp:1886
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::SystemZISD::ATOMIC_LOAD_128
@ ATOMIC_LOAD_128
Definition: SystemZISelLowering.h:346
llvm::SystemZISD::USUBO
@ USUBO
Definition: SystemZISelLowering.h:101
llvm::SystemZISD::RET_FLAG
@ RET_FLAG
Definition: SystemZISelLowering.h:30
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:149
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:66
llvm::SystemZTargetLowering::isTruncateFree
bool isTruncateFree(Type *, Type *) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: SystemZISelLowering.cpp:1022
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1106
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::SystemZTargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Definition: SystemZISelLowering.cpp:1017
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4569
llvm::SystemZTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT) const override
Return the ValueType of the result of SETCC operations.
Definition: SystemZISelLowering.cpp:692
llvm::SystemZISD::ICMP
@ ICMP
Definition: SystemZISelLowering.h:56
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::SystemZTargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: SystemZISelLowering.cpp:1343
llvm::SystemZICMP::SignedOnly
@ SignedOnly
Definition: SystemZISelLowering.h:380
llvm::SystemZISD::GET_CCMASK
@ GET_CCMASK
Definition: SystemZISelLowering.h:109
llvm::MVT::i128
@ i128
Definition: MachineValueType.h:50
llvm::SystemZTargetLowering::hasInlineStackProbe
bool hasInlineStackProbe(const MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
Definition: SystemZISelLowering.cpp:846
llvm::SystemZISD::VICMPH
@ VICMPH
Definition: SystemZISelLowering.h:236
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:150
llvm::SystemZTargetLowering
Definition: SystemZISelLowering.h:386
llvm::SmallVector< unsigned, 2 >
llvm::SystemZISD::PACKLS_CC
@ PACKLS_CC
Definition: SystemZISelLowering.h:210
llvm::SystemZISD::CLC
@ CLC
Definition: SystemZISelLowering.h:128
llvm::SystemZTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: SystemZISelLowering.h:427
llvm::SystemZTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: SystemZISelLowering.cpp:5690
llvm::SystemZISD::ATOMIC_CMP_SWAPW
@ ATOMIC_CMP_SWAPW
Definition: SystemZISelLowering.h:338
llvm::SystemZISD::VICMPHLS
@ VICMPHLS
Definition: SystemZISelLowering.h:242
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::SystemZISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: SystemZISelLowering.h:27
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
MachineBasicBlock.h
llvm::SystemZISD::ROTATE_MASK
@ ROTATE_MASK
Definition: SystemZISelLowering.h:169
llvm::SystemZISD::VFENEZ_CC
@ VFENEZ_CC
Definition: SystemZISelLowering.h:276
llvm::MemOp
Definition: TargetLowering.h:111
llvm::SystemZISD::VFAE_CC
@ VFAE_CC
Definition: SystemZISelLowering.h:271
llvm::SystemZISD::VSTRS_CC
@ VSTRS_CC
Definition: SystemZISelLowering.h:280
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::InlineAsm::Constraint_S
@ Constraint_S
Definition: InlineAsm.h:265
llvm::SystemZTargetLowering::allowTruncateForTailCall
bool allowTruncateForTailCall(Type *, Type *) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
Definition: SystemZISelLowering.cpp:1338
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::SystemZISD::PREFETCH
@ PREFETCH
Definition: SystemZISelLowering.h:365
llvm::SystemZTargetLowering::LowerCall
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: SystemZISelLowering.cpp:1663
llvm::AttributeList
Definition: Attributes.h:431
llvm::SystemZISD::VSTER
@ VSTER
Definition: SystemZISelLowering.h:360
llvm::SystemZTargetLowering::SystemZTargetLowering
SystemZTargetLowering(const TargetMachine &TM, const SystemZSubtarget &STI)
Definition: SystemZISelLowering.cpp:81
llvm::SystemZTargetLowering::preferZeroCompareBranch
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
Definition: SystemZISelLowering.h:428
llvm::SystemZTargetLowering::getExtendForAtomicCmpSwapArg
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
Definition: SystemZISelLowering.h:609
llvm::SystemZTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: SystemZISelLowering.h:437
llvm::SystemZTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: SystemZISelLowering.cpp:1264
llvm::SystemZISD::STRICT_VEXTEND
@ STRICT_VEXTEND
Definition: SystemZISelLowering.h:304
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:772
llvm::SystemZTargetLowering::splitValueIntoRegisterParts
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Definition: SystemZISelLowering.cpp:1452
llvm::SystemZTargetLowering::getConstraintType
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: SystemZISelLowering.cpp:1043
llvm::SystemZTargetLowering::getSingleConstraintMatchWeight
TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: SystemZISelLowering.cpp:1087
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2195
llvm::SystemZISD::VICMPHL
@ VICMPHL
Definition: SystemZISelLowering.h:237
SelectionDAG.h
llvm::APFloat::getSemantics
const fltSemantics & getSemantics() const
Definition: APFloat.h:1238
llvm::SystemZISD::VSHL_BY_SCALAR
@ VSHL_BY_SCALAR
Definition: SystemZISelLowering.h:223
llvm::SystemZISD::PERMUTE_DWORDS
@ PERMUTE_DWORDS
Definition: SystemZISelLowering.h:197
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::SystemZTargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: SystemZISelLowering.h:429
llvm::SystemZTargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: SystemZISelLowering.h:546
llvm::SystemZTargetLowering::getNumRegisters
unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT) const override
Return the number of registers that this ValueType will eventually require.
Definition: SystemZISelLowering.h:420
llvm::InlineAsm::Constraint_ZQ
@ Constraint_ZQ
Definition: InlineAsm.h:282
llvm::SystemZISD::TEND
@ TEND
Definition: SystemZISelLowering.h:159
llvm::SystemZTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: SystemZISelLowering.cpp:1939
llvm::APFloatBase::IEEEquad
static const fltSemantics & IEEEquad() LLVM_READNONE
Definition: APFloat.cpp:207
llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
Definition: SystemZISelLowering.cpp:7390
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::SystemZISD::ATOMIC_SWAPW
@ ATOMIC_SWAPW
Definition: SystemZISelLowering.h:317
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TargetLowering.h
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::SystemZTargetLowering::getVectorIdxTy
MVT getVectorIdxTy(const DataLayout &DL) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
Definition: SystemZISelLowering.h:397
llvm::SystemZISD::ATOMIC_LOADW_UMAX
@ ATOMIC_LOADW_UMAX
Definition: SystemZISelLowering.h:327
llvm::SystemZISD::BR_CCMASK
@ BR_CCMASK
Definition: SystemZISelLowering.h:72
llvm::SystemZISD::UNPACK_HIGH
@ UNPACK_HIGH
Definition: SystemZISelLowering.h:214
llvm::SystemZISD::ATOMIC_LOADW_ADD
@ ATOMIC_LOADW_ADD
Definition: SystemZISelLowering.h:318
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
SystemZInstrInfo.h
llvm::SystemZISD::TLS_LDCALL
@ TLS_LDCALL
Definition: SystemZISelLowering.h:41
llvm::SystemZISD::VSRA_BY_SCALAR
@ VSRA_BY_SCALAR
Definition: SystemZISelLowering.h:225
llvm::SystemZISD::TLS_GDCALL
@ TLS_GDCALL
Definition: SystemZISelLowering.h:40
llvm::SystemZISD::VFEEZ_CC
@ VFEEZ_CC
Definition: SystemZISelLowering.h:274
llvm::SystemZISD::ATOMIC_LOADW_UMIN
@ ATOMIC_LOADW_UMIN
Definition: SystemZISelLowering.h:326
llvm::SystemZTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: SystemZISelLowering.h:531
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:58
llvm::SystemZTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: SystemZISelLowering.cpp:854
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1862
llvm::SystemZISD::SIBCALL
@ SIBCALL
Definition: SystemZISelLowering.h:36
llvm::SystemZISD::JOIN_DWORDS
@ JOIN_DWORDS
Definition: SystemZISelLowering.h:175
llvm::SystemZISD::VSTRCZ_CC
@ VSTRCZ_CC
Definition: SystemZISelLowering.h:279
llvm::InlineAsm::Constraint_ZS
@ Constraint_ZS
Definition: InlineAsm.h:284
llvm::SystemZTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: SystemZISelLowering.cpp:8760
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3506
llvm::SystemZISD::VSRL_BY_SCALAR
@ VSRL_BY_SCALAR
Definition: SystemZISelLowering.h:224
llvm::SystemZTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: SystemZISelLowering.h:606
llvm::MVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: MachineValueType.h:1138
llvm::SystemZISD::UNPACKL_HIGH
@ UNPACKL_HIGH
Definition: SystemZISelLowering.h:215
llvm::SystemZISD::STRICT_VFCMPHES
@ STRICT_VFCMPHES
Definition: SystemZISelLowering.h:301
llvm::SystemZISD::VFCMPHES
@ VFCMPHES
Definition: SystemZISelLowering.h:254
llvm::SystemZISD::CALL
@ CALL
Definition: SystemZISelLowering.h:35
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::SystemZISD::ATOMIC_LOADW_AND
@ ATOMIC_LOADW_AND
Definition: SystemZISelLowering.h:320
llvm::SystemZTargetLowering::isMaskAndCmp0FoldingBeneficial
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
Definition: SystemZISelLowering.h:433
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::SystemZTargetLowering::joinRegisterPartsIntoValue
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
Definition: SystemZISelLowering.cpp:1468
llvm::Instruction
Definition: Instruction.h:42
llvm::InlineAsm::Constraint_ZR
@ Constraint_ZR
Definition: InlineAsm.h:283
llvm::SystemZVectorConstantInfo::isVectorConstantLegal
bool isVectorConstantLegal(const SystemZSubtarget &Subtarget)
Definition: SystemZISelLowering.cpp:721
llvm::SystemZISD::STRCMP
@ STRCMP
Definition: SystemZISelLowering.h:138
llvm::SystemZISD::STRICT_VROUND
@ STRICT_VROUND
Definition: SystemZISelLowering.h:305
llvm::SystemZISD::VFEE_CC
@ VFEE_CC
Definition: SystemZISelLowering.h:273
SystemZ.h
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:213
llvm::SystemZISD::VSUM
@ VSUM
Definition: SystemZISelLowering.h:230
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SystemZISD::FCMP
@ FCMP
Definition: SystemZISelLowering.h:59
llvm::SystemZTargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: SystemZISelLowering.h:613
llvm::SystemZISD::VFCMPE
@ VFCMPE
Definition: SystemZISelLowering.h:247
llvm::SystemZISD::UDIVREM
@ UDIVREM
Definition: SystemZISelLowering.h:96
llvm::SystemZISD::SSUBO
@ SSUBO
Definition: SystemZISelLowering.h:101
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::SystemZISD::VTM
@ VTM
Definition: SystemZISelLowering.h:268
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::SystemZTargetLowering::useSoftFloat
bool useSoftFloat() const override
Definition: SystemZISelLowering.cpp:688
llvm::SystemZISD::ATOMIC_LOADW_NAND
@ ATOMIC_LOADW_NAND
Definition: SystemZISelLowering.h:323
llvm::SystemZISD::SMUL_LOHI
@ SMUL_LOHI
Definition: SystemZISelLowering.h:93
llvm::SystemZISD::VFCMPHE
@ VFCMPHE
Definition: SystemZISelLowering.h:249
llvm::SystemZVectorConstantInfo::Opcode
unsigned Opcode
Definition: SystemZISelLowering.h:778
llvm::SystemZISD::UMUL_LOHI
@ UMUL_LOHI
Definition: SystemZISelLowering.h:94
llvm::SystemZTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: SystemZISelLowering.cpp:7124
llvm::SystemZISD::TBEGIN_NOFLOAT
@ TBEGIN_NOFLOAT
Definition: SystemZISelLowering.h:156
llvm::SystemZTargetLowering::findOptimalMemOpLowering
bool findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const override
Determines the optimal series of memory ops to replace the memset / memcpy.
Definition: SystemZISelLowering.cpp:998
llvm::APFloat
Definition: APFloat.h:716
llvm::SystemZISD::TDC
@ TDC
Definition: SystemZISelLowering.h:287
llvm::TargetLoweringBase::getNumRegisters
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
Definition: TargetLowering.h:1586
llvm::SystemZTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: SystemZISelLowering.cpp:7272
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::SystemZISD::VICMPHS
@ VICMPHS
Definition: SystemZISelLowering.h:241
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::SystemZVectorConstantInfo
Definition: SystemZISelLowering.h:770
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1313
llvm::SystemZISD::MVC
@ MVC
Definition: SystemZISelLowering.h:119
llvm::SystemZISD::SHL_DOUBLE
@ SHL_DOUBLE
Definition: SystemZISelLowering.h:190
llvm::SystemZISD::MERGE_HIGH
@ MERGE_HIGH
Definition: SystemZISelLowering.h:183
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::SystemZISD::LRV
@ LRV
Definition: SystemZISelLowering.h:357
llvm::SystemZISD::XC
@ XC
Definition: SystemZISelLowering.h:124
llvm::SystemZICMP::Any
@ Any
Definition: SystemZISelLowering.h:378
llvm::SystemZTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: SystemZISelLowering.cpp:859
llvm::InlineAsm::Constraint_R
@ Constraint_R
Definition: InlineAsm.h:264
llvm::SystemZTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: SystemZISelLowering.cpp:1919
llvm::SystemZTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: SystemZISelLowering.h:538
llvm::SystemZISD::VEXTEND
@ VEXTEND
Definition: SystemZISelLowering.h:261
llvm::SystemZISD::STRICT_VFCMPHS
@ STRICT_VFCMPHS
Definition: SystemZISelLowering.h:300
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::SystemZISD::VSTRC_CC
@ VSTRC_CC
Definition: SystemZISelLowering.h:278
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::SystemZISD::OC
@ OC
Definition: SystemZISelLowering.h:123
llvm::SystemZISD::SEARCH_STRING
@ SEARCH_STRING
Definition: SystemZISelLowering.h:144
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1424
llvm::SystemZVectorConstantInfo::SystemZVectorConstantInfo
SystemZVectorConstantInfo(APFloat FPImm)
Definition: SystemZISelLowering.h:782
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::SystemZISD::VFCMPES
@ VFCMPES
Definition: SystemZISelLowering.h:252
llvm::SystemZISD::VFCMPH
@ VFCMPH
Definition: SystemZISelLowering.h:248
llvm::SystemZSubtarget
Definition: SystemZSubtarget.h:33
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:66
llvm::SystemZISD::ATOMIC_LOADW_XOR
@ ATOMIC_LOADW_XOR
Definition: SystemZISelLowering.h:322
llvm::SystemZISD::VFCMPHS
@ VFCMPHS
Definition: SystemZISelLowering.h:253
llvm::SystemZISD::STRICT_VFCMPH
@ STRICT_VFCMPH
Definition: SystemZISelLowering.h:297
info
lazy value info
Definition: LazyValueInfo.cpp:59
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1883
llvm::SystemZISD::MEMSET_MVC
@ MEMSET_MVC
Definition: SystemZISelLowering.h:131
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::BuildVectorSDNode
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Definition: SelectionDAGNodes.h:1988
llvm::SystemZTargetLowering::shouldConsiderGEPOffsetSplit
bool shouldConsiderGEPOffsetSplit() const override
Definition: SystemZISelLowering.h:476
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::SystemZTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: SystemZISelLowering.cpp:971
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SystemZISD::VFENE_CC
@ VFENE_CC
Definition: SystemZISelLowering.h:275
llvm::InlineAsm::Constraint_ZT
@ Constraint_ZT
Definition: InlineAsm.h:285
llvm::SystemZTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: SystemZISelLowering.h:492
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::SystemZVectorConstantInfo::SystemZVectorConstantInfo
SystemZVectorConstantInfo(APInt IntImm)
Definition: SystemZISelLowering.cpp:796
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::InlineAsm::Constraint_o
@ Constraint_o
Definition: InlineAsm.h:260
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1307
llvm::SystemZISD::REPLICATE
@ REPLICATE
Definition: SystemZISelLowering.h:172
Node
Definition: ItaniumDemangle.h:156
llvm::SystemZTargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: SystemZISelLowering.h:402
llvm::SystemZISD::ATOMIC_LOADW_MIN
@ ATOMIC_LOADW_MIN
Definition: SystemZISelLowering.h:324
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SystemZISD::VROUND
@ VROUND
Definition: SystemZISelLowering.h:265
llvm::SystemZISD::ATOMIC_LOADW_OR
@ ATOMIC_LOADW_OR
Definition: SystemZISelLowering.h:321
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
llvm::SystemZTargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: SystemZISelLowering.h:394
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonISD::CP
@ CP
Definition: HexagonISelLowering.h:53
llvm::SystemZISD::STRICT_FCMP
@ STRICT_FCMP
Definition: SystemZISelLowering.h:291
llvm::SystemZISD::SADDO
@ SADDO
Definition: SystemZISelLowering.h:101
llvm::SystemZISD::STRICT_FCMPS
@ STRICT_FCMPS
Definition: SystemZISelLowering.h:292
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1759
llvm::KnownBits
Definition: KnownBits.h:23
llvm::SystemZISD::MEMBARRIER
@ MEMBARRIER
Definition: SystemZISelLowering.h:150
llvm::SystemZISD::PACKS_CC
@ PACKS_CC
Definition: SystemZISelLowering.h:209
uint16_t
llvm::SystemZTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: SystemZISelLowering.cpp:5905
llvm::EVT::getScalarType
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:295
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4579
llvm::SystemZISD::ATOMIC_CMP_SWAP_128
@ ATOMIC_CMP_SWAP_128
Definition: SystemZISelLowering.h:354
llvm::SystemZISD::PROBED_ALLOCA
@ PROBED_ALLOCA
Definition: SystemZISelLowering.h:86
llvm::SystemZISD::VICMPES
@ VICMPES
Definition: SystemZISelLowering.h:240
llvm::SystemZISD::VICMPE
@ VICMPE
Definition: SystemZISelLowering.h:235
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::SystemZISD::PACK
@ PACK
Definition: SystemZISelLowering.h:205
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:205
llvm::SystemZTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: SystemZISelLowering.cpp:836
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::SystemZTargetLowering::ShouldShrinkFPConstant
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Definition: SystemZISelLowering.h:446
llvm::SystemZISD::NC
@ NC
Definition: SystemZISelLowering.h:122
llvm::SystemZISD::PCREL_WRAPPER
@ PCREL_WRAPPER
Definition: SystemZISelLowering.h:45
llvm::SystemZISD::PCREL_OFFSET
@ PCREL_OFFSET
Definition: SystemZISelLowering.h:52
llvm::SystemZISD::VISTR_CC
@ VISTR_CC
Definition: SystemZISelLowering.h:277
llvm::SystemZISD::VFAEZ_CC
@ VFAEZ_CC
Definition: SystemZISelLowering.h:272
llvm::SystemZISD::MERGE_LOW
@ MERGE_LOW
Definition: SystemZISelLowering.h:186
llvm::SystemZTargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
Definition: SystemZISelLowering.h:543
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::SystemZISD::STRICT_VFCMPHE
@ STRICT_VFCMPHE
Definition: SystemZISelLowering.h:298
llvm::SystemZTargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: SystemZISelLowering.h:469
llvm::SystemZISD::UNPACK_LOW
@ UNPACK_LOW
Definition: SystemZISelLowering.h:218
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:60
llvm::SystemZISD::VLER
@ VLER
Definition: SystemZISelLowering.h:360
llvm::SystemZISD::ADJDYNALLOC
@ ADJDYNALLOC
Definition: SystemZISelLowering.h:82
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1319
N
#define N
llvm::SystemZISD::ATOMIC_STORE_128
@ ATOMIC_STORE_128
Definition: SystemZISelLowering.h:350
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4671
llvm::SystemZISD::UNPACKL_LOW
@ UNPACKL_LOW
Definition: SystemZISelLowering.h:219
llvm::SystemZISD::VFTCI
@ VFTCI
Definition: SystemZISelLowering.h:257
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::MVT::Untyped
@ Untyped
Definition: MachineValueType.h:286
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::SystemZISD::isPCREL
bool isPCREL(unsigned Opcode)
Definition: SystemZISelLowering.h:369
llvm::SystemZISD::ATOMIC_LOADW_MAX
@ ATOMIC_LOADW_MAX
Definition: SystemZISelLowering.h:325
RegName
#define RegName(no)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SystemZISD::SPLAT
@ SPLAT
Definition: SystemZISelLowering.h:179
llvm::SystemZISD::STRICT_VFCMPE
@ STRICT_VFCMPE
Definition: SystemZISelLowering.h:296
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1474
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::SystemZISD::STPCPY
@ STPCPY
Definition: SystemZISelLowering.h:134
llvm::SystemZTargetLowering::getScratchRegisters
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition: SystemZISelLowering.cpp:1331
llvm::SystemZISD::ADDCARRY
@ ADDCARRY
Definition: SystemZISelLowering.h:101
llvm::SystemZICMP::UnsignedOnly
@ UnsignedOnly
Definition: SystemZISelLowering.h:379
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::SystemZTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: SystemZISelLowering.cpp:1481
llvm::SystemZISD::VSTRSZ_CC
@ VSTRSZ_CC
Definition: SystemZISelLowering.h:281
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:263
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:57
llvm::SystemZISD::PERMUTE
@ PERMUTE
Definition: SystemZISelLowering.h:202
llvm::SystemZVectorConstantInfo::OpVals
SmallVector< unsigned, 2 > OpVals
Definition: SystemZISelLowering.h:779
llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: SystemZISelLowering.cpp:699
llvm::SystemZISD::IPM
@ IPM
Definition: SystemZISelLowering.h:147
llvm::SystemZISD::TBEGIN
@ TBEGIN
Definition: SystemZISelLowering.h:155
llvm::SystemZTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: SystemZISelLowering.cpp:1172
llvm::SystemZVectorConstantInfo::VecVT
MVT VecVT
Definition: SystemZISelLowering.h:780
llvm::SystemZTargetLowering::LowerOperationWrapper
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
Definition: SystemZISelLowering.cpp:5817
llvm::SystemZISD::POPCNT
@ POPCNT
Definition: SystemZISelLowering.h:89
llvm::SystemZISD::STRV
@ STRV
Definition: SystemZISelLowering.h:357
llvm::InlineAsm::Constraint_T
@ Constraint_T
Definition: InlineAsm.h:266
llvm::SystemZISD::STRICT_VFCMPES
@ STRICT_VFCMPES
Definition: SystemZISelLowering.h:299
llvm::SystemZISD::BYTE_MASK
@ BYTE_MASK
Definition: SystemZISelLowering.h:163
llvm::SystemZISD::NodeType
NodeType
Definition: SystemZISelLowering.h:26
llvm::SystemZISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Definition: SystemZISelLowering.h:342
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::SystemZTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Determine if the target supports unaligned memory accesses.
Definition: SystemZISelLowering.cpp:864