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SystemZISelLowering.h
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1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 
17 #include "SystemZ.h"
18 #include "SystemZInstrInfo.h"
22 
23 namespace llvm {
24 namespace SystemZISD {
25 enum NodeType : unsigned {
27 
28  // Return with a flag operand. Operand 0 is the chain operand.
30 
31  // Calls a function. Operand 0 is the chain operand and operand 1
32  // is the target address. The arguments start at operand 2.
33  // There is an optional glue operand at the end.
36 
37  // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38  // (The call target is implicitly __tls_get_offset.)
41 
42  // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43  // accesses (LARL). Operand 0 is the address.
45 
46  // Used in cases where an offset is applied to a TargetGlobalAddress.
47  // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48  // PCREL_WRAPPER for an anchor point. This is used so that we can
49  // cheaply refer to either the full address or the anchor point
50  // as a register base.
52 
53  // Integer comparisons. There are three operands: the two values
54  // to compare, and an integer of type SystemZICMP.
56 
57  // Floating-point comparisons. The two operands are the values to compare.
59 
60  // Test under mask. The first operand is ANDed with the second operand
61  // and the condition codes are set on the result. The third operand is
62  // a boolean that is true if the condition codes need to distinguish
63  // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
64  // register forms do but the memory forms don't).
65  TM,
66 
67  // Branches if a condition is true. Operand 0 is the chain operand;
68  // operand 1 is the 4-bit condition-code mask, with bit N in
69  // big-endian order meaning "branch if CC=N"; operand 2 is the
70  // target block and operand 3 is the flag operand.
72 
73  // Selects between operand 0 and operand 1. Operand 2 is the
74  // mask of condition-code values for which operand 0 should be
75  // chosen over operand 1; it has the same form as BR_CCMASK.
76  // Operand 3 is the flag operand.
78 
79  // Evaluates to the gap between the stack pointer and the
80  // base of the dynamically-allocatable area.
82 
83  // For allocating stack space when using stack clash protector.
84  // Allocation is performed by block, and each block is probed.
86 
87  // Count number of bits set in operand 0 per byte.
89 
90  // Wrappers around the ISD opcodes of the same name. The output is GR128.
91  // Input operands may be GR64 or GR32, depending on the instruction.
96 
97  // Add/subtract with overflow/carry. These have the same operands as
98  // the corresponding standard operations, except with the carry flag
99  // replaced by a condition code value.
101 
102  // Set the condition code from a boolean value in operand 0.
103  // Operand 1 is a mask of all condition-code values that may result of this
104  // operation, operand 2 is a mask of condition-code values that may result
105  // if the boolean is true.
106  // Note that this operation is always optimized away, we will never
107  // generate any code for it.
109 
110  // Use a series of MVCs to copy bytes from one memory location to another.
111  // The operands are:
112  // - the target address
113  // - the source address
114  // - the constant length
115  //
116  // This isn't a memory opcode because we'd need to attach two
117  // MachineMemOperands rather than one.
119 
120  // Similar to MVC, but for logic operations (AND, OR, XOR).
121  NC,
122  OC,
123  XC,
124 
125  // Use CLC to compare two blocks of memory, with the same comments
126  // as for MVC.
128 
129  // Use MVC to set a block of memory after storing the first byte.
131 
132  // Use an MVST-based sequence to implement stpcpy().
134 
135  // Use a CLST-based sequence to implement strcmp(). The two input operands
136  // are the addresses of the strings to compare.
138 
139  // Use an SRST-based sequence to search a block of memory. The first
140  // operand is the end address, the second is the start, and the third
141  // is the character to search for. CC is set to 1 on success and 2
142  // on failure.
144 
145  // Store the CC value in bits 29 and 28 of an integer.
147 
148  // Compiler barrier only; generate a no-op.
150 
151  // Transaction begin. The first operand is the chain, the second
152  // the TDB pointer, and the third the immediate control field.
153  // Returns CC value and chain.
156 
157  // Transaction end. Just the chain operand. Returns CC value and chain.
159 
160  // Create a vector constant by filling byte N of the result with bit
161  // 15-N of the single operand.
163 
164  // Create a vector constant by replicating an element-sized RISBG-style mask.
165  // The first operand specifies the starting set bit and the second operand
166  // specifies the ending set bit. Both operands count from the MSB of the
167  // element.
169 
170  // Replicate a GPR scalar value into all elements of a vector.
172 
173  // Create a vector from two i64 GPRs.
175 
176  // Replicate one element of a vector into all elements. The first operand
177  // is the vector and the second is the index of the element to replicate.
179 
180  // Interleave elements from the high half of operand 0 and the high half
181  // of operand 1.
183 
184  // Likewise for the low halves.
186 
187  // Concatenate the vectors in the first two operands, shift them left
188  // by the third operand, and take the first half of the result.
190 
191  // Take one element of the first v2i64 operand and the one element of
192  // the second v2i64 operand and concatenate them to form a v2i64 result.
193  // The third operand is a 4-bit value of the form 0A0B, where A and B
194  // are the element selectors for the first operand and second operands
195  // respectively.
197 
198  // Perform a general vector permute on vector operands 0 and 1.
199  // Each byte of operand 2 controls the corresponding byte of the result,
200  // in the same way as a byte-level VECTOR_SHUFFLE mask.
202 
203  // Pack vector operands 0 and 1 into a single vector with half-sized elements.
205 
206  // Likewise, but saturate the result and set CC. PACKS_CC does signed
207  // saturation and PACKLS_CC does unsigned saturation.
210 
211  // Unpack the first half of vector operand 0 into double-sized elements.
212  // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
215 
216  // Likewise for the second half.
219 
220  // Shift each element of vector operand 0 by the number of bits specified
221  // by scalar operand 1.
225 
226  // For each element of the output type, sum across all sub-elements of
227  // operand 0 belonging to the corresponding element, and add in the
228  // rightmost sub-element of the corresponding element of operand 1.
230 
231  // Compare integer vector operands 0 and 1 to produce the usual 0/-1
232  // vector result. VICMPE is for equality, VICMPH for "signed greater than"
233  // and VICMPHL for "unsigned greater than".
237 
238  // Likewise, but also set the condition codes on the result.
242 
243  // Compare floating-point vector operands 0 and 1 to produce the usual 0/-1
244  // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
245  // greater than" and VFCMPHE for "ordered and greater than or equal to".
249 
250  // Likewise, but also set the condition codes on the result.
254 
255  // Test floating-point data class for vectors.
257 
258  // Extend the even f32 elements of vector operand 0 to produce a vector
259  // of f64 elements.
261 
262  // Round the f64 elements of vector operand 0 to f32s and store them in the
263  // even elements of the result.
265 
266  // AND the two vector operands together and set CC based on the result.
268 
269  // String operations that set CC as a side-effect.
281 
282  // Test Data Class.
283  //
284  // Operand 0: the value to test
285  // Operand 1: the bit mask
287 
288  // Strict variants of scalar floating-point comparisons.
289  // Quiet and signaling versions.
292 
293  // Strict variants of vector floating-point comparisons.
294  // Quiet and signaling versions.
301 
302  // Strict variants of VEXTEND and VROUND.
305 
306  // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
307  // ATOMIC_LOAD_<op>.
308  //
309  // Operand 0: the address of the containing 32-bit-aligned field
310  // Operand 1: the second operand of <op>, in the high bits of an i32
311  // for everything except ATOMIC_SWAPW
312  // Operand 2: how many bits to rotate the i32 left to bring the first
313  // operand into the high bits
314  // Operand 3: the negative of operand 2, for rotating the other way
315  // Operand 4: the width of the field in bits (8 or 16)
327 
328  // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
329  //
330  // Operand 0: the address of the containing 32-bit-aligned field
331  // Operand 1: the compare value, in the low bits of an i32
332  // Operand 2: the swap value, in the low bits of an i32
333  // Operand 3: how many bits to rotate the i32 left to bring the first
334  // operand into the high bits
335  // Operand 4: the negative of operand 2, for rotating the other way
336  // Operand 5: the width of the field in bits (8 or 16)
338 
339  // Atomic compare-and-swap returning CC value.
340  // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
342 
343  // 128-bit atomic load.
344  // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr)
346 
347  // 128-bit atomic store.
348  // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr)
350 
351  // 128-bit atomic compare-and-swap.
352  // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
354 
355  // Byte swapping load/store. Same operands as regular load/store.
357 
358  // Element swapping load/store. Same operands as regular load/store.
360 
361  // Prefetch from the second operand using the 4-bit control code in
362  // the first operand. The code is 1 for a load prefetch and 2 for
363  // a store prefetch.
365 };
366 
367 // Return true if OPCODE is some kind of PC-relative address.
368 inline bool isPCREL(unsigned Opcode) {
369  return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
370 }
371 } // end namespace SystemZISD
372 
373 namespace SystemZICMP {
374 // Describes whether an integer comparison needs to be signed or unsigned,
375 // or whether either type is OK.
376 enum {
380 };
381 } // end namespace SystemZICMP
382 
383 class SystemZSubtarget;
384 
386 public:
387  explicit SystemZTargetLowering(const TargetMachine &TM,
388  const SystemZSubtarget &STI);
389 
390  bool useSoftFloat() const override;
391 
392  // Override TargetLowering.
393  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
394  return MVT::i32;
395  }
396  MVT getVectorIdxTy(const DataLayout &DL) const override {
397  // Only the lower 12 bits of an element index are used, so we don't
398  // want to clobber the upper 32 bits of a GPR unnecessarily.
399  return MVT::i32;
400  }
402  const override {
403  // Widen subvectors to the full width rather than promoting integer
404  // elements. This is better because:
405  //
406  // (a) it means that we can handle the ABI for passing and returning
407  // sub-128 vectors without having to handle them as legal types.
408  //
409  // (b) we don't have instructions to extend on load and truncate on store,
410  // so promoting the integers is less efficient.
411  //
412  // (c) there are no multiplication instructions for the widest integer
413  // type (v2i64).
414  if (VT.getScalarSizeInBits() % 8 == 0)
415  return TypeWidenVector;
417  }
418  unsigned
420  Optional<MVT> RegisterVT) const override {
421  // i128 inline assembly operand.
422  if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped)
423  return 1;
425  }
426  bool isCheapToSpeculateCtlz() const override { return true; }
427  bool preferZeroCompareBranch() const override { return true; }
428  bool hasBitPreservingFPLogic(EVT VT) const override {
429  EVT ScVT = VT.getScalarType();
430  return ScVT == MVT::f32 || ScVT == MVT::f64 || ScVT == MVT::f128;
431  }
432  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override {
433  ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1));
434  return Mask && Mask->getValue().isIntN(16);
435  }
436  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
437  return VT.isScalarInteger();
438  }
440  EVT) const override;
442  EVT VT) const override;
443  bool isFPImmLegal(const APFloat &Imm, EVT VT,
444  bool ForCodeSize) const override;
445  bool ShouldShrinkFPConstant(EVT VT) const override {
446  // Do not shrink 64-bit FP constpool entries since LDEB is slower than
447  // LD, and having the full constant in memory enables reg/mem opcodes.
448  return VT != MVT::f64;
449  }
450  bool hasInlineStackProbe(MachineFunction &MF) const override;
451  bool isLegalICmpImmediate(int64_t Imm) const override;
452  bool isLegalAddImmediate(int64_t Imm) const override;
453  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
454  unsigned AS,
455  Instruction *I = nullptr) const override;
456  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
458  bool *Fast) const override;
459  bool
460  findOptimalMemOpLowering(std::vector<EVT> &MemOps, unsigned Limit,
461  const MemOp &Op, unsigned DstAS, unsigned SrcAS,
462  const AttributeList &FuncAttributes) const override;
464  const AttributeList &FuncAttributes) const override;
465  bool isTruncateFree(Type *, Type *) const override;
466  bool isTruncateFree(EVT, EVT) const override;
467 
468  bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
469  bool MathUsed) const override {
470  // Form add and sub with overflow intrinsics regardless of any extra
471  // users of the math result.
472  return VT == MVT::i32 || VT == MVT::i64;
473  }
474 
475  bool shouldConsiderGEPOffsetSplit() const override { return true; }
476 
477  const char *getTargetNodeName(unsigned Opcode) const override;
478  std::pair<unsigned, const TargetRegisterClass *>
480  StringRef Constraint, MVT VT) const override;
482  getConstraintType(StringRef Constraint) const override;
484  getSingleConstraintMatchWeight(AsmOperandInfo &info,
485  const char *constraint) const override;
487  std::string &Constraint,
488  std::vector<SDValue> &Ops,
489  SelectionDAG &DAG) const override;
490 
491  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
492  if (ConstraintCode.size() == 1) {
493  switch(ConstraintCode[0]) {
494  default:
495  break;
496  case 'o':
498  case 'Q':
500  case 'R':
502  case 'S':
504  case 'T':
506  }
507  } else if (ConstraintCode.size() == 2 && ConstraintCode[0] == 'Z') {
508  switch (ConstraintCode[1]) {
509  default:
510  break;
511  case 'Q':
513  case 'R':
515  case 'S':
517  case 'T':
519  }
520  }
521  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
522  }
523 
524  Register getRegisterByName(const char *RegName, LLT VT,
525  const MachineFunction &MF) const override;
526 
527  /// If a physical register, this returns the register that receives the
528  /// exception address on entry to an EH pad.
529  Register
530  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
531  return SystemZ::R6D;
532  }
533 
534  /// If a physical register, this returns the register that receives the
535  /// exception typeid on entry to a landing pad.
536  Register
537  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
538  return SystemZ::R7D;
539  }
540 
541  /// Override to support customized stack guard loading.
542  bool useLoadStackGuardNode() const override {
543  return true;
544  }
545  void insertSSPDeclarations(Module &M) const override {
546  }
547 
550  MachineBasicBlock *BB) const override;
551  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
553  SelectionDAG &DAG) const override;
555  SelectionDAG &DAG) const override;
556  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
557  bool allowTruncateForTailCall(Type *, Type *) const override;
558  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
560  SDValue Val, SDValue *Parts,
561  unsigned NumParts, MVT PartVT,
562  Optional<CallingConv::ID> CC) const override;
563  SDValue
565  const SDValue *Parts, unsigned NumParts,
566  MVT PartVT, EVT ValueVT,
567  Optional<CallingConv::ID> CC) const override;
569  bool isVarArg,
571  const SDLoc &DL, SelectionDAG &DAG,
572  SmallVectorImpl<SDValue> &InVals) const override;
573  SDValue LowerCall(CallLoweringInfo &CLI,
574  SmallVectorImpl<SDValue> &InVals) const override;
575 
576  std::pair<SDValue, SDValue>
577  makeExternalCall(SDValue Chain, SelectionDAG &DAG, const char *CalleeName,
578  EVT RetVT, ArrayRef<SDValue> Ops, CallingConv::ID CallConv,
579  bool IsSigned, SDLoc DL, bool DoesNotReturn,
580  bool IsReturnValueUsed) const;
581 
583  bool isVarArg,
585  LLVMContext &Context) const override;
586  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
588  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
589  SelectionDAG &DAG) const override;
590  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
591 
592  /// Determine which of the bits specified in Mask are known to be either
593  /// zero or one and return them in the KnownZero/KnownOne bitsets.
595  KnownBits &Known,
596  const APInt &DemandedElts,
597  const SelectionDAG &DAG,
598  unsigned Depth = 0) const override;
599 
600  /// Determine the number of bits in the operation that are sign bits.
602  const APInt &DemandedElts,
603  const SelectionDAG &DAG,
604  unsigned Depth) const override;
605 
607  return ISD::ANY_EXTEND;
608  }
610  return ISD::ZERO_EXTEND;
611  }
612 
613  bool supportSwiftError() const override {
614  return true;
615  }
616 
617  unsigned getStackProbeSize(MachineFunction &MF) const;
618 
619 private:
620  const SystemZSubtarget &Subtarget;
621 
622  // Implement LowerOperation for individual opcodes.
623  SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
624  const SDLoc &DL, EVT VT,
625  SDValue CmpOp0, SDValue CmpOp1, SDValue Chain) const;
626  SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL,
627  EVT VT, ISD::CondCode CC,
628  SDValue CmpOp0, SDValue CmpOp1,
629  SDValue Chain = SDValue(),
630  bool IsSignaling = false) const;
631  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
632  SDValue lowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG,
633  bool IsSignaling) const;
634  SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
635  SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
636  SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
637  SelectionDAG &DAG) const;
638  SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
639  SelectionDAG &DAG, unsigned Opcode,
640  SDValue GOTOffset) const;
641  SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
642  SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
643  SelectionDAG &DAG) const;
644  SDValue lowerBlockAddress(BlockAddressSDNode *Node,
645  SelectionDAG &DAG) const;
646  SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
647  SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
648  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
649  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
650  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
651  SDValue lowerVASTART_ELF(SDValue Op, SelectionDAG &DAG) const;
652  SDValue lowerVASTART_XPLINK(SDValue Op, SelectionDAG &DAG) const;
653  SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
654  SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
655  SDValue lowerDYNAMIC_STACKALLOC_ELF(SDValue Op, SelectionDAG &DAG) const;
656  SDValue lowerDYNAMIC_STACKALLOC_XPLINK(SDValue Op, SelectionDAG &DAG) const;
657  SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
658  SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
659  SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
660  SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
661  SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
662  SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const;
663  SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) const;
664  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
665  SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
666  SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
667  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
668  SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
669  SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
670  SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
671  unsigned Opcode) const;
672  SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
673  SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
674  SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
675  SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
676  SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
677  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
678  SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
679  bool isVectorElementLoad(SDValue Op) const;
680  SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
681  SmallVectorImpl<SDValue> &Elems) const;
682  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
683  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
684  SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
685  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
686  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
687  SDValue lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
688  SDValue lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
689  SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
690  SDValue lowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
691 
692  bool canTreatAsByteVector(EVT VT) const;
693  SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
694  unsigned Index, DAGCombinerInfo &DCI,
695  bool Force) const;
696  SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
697  DAGCombinerInfo &DCI) const;
698  SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
699  SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
700  SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;
701  SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
702  bool canLoadStoreByteSwapped(EVT VT) const;
703  SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const;
704  SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
705  SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const;
706  SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
707  SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
708  SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
709  SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
710  SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const;
711  SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
712  SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
713  SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
714  SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
715  SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const;
716  SDValue combineINTRINSIC(SDNode *N, DAGCombinerInfo &DCI) const;
717 
718  SDValue unwrapAddress(SDValue N) const override;
719 
720  // If the last instruction before MBBI in MBB was some form of COMPARE,
721  // try to replace it with a COMPARE AND BRANCH just before MBBI.
722  // CCMask and Target are the BRC-like operands for the branch.
723  // Return true if the change was made.
724  bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
726  unsigned CCMask,
727  MachineBasicBlock *Target) const;
728 
729  // Implement EmitInstrWithCustomInserter for individual operation types.
730  MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
732  unsigned StoreOpcode, unsigned STOCOpcode,
733  bool Invert) const;
734  MachineBasicBlock *emitPair128(MachineInstr &MI,
735  MachineBasicBlock *MBB) const;
737  bool ClearEven) const;
738  MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
740  unsigned BinOpcode, unsigned BitSize,
741  bool Invert = false) const;
742  MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
744  unsigned CompareOpcode,
745  unsigned KeepOldMask,
746  unsigned BitSize) const;
747  MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
748  MachineBasicBlock *BB) const;
749  MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
750  unsigned Opcode,
751  bool IsMemset = false) const;
752  MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
753  unsigned Opcode) const;
754  MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
756  unsigned Opcode, bool NoFloat) const;
757  MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
759  unsigned Opcode) const;
760  MachineBasicBlock *emitProbedAlloca(MachineInstr &MI,
761  MachineBasicBlock *MBB) const;
762 
763  SDValue getBackchainAddress(SDValue SP, SelectionDAG &DAG) const;
764 
766  getTargetMMOFlags(const Instruction &I) const override;
767  const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
768 };
769 
771 private:
772  APInt IntBits; // The 128 bits as an integer.
773  APInt SplatBits; // Smallest splat value.
774  APInt SplatUndef; // Bits correspoding to undef operands of the BVN.
775  unsigned SplatBitSize = 0;
776  bool isFP128 = false;
777 public:
778  unsigned Opcode = 0;
783  : SystemZVectorConstantInfo(FPImm.bitcastToAPInt()) {
784  isFP128 = (&FPImm.getSemantics() == &APFloat::IEEEquad());
785  }
787  bool isVectorConstantLegal(const SystemZSubtarget &Subtarget);
788 };
789 
790 } // end namespace llvm
791 
792 #endif
llvm::TargetLoweringBase::getPreferredVectorAction
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Definition: TargetLowering.h:460
llvm::InlineAsm::Constraint_T
@ Constraint_T
Definition: InlineAsm.h:262
llvm::SystemZTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: SystemZISelLowering.cpp:5897
llvm::SystemZISD::UADDO
@ UADDO
Definition: SystemZISelLowering.h:100
llvm::SystemZISD::SELECT_CCMASK
@ SELECT_CCMASK
Definition: SystemZISelLowering.h:77
llvm::SystemZTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: SystemZISelLowering.cpp:1279
llvm::SystemZISD::SDIVREM
@ SDIVREM
Definition: SystemZISelLowering.h:94
llvm::SystemZISD::ATOMIC_LOADW_SUB
@ ATOMIC_LOADW_SUB
Definition: SystemZISelLowering.h:318
llvm::SystemZISD::SUBCARRY
@ SUBCARRY
Definition: SystemZISelLowering.h:100
llvm::SystemZTargetLowering::makeExternalCall
std::pair< SDValue, SDValue > makeExternalCall(SDValue Chain, SelectionDAG &DAG, const char *CalleeName, EVT RetVT, ArrayRef< SDValue > Ops, CallingConv::ID CallConv, bool IsSigned, SDLoc DL, bool DoesNotReturn, bool IsReturnValueUsed) const
Definition: SystemZISelLowering.cpp:1884
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::SystemZISD::ATOMIC_LOAD_128
@ ATOMIC_LOAD_128
Definition: SystemZISelLowering.h:345
llvm::SystemZISD::USUBO
@ USUBO
Definition: SystemZISelLowering.h:100
llvm::SystemZISD::RET_FLAG
@ RET_FLAG
Definition: SystemZISelLowering.h:29
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:149
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::SystemZTargetLowering::isTruncateFree
bool isTruncateFree(Type *, Type *) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: SystemZISelLowering.cpp:1021
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:259
llvm::SystemZTargetLowering::getNumRegisters
unsigned getNumRegisters(LLVMContext &Context, EVT VT, Optional< MVT > RegisterVT) const override
Return the number of registers that this ValueType will eventually require.
Definition: SystemZISelLowering.h:419
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1090
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::SystemZTargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Definition: SystemZISelLowering.cpp:1016
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4419
llvm::SystemZTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT) const override
Return the ValueType of the result of SETCC operations.
Definition: SystemZISelLowering.cpp:691
llvm::SystemZISD::ICMP
@ ICMP
Definition: SystemZISelLowering.h:55
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::SystemZTargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: SystemZISelLowering.cpp:1342
llvm::SystemZISD::GET_CCMASK
@ GET_CCMASK
Definition: SystemZISelLowering.h:108
llvm::MVT::i128
@ i128
Definition: MachineValueType.h:50
llvm::SystemZISD::VICMPH
@ VICMPH
Definition: SystemZISelLowering.h:235
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
llvm::SystemZTargetLowering
Definition: SystemZISelLowering.h:385
llvm::SmallVector< unsigned, 2 >
llvm::SystemZISD::PACKLS_CC
@ PACKLS_CC
Definition: SystemZISelLowering.h:209
llvm::SystemZISD::CLC
@ CLC
Definition: SystemZISelLowering.h:127
llvm::SystemZTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: SystemZISelLowering.cpp:5688
llvm::SystemZISD::ATOMIC_CMP_SWAPW
@ ATOMIC_CMP_SWAPW
Definition: SystemZISelLowering.h:337
llvm::SystemZISD::VICMPHLS
@ VICMPHLS
Definition: SystemZISelLowering.h:241
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::SystemZISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: SystemZISelLowering.h:26
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
MachineBasicBlock.h
llvm::SystemZISD::ROTATE_MASK
@ ROTATE_MASK
Definition: SystemZISelLowering.h:168
llvm::SystemZISD::VFENEZ_CC
@ VFENEZ_CC
Definition: SystemZISelLowering.h:275
llvm::MemOp
Definition: TargetLowering.h:111
llvm::SystemZISD::VFAE_CC
@ VFAE_CC
Definition: SystemZISelLowering.h:270
llvm::SystemZISD::VSTRS_CC
@ VSTRS_CC
Definition: SystemZISelLowering.h:279
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::SystemZTargetLowering::allowTruncateForTailCall
bool allowTruncateForTailCall(Type *, Type *) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
Definition: SystemZISelLowering.cpp:1337
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::SystemZISD::PREFETCH
@ PREFETCH
Definition: SystemZISelLowering.h:364
llvm::SystemZTargetLowering::LowerCall
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: SystemZISelLowering.cpp:1658
llvm::AttributeList
Definition: Attributes.h:425
llvm::SystemZISD::VSTER
@ VSTER
Definition: SystemZISelLowering.h:359
llvm::SystemZTargetLowering::SystemZTargetLowering
SystemZTargetLowering(const TargetMachine &TM, const SystemZSubtarget &STI)
Definition: SystemZISelLowering.cpp:80
llvm::Optional
Definition: APInt.h:33
llvm::SystemZTargetLowering::preferZeroCompareBranch
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
Definition: SystemZISelLowering.h:427
llvm::SystemZTargetLowering::getExtendForAtomicCmpSwapArg
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
Definition: SystemZISelLowering.h:609
llvm::SystemZTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: SystemZISelLowering.h:436
llvm::SystemZTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: SystemZISelLowering.cpp:1263
llvm::SystemZISD::STRICT_VEXTEND
@ STRICT_VEXTEND
Definition: SystemZISelLowering.h:303
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:848
llvm::SystemZTargetLowering::getStackProbeSize
unsigned getStackProbeSize(MachineFunction &MF) const
Definition: SystemZISelLowering.cpp:7441
llvm::InlineAsm::Constraint_ZR
@ Constraint_ZR
Definition: InlineAsm.h:278
llvm::SystemZTargetLowering::getConstraintType
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: SystemZISelLowering.cpp:1042
llvm::SystemZTargetLowering::getSingleConstraintMatchWeight
TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: SystemZISelLowering.cpp:1086
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2165
llvm::SystemZISD::VICMPHL
@ VICMPHL
Definition: SystemZISelLowering.h:236
SelectionDAG.h
llvm::APFloat::getSemantics
const fltSemantics & getSemantics() const
Definition: APFloat.h:1223
llvm::SystemZISD::VSHL_BY_SCALAR
@ VSHL_BY_SCALAR
Definition: SystemZISelLowering.h:222
llvm::SystemZISD::PERMUTE_DWORDS
@ PERMUTE_DWORDS
Definition: SystemZISelLowering.h:196
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::SystemZTargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: SystemZISelLowering.h:428
llvm::SystemZTargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: SystemZISelLowering.h:545
llvm::SystemZISD::TEND
@ TEND
Definition: SystemZISelLowering.h:158
llvm::SystemZTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: SystemZISelLowering.cpp:1937
llvm::APFloatBase::IEEEquad
static const fltSemantics & IEEEquad() LLVM_READNONE
Definition: APFloat.cpp:176
llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
Definition: SystemZISelLowering.cpp:7386
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::InlineAsm::Constraint_o
@ Constraint_o
Definition: InlineAsm.h:256
llvm::SystemZISD::ATOMIC_SWAPW
@ ATOMIC_SWAPW
Definition: SystemZISelLowering.h:316
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::InlineAsm::Constraint_ZS
@ Constraint_ZS
Definition: InlineAsm.h:279
TargetLowering.h
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::SystemZTargetLowering::getVectorIdxTy
MVT getVectorIdxTy(const DataLayout &DL) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
Definition: SystemZISelLowering.h:396
llvm::SystemZISD::ATOMIC_LOADW_UMAX
@ ATOMIC_LOADW_UMAX
Definition: SystemZISelLowering.h:326
llvm::SystemZISD::BR_CCMASK
@ BR_CCMASK
Definition: SystemZISelLowering.h:71
llvm::SystemZISD::UNPACK_HIGH
@ UNPACK_HIGH
Definition: SystemZISelLowering.h:213
llvm::SystemZISD::ATOMIC_LOADW_ADD
@ ATOMIC_LOADW_ADD
Definition: SystemZISelLowering.h:317
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
SystemZInstrInfo.h
llvm::SystemZISD::TLS_LDCALL
@ TLS_LDCALL
Definition: SystemZISelLowering.h:40
llvm::SystemZISD::VSRA_BY_SCALAR
@ VSRA_BY_SCALAR
Definition: SystemZISelLowering.h:224
llvm::SystemZISD::TLS_GDCALL
@ TLS_GDCALL
Definition: SystemZISelLowering.h:39
llvm::SystemZISD::VFEEZ_CC
@ VFEEZ_CC
Definition: SystemZISelLowering.h:273
llvm::SystemZISD::ATOMIC_LOADW_UMIN
@ ATOMIC_LOADW_UMIN
Definition: SystemZISelLowering.h:325
llvm::SystemZTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: SystemZISelLowering.h:530
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:58
llvm::SystemZTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: SystemZISelLowering.cpp:853
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1837
llvm::SystemZISD::SIBCALL
@ SIBCALL
Definition: SystemZISelLowering.h:35
llvm::SystemZISD::JOIN_DWORDS
@ JOIN_DWORDS
Definition: SystemZISelLowering.h:174
llvm::SystemZISD::VSTRCZ_CC
@ VSTRCZ_CC
Definition: SystemZISelLowering.h:278
llvm::SystemZTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: SystemZISelLowering.cpp:8759
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3412
llvm::SystemZISD::VSRL_BY_SCALAR
@ VSRL_BY_SCALAR
Definition: SystemZISelLowering.h:223
llvm::SystemZTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: SystemZISelLowering.h:606
llvm::MVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: MachineValueType.h:1091
llvm::SystemZISD::UNPACKL_HIGH
@ UNPACKL_HIGH
Definition: SystemZISelLowering.h:214
llvm::SystemZISD::STRICT_VFCMPHES
@ STRICT_VFCMPHES
Definition: SystemZISelLowering.h:300
llvm::SystemZISD::VFCMPHES
@ VFCMPHES
Definition: SystemZISelLowering.h:253
llvm::SystemZISD::CALL
@ CALL
Definition: SystemZISelLowering.h:34
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::SystemZISD::ATOMIC_LOADW_AND
@ ATOMIC_LOADW_AND
Definition: SystemZISelLowering.h:319
llvm::SystemZTargetLowering::isMaskAndCmp0FoldingBeneficial
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
Definition: SystemZISelLowering.h:432
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::Instruction
Definition: Instruction.h:42
llvm::SystemZVectorConstantInfo::isVectorConstantLegal
bool isVectorConstantLegal(const SystemZSubtarget &Subtarget)
Definition: SystemZISelLowering.cpp:720
llvm::SystemZISD::STRCMP
@ STRCMP
Definition: SystemZISelLowering.h:137
llvm::SystemZISD::STRICT_VROUND
@ STRICT_VROUND
Definition: SystemZISelLowering.h:304
llvm::SystemZISD::VFEE_CC
@ VFEE_CC
Definition: SystemZISelLowering.h:272
SystemZ.h
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:213
llvm::SystemZISD::VSUM
@ VSUM
Definition: SystemZISelLowering.h:229
llvm::SystemZICMP::SignedOnly
@ SignedOnly
Definition: SystemZISelLowering.h:379
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SystemZISD::FCMP
@ FCMP
Definition: SystemZISelLowering.h:58
llvm::SystemZTargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: SystemZISelLowering.h:613
llvm::SystemZISD::VFCMPE
@ VFCMPE
Definition: SystemZISelLowering.h:246
llvm::SystemZISD::UDIVREM
@ UDIVREM
Definition: SystemZISelLowering.h:95
llvm::SystemZISD::SSUBO
@ SSUBO
Definition: SystemZISelLowering.h:100
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::SystemZISD::VTM
@ VTM
Definition: SystemZISelLowering.h:267
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::SystemZTargetLowering::useSoftFloat
bool useSoftFloat() const override
Definition: SystemZISelLowering.cpp:687
llvm::SystemZISD::ATOMIC_LOADW_NAND
@ ATOMIC_LOADW_NAND
Definition: SystemZISelLowering.h:322
llvm::SystemZISD::SMUL_LOHI
@ SMUL_LOHI
Definition: SystemZISelLowering.h:92
llvm::SystemZISD::VFCMPHE
@ VFCMPHE
Definition: SystemZISelLowering.h:248
llvm::SystemZVectorConstantInfo::Opcode
unsigned Opcode
Definition: SystemZISelLowering.h:778
llvm::SystemZISD::UMUL_LOHI
@ UMUL_LOHI
Definition: SystemZISelLowering.h:93
llvm::SystemZTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: SystemZISelLowering.cpp:7120
llvm::InlineAsm::Constraint_ZT
@ Constraint_ZT
Definition: InlineAsm.h:280
llvm::SystemZISD::TBEGIN_NOFLOAT
@ TBEGIN_NOFLOAT
Definition: SystemZISelLowering.h:155
llvm::SystemZTargetLowering::findOptimalMemOpLowering
bool findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const override
Determines the optimal series of memory ops to replace the memset / memcpy.
Definition: SystemZISelLowering.cpp:997
llvm::APFloat
Definition: APFloat.h:701
llvm::SystemZISD::TDC
@ TDC
Definition: SystemZISelLowering.h:286
llvm::SystemZTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: SystemZISelLowering.cpp:7268
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::SystemZISD::VICMPHS
@ VICMPHS
Definition: SystemZISelLowering.h:240
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::SystemZVectorConstantInfo
Definition: SystemZISelLowering.h:770
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1300
llvm::SystemZISD::MVC
@ MVC
Definition: SystemZISelLowering.h:118
llvm::SystemZISD::SHL_DOUBLE
@ SHL_DOUBLE
Definition: SystemZISelLowering.h:189
llvm::SystemZISD::MERGE_HIGH
@ MERGE_HIGH
Definition: SystemZISelLowering.h:182
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::SystemZTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
Definition: SystemZISelLowering.cpp:863
llvm::SystemZISD::LRV
@ LRV
Definition: SystemZISelLowering.h:356
llvm::SystemZISD::XC
@ XC
Definition: SystemZISelLowering.h:123
llvm::SystemZTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: SystemZISelLowering.cpp:858
llvm::SystemZTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: SystemZISelLowering.cpp:1917
llvm::InlineAsm::Constraint_R
@ Constraint_R
Definition: InlineAsm.h:260
llvm::SystemZTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: SystemZISelLowering.h:537
llvm::SystemZISD::VEXTEND
@ VEXTEND
Definition: SystemZISelLowering.h:260
llvm::SystemZISD::STRICT_VFCMPHS
@ STRICT_VFCMPHS
Definition: SystemZISelLowering.h:299
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::SystemZISD::VSTRC_CC
@ VSTRC_CC
Definition: SystemZISelLowering.h:277
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::SystemZISD::OC
@ OC
Definition: SystemZISelLowering.h:122
llvm::SystemZISD::SEARCH_STRING
@ SEARCH_STRING
Definition: SystemZISelLowering.h:143
llvm::SystemZTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: SystemZISelLowering.h:426
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1411
llvm::SystemZVectorConstantInfo::SystemZVectorConstantInfo
SystemZVectorConstantInfo(APFloat FPImm)
Definition: SystemZISelLowering.h:782
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::SystemZISD::VFCMPES
@ VFCMPES
Definition: SystemZISelLowering.h:251
llvm::SystemZISD::VFCMPH
@ VFCMPH
Definition: SystemZISelLowering.h:247
llvm::SystemZSubtarget
Definition: SystemZSubtarget.h:33
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::SystemZISD::ATOMIC_LOADW_XOR
@ ATOMIC_LOADW_XOR
Definition: SystemZISelLowering.h:321
llvm::SystemZISD::VFCMPHS
@ VFCMPHS
Definition: SystemZISelLowering.h:252
llvm::SystemZISD::STRICT_VFCMPH
@ STRICT_VFCMPH
Definition: SystemZISelLowering.h:296
info
lazy value info
Definition: LazyValueInfo.cpp:58
llvm::SystemZTargetLowering::hasInlineStackProbe
bool hasInlineStackProbe(MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
Definition: SystemZISelLowering.cpp:845
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1858
llvm::SystemZISD::MEMSET_MVC
@ MEMSET_MVC
Definition: SystemZISelLowering.h:130
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::BuildVectorSDNode
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Definition: SelectionDAGNodes.h:1963
llvm::SystemZTargetLowering::shouldConsiderGEPOffsetSplit
bool shouldConsiderGEPOffsetSplit() const override
Definition: SystemZISelLowering.h:475
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::SystemZTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: SystemZISelLowering.cpp:970
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SystemZISD::VFENE_CC
@ VFENE_CC
Definition: SystemZISelLowering.h:274
llvm::SystemZTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: SystemZISelLowering.h:491
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::SystemZVectorConstantInfo::SystemZVectorConstantInfo
SystemZVectorConstantInfo(APInt IntImm)
Definition: SystemZISelLowering.cpp:795
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1294
llvm::InlineAsm::Constraint_ZQ
@ Constraint_ZQ
Definition: InlineAsm.h:277
llvm::SystemZISD::REPLICATE
@ REPLICATE
Definition: SystemZISelLowering.h:171
Node
Definition: ItaniumDemangle.h:155
llvm::SystemZTargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: SystemZISelLowering.h:401
llvm::SystemZISD::ATOMIC_LOADW_MIN
@ ATOMIC_LOADW_MIN
Definition: SystemZISelLowering.h:323
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SystemZISD::VROUND
@ VROUND
Definition: SystemZISelLowering.h:264
llvm::SystemZISD::ATOMIC_LOADW_OR
@ ATOMIC_LOADW_OR
Definition: SystemZISelLowering.h:320
llvm::SystemZTargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: SystemZISelLowering.h:393
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonISD::CP
@ CP
Definition: HexagonISelLowering.h:53
llvm::StringRef::size
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
llvm::SystemZISD::STRICT_FCMP
@ STRICT_FCMP
Definition: SystemZISelLowering.h:290
llvm::SystemZISD::SADDO
@ SADDO
Definition: SystemZISelLowering.h:100
llvm::SystemZISD::STRICT_FCMPS
@ STRICT_FCMPS
Definition: SystemZISelLowering.h:291
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1734
llvm::KnownBits
Definition: KnownBits.h:23
llvm::SystemZISD::MEMBARRIER
@ MEMBARRIER
Definition: SystemZISelLowering.h:149
llvm::SystemZISD::PACKS_CC
@ PACKS_CC
Definition: SystemZISelLowering.h:208
llvm::InlineAsm::Constraint_S
@ Constraint_S
Definition: InlineAsm.h:261
uint16_t
llvm::SystemZTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: SystemZISelLowering.cpp:5903
llvm::EVT::getScalarType
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:295
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4429
llvm::SystemZISD::ATOMIC_CMP_SWAP_128
@ ATOMIC_CMP_SWAP_128
Definition: SystemZISelLowering.h:353
llvm::SystemZISD::PROBED_ALLOCA
@ PROBED_ALLOCA
Definition: SystemZISelLowering.h:85
llvm::SystemZISD::VICMPES
@ VICMPES
Definition: SystemZISelLowering.h:239
llvm::SystemZISD::VICMPE
@ VICMPE
Definition: SystemZISelLowering.h:234
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::SystemZISD::PACK
@ PACK
Definition: SystemZISelLowering.h:204
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:205
llvm::SystemZTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: SystemZISelLowering.cpp:835
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::SystemZTargetLowering::ShouldShrinkFPConstant
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Definition: SystemZISelLowering.h:445
llvm::SystemZISD::NC
@ NC
Definition: SystemZISelLowering.h:121
llvm::SystemZISD::PCREL_WRAPPER
@ PCREL_WRAPPER
Definition: SystemZISelLowering.h:44
llvm::SystemZTargetLowering::splitValueIntoRegisterParts
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Definition: SystemZISelLowering.cpp:1447
llvm::SystemZISD::PCREL_OFFSET
@ PCREL_OFFSET
Definition: SystemZISelLowering.h:51
llvm::SystemZISD::VISTR_CC
@ VISTR_CC
Definition: SystemZISelLowering.h:276
llvm::SystemZISD::VFAEZ_CC
@ VFAEZ_CC
Definition: SystemZISelLowering.h:271
llvm::SystemZISD::MERGE_LOW
@ MERGE_LOW
Definition: SystemZISelLowering.h:185
llvm::SystemZTargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
Definition: SystemZISelLowering.h:542
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::SystemZISD::STRICT_VFCMPHE
@ STRICT_VFCMPHE
Definition: SystemZISelLowering.h:297
llvm::SystemZTargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: SystemZISelLowering.h:468
llvm::SystemZISD::UNPACK_LOW
@ UNPACK_LOW
Definition: SystemZISelLowering.h:217
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:60
llvm::SystemZTargetLowering::joinRegisterPartsIntoValue
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
Definition: SystemZISelLowering.cpp:1463
llvm::SystemZISD::VLER
@ VLER
Definition: SystemZISelLowering.h:359
llvm::SystemZISD::ADJDYNALLOC
@ ADJDYNALLOC
Definition: SystemZISelLowering.h:81
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1306
N
#define N
llvm::SystemZISD::ATOMIC_STORE_128
@ ATOMIC_STORE_128
Definition: SystemZISelLowering.h:349
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4521
llvm::SystemZISD::UNPACKL_LOW
@ UNPACKL_LOW
Definition: SystemZISelLowering.h:218
llvm::SystemZISD::VFTCI
@ VFTCI
Definition: SystemZISelLowering.h:256
llvm::SystemZICMP::Any
@ Any
Definition: SystemZISelLowering.h:377
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::MVT::Untyped
@ Untyped
Definition: MachineValueType.h:274
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::SystemZISD::isPCREL
bool isPCREL(unsigned Opcode)
Definition: SystemZISelLowering.h:368
llvm::SystemZISD::ATOMIC_LOADW_MAX
@ ATOMIC_LOADW_MAX
Definition: SystemZISelLowering.h:324
RegName
#define RegName(no)
llvm::TargetLoweringBase::getNumRegisters
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, Optional< MVT > RegisterVT=None) const
Return the number of registers that this ValueType will eventually require.
Definition: TargetLowering.h:1548
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SystemZISD::SPLAT
@ SPLAT
Definition: SystemZISelLowering.h:178
llvm::SystemZISD::STRICT_VFCMPE
@ STRICT_VFCMPE
Definition: SystemZISelLowering.h:295
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1461
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::SystemZISD::STPCPY
@ STPCPY
Definition: SystemZISelLowering.h:133
llvm::SystemZTargetLowering::getScratchRegisters
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition: SystemZISelLowering.cpp:1330
llvm::SystemZISD::ADDCARRY
@ ADDCARRY
Definition: SystemZISelLowering.h:100
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::SystemZTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: SystemZISelLowering.cpp:1476
llvm::SystemZISD::VSTRSZ_CC
@ VSTRSZ_CC
Definition: SystemZISelLowering.h:280
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:57
llvm::SystemZISD::PERMUTE
@ PERMUTE
Definition: SystemZISelLowering.h:201
llvm::SystemZVectorConstantInfo::OpVals
SmallVector< unsigned, 2 > OpVals
Definition: SystemZISelLowering.h:779
llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: SystemZISelLowering.cpp:698
llvm::SystemZISD::IPM
@ IPM
Definition: SystemZISelLowering.h:146
llvm::SystemZISD::TBEGIN
@ TBEGIN
Definition: SystemZISelLowering.h:154
llvm::SystemZTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: SystemZISelLowering.cpp:1171
llvm::SystemZVectorConstantInfo::VecVT
MVT VecVT
Definition: SystemZISelLowering.h:780
llvm::SystemZTargetLowering::LowerOperationWrapper
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
Definition: SystemZISelLowering.cpp:5815
llvm::SystemZISD::POPCNT
@ POPCNT
Definition: SystemZISelLowering.h:88
llvm::SystemZISD::STRV
@ STRV
Definition: SystemZISelLowering.h:356
llvm::SystemZICMP::UnsignedOnly
@ UnsignedOnly
Definition: SystemZISelLowering.h:378
llvm::SystemZISD::STRICT_VFCMPES
@ STRICT_VFCMPES
Definition: SystemZISelLowering.h:298
llvm::SystemZISD::BYTE_MASK
@ BYTE_MASK
Definition: SystemZISelLowering.h:162
llvm::SystemZISD::NodeType
NodeType
Definition: SystemZISelLowering.h:25
llvm::SystemZISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Definition: SystemZISelLowering.h:341
llvm::LLT
Definition: LowLevelTypeImpl.h:39