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SystemZISelLowering.h
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1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 
17 #include "SystemZ.h"
18 #include "SystemZInstrInfo.h"
22 
23 namespace llvm {
24 namespace SystemZISD {
25 enum NodeType : unsigned {
27 
28  // Return with a flag operand. Operand 0 is the chain operand.
30 
31  // Calls a function. Operand 0 is the chain operand and operand 1
32  // is the target address. The arguments start at operand 2.
33  // There is an optional glue operand at the end.
36 
37  // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38  // (The call target is implicitly __tls_get_offset.)
41 
42  // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43  // accesses (LARL). Operand 0 is the address.
45 
46  // Used in cases where an offset is applied to a TargetGlobalAddress.
47  // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48  // PCREL_WRAPPER for an anchor point. This is used so that we can
49  // cheaply refer to either the full address or the anchor point
50  // as a register base.
52 
53  // Integer comparisons. There are three operands: the two values
54  // to compare, and an integer of type SystemZICMP.
56 
57  // Floating-point comparisons. The two operands are the values to compare.
59 
60  // Test under mask. The first operand is ANDed with the second operand
61  // and the condition codes are set on the result. The third operand is
62  // a boolean that is true if the condition codes need to distinguish
63  // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
64  // register forms do but the memory forms don't).
65  TM,
66 
67  // Branches if a condition is true. Operand 0 is the chain operand;
68  // operand 1 is the 4-bit condition-code mask, with bit N in
69  // big-endian order meaning "branch if CC=N"; operand 2 is the
70  // target block and operand 3 is the flag operand.
72 
73  // Selects between operand 0 and operand 1. Operand 2 is the
74  // mask of condition-code values for which operand 0 should be
75  // chosen over operand 1; it has the same form as BR_CCMASK.
76  // Operand 3 is the flag operand.
78 
79  // Evaluates to the gap between the stack pointer and the
80  // base of the dynamically-allocatable area.
82 
83  // For allocating stack space when using stack clash protector.
84  // Allocation is performed by block, and each block is probed.
86 
87  // Count number of bits set in operand 0 per byte.
89 
90  // Wrappers around the ISD opcodes of the same name. The output is GR128.
91  // Input operands may be GR64 or GR32, depending on the instruction.
96 
97  // Add/subtract with overflow/carry. These have the same operands as
98  // the corresponding standard operations, except with the carry flag
99  // replaced by a condition code value.
101 
102  // Set the condition code from a boolean value in operand 0.
103  // Operand 1 is a mask of all condition-code values that may result of this
104  // operation, operand 2 is a mask of condition-code values that may result
105  // if the boolean is true.
106  // Note that this operation is always optimized away, we will never
107  // generate any code for it.
109 
110  // Use a series of MVCs to copy bytes from one memory location to another.
111  // The operands are:
112  // - the target address
113  // - the source address
114  // - the constant length
115  //
116  // This isn't a memory opcode because we'd need to attach two
117  // MachineMemOperands rather than one.
119 
120  // Similar to MVC, but for logic operations (AND, OR, XOR).
121  NC,
122  OC,
123  XC,
124 
125  // Use CLC to compare two blocks of memory, with the same comments
126  // as for MVC.
128 
129  // Use MVC to set a block of memory after storing the first byte.
131 
132  // Use an MVST-based sequence to implement stpcpy().
134 
135  // Use a CLST-based sequence to implement strcmp(). The two input operands
136  // are the addresses of the strings to compare.
138 
139  // Use an SRST-based sequence to search a block of memory. The first
140  // operand is the end address, the second is the start, and the third
141  // is the character to search for. CC is set to 1 on success and 2
142  // on failure.
144 
145  // Store the CC value in bits 29 and 28 of an integer.
147 
148  // Compiler barrier only; generate a no-op.
150 
151  // Transaction begin. The first operand is the chain, the second
152  // the TDB pointer, and the third the immediate control field.
153  // Returns CC value and chain.
156 
157  // Transaction end. Just the chain operand. Returns CC value and chain.
159 
160  // Create a vector constant by filling byte N of the result with bit
161  // 15-N of the single operand.
163 
164  // Create a vector constant by replicating an element-sized RISBG-style mask.
165  // The first operand specifies the starting set bit and the second operand
166  // specifies the ending set bit. Both operands count from the MSB of the
167  // element.
169 
170  // Replicate a GPR scalar value into all elements of a vector.
172 
173  // Create a vector from two i64 GPRs.
175 
176  // Replicate one element of a vector into all elements. The first operand
177  // is the vector and the second is the index of the element to replicate.
179 
180  // Interleave elements from the high half of operand 0 and the high half
181  // of operand 1.
183 
184  // Likewise for the low halves.
186 
187  // Concatenate the vectors in the first two operands, shift them left
188  // by the third operand, and take the first half of the result.
190 
191  // Take one element of the first v2i64 operand and the one element of
192  // the second v2i64 operand and concatenate them to form a v2i64 result.
193  // The third operand is a 4-bit value of the form 0A0B, where A and B
194  // are the element selectors for the first operand and second operands
195  // respectively.
197 
198  // Perform a general vector permute on vector operands 0 and 1.
199  // Each byte of operand 2 controls the corresponding byte of the result,
200  // in the same way as a byte-level VECTOR_SHUFFLE mask.
202 
203  // Pack vector operands 0 and 1 into a single vector with half-sized elements.
205 
206  // Likewise, but saturate the result and set CC. PACKS_CC does signed
207  // saturation and PACKLS_CC does unsigned saturation.
210 
211  // Unpack the first half of vector operand 0 into double-sized elements.
212  // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
215 
216  // Likewise for the second half.
219 
220  // Shift each element of vector operand 0 by the number of bits specified
221  // by scalar operand 1.
225 
226  // For each element of the output type, sum across all sub-elements of
227  // operand 0 belonging to the corresponding element, and add in the
228  // rightmost sub-element of the corresponding element of operand 1.
230 
231  // Compare integer vector operands 0 and 1 to produce the usual 0/-1
232  // vector result. VICMPE is for equality, VICMPH for "signed greater than"
233  // and VICMPHL for "unsigned greater than".
237 
238  // Likewise, but also set the condition codes on the result.
242 
243  // Compare floating-point vector operands 0 and 1 to produce the usual 0/-1
244  // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
245  // greater than" and VFCMPHE for "ordered and greater than or equal to".
249 
250  // Likewise, but also set the condition codes on the result.
254 
255  // Test floating-point data class for vectors.
257 
258  // Extend the even f32 elements of vector operand 0 to produce a vector
259  // of f64 elements.
261 
262  // Round the f64 elements of vector operand 0 to f32s and store them in the
263  // even elements of the result.
265 
266  // AND the two vector operands together and set CC based on the result.
268 
269  // String operations that set CC as a side-effect.
281 
282  // Test Data Class.
283  //
284  // Operand 0: the value to test
285  // Operand 1: the bit mask
287 
288  // Strict variants of scalar floating-point comparisons.
289  // Quiet and signaling versions.
292 
293  // Strict variants of vector floating-point comparisons.
294  // Quiet and signaling versions.
301 
302  // Strict variants of VEXTEND and VROUND.
305 
306  // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
307  // ATOMIC_LOAD_<op>.
308  //
309  // Operand 0: the address of the containing 32-bit-aligned field
310  // Operand 1: the second operand of <op>, in the high bits of an i32
311  // for everything except ATOMIC_SWAPW
312  // Operand 2: how many bits to rotate the i32 left to bring the first
313  // operand into the high bits
314  // Operand 3: the negative of operand 2, for rotating the other way
315  // Operand 4: the width of the field in bits (8 or 16)
327 
328  // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
329  //
330  // Operand 0: the address of the containing 32-bit-aligned field
331  // Operand 1: the compare value, in the low bits of an i32
332  // Operand 2: the swap value, in the low bits of an i32
333  // Operand 3: how many bits to rotate the i32 left to bring the first
334  // operand into the high bits
335  // Operand 4: the negative of operand 2, for rotating the other way
336  // Operand 5: the width of the field in bits (8 or 16)
338 
339  // Atomic compare-and-swap returning CC value.
340  // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
342 
343  // 128-bit atomic load.
344  // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr)
346 
347  // 128-bit atomic store.
348  // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr)
350 
351  // 128-bit atomic compare-and-swap.
352  // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
354 
355  // Byte swapping load/store. Same operands as regular load/store.
357 
358  // Element swapping load/store. Same operands as regular load/store.
360 
361  // Prefetch from the second operand using the 4-bit control code in
362  // the first operand. The code is 1 for a load prefetch and 2 for
363  // a store prefetch.
365 };
366 
367 // Return true if OPCODE is some kind of PC-relative address.
368 inline bool isPCREL(unsigned Opcode) {
369  return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
370 }
371 } // end namespace SystemZISD
372 
373 namespace SystemZICMP {
374 // Describes whether an integer comparison needs to be signed or unsigned,
375 // or whether either type is OK.
376 enum {
380 };
381 } // end namespace SystemZICMP
382 
383 class SystemZSubtarget;
384 
386 public:
387  explicit SystemZTargetLowering(const TargetMachine &TM,
388  const SystemZSubtarget &STI);
389 
390  bool useSoftFloat() const override;
391 
392  // Override TargetLowering.
393  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
394  return MVT::i32;
395  }
396  MVT getVectorIdxTy(const DataLayout &DL) const override {
397  // Only the lower 12 bits of an element index are used, so we don't
398  // want to clobber the upper 32 bits of a GPR unnecessarily.
399  return MVT::i32;
400  }
402  const override {
403  // Widen subvectors to the full width rather than promoting integer
404  // elements. This is better because:
405  //
406  // (a) it means that we can handle the ABI for passing and returning
407  // sub-128 vectors without having to handle them as legal types.
408  //
409  // (b) we don't have instructions to extend on load and truncate on store,
410  // so promoting the integers is less efficient.
411  //
412  // (c) there are no multiplication instructions for the widest integer
413  // type (v2i64).
414  if (VT.getScalarSizeInBits() % 8 == 0)
415  return TypeWidenVector;
417  }
418  unsigned
420  Optional<MVT> RegisterVT) const override {
421  // i128 inline assembly operand.
422  if (VT == MVT::i128 &&
423  RegisterVT.hasValue() && RegisterVT.getValue() == MVT::Untyped)
424  return 1;
426  }
427  bool isCheapToSpeculateCtlz() const override { return true; }
428  bool preferZeroCompareBranch() const override { return true; }
429  bool hasBitPreservingFPLogic(EVT VT) const override {
430  EVT ScVT = VT.getScalarType();
431  return ScVT == MVT::f32 || ScVT == MVT::f64 || ScVT == MVT::f128;
432  }
433  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override {
434  ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1));
435  return Mask && Mask->getValue().isIntN(16);
436  }
437  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
438  return VT.isScalarInteger();
439  }
441  EVT) const override;
443  EVT VT) const override;
444  bool isFPImmLegal(const APFloat &Imm, EVT VT,
445  bool ForCodeSize) const override;
446  bool ShouldShrinkFPConstant(EVT VT) const override {
447  // Do not shrink 64-bit FP constpool entries since LDEB is slower than
448  // LD, and having the full constant in memory enables reg/mem opcodes.
449  return VT != MVT::f64;
450  }
451  bool hasInlineStackProbe(MachineFunction &MF) const override;
452  bool isLegalICmpImmediate(int64_t Imm) const override;
453  bool isLegalAddImmediate(int64_t Imm) const override;
454  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
455  unsigned AS,
456  Instruction *I = nullptr) const override;
457  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
459  bool *Fast) const override;
460  bool isTruncateFree(Type *, Type *) const override;
461  bool isTruncateFree(EVT, EVT) const override;
462 
463  bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
464  bool MathUsed) const override {
465  // Form add and sub with overflow intrinsics regardless of any extra
466  // users of the math result.
467  return VT == MVT::i32 || VT == MVT::i64;
468  }
469 
470  const char *getTargetNodeName(unsigned Opcode) const override;
471  std::pair<unsigned, const TargetRegisterClass *>
473  StringRef Constraint, MVT VT) const override;
475  getConstraintType(StringRef Constraint) const override;
477  getSingleConstraintMatchWeight(AsmOperandInfo &info,
478  const char *constraint) const override;
480  std::string &Constraint,
481  std::vector<SDValue> &Ops,
482  SelectionDAG &DAG) const override;
483 
484  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
485  if (ConstraintCode.size() == 1) {
486  switch(ConstraintCode[0]) {
487  default:
488  break;
489  case 'o':
491  case 'Q':
493  case 'R':
495  case 'S':
497  case 'T':
499  }
500  }
501  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
502  }
503 
504  Register getRegisterByName(const char *RegName, LLT VT,
505  const MachineFunction &MF) const override;
506 
507  /// If a physical register, this returns the register that receives the
508  /// exception address on entry to an EH pad.
509  Register
510  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
511  return SystemZ::R6D;
512  }
513 
514  /// If a physical register, this returns the register that receives the
515  /// exception typeid on entry to a landing pad.
516  Register
517  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
518  return SystemZ::R7D;
519  }
520 
521  /// Override to support customized stack guard loading.
522  bool useLoadStackGuardNode() const override {
523  return true;
524  }
525  void insertSSPDeclarations(Module &M) const override {
526  }
527 
530  MachineBasicBlock *BB) const override;
531  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
533  SelectionDAG &DAG) const override;
535  SelectionDAG &DAG) const override;
536  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
537  bool allowTruncateForTailCall(Type *, Type *) const override;
538  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
540  SDValue Val, SDValue *Parts,
541  unsigned NumParts, MVT PartVT,
542  Optional<CallingConv::ID> CC) const override;
543  SDValue
545  const SDValue *Parts, unsigned NumParts,
546  MVT PartVT, EVT ValueVT,
547  Optional<CallingConv::ID> CC) const override;
549  bool isVarArg,
551  const SDLoc &DL, SelectionDAG &DAG,
552  SmallVectorImpl<SDValue> &InVals) const override;
553  SDValue LowerCall(CallLoweringInfo &CLI,
554  SmallVectorImpl<SDValue> &InVals) const override;
555 
557  bool isVarArg,
559  LLVMContext &Context) const override;
560  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
562  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
563  SelectionDAG &DAG) const override;
564  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
565 
566  /// Determine which of the bits specified in Mask are known to be either
567  /// zero or one and return them in the KnownZero/KnownOne bitsets.
569  KnownBits &Known,
570  const APInt &DemandedElts,
571  const SelectionDAG &DAG,
572  unsigned Depth = 0) const override;
573 
574  /// Determine the number of bits in the operation that are sign bits.
576  const APInt &DemandedElts,
577  const SelectionDAG &DAG,
578  unsigned Depth) const override;
579 
581  return ISD::ANY_EXTEND;
582  }
584  return ISD::ZERO_EXTEND;
585  }
586 
587  bool supportSwiftError() const override {
588  return true;
589  }
590 
591  unsigned getStackProbeSize(MachineFunction &MF) const;
592 
593 private:
594  const SystemZSubtarget &Subtarget;
595 
596  // Implement LowerOperation for individual opcodes.
597  SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
598  const SDLoc &DL, EVT VT,
599  SDValue CmpOp0, SDValue CmpOp1, SDValue Chain) const;
600  SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL,
601  EVT VT, ISD::CondCode CC,
602  SDValue CmpOp0, SDValue CmpOp1,
603  SDValue Chain = SDValue(),
604  bool IsSignaling = false) const;
605  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
606  SDValue lowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG,
607  bool IsSignaling) const;
608  SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
609  SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
610  SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
611  SelectionDAG &DAG) const;
612  SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
613  SelectionDAG &DAG, unsigned Opcode,
614  SDValue GOTOffset) const;
615  SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
616  SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
617  SelectionDAG &DAG) const;
618  SDValue lowerBlockAddress(BlockAddressSDNode *Node,
619  SelectionDAG &DAG) const;
620  SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
621  SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
622  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
623  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
624  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
625  SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
626  SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
627  SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
628  SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
629  SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
630  SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
631  SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
632  SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const;
633  SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) const;
634  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
635  SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
636  SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
637  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
638  SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
639  SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
640  SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
641  unsigned Opcode) const;
642  SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
643  SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
644  SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
645  SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
646  SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
647  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
648  SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
649  bool isVectorElementLoad(SDValue Op) const;
650  SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
651  SmallVectorImpl<SDValue> &Elems) const;
652  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
653  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
654  SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
655  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
656  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
657  SDValue lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
658  SDValue lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
659  SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
660 
661  bool canTreatAsByteVector(EVT VT) const;
662  SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
663  unsigned Index, DAGCombinerInfo &DCI,
664  bool Force) const;
665  SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
666  DAGCombinerInfo &DCI) const;
667  SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
668  SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
669  SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;
670  SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
671  bool canLoadStoreByteSwapped(EVT VT) const;
672  SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const;
673  SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
674  SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const;
675  SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
676  SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
677  SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
678  SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
679  SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const;
680  SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
681  SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
682  SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
683  SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
684  SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const;
685  SDValue combineINTRINSIC(SDNode *N, DAGCombinerInfo &DCI) const;
686 
687  SDValue unwrapAddress(SDValue N) const override;
688 
689  // If the last instruction before MBBI in MBB was some form of COMPARE,
690  // try to replace it with a COMPARE AND BRANCH just before MBBI.
691  // CCMask and Target are the BRC-like operands for the branch.
692  // Return true if the change was made.
693  bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
695  unsigned CCMask,
696  MachineBasicBlock *Target) const;
697 
698  // Implement EmitInstrWithCustomInserter for individual operation types.
699  MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
700  MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
701  unsigned StoreOpcode, unsigned STOCOpcode,
702  bool Invert) const;
703  MachineBasicBlock *emitPair128(MachineInstr &MI,
704  MachineBasicBlock *MBB) const;
706  bool ClearEven) const;
707  MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
708  MachineBasicBlock *BB,
709  unsigned BinOpcode, unsigned BitSize,
710  bool Invert = false) const;
711  MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
713  unsigned CompareOpcode,
714  unsigned KeepOldMask,
715  unsigned BitSize) const;
716  MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
717  MachineBasicBlock *BB) const;
718  MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
719  unsigned Opcode,
720  bool IsMemset = false) const;
721  MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
722  unsigned Opcode) const;
723  MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
725  unsigned Opcode, bool NoFloat) const;
726  MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
728  unsigned Opcode) const;
729  MachineBasicBlock *emitProbedAlloca(MachineInstr &MI,
730  MachineBasicBlock *MBB) const;
731 
732  SDValue getBackchainAddress(SDValue SP, SelectionDAG &DAG) const;
733 
735  getTargetMMOFlags(const Instruction &I) const override;
736  const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
737 };
738 
740 private:
741  APInt IntBits; // The 128 bits as an integer.
742  APInt SplatBits; // Smallest splat value.
743  APInt SplatUndef; // Bits correspoding to undef operands of the BVN.
744  unsigned SplatBitSize = 0;
745  bool isFP128 = false;
746 
747 public:
748  unsigned Opcode = 0;
753  bool isVectorConstantLegal(const SystemZSubtarget &Subtarget);
754 };
755 
756 } // end namespace llvm
757 
758 #endif
llvm::TargetLoweringBase::getPreferredVectorAction
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Definition: TargetLowering.h:451
llvm::SystemZTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: SystemZISelLowering.cpp:5678
llvm::SystemZISD::UADDO
@ UADDO
Definition: SystemZISelLowering.h:100
llvm::SystemZISD::SELECT_CCMASK
@ SELECT_CCMASK
Definition: SystemZISelLowering.h:77
llvm::SystemZTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: SystemZISelLowering.cpp:1233
llvm::SystemZISD::SDIVREM
@ SDIVREM
Definition: SystemZISelLowering.h:94
llvm::SystemZISD::ATOMIC_LOADW_SUB
@ ATOMIC_LOADW_SUB
Definition: SystemZISelLowering.h:318
llvm::SystemZISD::SUBCARRY
@ SUBCARRY
Definition: SystemZISelLowering.h:100
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:22
llvm::SystemZISD::ATOMIC_LOAD_128
@ ATOMIC_LOAD_128
Definition: SystemZISelLowering.h:345
llvm::SystemZISD::USUBO
@ USUBO
Definition: SystemZISelLowering.h:100
llvm::SystemZISD::RET_FLAG
@ RET_FLAG
Definition: SystemZISelLowering.h:29
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:150
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::SystemZTargetLowering::isTruncateFree
bool isTruncateFree(Type *, Type *) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: SystemZISelLowering.cpp:991
llvm::SystemZTargetLowering::getNumRegisters
unsigned getNumRegisters(LLVMContext &Context, EVT VT, Optional< MVT > RegisterVT) const override
Return the number of registers that this ValueType will eventually require.
Definition: SystemZISelLowering.h:419
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1088
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4263
llvm::SystemZTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT) const override
Return the ValueType of the result of SETCC operations.
Definition: SystemZISelLowering.cpp:688
llvm::SystemZISD::ICMP
@ ICMP
Definition: SystemZISelLowering.h:55
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::SystemZTargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: SystemZISelLowering.cpp:1296
llvm::SystemZISD::GET_CCMASK
@ GET_CCMASK
Definition: SystemZISelLowering.h:108
llvm::MVT::i128
@ i128
Definition: MachineValueType.h:48
llvm::SystemZISD::VICMPH
@ VICMPH
Definition: SystemZISelLowering.h:235
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::SystemZTargetLowering
Definition: SystemZISelLowering.h:385
llvm::SmallVector< unsigned, 2 >
llvm::SystemZISD::PACKLS_CC
@ PACKLS_CC
Definition: SystemZISelLowering.h:209
llvm::SystemZISD::CLC
@ CLC
Definition: SystemZISelLowering.h:127
llvm::SystemZTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: SystemZISelLowering.cpp:5471
llvm::SystemZISD::ATOMIC_CMP_SWAPW
@ ATOMIC_CMP_SWAPW
Definition: SystemZISelLowering.h:337
llvm::SystemZISD::VICMPHLS
@ VICMPHLS
Definition: SystemZISelLowering.h:241
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:732
llvm::SystemZISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: SystemZISelLowering.h:26
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
MachineBasicBlock.h
llvm::SystemZISD::ROTATE_MASK
@ ROTATE_MASK
Definition: SystemZISelLowering.h:168
llvm::SystemZISD::VFENEZ_CC
@ VFENEZ_CC
Definition: SystemZISelLowering.h:275
llvm::SystemZISD::VFAE_CC
@ VFAE_CC
Definition: SystemZISelLowering.h:270
llvm::SystemZISD::VSTRS_CC
@ VSTRS_CC
Definition: SystemZISelLowering.h:279
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::SystemZTargetLowering::allowTruncateForTailCall
bool allowTruncateForTailCall(Type *, Type *) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
Definition: SystemZISelLowering.cpp:1291
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::SystemZISD::PREFETCH
@ PREFETCH
Definition: SystemZISelLowering.h:364
llvm::SystemZTargetLowering::LowerCall
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: SystemZISelLowering.cpp:1612
llvm::SystemZICMP::Any
@ Any
Definition: SystemZISelLowering.h:377
llvm::SystemZISD::VSTER
@ VSTER
Definition: SystemZISelLowering.h:359
llvm::SystemZTargetLowering::SystemZTargetLowering
SystemZTargetLowering(const TargetMachine &TM, const SystemZSubtarget &STI)
Definition: SystemZISelLowering.cpp:80
llvm::Optional
Definition: APInt.h:33
llvm::SystemZTargetLowering::preferZeroCompareBranch
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
Definition: SystemZISelLowering.h:428
llvm::SystemZICMP::SignedOnly
@ SignedOnly
Definition: SystemZISelLowering.h:379
llvm::SystemZTargetLowering::getExtendForAtomicCmpSwapArg
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
Definition: SystemZISelLowering.h:583
llvm::SystemZTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: SystemZISelLowering.h:437
llvm::SystemZTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: SystemZISelLowering.cpp:1221
llvm::SystemZISD::STRICT_VEXTEND
@ STRICT_VEXTEND
Definition: SystemZISelLowering.h:303
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:849
llvm::SystemZTargetLowering::getStackProbeSize
unsigned getStackProbeSize(MachineFunction &MF) const
Definition: SystemZISelLowering.cpp:7125
llvm::SystemZTargetLowering::getConstraintType
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: SystemZISelLowering.cpp:1012
llvm::SystemZTargetLowering::getSingleConstraintMatchWeight
TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: SystemZISelLowering.cpp:1045
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2151
llvm::SystemZISD::VICMPHL
@ VICMPHL
Definition: SystemZISelLowering.h:236
SelectionDAG.h
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::SystemZISD::VSHL_BY_SCALAR
@ VSHL_BY_SCALAR
Definition: SystemZISelLowering.h:222
llvm::SystemZISD::PERMUTE_DWORDS
@ PERMUTE_DWORDS
Definition: SystemZISelLowering.h:196
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1564
llvm::SystemZTargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: SystemZISelLowering.h:429
llvm::SystemZTargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: SystemZISelLowering.h:525
llvm::SystemZISD::TEND
@ TEND
Definition: SystemZISelLowering.h:158
llvm::SystemZTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: SystemZISelLowering.cpp:1857
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
Definition: SystemZISelLowering.cpp:7070
llvm::Optional::hasValue
constexpr bool hasValue() const
Definition: Optional.h:288
llvm::SystemZISD::ATOMIC_SWAPW
@ ATOMIC_SWAPW
Definition: SystemZISelLowering.h:316
TargetLowering.h
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::SystemZTargetLowering::getVectorIdxTy
MVT getVectorIdxTy(const DataLayout &DL) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
Definition: SystemZISelLowering.h:396
llvm::SystemZISD::ATOMIC_LOADW_UMAX
@ ATOMIC_LOADW_UMAX
Definition: SystemZISelLowering.h:326
llvm::InlineAsm::Constraint_T
@ Constraint_T
Definition: InlineAsm.h:259
llvm::SystemZISD::BR_CCMASK
@ BR_CCMASK
Definition: SystemZISelLowering.h:71
llvm::SystemZISD::UNPACK_HIGH
@ UNPACK_HIGH
Definition: SystemZISelLowering.h:213
llvm::SystemZISD::ATOMIC_LOADW_ADD
@ ATOMIC_LOADW_ADD
Definition: SystemZISelLowering.h:317
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:729
SystemZInstrInfo.h
llvm::SystemZISD::TLS_LDCALL
@ TLS_LDCALL
Definition: SystemZISelLowering.h:40
llvm::SystemZISD::VSRA_BY_SCALAR
@ VSRA_BY_SCALAR
Definition: SystemZISelLowering.h:224
llvm::SystemZISD::TLS_GDCALL
@ TLS_GDCALL
Definition: SystemZISelLowering.h:39
llvm::SystemZISD::VFEEZ_CC
@ VFEEZ_CC
Definition: SystemZISelLowering.h:273
llvm::SystemZISD::ATOMIC_LOADW_UMIN
@ ATOMIC_LOADW_UMIN
Definition: SystemZISelLowering.h:325
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:256
llvm::SystemZTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: SystemZISelLowering.h:510
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:56
llvm::SystemZTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: SystemZISelLowering.cpp:848
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1823
llvm::SystemZISD::SIBCALL
@ SIBCALL
Definition: SystemZISelLowering.h:35
llvm::SystemZISD::JOIN_DWORDS
@ JOIN_DWORDS
Definition: SystemZISelLowering.h:174
llvm::SystemZISD::VSTRCZ_CC
@ VSTRCZ_CC
Definition: SystemZISelLowering.h:278
llvm::SystemZTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: SystemZISelLowering.cpp:8454
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3277
llvm::SystemZISD::VSRL_BY_SCALAR
@ VSRL_BY_SCALAR
Definition: SystemZISelLowering.h:223
llvm::SystemZTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: SystemZISelLowering.h:580
llvm::MVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: MachineValueType.h:1066
llvm::SystemZISD::UNPACKL_HIGH
@ UNPACKL_HIGH
Definition: SystemZISelLowering.h:214
llvm::SystemZISD::STRICT_VFCMPHES
@ STRICT_VFCMPHES
Definition: SystemZISelLowering.h:300
llvm::SystemZISD::VFCMPHES
@ VFCMPHES
Definition: SystemZISelLowering.h:253
llvm::SystemZISD::CALL
@ CALL
Definition: SystemZISelLowering.h:34
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SystemZISD::ATOMIC_LOADW_AND
@ ATOMIC_LOADW_AND
Definition: SystemZISelLowering.h:319
llvm::SystemZTargetLowering::isMaskAndCmp0FoldingBeneficial
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
Definition: SystemZISelLowering.h:433
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::Instruction
Definition: Instruction.h:45
llvm::SystemZVectorConstantInfo::isVectorConstantLegal
bool isVectorConstantLegal(const SystemZSubtarget &Subtarget)
Definition: SystemZISelLowering.cpp:717
llvm::SystemZISD::STRCMP
@ STRCMP
Definition: SystemZISelLowering.h:137
llvm::SystemZISD::STRICT_VROUND
@ STRICT_VROUND
Definition: SystemZISelLowering.h:304
llvm::SystemZICMP::UnsignedOnly
@ UnsignedOnly
Definition: SystemZISelLowering.h:378
llvm::SystemZISD::VFEE_CC
@ VFEE_CC
Definition: SystemZISelLowering.h:272
SystemZ.h
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:213
llvm::SystemZISD::VSUM
@ VSUM
Definition: SystemZISelLowering.h:229
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SystemZISD::FCMP
@ FCMP
Definition: SystemZISelLowering.h:58
llvm::SystemZTargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: SystemZISelLowering.h:587
llvm::SystemZISD::VFCMPE
@ VFCMPE
Definition: SystemZISelLowering.h:246
llvm::SystemZISD::UDIVREM
@ UDIVREM
Definition: SystemZISelLowering.h:95
llvm::SystemZISD::SSUBO
@ SSUBO
Definition: SystemZISelLowering.h:100
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::SystemZISD::VTM
@ VTM
Definition: SystemZISelLowering.h:267
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SystemZTargetLowering::useSoftFloat
bool useSoftFloat() const override
Definition: SystemZISelLowering.cpp:684
llvm::SystemZISD::ATOMIC_LOADW_NAND
@ ATOMIC_LOADW_NAND
Definition: SystemZISelLowering.h:322
llvm::SystemZISD::SMUL_LOHI
@ SMUL_LOHI
Definition: SystemZISelLowering.h:92
llvm::SystemZISD::VFCMPHE
@ VFCMPHE
Definition: SystemZISelLowering.h:248
llvm::SystemZVectorConstantInfo::Opcode
unsigned Opcode
Definition: SystemZISelLowering.h:748
llvm::SystemZISD::UMUL_LOHI
@ UMUL_LOHI
Definition: SystemZISelLowering.h:93
llvm::SystemZTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: SystemZISelLowering.cpp:6804
llvm::InlineAsm::Constraint_o
@ Constraint_o
Definition: InlineAsm.h:253
llvm::SystemZISD::TBEGIN_NOFLOAT
@ TBEGIN_NOFLOAT
Definition: SystemZISelLowering.h:155
llvm::APFloat
Definition: APFloat.h:701
llvm::SystemZISD::TDC
@ TDC
Definition: SystemZISelLowering.h:286
llvm::SystemZTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: SystemZISelLowering.cpp:6952
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::SystemZISD::VICMPHS
@ VICMPHS
Definition: SystemZISelLowering.h:240
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::SystemZVectorConstantInfo
Definition: SystemZISelLowering.h:739
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1259
llvm::SystemZISD::MVC
@ MVC
Definition: SystemZISelLowering.h:118
llvm::SystemZISD::SHL_DOUBLE
@ SHL_DOUBLE
Definition: SystemZISelLowering.h:189
llvm::SystemZISD::MERGE_HIGH
@ MERGE_HIGH
Definition: SystemZISelLowering.h:182
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::SystemZTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
Definition: SystemZISelLowering.cpp:858
llvm::SystemZISD::LRV
@ LRV
Definition: SystemZISelLowering.h:356
llvm::SystemZISD::XC
@ XC
Definition: SystemZISelLowering.h:123
llvm::SystemZTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: SystemZISelLowering.cpp:853
llvm::SystemZTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: SystemZISelLowering.cpp:1837
llvm::SystemZTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: SystemZISelLowering.h:517
llvm::SystemZISD::VEXTEND
@ VEXTEND
Definition: SystemZISelLowering.h:260
llvm::SystemZISD::STRICT_VFCMPHS
@ STRICT_VFCMPHS
Definition: SystemZISelLowering.h:299
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::SystemZISD::VSTRC_CC
@ VSTRC_CC
Definition: SystemZISelLowering.h:277
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::SystemZISD::OC
@ OC
Definition: SystemZISelLowering.h:122
llvm::SystemZISD::SEARCH_STRING
@ SEARCH_STRING
Definition: SystemZISelLowering.h:143
llvm::SystemZTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: SystemZISelLowering.h:427
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1370
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::SystemZISD::VFCMPES
@ VFCMPES
Definition: SystemZISelLowering.h:251
llvm::SystemZISD::VFCMPH
@ VFCMPH
Definition: SystemZISelLowering.h:247
llvm::SystemZSubtarget
Definition: SystemZSubtarget.h:33
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::SystemZISD::ATOMIC_LOADW_XOR
@ ATOMIC_LOADW_XOR
Definition: SystemZISelLowering.h:321
llvm::SystemZISD::VFCMPHS
@ VFCMPHS
Definition: SystemZISelLowering.h:252
llvm::SystemZISD::STRICT_VFCMPH
@ STRICT_VFCMPH
Definition: SystemZISelLowering.h:296
info
lazy value info
Definition: LazyValueInfo.cpp:59
llvm::SystemZTargetLowering::hasInlineStackProbe
bool hasInlineStackProbe(MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
Definition: SystemZISelLowering.cpp:840
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1844
llvm::SystemZISD::MEMSET_MVC
@ MEMSET_MVC
Definition: SystemZISelLowering.h:130
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::BuildVectorSDNode
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Definition: SelectionDAGNodes.h:1949
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::SystemZTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: SystemZISelLowering.cpp:965
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SystemZISD::VFENE_CC
@ VFENE_CC
Definition: SystemZISelLowering.h:274
llvm::SystemZTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: SystemZISelLowering.h:484
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1253
llvm::SystemZISD::REPLICATE
@ REPLICATE
Definition: SystemZISelLowering.h:171
Node
Definition: ItaniumDemangle.h:238
llvm::SystemZTargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: SystemZISelLowering.h:401
llvm::SystemZISD::ATOMIC_LOADW_MIN
@ ATOMIC_LOADW_MIN
Definition: SystemZISelLowering.h:323
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SystemZISD::VROUND
@ VROUND
Definition: SystemZISelLowering.h:264
llvm::SystemZISD::ATOMIC_LOADW_OR
@ ATOMIC_LOADW_OR
Definition: SystemZISelLowering.h:320
llvm::SystemZTargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: SystemZISelLowering.h:393
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonISD::CP
@ CP
Definition: HexagonISelLowering.h:53
llvm::StringRef::size
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
llvm::SystemZISD::STRICT_FCMP
@ STRICT_FCMP
Definition: SystemZISelLowering.h:290
llvm::SystemZISD::SADDO
@ SADDO
Definition: SystemZISelLowering.h:100
llvm::SystemZISD::STRICT_FCMPS
@ STRICT_FCMPS
Definition: SystemZISelLowering.h:291
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1720
llvm::KnownBits
Definition: KnownBits.h:23
llvm::SystemZISD::MEMBARRIER
@ MEMBARRIER
Definition: SystemZISelLowering.h:149
llvm::SystemZISD::PACKS_CC
@ PACKS_CC
Definition: SystemZISelLowering.h:208
uint16_t
llvm::SystemZTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: SystemZISelLowering.cpp:5684
llvm::EVT::getScalarType
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:296
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4272
llvm::SystemZISD::ATOMIC_CMP_SWAP_128
@ ATOMIC_CMP_SWAP_128
Definition: SystemZISelLowering.h:353
llvm::SystemZISD::PROBED_ALLOCA
@ PROBED_ALLOCA
Definition: SystemZISelLowering.h:85
llvm::SystemZISD::VICMPES
@ VICMPES
Definition: SystemZISelLowering.h:239
llvm::SystemZISD::VICMPE
@ VICMPE
Definition: SystemZISelLowering.h:234
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::SystemZISD::PACK
@ PACK
Definition: SystemZISelLowering.h:204
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:205
llvm::SystemZTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: SystemZISelLowering.cpp:830
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::SystemZTargetLowering::ShouldShrinkFPConstant
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Definition: SystemZISelLowering.h:446
llvm::SystemZISD::NC
@ NC
Definition: SystemZISelLowering.h:121
llvm::InlineAsm::Constraint_S
@ Constraint_S
Definition: InlineAsm.h:258
llvm::SystemZISD::PCREL_WRAPPER
@ PCREL_WRAPPER
Definition: SystemZISelLowering.h:44
llvm::SystemZTargetLowering::splitValueIntoRegisterParts
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Definition: SystemZISelLowering.cpp:1401
llvm::SystemZISD::PCREL_OFFSET
@ PCREL_OFFSET
Definition: SystemZISelLowering.h:51
llvm::SystemZISD::VISTR_CC
@ VISTR_CC
Definition: SystemZISelLowering.h:276
llvm::SystemZISD::VFAEZ_CC
@ VFAEZ_CC
Definition: SystemZISelLowering.h:271
llvm::SystemZISD::MERGE_LOW
@ MERGE_LOW
Definition: SystemZISelLowering.h:185
llvm::SystemZTargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
Definition: SystemZISelLowering.h:522
llvm::SystemZISD::STRICT_VFCMPHE
@ STRICT_VFCMPHE
Definition: SystemZISelLowering.h:297
llvm::SystemZTargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: SystemZISelLowering.h:463
llvm::SystemZISD::UNPACK_LOW
@ UNPACK_LOW
Definition: SystemZISelLowering.h:217
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:58
llvm::SystemZTargetLowering::joinRegisterPartsIntoValue
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
Definition: SystemZISelLowering.cpp:1417
llvm::SystemZISD::VLER
@ VLER
Definition: SystemZISelLowering.h:359
llvm::SystemZISD::ADJDYNALLOC
@ ADJDYNALLOC
Definition: SystemZISelLowering.h:81
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1265
N
#define N
llvm::SystemZISD::ATOMIC_STORE_128
@ ATOMIC_STORE_128
Definition: SystemZISelLowering.h:349
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4364
llvm::SystemZISD::UNPACKL_LOW
@ UNPACKL_LOW
Definition: SystemZISelLowering.h:218
llvm::SystemZISD::VFTCI
@ VFTCI
Definition: SystemZISelLowering.h:256
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::MVT::Untyped
@ Untyped
Definition: MachineValueType.h:266
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::SystemZISD::isPCREL
bool isPCREL(unsigned Opcode)
Definition: SystemZISelLowering.h:368
llvm::SystemZISD::ATOMIC_LOADW_MAX
@ ATOMIC_LOADW_MAX
Definition: SystemZISelLowering.h:324
RegName
#define RegName(no)
llvm::TargetLoweringBase::getNumRegisters
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, Optional< MVT > RegisterVT=None) const
Return the number of registers that this ValueType will eventually require.
Definition: TargetLowering.h:1528
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SystemZISD::SPLAT
@ SPLAT
Definition: SystemZISelLowering.h:178
llvm::SystemZISD::STRICT_VFCMPE
@ STRICT_VFCMPE
Definition: SystemZISelLowering.h:295
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1478
llvm::SystemZISD::STPCPY
@ STPCPY
Definition: SystemZISelLowering.h:133
llvm::SystemZTargetLowering::getScratchRegisters
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition: SystemZISelLowering.cpp:1284
llvm::SystemZISD::ADDCARRY
@ ADDCARRY
Definition: SystemZISelLowering.h:100
llvm::SystemZVectorConstantInfo::SystemZVectorConstantInfo
SystemZVectorConstantInfo(APFloat FPImm)
Definition: SystemZISelLowering.cpp:793
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::SystemZTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: SystemZISelLowering.cpp:1430
llvm::SystemZISD::VSTRSZ_CC
@ VSTRSZ_CC
Definition: SystemZISelLowering.h:280
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:55
llvm::SystemZISD::PERMUTE
@ PERMUTE
Definition: SystemZISelLowering.h:201
llvm::SystemZVectorConstantInfo::OpVals
SmallVector< unsigned, 2 > OpVals
Definition: SystemZISelLowering.h:749
llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: SystemZISelLowering.cpp:695
llvm::InlineAsm::Constraint_R
@ Constraint_R
Definition: InlineAsm.h:257
llvm::SystemZISD::IPM
@ IPM
Definition: SystemZISelLowering.h:146
llvm::SystemZISD::TBEGIN
@ TBEGIN
Definition: SystemZISelLowering.h:154
llvm::SystemZTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: SystemZISelLowering.cpp:1130
llvm::SystemZVectorConstantInfo::VecVT
MVT VecVT
Definition: SystemZISelLowering.h:750
llvm::SystemZTargetLowering::LowerOperationWrapper
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
Definition: SystemZISelLowering.cpp:5596
llvm::SystemZISD::POPCNT
@ POPCNT
Definition: SystemZISelLowering.h:88
llvm::SystemZISD::STRV
@ STRV
Definition: SystemZISelLowering.h:356
llvm::Optional::getValue
constexpr const T & getValue() const LLVM_LVALUE_FUNCTION
Definition: Optional.h:282
llvm::SystemZISD::STRICT_VFCMPES
@ STRICT_VFCMPES
Definition: SystemZISelLowering.h:298
llvm::SystemZISD::BYTE_MASK
@ BYTE_MASK
Definition: SystemZISelLowering.h:162
llvm::SystemZISD::NodeType
NodeType
Definition: SystemZISelLowering.h:25
llvm::SystemZISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Definition: SystemZISelLowering.h:341
llvm::LLT
Definition: LowLevelTypeImpl.h:39