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14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
24 namespace SystemZISD {
373 namespace SystemZICMP {
383 class SystemZSubtarget;
434 return Mask &&
Mask->getValue().isIntN(16);
442 EVT VT)
const override;
444 bool ForCodeSize)
const override;
458 bool *Fast)
const override;
461 const MemOp &
Op,
unsigned DstAS,
unsigned SrcAS,
469 bool MathUsed)
const override {
478 std::pair<unsigned, const TargetRegisterClass *>
485 const char *constraint)
const override;
487 std::string &Constraint,
488 std::vector<SDValue> &Ops,
492 if (ConstraintCode.
size() == 1) {
493 switch(ConstraintCode[0]) {
507 }
else if (ConstraintCode.
size() == 2 && ConstraintCode[0] ==
'Z') {
508 switch (ConstraintCode[1]) {
561 unsigned NumParts,
MVT PartVT,
565 const SDValue *Parts,
unsigned NumParts,
576 std::pair<SDValue, SDValue>
579 bool IsSigned,
SDLoc DL,
bool DoesNotReturn,
580 bool IsReturnValueUsed)
const;
596 const APInt &DemandedElts,
598 unsigned Depth = 0)
const override;
602 const APInt &DemandedElts,
604 unsigned Depth)
const override;
630 bool IsSignaling =
false)
const;
633 bool IsSignaling)
const;
671 unsigned Opcode)
const;
679 bool isVectorElementLoad(
SDValue Op)
const;
692 bool canTreatAsByteVector(
EVT VT)
const;
694 unsigned Index, DAGCombinerInfo &DCI,
697 DAGCombinerInfo &DCI)
const;
698 SDValue combineZERO_EXTEND(
SDNode *
N, DAGCombinerInfo &DCI)
const;
699 SDValue combineSIGN_EXTEND(
SDNode *
N, DAGCombinerInfo &DCI)
const;
700 SDValue combineSIGN_EXTEND_INREG(
SDNode *
N, DAGCombinerInfo &DCI)
const;
702 bool canLoadStoreByteSwapped(
EVT VT)
const;
705 SDValue combineVECTOR_SHUFFLE(
SDNode *
N, DAGCombinerInfo &DCI)
const;
706 SDValue combineEXTRACT_VECTOR_ELT(
SDNode *
N, DAGCombinerInfo &DCI)
const;
707 SDValue combineJOIN_DWORDS(
SDNode *
N, DAGCombinerInfo &DCI)
const;
713 SDValue combineSELECT_CCMASK(
SDNode *
N, DAGCombinerInfo &DCI)
const;
732 unsigned StoreOpcode,
unsigned STOCOpcode,
737 bool ClearEven)
const;
740 unsigned BinOpcode,
unsigned BitSize,
741 bool Invert =
false)
const;
744 unsigned CompareOpcode,
745 unsigned KeepOldMask,
746 unsigned BitSize)
const;
751 bool IsMemset =
false)
const;
753 unsigned Opcode)
const;
756 unsigned Opcode,
bool NoFloat)
const;
759 unsigned Opcode)
const;
775 unsigned SplatBitSize = 0;
776 bool isFP128 =
false;
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
std::pair< SDValue, SDValue > makeExternalCall(SDValue Chain, SelectionDAG &DAG, const char *CalleeName, EVT RetVT, ArrayRef< SDValue > Ops, CallingConv::ID CallConv, bool IsSigned, SDLoc DL, bool DoesNotReturn, bool IsReturnValueUsed) const
This is an optimization pass for GlobalISel generic memory operations.
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
bool isTruncateFree(Type *, Type *) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
unsigned getNumRegisters(LLVMContext &Context, EVT VT, Optional< MVT > RegisterVT) const override
Return the number of registers that this ValueType will eventually require.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT) const override
Return the ValueType of the result of SETCC operations.
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Target - Wrapper for Target specific information.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Represents one node in the SelectionDAG.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool allowTruncateForTailCall(Type *, Type *) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
The instances of the Type class are immutable: once they are created, they are never changed.
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
SystemZTargetLowering(const TargetMachine &TM, const SystemZSubtarget &STI)
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Function Alias Analysis Results
unsigned getStackProbeSize(MachineFunction &MF) const
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
const fltSemantics & getSemantics() const
unsigned const TargetRegisterInfo * TRI
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
static const fltSemantics & IEEEquad() LLVM_READNONE
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
This is the shared class of boolean and integer constants.
MVT getVectorIdxTy(const DataLayout &DL) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
uint64_t getScalarSizeInBits() const
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
bool isVectorConstantLegal(const SystemZSubtarget &Subtarget)
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool useSoftFloat() const override
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const override
Determines the optimal series of memory ops to replace the memset / memcpy.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
This is an important base class in LLVM.
Representation of each machine instruction.
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
This is an important class for using LLVM in a threaded context.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Flags
Flags values. These may be or'd together.
Primary interface to the complete machine description for the target machine.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
SystemZVectorConstantInfo(APFloat FPImm)
A Module instance is used to store all the information related to an LLVM module.
bool hasInlineStackProbe(MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
Class for arbitrary precision integers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
StringRef - Represent a constant reference to a string, i.e.
A "pseudo-class" with methods for operating on BUILD_VECTORs.
bool shouldConsiderGEPOffsetSplit() const override
MachineBasicBlock MachineBasicBlock::iterator MBBI
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
SystemZVectorConstantInfo(APInt IntImm)
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Wrapper class representing virtual and physical registers.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isPCREL(unsigned Opcode)
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, Optional< MVT > RegisterVT=None) const
Return the number of registers that this ValueType will eventually require.
const char LLVMTargetMachineRef TM
This class represents a function call, abstracting a target machine's calling convention.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Value * getOperand(unsigned i) const
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
SmallVector< unsigned, 2 > OpVals
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...