LLVM 24.0.0git
SystemZISelLowering.h
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1//===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that SystemZ uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
15#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16
17#include "SystemZ.h"
18#include "SystemZInstrInfo.h"
19#include "llvm/CodeGen/LibcallLoweringInfo.h"
20#include "llvm/CodeGen/MachineBasicBlock.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/CodeGen/TargetLowering.h"
23#include <optional>
24
25namespace llvm {
26
27namespace SystemZICMP {
28// Describes whether an integer comparison needs to be signed or unsigned,
29// or whether either type is OK.
30enum {
31 Any,
32 UnsignedOnly,
33 SignedOnly
34};
35} // end namespace SystemZICMP
36
37class SystemZSubtarget;
38
39class SystemZTargetLowering : public TargetLowering {
40public:
41 explicit SystemZTargetLowering(const TargetMachine &TM,
42 const SystemZSubtarget &STI);
43
44 bool useSoftFloat() const override;
45
46 // Override TargetLowering.
47 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
48 return MVT::i32;
49 }
50 unsigned getVectorIdxWidth(const DataLayout &DL) const override {
51 // Only the lower 12 bits of an element index are used, so we don't
52 // want to clobber the upper 32 bits of a GPR unnecessarily.
53 return 32;
54 }
55 TargetLoweringBase::LegalizeTypeAction
56 getPreferredVectorAction(MVT VT) const override;
57 unsigned
58 getNumRegisters(LLVMContext &Context, EVT VT,
59 std::optional<MVT> RegisterVT) const override {
60 // i128 inline assembly operand.
61 if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped)
62 return 1;
63 return TargetLowering::getNumRegisters(Context, VT);
64 }
65 unsigned
66 getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC,
67 EVT VT, EVT &IntermediateVT,
68 unsigned &NumIntermediates,
69 MVT &RegisterVT) const override;
70 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
71 EVT VT) const override;
72 unsigned getNumRegistersForCallingConv(LLVMContext &Context,
73 CallingConv::ID CC,
74 EVT VT) const override;
75 bool isCheapToSpeculateCtlz(Type *) const override { return true; }
76 bool isCheapToSpeculateCttz(Type *) const override { return true; }
77 bool preferZeroCompareBranch() const override { return true; }
78 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override {
79 ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1));
80 return Mask && Mask->getValue().isIntN(16);
81 }
82 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
83 return VT.isScalarInteger();
84 }
85 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
86 EVT) const override;
87 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
88 EVT VT) const override;
89 FPImmAction getFPImmAction(const APFloat &Imm, EVT VT,
90 bool ForCodeSize) const override;
91 bool ShouldShrinkFPConstant(EVT VT) const override {
92 // Do not shrink 64-bit FP constpool entries since LDEB is slower than
93 // LD, and having the full constant in memory enables reg/mem opcodes.
94 return VT != MVT::f64;
95 }
96 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
97 MachineBasicBlock *MBB) const;
98
99 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
100 MachineBasicBlock *MBB) const;
101
102 bool canMergeStoresTo(unsigned AS, EVT MemVT,
103 const MachineFunction &MF) const override;
104
105 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
106
107 bool hasInlineStackProbe(const MachineFunction &MF) const override;
108 AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override;
109 AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override;
110 AtomicExpansionKind
111 shouldExpandAtomicRMWInIR(const AtomicRMWInst *RMW) const override;
112 bool isLegalICmpImmediate(int64_t Imm) const override;
113 bool isLegalAddImmediate(int64_t Imm) const override;
114 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
115 unsigned AS,
116 Instruction *I = nullptr) const override;
117 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
118 MachineMemOperand::Flags Flags,
119 unsigned *Fast) const override;
120 bool findOptimalMemOpLowering(LLVMContext &Context, std::vector<EVT> &MemOps,
121 unsigned Limit, const MemOp &Op, unsigned DstAS,
122 unsigned SrcAS,
123 const AttributeList &FuncAttributes,
124 EVT *LargestVT = nullptr) const override;
125 EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
126 const AttributeList &FuncAttributes) const override;
127 bool isTruncateFree(Type *, Type *) const override;
128 bool isTruncateFree(EVT, EVT) const override;
129
130 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
131 bool MathUsed) const override {
132 // Form add and sub with overflow intrinsics regardless of any extra
133 // users of the math result.
134 return VT == MVT::i32 || VT == MVT::i64 || VT == MVT::i128;
135 }
136
137 bool shouldConsiderGEPOffsetSplit() const override { return true; }
138
139 bool preferSelectsOverBooleanArithmetic(EVT VT) const override {
140 return true;
141 }
142
143 bool isProfitableToCombineMinNumMaxNum(EVT VT) const override {
144 // We have instructions for pseudo min/max, no need to convert them to
145 // minnum/maxnum.
146 return false;
147 }
148
149 // This function currently returns cost for srl/ipm/cc sequence for merging.
150 CondMergingParams
151 getJumpConditionMergingParams(Instruction::BinaryOps Opc, const Value *Lhs,
152 const Value *Rhs,
153 const Function *F) const override;
154
155 // Handle Lowering flag assembly outputs.
156 SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
157 const SDLoc &DL,
158 const AsmOperandInfo &Constraint,
159 SelectionDAG &DAG) const override;
160
161 std::pair<unsigned, const TargetRegisterClass *>
162 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
163 StringRef Constraint, MVT VT) const override;
164 TargetLowering::ConstraintType
165 getConstraintType(StringRef Constraint) const override;
166 TargetLowering::ConstraintWeight
167 getSingleConstraintMatchWeight(AsmOperandInfo &info,
168 const char *constraint) const override;
169 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
170 std::vector<SDValue> &Ops,
171 SelectionDAG &DAG) const override;
172
173 InlineAsm::ConstraintCode
174 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
175 if (ConstraintCode.size() == 1) {
176 switch(ConstraintCode[0]) {
177 default:
178 break;
179 case 'o':
180 return InlineAsm::ConstraintCode::o;
181 case 'Q':
182 return InlineAsm::ConstraintCode::Q;
183 case 'R':
184 return InlineAsm::ConstraintCode::R;
185 case 'S':
186 return InlineAsm::ConstraintCode::S;
187 case 'T':
188 return InlineAsm::ConstraintCode::T;
189 }
190 } else if (ConstraintCode.size() == 2 && ConstraintCode[0] == 'Z') {
191 switch (ConstraintCode[1]) {
192 default:
193 break;
194 case 'Q':
195 return InlineAsm::ConstraintCode::ZQ;
196 case 'R':
197 return InlineAsm::ConstraintCode::ZR;
198 case 'S':
199 return InlineAsm::ConstraintCode::ZS;
200 case 'T':
201 return InlineAsm::ConstraintCode::ZT;
202 }
203 }
204 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
205 }
206
207 Register getRegisterByName(const char *RegName, LLT VT,
208 const MachineFunction &MF) const override;
209
210 /// If a physical register, this returns the register that receives the
211 /// exception address on entry to an EH pad.
212 Register
213 getExceptionPointerRegister(ExceptionHandling EH,
214 const Constant *PersonalityFn) const override;
215
216 /// If a physical register, this returns the register that receives the
217 /// exception typeid on entry to a landing pad.
218 Register
219 getExceptionSelectorRegister(ExceptionHandling EH,
220 const Constant *PersonalityFn) const override;
221
222 /// Override to support customized stack guard loading.
223 bool useLoadStackGuardNode(const Module &M) const override { return true; }
224 /// Insert SSP declaration if global stack protector is used.
225 void
226 insertSSPDeclarations(Module &M,
227 const LibcallLoweringInfo &Libcalls) const override;
228 MachineBasicBlock *
229 EmitInstrWithCustomInserter(MachineInstr &MI,
230 MachineBasicBlock *BB) const override;
231 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
232 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
233 SelectionDAG &DAG) const override;
234 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
235 SelectionDAG &DAG) const override;
236 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
237 bool allowTruncateForTailCall(Type *, Type *) const override;
238 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
239 bool splitValueIntoRegisterParts(
240 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
241 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
242 const override;
243 SDValue joinRegisterPartsIntoValue(
244 SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
245 unsigned NumParts, MVT PartVT, EVT ValueVT,
246 std::optional<CallingConv::ID> CC) const override;
247 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
248 bool isVarArg,
249 const SmallVectorImpl<ISD::InputArg> &Ins,
250 const SDLoc &DL, SelectionDAG &DAG,
251 SmallVectorImpl<SDValue> &InVals) const override;
252 SDValue LowerCall(CallLoweringInfo &CLI,
253 SmallVectorImpl<SDValue> &InVals) const override;
254
255 std::pair<SDValue, SDValue>
256 makeExternalCall(SDValue Chain, SelectionDAG &DAG, const char *CalleeName,
257 EVT RetVT, ArrayRef<SDValue> Ops, CallingConv::ID CallConv,
258 bool IsSigned, SDLoc DL, bool DoesNotReturn,
259 bool IsReturnValueUsed) const;
260
261 SDValue useLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, MVT VT, SDValue Arg,
262 SDLoc DL, SDValue Chain, bool IsStrict) const;
263
264 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
265 bool isVarArg,
266 const SmallVectorImpl<ISD::OutputArg> &Outs,
267 LLVMContext &Context,
268 const Type *RetTy) const override;
269 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
270 const SmallVectorImpl<ISD::OutputArg> &Outs,
271 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
272 SelectionDAG &DAG) const override;
273 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
274
275 /// Determine which of the bits specified in Mask are known to be either
276 /// zero or one and return them in the KnownZero/KnownOne bitsets.
277 void computeKnownBitsForTargetNode(const SDValue Op,
278 KnownBits &Known,
279 const APInt &DemandedElts,
280 const SelectionDAG &DAG,
281 unsigned Depth = 0) const override;
282
283 /// Determine the number of bits in the operation that are sign bits.
284 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
285 const APInt &DemandedElts,
286 const SelectionDAG &DAG,
287 unsigned Depth) const override;
288
289 bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(
290 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
291 UndefPoisonKind Kind, unsigned Depth) const override;
292
293 ISD::NodeType getExtendForAtomicOps() const override {
294 return ISD::ANY_EXTEND;
295 }
296 ISD::NodeType getExtendForAtomicCmpSwapArg() const override {
297 return ISD::ZERO_EXTEND;
298 }
299
300 bool supportSwiftError() const override {
301 return true;
302 }
303
304 unsigned getStackProbeSize(const MachineFunction &MF) const;
305 bool hasAndNot(SDValue Y) const override;
306
307private:
308 const SystemZSubtarget &Subtarget;
309
310 // Implement LowerOperation for individual opcodes.
311 SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
312 const SDLoc &DL, EVT VT,
313 SDValue CmpOp0, SDValue CmpOp1, SDValue Chain) const;
314 SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL,
315 EVT VT, ISD::CondCode CC,
316 SDValue CmpOp0, SDValue CmpOp1,
317 SDValue Chain = SDValue(),
318 bool IsSignaling = false) const;
319 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
320 SDValue lowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG,
321 bool IsSignaling) const;
322 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
323 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
324 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
325 SelectionDAG &DAG) const;
326 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
327 SelectionDAG &DAG, unsigned Opcode,
328 SDValue GOTOffset) const;
329 SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
330 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
331 SelectionDAG &DAG) const;
332 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
333 SelectionDAG &DAG) const;
334 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
335 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
336 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
337 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
338 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
339 SDValue lowerVASTART_ELF(SDValue Op, SelectionDAG &DAG) const;
340 SDValue lowerVASTART_XPLINK(SDValue Op, SelectionDAG &DAG) const;
341 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
342 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
343 SDValue lowerDYNAMIC_STACKALLOC_ELF(SDValue Op, SelectionDAG &DAG) const;
344 SDValue lowerDYNAMIC_STACKALLOC_XPLINK(SDValue Op, SelectionDAG &DAG) const;
345 SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
346 SDValue lowerMULH(SDValue Op, SelectionDAG &DAG, unsigned Opcode) const;
347 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
348 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
349 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
350 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
351 SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const;
352 SDValue lowerUADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG) const;
353 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
354 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
355 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
356 SDValue lowerVECREDUCE_ADD(SDValue Op, SelectionDAG &DAG) const;
357 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
358 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
359 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
360 SDValue lowerATOMIC_LDST_I128(SDValue Op, SelectionDAG &DAG) const;
361 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
362 unsigned Opcode) const;
363 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
364 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
365 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
366 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
367 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
368 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
369 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
370 bool isVectorElementLoad(SDValue Op) const;
371 SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
372 SmallVectorImpl<SDValue> &Elems) const;
373 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
374 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
375 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
376 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
377 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
378 SDValue lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
379 SDValue lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
380 SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
381 SDValue lowerFSHL(SDValue Op, SelectionDAG &DAG) const;
382 SDValue lowerFSHR(SDValue Op, SelectionDAG &DAG) const;
383 SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
384 SDValue lower_FP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
385 SDValue lower_INT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
386 SDValue lowerLoadF16(SDValue Op, SelectionDAG &DAG) const;
387 SDValue lowerStoreF16(SDValue Op, SelectionDAG &DAG) const;
388
389 SDValue lowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
390 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
391 SDValue lowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
392
393 bool canTreatAsByteVector(EVT VT) const;
394 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
395 unsigned Index, DAGCombinerInfo &DCI,
396 bool Force) const;
397 SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
398 DAGCombinerInfo &DCI) const;
399 SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
400 SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
401 SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;
402 SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
403 bool canLoadStoreByteSwapped(EVT VT) const;
404 SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const;
405 SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
406 SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const;
407 SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
408 SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
409 SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
410 SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
411 SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const;
412 SDValue combineFCOPYSIGN(SDNode *N, DAGCombinerInfo &DCI) const;
413 SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
414 SDValue combineSETCC(SDNode *N, DAGCombinerInfo &DCI) const;
415 SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
416 SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
417 SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
418 SDValue combineShiftToMulAddHigh(SDNode *N, DAGCombinerInfo &DCI) const;
419 SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;
420 SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const;
421 SDValue combineINTRINSIC(SDNode *N, DAGCombinerInfo &DCI) const;
422
423 SDValue unwrapAddress(SDValue N) const override;
424
425 // Implement EmitInstrWithCustomInserter for individual operation types.
426 MachineBasicBlock *emitAdjCallStack(MachineInstr &MI,
427 MachineBasicBlock *BB) const;
428 MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
429 MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
430 unsigned StoreOpcode, unsigned STOCOpcode,
431 bool Invert) const;
432 MachineBasicBlock *emitICmp128Hi(MachineInstr &MI, MachineBasicBlock *BB,
433 bool Unsigned) const;
434 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
435 MachineBasicBlock *BB,
436 unsigned BinOpcode,
437 bool Invert = false) const;
438 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
439 MachineBasicBlock *MBB,
440 unsigned CompareOpcode,
441 unsigned KeepOldMask) const;
442 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
443 MachineBasicBlock *BB) const;
444 MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
445 unsigned Opcode,
446 bool IsMemset = false) const;
447 MachineBasicBlock *emitMemmoveImm(MachineInstr &MI,
448 MachineBasicBlock *BB) const;
449 MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
450 unsigned Opcode) const;
451 MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
452 MachineBasicBlock *MBB,
453 unsigned Opcode, bool NoFloat) const;
454 MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
455 MachineBasicBlock *MBB,
456 unsigned Opcode) const;
457 MachineBasicBlock *emitProbedAlloca(MachineInstr &MI,
458 MachineBasicBlock *MBB) const;
459 MachineBasicBlock *emitStackGuardPseudo(MachineInstr &MI,
460 MachineBasicBlock *MBB,
461 unsigned PseudoOp) const;
462 SDValue getBackchainAddress(SDValue SP, SelectionDAG &DAG) const;
463
464 MachineMemOperand::Flags
465 getTargetMMOFlags(const Instruction &I) const override;
466
467private:
468 bool enableNarrowIntArgsVerification() const;
469 bool isInternal(const Function *Fn) const;
470 mutable std::map<const Function *, bool> IsInternalCache;
471 void verifyNarrowIntegerArgs_Call(CallLoweringInfo &CLI,
472 const SmallVectorImpl<ISD::OutputArg> &Outs,
473 const Function *F, SDValue Callee) const;
474 void verifyNarrowIntegerArgs_Ret(CallingConv::ID CallConv,
475 const SmallVectorImpl<ISD::OutputArg> &Outs,
476 const Function *F) const;
477 bool verifyNarrowIntegerArgs(bool C_ABI,
478 const SmallVectorImpl<ISD::OutputArg> &Outs,
479 const Function *FunHeader, bool IsRet) const;
480
481public:
482};
483
484struct SystemZVectorConstantInfo {
485private:
486 APInt IntBits; // The 128 bits as an integer.
487 APInt SplatBits; // Smallest splat value.
488 APInt SplatUndef; // Bits correspoding to undef operands of the BVN.
489 unsigned SplatBitSize = 0;
490 bool isFP128 = false;
491public:
492 unsigned Opcode = 0;
493 SmallVector<unsigned, 2> OpVals;
494 MVT VecVT;
495 SystemZVectorConstantInfo(APInt IntImm);
496 SystemZVectorConstantInfo(APFloat FPImm)
497 : SystemZVectorConstantInfo(FPImm.bitcastToAPInt()) {
498 isFP128 = (&FPImm.getSemantics() == &APFloat::IEEEquad());
499 }
500 SystemZVectorConstantInfo(BuildVectorSDNode *BVN);
501 bool isVectorConstantLegal(const SystemZSubtarget &Subtarget);
502};
503
504} // end namespace llvm
505
506#endif
Imm
uint64_t Imm
Definition AMDGPUDisassembler.cpp:552
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
Results
Function Alias Analysis Results
Definition AliasAnalysis.cpp:802
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:870
Ops
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
Definition ItaniumDemangle.h:3392
RegName
#define RegName(no)
info
lazy value info
Definition LazyValueInfo.cpp:61
combineFP_ROUND
static SDValue combineFP_ROUND(SDValue N, const SDLoc &DL, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
Definition LoongArchISelLowering.cpp:769
F
#define F(x, y, z)
Definition MD5.cpp:54
I
#define I(x, y, z)
Definition MD5.cpp:57
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2128
combineLOAD
static SDValue combineLOAD(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const NVPTXSubtarget &STI)
Definition NVPTXISelLowering.cpp:6343
combineSTORE
static SDValue combineSTORE(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const NVPTXSubtarget &STI)
Definition NVPTXISelLowering.cpp:6328
emitSelect
static MachineBasicBlock * emitSelect(MachineInstr &MI, MachineBasicBlock *BB, const TargetInstrInfo *TII, const PPCSubtarget &Subtarget)
Emit SELECT instruction, using ISEL if available, otherwise use branch-based control flow.
Definition PPCISelLowering.cpp:14222
lowerBUILD_VECTOR
static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
Definition RISCVISelLowering.cpp:4799
CC
RISCVCC::CondCode CC
Definition RISCVLateBranchOpt.cpp:57
Y
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
TargetLowering.h
This file describes how to lower LLVM code to machine code.
lowerFRAMEADDR
static SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)
Definition VEISelLowering.cpp:1668
lowerRETURNADDR
static SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)
Definition VEISelLowering.cpp:1689
combineFP_EXTEND
static SDValue combineFP_EXTEND(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
Definition X86ISelLowering.cpp:63849
lowerVECTOR_SHUFFLE
static SDValue lowerVECTOR_SHUFFLE(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
Top-level lowering for x86 vector shuffles.
Definition X86ISelLowering.cpp:18653
llvm::APFloatBase::IEEEquad
static const fltSemantics & IEEEquad()
Definition APFloat.h:306
llvm::APFloat::getSemantics
const fltSemantics & getSemantics() const
Definition APFloat.h:1591
llvm::APInt
Class for arbitrary precision integers.
Definition APInt.h:78
llvm::ArrayRef
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition Instructions.h:774
llvm::BuildVectorSDNode
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Definition SelectionDAGNodes.h:2329
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition Instructions.h:1595
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition Constants.h:87
llvm::Constant
This is an important base class in LLVM.
Definition Constant.h:44
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition DataLayout.h:64
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition LLVMContext.h:76
llvm::LibcallLoweringInfo
Tracks which library functions to use for a particular subtarget or function.
Definition LibcallLoweringInfo.h:28
llvm::LoadInst
An instruction for reading from memory.
Definition Instructions.h:197
llvm::MVT
Machine Value Type.
Definition MachineValueType.h:36
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:74
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition MachineMemOperand.h:144
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition Module.h:68
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition SelectionDAGNodes.h:1252
llvm::SDNode
Represents one node in the SelectionDAG.
Definition SelectionDAGNodes.h:515
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition SelectionDAGNodes.h:147
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition SelectionDAG.h:227
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition SmallVector.h:594
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1261
llvm::StoreInst
An instruction for storing to memory.
Definition Instructions.h:338
llvm::StringRef
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
llvm::StringRef::size
constexpr size_t size() const
Get the string size.
Definition StringRef.h:144
llvm::SystemZTargetLowering::shouldExpandAtomicRMWInIR
AtomicExpansionKind shouldExpandAtomicRMWInIR(const AtomicRMWInst *RMW) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition SystemZISelLowering.cpp:1360
llvm::SystemZTargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition SystemZISelLowering.h:130
llvm::SystemZTargetLowering::isMaskAndCmp0FoldingBeneficial
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
Definition SystemZISelLowering.h:78
llvm::SystemZTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition SystemZISelLowering.cpp:7283
llvm::SystemZTargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Definition SystemZISelLowering.cpp:1566
llvm::SystemZTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition SystemZISelLowering.h:293
llvm::SystemZTargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode(const Module &M) const override
Override to support customized stack guard loading.
Definition SystemZISelLowering.h:223
llvm::SystemZTargetLowering::hasInlineStackProbe
bool hasInlineStackProbe(const MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
Definition SystemZISelLowering.cpp:1341
llvm::SystemZTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition SystemZISelLowering.cpp:11237
llvm::SystemZTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition SystemZISelLowering.h:82
llvm::SystemZTargetLowering::emitEHSjLjSetJmp
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition SystemZISelLowering.cpp:1094
llvm::SystemZTargetLowering::shouldCastAtomicLoadInIR
AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.
Definition SystemZISelLowering.cpp:1350
llvm::SystemZTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT) const override
Return the ValueType of the result of SETCC operations.
Definition SystemZISelLowering.cpp:934
llvm::SystemZTargetLowering::allowTruncateForTailCall
bool allowTruncateForTailCall(Type *, Type *) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
Definition SystemZISelLowering.cpp:1949
llvm::SystemZTargetLowering::LowerAsmOutputForConstraint
SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, const SDLoc &DL, const AsmOperandInfo &Constraint, SelectionDAG &DAG) const override
Definition SystemZISelLowering.cpp:1871
llvm::SystemZTargetLowering::preferSelectsOverBooleanArithmetic
bool preferSelectsOverBooleanArithmetic(EVT VT) const override
Should we prefer selects to doing arithmetic on boolean types.
Definition SystemZISelLowering.h:139
llvm::SystemZTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition SystemZISelLowering.cpp:2690
llvm::SystemZTargetLowering::preferZeroCompareBranch
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
Definition SystemZISelLowering.h:77
llvm::SystemZTargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition SystemZISelLowering.cpp:902
llvm::SystemZTargetLowering::emitEHSjLjLongJmp
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition SystemZISelLowering.cpp:1254
llvm::SystemZTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context, const Type *RetTy) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition SystemZISelLowering.cpp:2674
llvm::SystemZTargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AS, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition SystemZISelLowering.cpp:1328
llvm::SystemZTargetLowering::makeExternalCall
std::pair< SDValue, SDValue > makeExternalCall(SDValue Chain, SelectionDAG &DAG, const char *CalleeName, EVT RetVT, ArrayRef< SDValue > Ops, CallingConv::ID CallConv, bool IsSigned, SDLoc DL, bool DoesNotReturn, bool IsReturnValueUsed) const
Definition SystemZISelLowering.cpp:2643
llvm::SystemZTargetLowering::shouldConsiderGEPOffsetSplit
bool shouldConsiderGEPOffsetSplit() const override
Definition SystemZISelLowering.h:137
llvm::SystemZTargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M, const LibcallLoweringInfo &Libcalls) const override
Insert SSP declaration if global stack protector is used.
Definition SystemZISelLowering.cpp:11607
llvm::SystemZTargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition SystemZISelLowering.h:300
llvm::SystemZTargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition SystemZISelLowering.cpp:1954
llvm::SystemZTargetLowering::splitValueIntoRegisterParts
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Definition SystemZISelLowering.cpp:2058
llvm::SystemZTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition SystemZISelLowering.cpp:1510
llvm::SystemZTargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
Definition SystemZISelLowering.cpp:920
llvm::SystemZTargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode
bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, UndefPoisonKind Kind, unsigned Depth) const override
Return true if this function can prove that Op is never poison and, Kind can be used to track poison ...
Definition SystemZISelLowering.cpp:9829
llvm::SystemZTargetLowering::SystemZTargetLowering
SystemZTargetLowering(const TargetMachine &TM, const SystemZSubtarget &STI)
Definition SystemZISelLowering.cpp:93
llvm::SystemZTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition SystemZISelLowering.h:75
llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition SystemZISelLowering.cpp:941
llvm::SystemZTargetLowering::getFPImmAction
FPImmAction getFPImmAction(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns how the legalizer should materialize the specified FP immediate.
Definition SystemZISelLowering.cpp:1082
llvm::SystemZTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition SystemZISelLowering.cpp:1379
llvm::SystemZTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition SystemZISelLowering.cpp:1725
llvm::SystemZTargetLowering::getSingleConstraintMatchWeight
TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition SystemZISelLowering.cpp:1640
llvm::SystemZTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Determine if the target supports unaligned memory accesses.
Definition SystemZISelLowering.cpp:1389
llvm::SystemZTargetLowering::getScratchRegisters
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition SystemZISelLowering.cpp:1942
llvm::SystemZTargetLowering::getConstraintType
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition SystemZISelLowering.cpp:1593
llvm::SystemZTargetLowering::ShouldShrinkFPConstant
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Definition SystemZISelLowering.h:91
llvm::SystemZTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(ExceptionHandling EH, const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition SystemZISelLowering.cpp:1857
llvm::SystemZTargetLowering::joinRegisterPartsIntoValue
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
Definition SystemZISelLowering.cpp:2071
llvm::SystemZTargetLowering::getNumRegisters
unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT) const override
Return the number of registers that this ValueType will eventually require.
Definition SystemZISelLowering.h:58
llvm::SystemZTargetLowering::isTruncateFree
bool isTruncateFree(Type *, Type *) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition SystemZISelLowering.cpp:1572
llvm::SystemZTargetLowering::useLibCall
SDValue useLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, MVT VT, SDValue Arg, SDLoc DL, SDValue Chain, bool IsStrict) const
Definition SystemZISelLowering.cpp:7109
llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
Definition SystemZISelLowering.cpp:9775
llvm::SystemZTargetLowering::getExtendForAtomicCmpSwapArg
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
Definition SystemZISelLowering.h:296
llvm::SystemZTargetLowering::LowerOperationWrapper
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
Definition SystemZISelLowering.cpp:7496
llvm::SystemZTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition SystemZISelLowering.cpp:9504
llvm::SystemZTargetLowering::getInlineAsmMemConstraint
InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition SystemZISelLowering.h:174
llvm::SystemZTargetLowering::LowerCall
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition SystemZISelLowering.cpp:2417
llvm::SystemZTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition SystemZISelLowering.cpp:1384
llvm::SystemZTargetLowering::getJumpConditionMergingParams
CondMergingParams getJumpConditionMergingParams(Instruction::BinaryOps Opc, const Value *Lhs, const Value *Rhs, const Function *F) const override
Definition SystemZISelLowering.cpp:9061
llvm::SystemZTargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition SystemZISelLowering.cpp:856
llvm::SystemZTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition SystemZISelLowering.h:76
llvm::SystemZTargetLowering::findOptimalMemOpLowering
bool findOptimalMemOpLowering(LLVMContext &Context, std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes, EVT *LargestVT=nullptr) const override
Determines the optimal series of memory ops to replace the memset / memcpy.
Definition SystemZISelLowering.cpp:1538
llvm::SystemZTargetLowering::isProfitableToCombineMinNumMaxNum
bool isProfitableToCombineMinNumMaxNum(EVT VT) const override
Definition SystemZISelLowering.h:143
llvm::SystemZTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition SystemZISelLowering.cpp:7644
llvm::SystemZTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition SystemZISelLowering.cpp:1890
llvm::SystemZTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(ExceptionHandling EH, const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition SystemZISelLowering.cpp:1852
llvm::SystemZTargetLowering::getVectorTypeBreakdownForCallingConv
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
Definition SystemZISelLowering.cpp:881
llvm::SystemZTargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition SystemZISelLowering.h:47
llvm::SystemZTargetLowering::aggressivelyPreferBuildVectorSources
bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override
Definition SystemZISelLowering.cpp:1334
llvm::SystemZTargetLowering::shouldCastAtomicStoreInIR
AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.
Definition SystemZISelLowering.cpp:1355
llvm::SystemZTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition SystemZISelLowering.cpp:1839
llvm::SystemZTargetLowering::hasAndNot
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
Definition SystemZISelLowering.cpp:1399
llvm::SystemZTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition SystemZISelLowering.cpp:2105
llvm::SystemZTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition SystemZISelLowering.cpp:9657
llvm::SystemZTargetLowering::getStackProbeSize
unsigned getStackProbeSize(const MachineFunction &MF) const
Definition SystemZISelLowering.cpp:9841
llvm::SystemZTargetLowering::getVectorIdxWidth
unsigned getVectorIdxWidth(const DataLayout &DL) const override
Returns the type to be used for the index operand vector operations.
Definition SystemZISelLowering.h:50
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition TargetLowering.h:232
llvm::TargetLoweringBase::getNumRegisters
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
Definition TargetLowering.h:1946
llvm::TargetLoweringBase::FPImmAction
FPImmAction
How the legalizer should materialize a floating-point immediate.
Definition TargetLowering.h:1313
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition TargetLowering.h:275
llvm::TargetLowering::getInlineAsmMemConstraint
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition TargetLowering.h:5610
llvm::TargetLowering::TargetLowering
TargetLowering(const TargetLowering &)=delete
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition TargetMachine.h:84
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition TargetRegisterInfo.h:74
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:46
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition User.h:207
llvm::Value
LLVM Value Representation.
Definition Value.h:75
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition ISDOpcodes.h:43
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition ISDOpcodes.h:879
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition ISDOpcodes.h:876
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition ISDOpcodes.h:1817
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition DefaultTargetInfo.h:21
llvm::NoCommonBitsSetResult::Known
@ Known
Known to have no common set bits.
Definition ValueTracking.h:126
llvm::dyn_cast
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:643
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
llvm::Fast
@ Fast
Assign the register banks as fast as possible (default).
Definition RegBankSelect.h:79
llvm::Op
DWARFExpression::Operation Op
Definition DWARFExpressionPrinter.cpp:25
llvm::ExceptionHandling
ExceptionHandling
Definition CodeGen.h:54
llvm::UndefPoisonKind
UndefPoisonKind
Enumeration to track whether we are interested in Undef, Poison, or both.
Definition UndefPoison.h:20
N
#define N
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
llvm::EVT
Extended Value Type.
Definition ValueTypes.h:35
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition ValueTypes.h:165
llvm::SystemZVectorConstantInfo::OpVals
SmallVector< unsigned, 2 > OpVals
Definition SystemZISelLowering.h:493
llvm::SystemZVectorConstantInfo::isVectorConstantLegal
bool isVectorConstantLegal(const SystemZSubtarget &Subtarget)
Definition SystemZISelLowering.cpp:966
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