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14 using namespace MIPatternMatch;
16 std::pair<Register, unsigned>
20 return std::make_pair(
Reg, 0);
22 if (
Def->getOpcode() == TargetOpcode::G_CONSTANT) {
28 Offset =
Op.getCImm()->getZExtValue();
30 return std::make_pair(
Register(), Offset);
34 if (
Def->getOpcode() == TargetOpcode::G_ADD) {
37 return std::make_pair(
Def->getOperand(1).getReg(), Offset);
41 return std::make_pair(
Def->getOperand(1).getReg(), Offset);
45 if (
Def->getOpcode() == TargetOpcode::G_PTRTOINT) {
50 if (
Base->getOpcode() == TargetOpcode::G_INTTOPTR)
51 return std::make_pair(
Base->getOperand(1).getReg(), Offset);
54 return std::make_pair(
Base->getOperand(0).getReg(), Offset);
58 return std::make_pair(
Reg, 0);
67 return (
Mask[0] & 2) == (
Mask[1] & 2);
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
This is an optimization pass for GlobalISel generic memory operations.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Reg
All possible values of the reg field in the ModR/M byte.
BinaryOp_match< LHS, RHS, TargetOpcode::G_PTR_ADD, false > m_GPtrAdd(const LHS &L, const RHS &R)
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
MachineOperand class - Representation of each machine instruction operand.
bind_ty< MachineInstr * > m_MInstr(MachineInstr *&MI)
Representation of each machine instruction.
std::pair< Register, unsigned > getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg)
Returns base register and constant offset.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
UnaryOp_match< SrcTy, TargetOpcode::COPY > m_Copy(SrcTy &&Src)
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
ConstantMatch< APInt > m_ICst(APInt &Cst)
bool isLegalVOP3PShuffleMask(ArrayRef< int > Mask)
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)