LLVM 20.0.0git
AMDGPUGlobalISelUtils.cpp
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1//===- AMDGPUGlobalISelUtils.cpp ---------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
12#include "llvm/ADT/DenseSet.h"
18#include "llvm/IR/Constants.h"
19#include "llvm/IR/IntrinsicsAMDGPU.h"
20
21using namespace llvm;
22using namespace AMDGPU;
23using namespace MIPatternMatch;
24
25std::pair<Register, unsigned>
27 GISelKnownBits *KnownBits, bool CheckNUW) {
29 if (Def->getOpcode() == TargetOpcode::G_CONSTANT) {
30 unsigned Offset;
31 const MachineOperand &Op = Def->getOperand(1);
32 if (Op.isImm())
33 Offset = Op.getImm();
34 else
35 Offset = Op.getCImm()->getZExtValue();
36
37 return std::pair(Register(), Offset);
38 }
39
40 int64_t Offset;
41 if (Def->getOpcode() == TargetOpcode::G_ADD) {
42 // A 32-bit (address + offset) should not cause unsigned 32-bit integer
43 // wraparound, because s_load instructions perform the addition in 64 bits.
44 if (CheckNUW && !Def->getFlag(MachineInstr::NoUWrap)) {
45 assert(MRI.getType(Reg).getScalarSizeInBits() == 32);
46 return std::pair(Reg, 0);
47 }
48 // TODO: Handle G_OR used for add case
49 if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
50 return std::pair(Def->getOperand(1).getReg(), Offset);
51
52 // FIXME: matcher should ignore copies
53 if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
54 return std::pair(Def->getOperand(1).getReg(), Offset);
55 }
56
58 if (KnownBits && mi_match(Reg, MRI, m_GOr(m_Reg(Base), m_ICst(Offset))) &&
59 KnownBits->maskedValueIsZero(Base, APInt(32, Offset)))
60 return std::pair(Base, Offset);
61
62 // Handle G_PTRTOINT (G_PTR_ADD base, const) case
63 if (Def->getOpcode() == TargetOpcode::G_PTRTOINT) {
65 if (mi_match(Def->getOperand(1).getReg(), MRI,
67 // If Base was int converted to pointer, simply return int and offset.
68 if (Base->getOpcode() == TargetOpcode::G_INTTOPTR)
69 return std::pair(Base->getOperand(1).getReg(), Offset);
70
71 // Register returned here will be of pointer type.
72 return std::pair(Base->getOperand(0).getReg(), Offset);
73 }
74 }
75
76 return std::pair(Reg, 0);
77}
78
80 : MRI(MF.getRegInfo()) {
81 initLaneMaskIntrinsics(MF);
82}
83
85 return S32S64LaneMask.contains(Reg);
86}
87
88void IntrinsicLaneMaskAnalyzer::initLaneMaskIntrinsics(MachineFunction &MF) {
89 for (auto &MBB : MF) {
90 for (auto &MI : MBB) {
91 GIntrinsic *GI = dyn_cast<GIntrinsic>(&MI);
92 if (GI && GI->is(Intrinsic::amdgcn_if_break)) {
93 S32S64LaneMask.insert(MI.getOperand(3).getReg());
94 findLCSSAPhi(MI.getOperand(0).getReg());
95 }
96
97 if (MI.getOpcode() == AMDGPU::SI_IF ||
98 MI.getOpcode() == AMDGPU::SI_ELSE) {
99 findLCSSAPhi(MI.getOperand(0).getReg());
100 }
101 }
102 }
103}
104
105void IntrinsicLaneMaskAnalyzer::findLCSSAPhi(Register Reg) {
106 S32S64LaneMask.insert(Reg);
107 for (const MachineInstr &LCSSAPhi : MRI.use_instructions(Reg)) {
108 if (LCSSAPhi.isPHI())
109 S32S64LaneMask.insert(LCSSAPhi.getOperand(0).getReg());
110 }
111}
112
114 if (Ty.isVector()) {
115 LLT ElTy = Ty.getElementType();
116 if (ElTy.getSizeInBits() == 16)
117 return LLT::fixed_vector(2, ElTy);
118 // S32, S64 or pointer
119 return ElTy;
120 }
121
122 // Large scalars and 64-bit pointers
123 return LLT::scalar(32);
124}
125
127 const RegisterBankInfo &RBI);
128
130 SmallVectorImpl<Register> &SgprDstParts,
131 LLT UnmergeTy, Register VgprSrc,
132 const RegisterBankInfo &RBI) {
133 const RegisterBank *VgprRB = &RBI.getRegBank(AMDGPU::VGPRRegBankID);
134 auto Unmerge = B.buildUnmerge({VgprRB, UnmergeTy}, VgprSrc);
135 for (unsigned i = 0; i < Unmerge->getNumOperands() - 1; ++i) {
136 SgprDstParts.push_back(buildReadAnyLane(B, Unmerge.getReg(i), RBI));
137 }
138}
139
141 const RegisterBankInfo &RBI) {
142 LLT Ty = B.getMRI()->getType(VgprSrc);
143 const RegisterBank *SgprRB = &RBI.getRegBank(AMDGPU::SGPRRegBankID);
144 if (Ty.getSizeInBits() == 32) {
145 return B.buildInstr(AMDGPU::G_AMDGPU_READANYLANE, {{SgprRB, Ty}}, {VgprSrc})
146 .getReg(0);
147 }
148
149 SmallVector<Register, 8> SgprDstParts;
150 unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI);
151
152 return B.buildMergeLikeInstr({SgprRB, Ty}, SgprDstParts).getReg(0);
153}
154
156 Register VgprSrc, const RegisterBankInfo &RBI) {
157 LLT Ty = B.getMRI()->getType(VgprSrc);
158 if (Ty.getSizeInBits() == 32) {
159 B.buildInstr(AMDGPU::G_AMDGPU_READANYLANE, {SgprDst}, {VgprSrc});
160 return;
161 }
162
163 SmallVector<Register, 8> SgprDstParts;
164 unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI);
165
166 B.buildMergeLikeInstr(SgprDst, SgprDstParts).getReg(0);
167}
unsigned const MachineRegisterInfo * MRI
static LLT getReadAnyLaneSplitTy(LLT Ty)
static void unmergeReadAnyLane(MachineIRBuilder &B, SmallVectorImpl< Register > &SgprDstParts, LLT UnmergeTy, Register VgprSrc, const RegisterBankInfo &RBI)
Provides AMDGPU specific target descriptions.
This file declares the targeting of the RegisterBankInfo class for AMDGPU.
MachineBasicBlock & MBB
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
This file defines the DenseSet and SmallDenseSet classes.
Provides analysis for querying information about KnownBits during GISel passes.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
IRTranslator LLVM IR MI
Implement a low-level type suitable for MachineInstr level instruction selection.
Contains matchers for matching SSA Machine Instructions.
This file declares the MachineIRBuilder class.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Class for arbitrary precision integers.
Definition: APInt.h:78
This class represents an Operation in the Expression.
Represents a call to an intrinsic.
bool is(Intrinsic::ID ID) const
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
constexpr bool isVector() const
Definition: LowLevelType.h:148
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:190
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelType.h:277
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelType.h:100
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:71
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
Holds all the information related to register banks.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
void push_back(const T &Elt)
Definition: SmallVector.h:413
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1196
void buildReadAnyLane(MachineIRBuilder &B, Register SgprDst, Register VgprSrc, const RegisterBankInfo &RBI)
std::pair< Register, unsigned > getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg, GISelKnownBits *KnownBits=nullptr, bool CheckNUW=false)
Returns base register and constant offset.
operand_type_match m_Reg()
UnaryOp_match< SrcTy, TargetOpcode::COPY > m_Copy(SrcTy &&Src)
ConstantMatch< APInt > m_ICst(APInt &Cst)
BinaryOp_match< LHS, RHS, TargetOpcode::G_OR, true > m_GOr(const LHS &L, const RHS &R)
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
BinaryOp_match< LHS, RHS, TargetOpcode::G_PTR_ADD, false > m_GPtrAdd(const LHS &L, const RHS &R)
bind_ty< MachineInstr * > m_MInstr(MachineInstr *&MI)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:486