LLVM  12.0.0git
AMDGPUGlobalISelUtils.cpp
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1 //===- AMDGPUGlobalISelUtils.cpp ---------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
11 #include "llvm/IR/Constants.h"
12 
13 using namespace llvm;
14 using namespace MIPatternMatch;
15 
16 std::tuple<Register, unsigned, MachineInstr *>
19  if (!Def)
20  return std::make_tuple(Reg, 0, nullptr);
21 
22  if (Def->getOpcode() == TargetOpcode::G_CONSTANT) {
23  unsigned Offset;
24  const MachineOperand &Op = Def->getOperand(1);
25  if (Op.isImm())
26  Offset = Op.getImm();
27  else
28  Offset = Op.getCImm()->getZExtValue();
29 
30  return std::make_tuple(Register(), Offset, Def);
31  }
32 
33  int64_t Offset;
34  if (Def->getOpcode() == TargetOpcode::G_ADD) {
35  // TODO: Handle G_OR used for add case
36  if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
37  return std::make_tuple(Def->getOperand(1).getReg(), Offset, Def);
38 
39  // FIXME: matcher should ignore copies
40  if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
41  return std::make_tuple(Def->getOperand(1).getReg(), Offset, Def);
42  }
43 
44  return std::make_tuple(Reg, 0, Def);
45 }
46 
48  assert(Mask.size() == 2);
49 
50  // If one half is undef, the other is trivially in the same reg.
51  if (Mask[0] == -1 || Mask[1] == -1)
52  return true;
53  return (Mask[0] & 2) == (Mask[1] & 2);
54 }
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned Reg
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:366
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:456
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
UnaryOp_match< SrcTy, TargetOpcode::COPY > m_Copy(SrcTy &&Src)
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:142
unsigned const MachineRegisterInfo * MRI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:156
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isLegalVOP3PShuffleMask(ArrayRef< int > Mask)
MachineOperand class - Representation of each machine instruction operand.
Promote Memory to Register
Definition: Mem2Reg.cpp:110
std::tuple< Register, unsigned, MachineInstr * > getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg)
Returns Base register, constant offset, and offset def point.
int64_t getImm() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:62
ConstantMatch m_ICst(int64_t &Cst)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:466
const ConstantInt * getCImm() const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19