17using namespace MIPatternMatch;
19std::pair<Register, unsigned>
23 if (Def->getOpcode() == TargetOpcode::G_CONSTANT) {
29 Offset =
Op.getCImm()->getZExtValue();
35 if (Def->getOpcode() == TargetOpcode::G_ADD) {
39 assert(
MRI.getType(Reg).getScalarSizeInBits() == 32);
40 return std::pair(Reg, 0);
44 return std::pair(Def->getOperand(1).getReg(),
Offset);
48 return std::pair(Def->getOperand(1).getReg(),
Offset);
57 if (Def->getOpcode() == TargetOpcode::G_PTRTOINT) {
62 if (
Base->getOpcode() == TargetOpcode::G_INTTOPTR)
63 return std::pair(
Base->getOperand(1).getReg(),
Offset);
66 return std::pair(
Base->getOperand(0).getReg(),
Offset);
70 return std::pair(Reg, 0);
unsigned const MachineRegisterInfo * MRI
This file contains the declarations for the subclasses of Constant, which represent the different fla...
AMD GCN specific subclass of TargetSubtarget.
Provides analysis for querying information about KnownBits during GISel passes.
Implement a low-level type suitable for MachineInstr level instruction selection.
Contains matchers for matching SSA Machine Instructions.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Class for arbitrary precision integers.
This class represents an Operation in the Expression.
bool hasGFX90AInsts() const
bool hasAtomicFaddRtnInsts() const
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
bool hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget, const LLT &Ty)
std::pair< Register, unsigned > getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg, GISelKnownBits *KnownBits=nullptr, bool CheckNUW=false)
Returns base register and constant offset.
operand_type_match m_Reg()
UnaryOp_match< SrcTy, TargetOpcode::COPY > m_Copy(SrcTy &&Src)
ConstantMatch< APInt > m_ICst(APInt &Cst)
BinaryOp_match< LHS, RHS, TargetOpcode::G_OR, true > m_GOr(const LHS &L, const RHS &R)
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
BinaryOp_match< LHS, RHS, TargetOpcode::G_PTR_ADD, false > m_GPtrAdd(const LHS &L, const RHS &R)
bind_ty< MachineInstr * > m_MInstr(MachineInstr *&MI)
This is an optimization pass for GlobalISel generic memory operations.
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.