AMDGPURegBankSelect.cpp File Reference

#include "AMDGPU.h"
#include "AMDGPUGlobalISelUtils.h"
#include "GCNSubtarget.h"
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
#include "llvm/CodeGen/MachineUniformityAnalysis.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/InitializePasses.h"

Go to the source code of this file.

Classes
class	RegBankSelectHelper

Macros
#define	DEBUG_TYPE   "amdgpu-regbankselect"
	Assign register banks to all register operands of G_ instructions using machine uniformity analysis.

Functions
	INITIALIZE_PASS_BEGIN (AMDGPURegBankSelect, DEBUG_TYPE, "AMDGPU Register Bank Select", false, false) INITIALIZE_PASS_END(AMDGPURegBankSelect
static Register	getVReg (MachineOperand &Op)

Variables
	DEBUG_TYPE
AMDGPU Register Bank	Select
AMDGPU Register Bank	false

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-regbankselect"

Assign register banks to all register operands of G_ instructions using machine uniformity analysis.

Sgpr - uniform values and some lane masks Vgpr - divergent, non S1, values Vcc - divergent S1 values(lane masks) However in some cases G_ instructions with this register bank assignment can't be inst-selected. This is solved in AMDGPURegBankLegalize.

Definition at line 27 of file AMDGPURegBankSelect.cpp.

Function Documentation

getVReg()

Register getVReg ( MachineOperand & Op )

static

Definition at line 188 of file AMDGPURegBankSelect.cpp.

References Reg.

INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN	(	AMDGPURegBankSelect	,
		DEBUG_TYPE	,
		"AMDGPU Register Bank Select"	,
		false	,
		false	)

References DEBUG_TYPE, and INITIALIZE_PASS_DEPENDENCY.

Variable Documentation

DEBUG_TYPE

DEBUG_TYPE

Definition at line 67 of file AMDGPURegBankSelect.cpp.

false

AMDGPU Register Bank false

Definition at line 68 of file AMDGPURegBankSelect.cpp.

Select

AMDGPU Register Bank Select

Definition at line 68 of file AMDGPURegBankSelect.cpp.

Referenced by llvm::CombinerHelper::applyFoldBinOpIntoSelect(), llvm::InstCombinerImpl::canonicalizeCondSignextOfHighBitExtractToSignextHighBitExtract(), combineAdd(), combineMulSelectConstOne(), combineSelect(), constantFold(), llvm::VPlanTransforms::convertToConcreteRecipes(), llvm::createMinMaxOp(), llvm::VPBuilder::createSelect(), llvm::logicalview::LVReader::doLoad(), llvm::VPReductionRecipe::execute(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandVPCTTZElements(), llvm::InstCombinerImpl::foldICmpSelectConstant(), llvm::InstCombinerImpl::foldVectorSelect(), getV_CMPOpcode(), getValueOnFirstIteration(), INITIALIZE_PASS(), llvm::SIInstrInfo::insertSelect(), instCombineSVESel(), llvm::TargetLoweringBase::InstructionOpcodeToISD(), llvm::RecurrenceDescriptor::isAnyOfPattern(), isFixedVectorShuffle(), llvm::RecurrenceDescriptor::isMinMaxPattern(), isSignedMinMaxClamp(), LowerBUILD_VECTORvXi1(), lowerDisjointIndicesShuffle(), LowerMLOAD(), lowerSELECT(), llvm::PatternMatch::LogicalOp_match< LHS, RHS, Opcode, Commutable >::match(), llvm::CombinerHelper::matchCastOfSelect(), llvm::CombinerHelper::matchFoldBinOpIntoSelect(), llvm::CombinerHelper::matchSelect(), llvm::CombinerHelper::matchSelectIMinMax(), llvm::LegalizerHelper::narrowScalarSelect(), llvm::RISCVTargetLowering::PerformDAGCombine(), simplifySwitchOnSelectUsingRanges(), tryToRecognizeTableBasedCttz(), upgradeMaskedMove(), llvm::InstCombinerImpl::visitCallInst(), llvm::InstCombinerImpl::visitSub(), and llvm::InstCombinerImpl::visitSwitchInst().