22#define DEBUG_TYPE "loongarch-isel"
23#define PASS_NAME "LoongArch DAG->DAG Pattern Instruction Selection"
36 if (
Node->isMachineOpcode()) {
44 unsigned Opcode =
Node->getOpcode();
45 MVT GRLenVT = Subtarget->getGRLenVT();
47 MVT VT =
Node->getSimpleValueType(0);
53 int64_t Imm = cast<ConstantSDNode>(
Node)->getSExtValue();
54 if (Imm == 0 && VT == GRLenVT) {
55 SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
DL,
56 LoongArch::R0, GRLenVT);
57 ReplaceNode(
Node, New.getNode());
61 SDValue SrcReg = CurDAG->getRegister(LoongArch::R0, GRLenVT);
64 SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm,
DL, GRLenVT);
65 if (Inst.Opc == LoongArch::LU12I_W)
66 Result = CurDAG->getMachineNode(LoongArch::LU12I_W,
DL, GRLenVT, SDImm);
68 Result = CurDAG->getMachineNode(Inst.Opc,
DL, GRLenVT, SrcReg, SDImm);
72 ReplaceNode(
Node, Result);
76 SDValue Imm = CurDAG->getTargetConstant(0,
DL, GRLenVT);
77 int FI = cast<FrameIndexSDNode>(
Node)->getIndex();
78 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
80 Subtarget->is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
81 ReplaceNode(
Node, CurDAG->getMachineNode(ADDIOp,
DL, VT, TFI, Imm));
87 CurDAG->RemoveDeadNode(
Node);
96 APInt SplatValue, SplatUndef;
97 unsigned SplatBitSize;
104 if (!Subtarget->hasExtLSX() || (!Is128Vec && !Is256Vec))
110 switch (SplatBitSize) {
114 Op = Is256Vec ? LoongArch::PseudoXVREPLI_B : LoongArch::PseudoVREPLI_B;
115 ViaVecTy = Is256Vec ? MVT::v32i8 : MVT::v16i8;
118 Op = Is256Vec ? LoongArch::PseudoXVREPLI_H : LoongArch::PseudoVREPLI_H;
119 ViaVecTy = Is256Vec ? MVT::v16i16 : MVT::v8i16;
122 Op = Is256Vec ? LoongArch::PseudoXVREPLI_W : LoongArch::PseudoVREPLI_W;
123 ViaVecTy = Is256Vec ? MVT::v8i32 : MVT::v4i32;
126 Op = Is256Vec ? LoongArch::PseudoXVREPLI_D : LoongArch::PseudoVREPLI_D;
127 ViaVecTy = Is256Vec ? MVT::v4i64 : MVT::v2i64;
134 SDValue Imm = CurDAG->getTargetConstant(SplatValue,
DL,
136 Res = CurDAG->getMachineNode(
Op,
DL, ViaVecTy, Imm);
137 ReplaceNode(
Node, Res);
150 std::vector<SDValue> &OutOps) {
154 switch (ConstraintID) {
189 OutOps.push_back(
Base);
197 if (
auto *FIN = dyn_cast<FrameIndexSDNode>(
Addr))
209 MVT VT =
Addr.getSimpleValueType();
211 if (!isa<ConstantSDNode>(
Addr))
216 int64_t CVal = cast<ConstantSDNode>(
Addr)->getSExtValue();
217 if (!isInt<12>(CVal))
226 if (isa<FrameIndexSDNode>(
Addr))
237 if (
N.getOpcode() ==
ISD::AND && isa<ConstantSDNode>(
N.getOperand(1))) {
238 const APInt &AndMask =
N->getConstantOperandAPInt(1);
246 ShAmt =
N.getOperand(0);
254 ShAmt =
N.getOperand(0);
261 assert(isa<ConstantSDNode>(
N.getOperand(1)) &&
"Illegal msb operand!");
262 assert(isa<ConstantSDNode>(
N.getOperand(2)) &&
"Illegal lsb operand!");
263 uint64_t msb =
N.getConstantOperandVal(1), lsb =
N.getConstantOperandVal(2);
264 if (lsb == 0 &&
Log2_32(ShiftWidth) <= msb + 1) {
265 ShAmt =
N.getOperand(0);
269 isa<ConstantSDNode>(
N.getOperand(0))) {
270 uint64_t Imm =
N.getConstantOperandVal(0);
273 if (Imm != 0 && Imm % ShiftWidth == 0) {
275 EVT VT =
N.getValueType();
278 unsigned NegOpc = VT == MVT::i64 ? LoongArch::SUB_D : LoongArch::SUB_W;
292 cast<VTSDNode>(
N.getOperand(1))->getVT() == MVT::i32) {
293 Val =
N.getOperand(0);
297 N.getConstantOperandVal(1) < UINT64_C(0X1F) &&
298 N.getConstantOperandVal(2) == UINT64_C(0)) {
302 MVT VT =
N.getSimpleValueType();
313 auto *
C = dyn_cast<ConstantSDNode>(
N.getOperand(1));
314 if (
C &&
C->getZExtValue() == UINT64_C(0xFFFFFFFF)) {
315 Val =
N.getOperand(0);
319 MVT VT =
N.getSimpleValueType();
330 unsigned MinSizeInBits)
const {
331 if (!Subtarget->hasExtLSX())
339 APInt SplatValue, SplatUndef;
340 unsigned SplatBitSize;
343 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
344 MinSizeInBits,
false))
352template <
unsigned ImmBitSize,
bool IsSigned>
355 EVT EltTy =
N->getValueType(0).getVectorElementType();
358 N =
N->getOperand(0);
367 if (!IsSigned && ImmValue.
isIntN(ImmBitSize)) {
380 EVT EltTy =
N->getValueType(0).getVectorElementType();
383 N =
N->getOperand(0);
387 int32_t
Log2 = (~ImmValue).exactLogBase2();
401 EVT EltTy =
N->getValueType(0).getVectorElementType();
404 N =
N->getOperand(0);
amdgpu AMDGPU Register Bank Select
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
DEMANGLE_DUMP_METHOD void dump() const
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
unsigned getBitWidth() const
Return the number of bits in the APInt.
int32_t exactLogBase2() const
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
bool isIntN(unsigned N) const
Check if this APInt has an N-bits unsigned integer value.
int64_t getSExtValue() const
Get sign extended value.
A "pseudo-class" with methods for operating on BUILD_VECTORs.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector.
uint64_t getZExtValue() const
int64_t getSExtValue() const
This class represents an Operation in the Expression.
FunctionPass class - This class is used to implement most global optimizations.
LoongArchDAGToDAGISelLegacy(LoongArchTargetMachine &TM)
bool selectNonFIBaseAddr(SDValue Addr, SDValue &Base)
bool selectSExti32(SDValue N, SDValue &Val)
bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
bool selectVSplatUimmPow2(SDValue N, SDValue &SplatImm) const
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
bool selectZExti32(SDValue N, SDValue &Val)
bool SelectAddrConstant(SDValue Addr, SDValue &Base, SDValue &Offset)
bool selectVSplat(SDNode *N, APInt &Imm, unsigned MinSizeInBits) const
bool selectVSplatImm(SDValue N, SDValue &SplatVal)
bool selectVSplatUimmInvPow2(SDValue N, SDValue &SplatImm) const
bool SelectBaseAddr(SDValue Addr, SDValue &Base)
bool is128BitVector() const
Return true if this is a 128-bit vector type.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
bool is256BitVector() const
Return true if this is a 256-bit vector type.
An SDNode that represents everything that will be needed to construct a MachineInstr.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue getTargetFrameIndex(int FI, EVT VT)
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits.
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side,...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
InstSeq generateInstSeq(int64_t Val)
This is an optimization pass for GlobalISel generic memory operations.
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
FunctionPass * createLoongArchISelDag(LoongArchTargetMachine &TM)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
DWARFExpression::Operation Op
unsigned Log2(Align A)
Returns the log2 of the alignment.
Implement std::hash so that hash_code can be used in STL containers.
This struct is a compact representation of a valid (non-zero power of two) alignment.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
bool is128BitVector() const
Return true if this is a 128-bit vector type.
bool is256BitVector() const
Return true if this is a 256-bit vector type.
EVT getVectorElementType() const
Given a vector type, return the type of each element.