LLVM 17.0.0git
LoongArchISelDAGToDAG.h
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1//=- LoongArchISelDAGToDAG.h - A dag to dag inst selector for LoongArch ---===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines an instruction selector for the LoongArch target.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELDAGTODAG_H
14#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELDAGTODAG_H
15
16#include "LoongArch.h"
19
20// LoongArch-specific code to select LoongArch machine instructions for
21// SelectionDAG operations.
22namespace llvm {
24 const LoongArchSubtarget *Subtarget = nullptr;
25
26public:
27 static char ID;
28
30
33
35 Subtarget = &MF.getSubtarget<LoongArchSubtarget>();
37 }
38
39 void Select(SDNode *Node) override;
40
41 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
42 std::vector<SDValue> &OutOps) override;
43
46
47 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
49 return selectShiftMask(N, Subtarget->getGRLen(), ShAmt);
50 }
52 return selectShiftMask(N, 32, ShAmt);
53 }
54
55 bool selectSExti32(SDValue N, SDValue &Val);
56 bool selectZExti32(SDValue N, SDValue &Val);
57
58// Include the pieces autogenerated from the target description.
59#include "LoongArchGenDAGISel.inc"
60};
61
62} // end namespace llvm
63
64#endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELDAGTODAG_H
amdgpu AMDGPU Register Bank Select
uint64_t Addr
bool selectNonFIBaseAddr(SDValue Addr, SDValue &Base)
bool selectShiftMask32(SDValue N, SDValue &ShAmt)
bool selectSExti32(SDValue N, SDValue &Val)
LoongArchDAGToDAGISel(LoongArchTargetMachine &TM)
bool selectShiftMaskGRLen(SDValue N, SDValue &ShAmt)
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
bool selectZExti32(SDValue N, SDValue &Val)
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool SelectBaseAddr(SDValue Addr, SDValue &Base)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
MachineFunction * MF
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
#define N