LLVM  9.0.0svn
InstCombineSimplifyDemanded.cpp
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1 //===- InstCombineSimplifyDemanded.cpp ------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains logic for simplifying instructions based on information
10 // about how they are used.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "InstCombineInternal.h"
16 #include "llvm/IR/IntrinsicInst.h"
17 #include "llvm/IR/PatternMatch.h"
18 #include "llvm/Support/KnownBits.h"
19 
20 using namespace llvm;
21 using namespace llvm::PatternMatch;
22 
23 #define DEBUG_TYPE "instcombine"
24 
25 namespace {
26 
27 struct AMDGPUImageDMaskIntrinsic {
28  unsigned Intr;
29 };
30 
31 #define GET_AMDGPUImageDMaskIntrinsicTable_IMPL
32 #include "InstCombineTables.inc"
33 
34 } // end anonymous namespace
35 
36 /// Check to see if the specified operand of the specified instruction is a
37 /// constant integer. If so, check to see if there are any bits set in the
38 /// constant that are not demanded. If so, shrink the constant and return true.
39 static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo,
40  const APInt &Demanded) {
41  assert(I && "No instruction?");
42  assert(OpNo < I->getNumOperands() && "Operand index too large");
43 
44  // The operand must be a constant integer or splat integer.
45  Value *Op = I->getOperand(OpNo);
46  const APInt *C;
47  if (!match(Op, m_APInt(C)))
48  return false;
49 
50  // If there are no bits set that aren't demanded, nothing to do.
51  if (C->isSubsetOf(Demanded))
52  return false;
53 
54  // This instruction is producing bits that are not demanded. Shrink the RHS.
55  I->setOperand(OpNo, ConstantInt::get(Op->getType(), *C & Demanded));
56 
57  return true;
58 }
59 
60 
61 
62 /// Inst is an integer instruction that SimplifyDemandedBits knows about. See if
63 /// the instruction has any properties that allow us to simplify its operands.
64 bool InstCombiner::SimplifyDemandedInstructionBits(Instruction &Inst) {
65  unsigned BitWidth = Inst.getType()->getScalarSizeInBits();
66  KnownBits Known(BitWidth);
67  APInt DemandedMask(APInt::getAllOnesValue(BitWidth));
68 
69  Value *V = SimplifyDemandedUseBits(&Inst, DemandedMask, Known,
70  0, &Inst);
71  if (!V) return false;
72  if (V == &Inst) return true;
73  replaceInstUsesWith(Inst, V);
74  return true;
75 }
76 
77 /// This form of SimplifyDemandedBits simplifies the specified instruction
78 /// operand if possible, updating it in place. It returns true if it made any
79 /// change and false otherwise.
80 bool InstCombiner::SimplifyDemandedBits(Instruction *I, unsigned OpNo,
81  const APInt &DemandedMask,
82  KnownBits &Known,
83  unsigned Depth) {
84  Use &U = I->getOperandUse(OpNo);
85  Value *NewVal = SimplifyDemandedUseBits(U.get(), DemandedMask, Known,
86  Depth, I);
87  if (!NewVal) return false;
88  U = NewVal;
89  return true;
90 }
91 
92 
93 /// This function attempts to replace V with a simpler value based on the
94 /// demanded bits. When this function is called, it is known that only the bits
95 /// set in DemandedMask of the result of V are ever used downstream.
96 /// Consequently, depending on the mask and V, it may be possible to replace V
97 /// with a constant or one of its operands. In such cases, this function does
98 /// the replacement and returns true. In all other cases, it returns false after
99 /// analyzing the expression and setting KnownOne and known to be one in the
100 /// expression. Known.Zero contains all the bits that are known to be zero in
101 /// the expression. These are provided to potentially allow the caller (which
102 /// might recursively be SimplifyDemandedBits itself) to simplify the
103 /// expression.
104 /// Known.One and Known.Zero always follow the invariant that:
105 /// Known.One & Known.Zero == 0.
106 /// That is, a bit can't be both 1 and 0. Note that the bits in Known.One and
107 /// Known.Zero may only be accurate for those bits set in DemandedMask. Note
108 /// also that the bitwidth of V, DemandedMask, Known.Zero and Known.One must all
109 /// be the same.
110 ///
111 /// This returns null if it did not change anything and it permits no
112 /// simplification. This returns V itself if it did some simplification of V's
113 /// operands based on the information about what bits are demanded. This returns
114 /// some other non-null value if it found out that V is equal to another value
115 /// in the context where the specified bits are demanded, but not for all users.
116 Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
117  KnownBits &Known, unsigned Depth,
118  Instruction *CxtI) {
119  assert(V != nullptr && "Null pointer of Value???");
120  assert(Depth <= 6 && "Limit Search Depth");
121  uint32_t BitWidth = DemandedMask.getBitWidth();
122  Type *VTy = V->getType();
123  assert(
124  (!VTy->isIntOrIntVectorTy() || VTy->getScalarSizeInBits() == BitWidth) &&
125  Known.getBitWidth() == BitWidth &&
126  "Value *V, DemandedMask and Known must have same BitWidth");
127 
128  if (isa<Constant>(V)) {
129  computeKnownBits(V, Known, Depth, CxtI);
130  return nullptr;
131  }
132 
133  Known.resetAll();
134  if (DemandedMask.isNullValue()) // Not demanding any bits from V.
135  return UndefValue::get(VTy);
136 
137  if (Depth == 6) // Limit search depth.
138  return nullptr;
139 
141  if (!I) {
142  computeKnownBits(V, Known, Depth, CxtI);
143  return nullptr; // Only analyze instructions.
144  }
145 
146  // If there are multiple uses of this value and we aren't at the root, then
147  // we can't do any simplifications of the operands, because DemandedMask
148  // only reflects the bits demanded by *one* of the users.
149  if (Depth != 0 && !I->hasOneUse())
150  return SimplifyMultipleUseDemandedBits(I, DemandedMask, Known, Depth, CxtI);
151 
152  KnownBits LHSKnown(BitWidth), RHSKnown(BitWidth);
153 
154  // If this is the root being simplified, allow it to have multiple uses,
155  // just set the DemandedMask to all bits so that we can try to simplify the
156  // operands. This allows visitTruncInst (for example) to simplify the
157  // operand of a trunc without duplicating all the logic below.
158  if (Depth == 0 && !V->hasOneUse())
159  DemandedMask.setAllBits();
160 
161  switch (I->getOpcode()) {
162  default:
163  computeKnownBits(I, Known, Depth, CxtI);
164  break;
165  case Instruction::And: {
166  // If either the LHS or the RHS are Zero, the result is zero.
167  if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) ||
168  SimplifyDemandedBits(I, 0, DemandedMask & ~RHSKnown.Zero, LHSKnown,
169  Depth + 1))
170  return I;
171  assert(!RHSKnown.hasConflict() && "Bits known to be one AND zero?");
172  assert(!LHSKnown.hasConflict() && "Bits known to be one AND zero?");
173 
174  // Output known-0 are known to be clear if zero in either the LHS | RHS.
175  APInt IKnownZero = RHSKnown.Zero | LHSKnown.Zero;
176  // Output known-1 bits are only known if set in both the LHS & RHS.
177  APInt IKnownOne = RHSKnown.One & LHSKnown.One;
178 
179  // If the client is only demanding bits that we know, return the known
180  // constant.
181  if (DemandedMask.isSubsetOf(IKnownZero|IKnownOne))
182  return Constant::getIntegerValue(VTy, IKnownOne);
183 
184  // If all of the demanded bits are known 1 on one side, return the other.
185  // These bits cannot contribute to the result of the 'and'.
186  if (DemandedMask.isSubsetOf(LHSKnown.Zero | RHSKnown.One))
187  return I->getOperand(0);
188  if (DemandedMask.isSubsetOf(RHSKnown.Zero | LHSKnown.One))
189  return I->getOperand(1);
190 
191  // If the RHS is a constant, see if we can simplify it.
192  if (ShrinkDemandedConstant(I, 1, DemandedMask & ~LHSKnown.Zero))
193  return I;
194 
195  Known.Zero = std::move(IKnownZero);
196  Known.One = std::move(IKnownOne);
197  break;
198  }
199  case Instruction::Or: {
200  // If either the LHS or the RHS are One, the result is One.
201  if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) ||
202  SimplifyDemandedBits(I, 0, DemandedMask & ~RHSKnown.One, LHSKnown,
203  Depth + 1))
204  return I;
205  assert(!RHSKnown.hasConflict() && "Bits known to be one AND zero?");
206  assert(!LHSKnown.hasConflict() && "Bits known to be one AND zero?");
207 
208  // Output known-0 bits are only known if clear in both the LHS & RHS.
209  APInt IKnownZero = RHSKnown.Zero & LHSKnown.Zero;
210  // Output known-1 are known. to be set if s.et in either the LHS | RHS.
211  APInt IKnownOne = RHSKnown.One | LHSKnown.One;
212 
213  // If the client is only demanding bits that we know, return the known
214  // constant.
215  if (DemandedMask.isSubsetOf(IKnownZero|IKnownOne))
216  return Constant::getIntegerValue(VTy, IKnownOne);
217 
218  // If all of the demanded bits are known zero on one side, return the other.
219  // These bits cannot contribute to the result of the 'or'.
220  if (DemandedMask.isSubsetOf(LHSKnown.One | RHSKnown.Zero))
221  return I->getOperand(0);
222  if (DemandedMask.isSubsetOf(RHSKnown.One | LHSKnown.Zero))
223  return I->getOperand(1);
224 
225  // If the RHS is a constant, see if we can simplify it.
226  if (ShrinkDemandedConstant(I, 1, DemandedMask))
227  return I;
228 
229  Known.Zero = std::move(IKnownZero);
230  Known.One = std::move(IKnownOne);
231  break;
232  }
233  case Instruction::Xor: {
234  if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) ||
235  SimplifyDemandedBits(I, 0, DemandedMask, LHSKnown, Depth + 1))
236  return I;
237  assert(!RHSKnown.hasConflict() && "Bits known to be one AND zero?");
238  assert(!LHSKnown.hasConflict() && "Bits known to be one AND zero?");
239 
240  // Output known-0 bits are known if clear or set in both the LHS & RHS.
241  APInt IKnownZero = (RHSKnown.Zero & LHSKnown.Zero) |
242  (RHSKnown.One & LHSKnown.One);
243  // Output known-1 are known to be set if set in only one of the LHS, RHS.
244  APInt IKnownOne = (RHSKnown.Zero & LHSKnown.One) |
245  (RHSKnown.One & LHSKnown.Zero);
246 
247  // If the client is only demanding bits that we know, return the known
248  // constant.
249  if (DemandedMask.isSubsetOf(IKnownZero|IKnownOne))
250  return Constant::getIntegerValue(VTy, IKnownOne);
251 
252  // If all of the demanded bits are known zero on one side, return the other.
253  // These bits cannot contribute to the result of the 'xor'.
254  if (DemandedMask.isSubsetOf(RHSKnown.Zero))
255  return I->getOperand(0);
256  if (DemandedMask.isSubsetOf(LHSKnown.Zero))
257  return I->getOperand(1);
258 
259  // If all of the demanded bits are known to be zero on one side or the
260  // other, turn this into an *inclusive* or.
261  // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
262  if (DemandedMask.isSubsetOf(RHSKnown.Zero | LHSKnown.Zero)) {
263  Instruction *Or =
264  BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1),
265  I->getName());
266  return InsertNewInstWith(Or, *I);
267  }
268 
269  // If all of the demanded bits on one side are known, and all of the set
270  // bits on that side are also known to be set on the other side, turn this
271  // into an AND, as we know the bits will be cleared.
272  // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
273  if (DemandedMask.isSubsetOf(RHSKnown.Zero|RHSKnown.One) &&
274  RHSKnown.One.isSubsetOf(LHSKnown.One)) {
276  ~RHSKnown.One & DemandedMask);
277  Instruction *And = BinaryOperator::CreateAnd(I->getOperand(0), AndC);
278  return InsertNewInstWith(And, *I);
279  }
280 
281  // If the RHS is a constant, see if we can simplify it.
282  // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
283  if (ShrinkDemandedConstant(I, 1, DemandedMask))
284  return I;
285 
286  // If our LHS is an 'and' and if it has one use, and if any of the bits we
287  // are flipping are known to be set, then the xor is just resetting those
288  // bits to zero. We can just knock out bits from the 'and' and the 'xor',
289  // simplifying both of them.
290  if (Instruction *LHSInst = dyn_cast<Instruction>(I->getOperand(0)))
291  if (LHSInst->getOpcode() == Instruction::And && LHSInst->hasOneUse() &&
292  isa<ConstantInt>(I->getOperand(1)) &&
293  isa<ConstantInt>(LHSInst->getOperand(1)) &&
294  (LHSKnown.One & RHSKnown.One & DemandedMask) != 0) {
295  ConstantInt *AndRHS = cast<ConstantInt>(LHSInst->getOperand(1));
296  ConstantInt *XorRHS = cast<ConstantInt>(I->getOperand(1));
297  APInt NewMask = ~(LHSKnown.One & RHSKnown.One & DemandedMask);
298 
299  Constant *AndC =
300  ConstantInt::get(I->getType(), NewMask & AndRHS->getValue());
301  Instruction *NewAnd = BinaryOperator::CreateAnd(I->getOperand(0), AndC);
302  InsertNewInstWith(NewAnd, *I);
303 
304  Constant *XorC =
305  ConstantInt::get(I->getType(), NewMask & XorRHS->getValue());
306  Instruction *NewXor = BinaryOperator::CreateXor(NewAnd, XorC);
307  return InsertNewInstWith(NewXor, *I);
308  }
309 
310  // Output known-0 bits are known if clear or set in both the LHS & RHS.
311  Known.Zero = std::move(IKnownZero);
312  // Output known-1 are known to be set if set in only one of the LHS, RHS.
313  Known.One = std::move(IKnownOne);
314  break;
315  }
316  case Instruction::Select: {
317  Value *LHS, *RHS;
318  SelectPatternFlavor SPF = matchSelectPattern(I, LHS, RHS).Flavor;
319  if (SPF == SPF_UMAX) {
320  // UMax(A, C) == A if ...
321  // The lowest non-zero bit of DemandMask is higher than the highest
322  // non-zero bit of C.
323  const APInt *C;
324  unsigned CTZ = DemandedMask.countTrailingZeros();
325  if (match(RHS, m_APInt(C)) && CTZ >= C->getActiveBits())
326  return LHS;
327  } else if (SPF == SPF_UMIN) {
328  // UMin(A, C) == A if ...
329  // The lowest non-zero bit of DemandMask is higher than the highest
330  // non-one bit of C.
331  // This comes from using DeMorgans on the above umax example.
332  const APInt *C;
333  unsigned CTZ = DemandedMask.countTrailingZeros();
334  if (match(RHS, m_APInt(C)) &&
335  CTZ >= C->getBitWidth() - C->countLeadingOnes())
336  return LHS;
337  }
338 
339  // If this is a select as part of any other min/max pattern, don't simplify
340  // any further in case we break the structure.
341  if (SPF != SPF_UNKNOWN)
342  return nullptr;
343 
344  if (SimplifyDemandedBits(I, 2, DemandedMask, RHSKnown, Depth + 1) ||
345  SimplifyDemandedBits(I, 1, DemandedMask, LHSKnown, Depth + 1))
346  return I;
347  assert(!RHSKnown.hasConflict() && "Bits known to be one AND zero?");
348  assert(!LHSKnown.hasConflict() && "Bits known to be one AND zero?");
349 
350  // If the operands are constants, see if we can simplify them.
351  if (ShrinkDemandedConstant(I, 1, DemandedMask) ||
352  ShrinkDemandedConstant(I, 2, DemandedMask))
353  return I;
354 
355  // Only known if known in both the LHS and RHS.
356  Known.One = RHSKnown.One & LHSKnown.One;
357  Known.Zero = RHSKnown.Zero & LHSKnown.Zero;
358  break;
359  }
360  case Instruction::ZExt:
361  case Instruction::Trunc: {
362  unsigned SrcBitWidth = I->getOperand(0)->getType()->getScalarSizeInBits();
363 
364  APInt InputDemandedMask = DemandedMask.zextOrTrunc(SrcBitWidth);
365  KnownBits InputKnown(SrcBitWidth);
366  if (SimplifyDemandedBits(I, 0, InputDemandedMask, InputKnown, Depth + 1))
367  return I;
368  assert(InputKnown.getBitWidth() == SrcBitWidth && "Src width changed?");
369  Known = InputKnown.zextOrTrunc(BitWidth,
370  true /* ExtendedBitsAreKnownZero */);
371  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
372  break;
373  }
374  case Instruction::BitCast:
375  if (!I->getOperand(0)->getType()->isIntOrIntVectorTy())
376  return nullptr; // vector->int or fp->int?
377 
378  if (VectorType *DstVTy = dyn_cast<VectorType>(I->getType())) {
379  if (VectorType *SrcVTy =
380  dyn_cast<VectorType>(I->getOperand(0)->getType())) {
381  if (DstVTy->getNumElements() != SrcVTy->getNumElements())
382  // Don't touch a bitcast between vectors of different element counts.
383  return nullptr;
384  } else
385  // Don't touch a scalar-to-vector bitcast.
386  return nullptr;
387  } else if (I->getOperand(0)->getType()->isVectorTy())
388  // Don't touch a vector-to-scalar bitcast.
389  return nullptr;
390 
391  if (SimplifyDemandedBits(I, 0, DemandedMask, Known, Depth + 1))
392  return I;
393  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
394  break;
395  case Instruction::SExt: {
396  // Compute the bits in the result that are not present in the input.
397  unsigned SrcBitWidth = I->getOperand(0)->getType()->getScalarSizeInBits();
398 
399  APInt InputDemandedBits = DemandedMask.trunc(SrcBitWidth);
400 
401  // If any of the sign extended bits are demanded, we know that the sign
402  // bit is demanded.
403  if (DemandedMask.getActiveBits() > SrcBitWidth)
404  InputDemandedBits.setBit(SrcBitWidth-1);
405 
406  KnownBits InputKnown(SrcBitWidth);
407  if (SimplifyDemandedBits(I, 0, InputDemandedBits, InputKnown, Depth + 1))
408  return I;
409 
410  // If the input sign bit is known zero, or if the NewBits are not demanded
411  // convert this into a zero extension.
412  if (InputKnown.isNonNegative() ||
413  DemandedMask.getActiveBits() <= SrcBitWidth) {
414  // Convert to ZExt cast.
415  CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName());
416  return InsertNewInstWith(NewCast, *I);
417  }
418 
419  // If the sign bit of the input is known set or clear, then we know the
420  // top bits of the result.
421  Known = InputKnown.sext(BitWidth);
422  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
423  break;
424  }
425  case Instruction::Add:
426  case Instruction::Sub: {
427  /// If the high-bits of an ADD/SUB are not demanded, then we do not care
428  /// about the high bits of the operands.
429  unsigned NLZ = DemandedMask.countLeadingZeros();
430  // Right fill the mask of bits for this ADD/SUB to demand the most
431  // significant bit and all those below it.
432  APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ));
433  if (ShrinkDemandedConstant(I, 0, DemandedFromOps) ||
434  SimplifyDemandedBits(I, 0, DemandedFromOps, LHSKnown, Depth + 1) ||
435  ShrinkDemandedConstant(I, 1, DemandedFromOps) ||
436  SimplifyDemandedBits(I, 1, DemandedFromOps, RHSKnown, Depth + 1)) {
437  if (NLZ > 0) {
438  // Disable the nsw and nuw flags here: We can no longer guarantee that
439  // we won't wrap after simplification. Removing the nsw/nuw flags is
440  // legal here because the top bit is not demanded.
441  BinaryOperator &BinOP = *cast<BinaryOperator>(I);
442  BinOP.setHasNoSignedWrap(false);
443  BinOP.setHasNoUnsignedWrap(false);
444  }
445  return I;
446  }
447 
448  // If we are known to be adding/subtracting zeros to every bit below
449  // the highest demanded bit, we just return the other side.
450  if (DemandedFromOps.isSubsetOf(RHSKnown.Zero))
451  return I->getOperand(0);
452  // We can't do this with the LHS for subtraction, unless we are only
453  // demanding the LSB.
454  if ((I->getOpcode() == Instruction::Add ||
455  DemandedFromOps.isOneValue()) &&
456  DemandedFromOps.isSubsetOf(LHSKnown.Zero))
457  return I->getOperand(1);
458 
459  // Otherwise just compute the known bits of the result.
460  bool NSW = cast<OverflowingBinaryOperator>(I)->hasNoSignedWrap();
462  NSW, LHSKnown, RHSKnown);
463  break;
464  }
465  case Instruction::Shl: {
466  const APInt *SA;
467  if (match(I->getOperand(1), m_APInt(SA))) {
468  const APInt *ShrAmt;
469  if (match(I->getOperand(0), m_Shr(m_Value(), m_APInt(ShrAmt))))
470  if (Instruction *Shr = dyn_cast<Instruction>(I->getOperand(0)))
471  if (Value *R = simplifyShrShlDemandedBits(Shr, *ShrAmt, I, *SA,
472  DemandedMask, Known))
473  return R;
474 
475  uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
476  APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
477 
478  // If the shift is NUW/NSW, then it does demand the high bits.
479  ShlOperator *IOp = cast<ShlOperator>(I);
480  if (IOp->hasNoSignedWrap())
481  DemandedMaskIn.setHighBits(ShiftAmt+1);
482  else if (IOp->hasNoUnsignedWrap())
483  DemandedMaskIn.setHighBits(ShiftAmt);
484 
485  if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1))
486  return I;
487  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
488  Known.Zero <<= ShiftAmt;
489  Known.One <<= ShiftAmt;
490  // low bits known zero.
491  if (ShiftAmt)
492  Known.Zero.setLowBits(ShiftAmt);
493  }
494  break;
495  }
496  case Instruction::LShr: {
497  const APInt *SA;
498  if (match(I->getOperand(1), m_APInt(SA))) {
499  uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
500 
501  // Unsigned shift right.
502  APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
503 
504  // If the shift is exact, then it does demand the low bits (and knows that
505  // they are zero).
506  if (cast<LShrOperator>(I)->isExact())
507  DemandedMaskIn.setLowBits(ShiftAmt);
508 
509  if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1))
510  return I;
511  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
512  Known.Zero.lshrInPlace(ShiftAmt);
513  Known.One.lshrInPlace(ShiftAmt);
514  if (ShiftAmt)
515  Known.Zero.setHighBits(ShiftAmt); // high bits known zero.
516  }
517  break;
518  }
519  case Instruction::AShr: {
520  // If this is an arithmetic shift right and only the low-bit is set, we can
521  // always convert this into a logical shr, even if the shift amount is
522  // variable. The low bit of the shift cannot be an input sign bit unless
523  // the shift amount is >= the size of the datatype, which is undefined.
524  if (DemandedMask.isOneValue()) {
525  // Perform the logical shift right.
526  Instruction *NewVal = BinaryOperator::CreateLShr(
527  I->getOperand(0), I->getOperand(1), I->getName());
528  return InsertNewInstWith(NewVal, *I);
529  }
530 
531  // If the sign bit is the only bit demanded by this ashr, then there is no
532  // need to do it, the shift doesn't change the high bit.
533  if (DemandedMask.isSignMask())
534  return I->getOperand(0);
535 
536  const APInt *SA;
537  if (match(I->getOperand(1), m_APInt(SA))) {
538  uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
539 
540  // Signed shift right.
541  APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
542  // If any of the high bits are demanded, we should set the sign bit as
543  // demanded.
544  if (DemandedMask.countLeadingZeros() <= ShiftAmt)
545  DemandedMaskIn.setSignBit();
546 
547  // If the shift is exact, then it does demand the low bits (and knows that
548  // they are zero).
549  if (cast<AShrOperator>(I)->isExact())
550  DemandedMaskIn.setLowBits(ShiftAmt);
551 
552  if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1))
553  return I;
554 
555  unsigned SignBits = ComputeNumSignBits(I->getOperand(0), Depth + 1, CxtI);
556 
557  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
558  // Compute the new bits that are at the top now plus sign bits.
559  APInt HighBits(APInt::getHighBitsSet(
560  BitWidth, std::min(SignBits + ShiftAmt - 1, BitWidth)));
561  Known.Zero.lshrInPlace(ShiftAmt);
562  Known.One.lshrInPlace(ShiftAmt);
563 
564  // If the input sign bit is known to be zero, or if none of the top bits
565  // are demanded, turn this into an unsigned shift right.
566  assert(BitWidth > ShiftAmt && "Shift amount not saturated?");
567  if (Known.Zero[BitWidth-ShiftAmt-1] ||
568  !DemandedMask.intersects(HighBits)) {
569  BinaryOperator *LShr = BinaryOperator::CreateLShr(I->getOperand(0),
570  I->getOperand(1));
571  LShr->setIsExact(cast<BinaryOperator>(I)->isExact());
572  return InsertNewInstWith(LShr, *I);
573  } else if (Known.One[BitWidth-ShiftAmt-1]) { // New bits are known one.
574  Known.One |= HighBits;
575  }
576  }
577  break;
578  }
579  case Instruction::UDiv: {
580  // UDiv doesn't demand low bits that are zero in the divisor.
581  const APInt *SA;
582  if (match(I->getOperand(1), m_APInt(SA))) {
583  // If the shift is exact, then it does demand the low bits.
584  if (cast<UDivOperator>(I)->isExact())
585  break;
586 
587  // FIXME: Take the demanded mask of the result into account.
588  unsigned RHSTrailingZeros = SA->countTrailingZeros();
589  APInt DemandedMaskIn =
590  APInt::getHighBitsSet(BitWidth, BitWidth - RHSTrailingZeros);
591  if (SimplifyDemandedBits(I, 0, DemandedMaskIn, LHSKnown, Depth + 1))
592  return I;
593 
594  // Propagate zero bits from the input.
595  Known.Zero.setHighBits(std::min(
596  BitWidth, LHSKnown.Zero.countLeadingOnes() + RHSTrailingZeros));
597  }
598  break;
599  }
600  case Instruction::SRem:
601  if (ConstantInt *Rem = dyn_cast<ConstantInt>(I->getOperand(1))) {
602  // X % -1 demands all the bits because we don't want to introduce
603  // INT_MIN % -1 (== undef) by accident.
604  if (Rem->isMinusOne())
605  break;
606  APInt RA = Rem->getValue().abs();
607  if (RA.isPowerOf2()) {
608  if (DemandedMask.ult(RA)) // srem won't affect demanded bits
609  return I->getOperand(0);
610 
611  APInt LowBits = RA - 1;
612  APInt Mask2 = LowBits | APInt::getSignMask(BitWidth);
613  if (SimplifyDemandedBits(I, 0, Mask2, LHSKnown, Depth + 1))
614  return I;
615 
616  // The low bits of LHS are unchanged by the srem.
617  Known.Zero = LHSKnown.Zero & LowBits;
618  Known.One = LHSKnown.One & LowBits;
619 
620  // If LHS is non-negative or has all low bits zero, then the upper bits
621  // are all zero.
622  if (LHSKnown.isNonNegative() || LowBits.isSubsetOf(LHSKnown.Zero))
623  Known.Zero |= ~LowBits;
624 
625  // If LHS is negative and not all low bits are zero, then the upper bits
626  // are all one.
627  if (LHSKnown.isNegative() && LowBits.intersects(LHSKnown.One))
628  Known.One |= ~LowBits;
629 
630  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
631  break;
632  }
633  }
634 
635  // The sign bit is the LHS's sign bit, except when the result of the
636  // remainder is zero.
637  if (DemandedMask.isSignBitSet()) {
638  computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1, CxtI);
639  // If it's known zero, our sign bit is also zero.
640  if (LHSKnown.isNonNegative())
641  Known.makeNonNegative();
642  }
643  break;
644  case Instruction::URem: {
645  KnownBits Known2(BitWidth);
646  APInt AllOnes = APInt::getAllOnesValue(BitWidth);
647  if (SimplifyDemandedBits(I, 0, AllOnes, Known2, Depth + 1) ||
648  SimplifyDemandedBits(I, 1, AllOnes, Known2, Depth + 1))
649  return I;
650 
651  unsigned Leaders = Known2.countMinLeadingZeros();
652  Known.Zero = APInt::getHighBitsSet(BitWidth, Leaders) & DemandedMask;
653  break;
654  }
655  case Instruction::Call:
656  if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
657  switch (II->getIntrinsicID()) {
658  default: break;
659  case Intrinsic::bswap: {
660  // If the only bits demanded come from one byte of the bswap result,
661  // just shift the input byte into position to eliminate the bswap.
662  unsigned NLZ = DemandedMask.countLeadingZeros();
663  unsigned NTZ = DemandedMask.countTrailingZeros();
664 
665  // Round NTZ down to the next byte. If we have 11 trailing zeros, then
666  // we need all the bits down to bit 8. Likewise, round NLZ. If we
667  // have 14 leading zeros, round to 8.
668  NLZ &= ~7;
669  NTZ &= ~7;
670  // If we need exactly one byte, we can do this transformation.
671  if (BitWidth-NLZ-NTZ == 8) {
672  unsigned ResultBit = NTZ;
673  unsigned InputBit = BitWidth-NTZ-8;
674 
675  // Replace this with either a left or right shift to get the byte into
676  // the right place.
677  Instruction *NewVal;
678  if (InputBit > ResultBit)
679  NewVal = BinaryOperator::CreateLShr(II->getArgOperand(0),
680  ConstantInt::get(I->getType(), InputBit-ResultBit));
681  else
682  NewVal = BinaryOperator::CreateShl(II->getArgOperand(0),
683  ConstantInt::get(I->getType(), ResultBit-InputBit));
684  NewVal->takeName(I);
685  return InsertNewInstWith(NewVal, *I);
686  }
687 
688  // TODO: Could compute known zero/one bits based on the input.
689  break;
690  }
691  case Intrinsic::fshr:
692  case Intrinsic::fshl: {
693  const APInt *SA;
694  if (!match(I->getOperand(2), m_APInt(SA)))
695  break;
696 
697  // Normalize to funnel shift left. APInt shifts of BitWidth are well-
698  // defined, so no need to special-case zero shifts here.
699  uint64_t ShiftAmt = SA->urem(BitWidth);
700  if (II->getIntrinsicID() == Intrinsic::fshr)
701  ShiftAmt = BitWidth - ShiftAmt;
702 
703  APInt DemandedMaskLHS(DemandedMask.lshr(ShiftAmt));
704  APInt DemandedMaskRHS(DemandedMask.shl(BitWidth - ShiftAmt));
705  if (SimplifyDemandedBits(I, 0, DemandedMaskLHS, LHSKnown, Depth + 1) ||
706  SimplifyDemandedBits(I, 1, DemandedMaskRHS, RHSKnown, Depth + 1))
707  return I;
708 
709  Known.Zero = LHSKnown.Zero.shl(ShiftAmt) |
710  RHSKnown.Zero.lshr(BitWidth - ShiftAmt);
711  Known.One = LHSKnown.One.shl(ShiftAmt) |
712  RHSKnown.One.lshr(BitWidth - ShiftAmt);
713  break;
714  }
715  case Intrinsic::x86_mmx_pmovmskb:
716  case Intrinsic::x86_sse_movmsk_ps:
717  case Intrinsic::x86_sse2_movmsk_pd:
718  case Intrinsic::x86_sse2_pmovmskb_128:
719  case Intrinsic::x86_avx_movmsk_ps_256:
720  case Intrinsic::x86_avx_movmsk_pd_256:
721  case Intrinsic::x86_avx2_pmovmskb: {
722  // MOVMSK copies the vector elements' sign bits to the low bits
723  // and zeros the high bits.
724  unsigned ArgWidth;
725  if (II->getIntrinsicID() == Intrinsic::x86_mmx_pmovmskb) {
726  ArgWidth = 8; // Arg is x86_mmx, but treated as <8 x i8>.
727  } else {
728  auto Arg = II->getArgOperand(0);
729  auto ArgType = cast<VectorType>(Arg->getType());
730  ArgWidth = ArgType->getNumElements();
731  }
732 
733  // If we don't need any of low bits then return zero,
734  // we know that DemandedMask is non-zero already.
735  APInt DemandedElts = DemandedMask.zextOrTrunc(ArgWidth);
736  if (DemandedElts.isNullValue())
737  return ConstantInt::getNullValue(VTy);
738 
739  // We know that the upper bits are set to zero.
740  Known.Zero.setBitsFrom(ArgWidth);
741  return nullptr;
742  }
743  case Intrinsic::x86_sse42_crc32_64_64:
744  Known.Zero.setBitsFrom(32);
745  return nullptr;
746  }
747  }
748  computeKnownBits(V, Known, Depth, CxtI);
749  break;
750  }
751 
752  // If the client is only demanding bits that we know, return the known
753  // constant.
754  if (DemandedMask.isSubsetOf(Known.Zero|Known.One))
755  return Constant::getIntegerValue(VTy, Known.One);
756  return nullptr;
757 }
758 
759 /// Helper routine of SimplifyDemandedUseBits. It computes Known
760 /// bits. It also tries to handle simplifications that can be done based on
761 /// DemandedMask, but without modifying the Instruction.
762 Value *InstCombiner::SimplifyMultipleUseDemandedBits(Instruction *I,
763  const APInt &DemandedMask,
764  KnownBits &Known,
765  unsigned Depth,
766  Instruction *CxtI) {
767  unsigned BitWidth = DemandedMask.getBitWidth();
768  Type *ITy = I->getType();
769 
770  KnownBits LHSKnown(BitWidth);
771  KnownBits RHSKnown(BitWidth);
772 
773  // Despite the fact that we can't simplify this instruction in all User's
774  // context, we can at least compute the known bits, and we can
775  // do simplifications that apply to *just* the one user if we know that
776  // this instruction has a simpler value in that context.
777  switch (I->getOpcode()) {
778  case Instruction::And: {
779  // If either the LHS or the RHS are Zero, the result is zero.
780  computeKnownBits(I->getOperand(1), RHSKnown, Depth + 1, CxtI);
781  computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1,
782  CxtI);
783 
784  // Output known-0 are known to be clear if zero in either the LHS | RHS.
785  APInt IKnownZero = RHSKnown.Zero | LHSKnown.Zero;
786  // Output known-1 bits are only known if set in both the LHS & RHS.
787  APInt IKnownOne = RHSKnown.One & LHSKnown.One;
788 
789  // If the client is only demanding bits that we know, return the known
790  // constant.
791  if (DemandedMask.isSubsetOf(IKnownZero|IKnownOne))
792  return Constant::getIntegerValue(ITy, IKnownOne);
793 
794  // If all of the demanded bits are known 1 on one side, return the other.
795  // These bits cannot contribute to the result of the 'and' in this
796  // context.
797  if (DemandedMask.isSubsetOf(LHSKnown.Zero | RHSKnown.One))
798  return I->getOperand(0);
799  if (DemandedMask.isSubsetOf(RHSKnown.Zero | LHSKnown.One))
800  return I->getOperand(1);
801 
802  Known.Zero = std::move(IKnownZero);
803  Known.One = std::move(IKnownOne);
804  break;
805  }
806  case Instruction::Or: {
807  // We can simplify (X|Y) -> X or Y in the user's context if we know that
808  // only bits from X or Y are demanded.
809 
810  // If either the LHS or the RHS are One, the result is One.
811  computeKnownBits(I->getOperand(1), RHSKnown, Depth + 1, CxtI);
812  computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1,
813  CxtI);
814 
815  // Output known-0 bits are only known if clear in both the LHS & RHS.
816  APInt IKnownZero = RHSKnown.Zero & LHSKnown.Zero;
817  // Output known-1 are known to be set if set in either the LHS | RHS.
818  APInt IKnownOne = RHSKnown.One | LHSKnown.One;
819 
820  // If the client is only demanding bits that we know, return the known
821  // constant.
822  if (DemandedMask.isSubsetOf(IKnownZero|IKnownOne))
823  return Constant::getIntegerValue(ITy, IKnownOne);
824 
825  // If all of the demanded bits are known zero on one side, return the
826  // other. These bits cannot contribute to the result of the 'or' in this
827  // context.
828  if (DemandedMask.isSubsetOf(LHSKnown.One | RHSKnown.Zero))
829  return I->getOperand(0);
830  if (DemandedMask.isSubsetOf(RHSKnown.One | LHSKnown.Zero))
831  return I->getOperand(1);
832 
833  Known.Zero = std::move(IKnownZero);
834  Known.One = std::move(IKnownOne);
835  break;
836  }
837  case Instruction::Xor: {
838  // We can simplify (X^Y) -> X or Y in the user's context if we know that
839  // only bits from X or Y are demanded.
840 
841  computeKnownBits(I->getOperand(1), RHSKnown, Depth + 1, CxtI);
842  computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1,
843  CxtI);
844 
845  // Output known-0 bits are known if clear or set in both the LHS & RHS.
846  APInt IKnownZero = (RHSKnown.Zero & LHSKnown.Zero) |
847  (RHSKnown.One & LHSKnown.One);
848  // Output known-1 are known to be set if set in only one of the LHS, RHS.
849  APInt IKnownOne = (RHSKnown.Zero & LHSKnown.One) |
850  (RHSKnown.One & LHSKnown.Zero);
851 
852  // If the client is only demanding bits that we know, return the known
853  // constant.
854  if (DemandedMask.isSubsetOf(IKnownZero|IKnownOne))
855  return Constant::getIntegerValue(ITy, IKnownOne);
856 
857  // If all of the demanded bits are known zero on one side, return the
858  // other.
859  if (DemandedMask.isSubsetOf(RHSKnown.Zero))
860  return I->getOperand(0);
861  if (DemandedMask.isSubsetOf(LHSKnown.Zero))
862  return I->getOperand(1);
863 
864  // Output known-0 bits are known if clear or set in both the LHS & RHS.
865  Known.Zero = std::move(IKnownZero);
866  // Output known-1 are known to be set if set in only one of the LHS, RHS.
867  Known.One = std::move(IKnownOne);
868  break;
869  }
870  default:
871  // Compute the Known bits to simplify things downstream.
872  computeKnownBits(I, Known, Depth, CxtI);
873 
874  // If this user is only demanding bits that we know, return the known
875  // constant.
876  if (DemandedMask.isSubsetOf(Known.Zero|Known.One))
877  return Constant::getIntegerValue(ITy, Known.One);
878 
879  break;
880  }
881 
882  return nullptr;
883 }
884 
885 
886 /// Helper routine of SimplifyDemandedUseBits. It tries to simplify
887 /// "E1 = (X lsr C1) << C2", where the C1 and C2 are constant, into
888 /// "E2 = X << (C2 - C1)" or "E2 = X >> (C1 - C2)", depending on the sign
889 /// of "C2-C1".
890 ///
891 /// Suppose E1 and E2 are generally different in bits S={bm, bm+1,
892 /// ..., bn}, without considering the specific value X is holding.
893 /// This transformation is legal iff one of following conditions is hold:
894 /// 1) All the bit in S are 0, in this case E1 == E2.
895 /// 2) We don't care those bits in S, per the input DemandedMask.
896 /// 3) Combination of 1) and 2). Some bits in S are 0, and we don't care the
897 /// rest bits.
898 ///
899 /// Currently we only test condition 2).
900 ///
901 /// As with SimplifyDemandedUseBits, it returns NULL if the simplification was
902 /// not successful.
903 Value *
904 InstCombiner::simplifyShrShlDemandedBits(Instruction *Shr, const APInt &ShrOp1,
905  Instruction *Shl, const APInt &ShlOp1,
906  const APInt &DemandedMask,
907  KnownBits &Known) {
908  if (!ShlOp1 || !ShrOp1)
909  return nullptr; // No-op.
910 
911  Value *VarX = Shr->getOperand(0);
912  Type *Ty = VarX->getType();
913  unsigned BitWidth = Ty->getScalarSizeInBits();
914  if (ShlOp1.uge(BitWidth) || ShrOp1.uge(BitWidth))
915  return nullptr; // Undef.
916 
917  unsigned ShlAmt = ShlOp1.getZExtValue();
918  unsigned ShrAmt = ShrOp1.getZExtValue();
919 
920  Known.One.clearAllBits();
921  Known.Zero.setLowBits(ShlAmt - 1);
922  Known.Zero &= DemandedMask;
923 
924  APInt BitMask1(APInt::getAllOnesValue(BitWidth));
925  APInt BitMask2(APInt::getAllOnesValue(BitWidth));
926 
927  bool isLshr = (Shr->getOpcode() == Instruction::LShr);
928  BitMask1 = isLshr ? (BitMask1.lshr(ShrAmt) << ShlAmt) :
929  (BitMask1.ashr(ShrAmt) << ShlAmt);
930 
931  if (ShrAmt <= ShlAmt) {
932  BitMask2 <<= (ShlAmt - ShrAmt);
933  } else {
934  BitMask2 = isLshr ? BitMask2.lshr(ShrAmt - ShlAmt):
935  BitMask2.ashr(ShrAmt - ShlAmt);
936  }
937 
938  // Check if condition-2 (see the comment to this function) is satified.
939  if ((BitMask1 & DemandedMask) == (BitMask2 & DemandedMask)) {
940  if (ShrAmt == ShlAmt)
941  return VarX;
942 
943  if (!Shr->hasOneUse())
944  return nullptr;
945 
946  BinaryOperator *New;
947  if (ShrAmt < ShlAmt) {
948  Constant *Amt = ConstantInt::get(VarX->getType(), ShlAmt - ShrAmt);
949  New = BinaryOperator::CreateShl(VarX, Amt);
950  BinaryOperator *Orig = cast<BinaryOperator>(Shl);
951  New->setHasNoSignedWrap(Orig->hasNoSignedWrap());
952  New->setHasNoUnsignedWrap(Orig->hasNoUnsignedWrap());
953  } else {
954  Constant *Amt = ConstantInt::get(VarX->getType(), ShrAmt - ShlAmt);
955  New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) :
956  BinaryOperator::CreateAShr(VarX, Amt);
957  if (cast<BinaryOperator>(Shr)->isExact())
958  New->setIsExact(true);
959  }
960 
961  return InsertNewInstWith(New, *Shl);
962  }
963 
964  return nullptr;
965 }
966 
967 /// Implement SimplifyDemandedVectorElts for amdgcn buffer and image intrinsics.
968 ///
969 /// Note: This only supports non-TFE/LWE image intrinsic calls; those have
970 /// struct returns.
971 Value *InstCombiner::simplifyAMDGCNMemoryIntrinsicDemanded(IntrinsicInst *II,
972  APInt DemandedElts,
973  int DMaskIdx) {
974  unsigned VWidth = II->getType()->getVectorNumElements();
975  if (VWidth == 1)
976  return nullptr;
977 
978  ConstantInt *NewDMask = nullptr;
979 
980  if (DMaskIdx < 0) {
981  // Pretend that a prefix of elements is demanded to simplify the code
982  // below.
983  DemandedElts = (1 << DemandedElts.getActiveBits()) - 1;
984  } else {
985  ConstantInt *DMask = cast<ConstantInt>(II->getArgOperand(DMaskIdx));
986  unsigned DMaskVal = DMask->getZExtValue() & 0xf;
987 
988  // Mask off values that are undefined because the dmask doesn't cover them
989  DemandedElts &= (1 << countPopulation(DMaskVal)) - 1;
990 
991  unsigned NewDMaskVal = 0;
992  unsigned OrigLoadIdx = 0;
993  for (unsigned SrcIdx = 0; SrcIdx < 4; ++SrcIdx) {
994  const unsigned Bit = 1 << SrcIdx;
995  if (!!(DMaskVal & Bit)) {
996  if (!!DemandedElts[OrigLoadIdx])
997  NewDMaskVal |= Bit;
998  OrigLoadIdx++;
999  }
1000  }
1001 
1002  if (DMaskVal != NewDMaskVal)
1003  NewDMask = ConstantInt::get(DMask->getType(), NewDMaskVal);
1004  }
1005 
1006  unsigned NewNumElts = DemandedElts.countPopulation();
1007  if (!NewNumElts)
1008  return UndefValue::get(II->getType());
1009 
1010  if (NewNumElts >= VWidth && DemandedElts.isMask()) {
1011  if (NewDMask)
1012  II->setArgOperand(DMaskIdx, NewDMask);
1013  return nullptr;
1014  }
1015 
1016  // Determine the overload types of the original intrinsic.
1017  auto IID = II->getIntrinsicID();
1019  getIntrinsicInfoTableEntries(IID, Table);
1021 
1023  SmallVector<Type *, 6> OverloadTys;
1024  Intrinsic::matchIntrinsicType(FTy->getReturnType(), TableRef, OverloadTys);
1025  for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i)
1026  Intrinsic::matchIntrinsicType(FTy->getParamType(i), TableRef, OverloadTys);
1027 
1028  // Get the new return type overload of the intrinsic.
1029  Module *M = II->getParent()->getParent()->getParent();
1030  Type *EltTy = II->getType()->getVectorElementType();
1031  Type *NewTy = (NewNumElts == 1) ? EltTy : VectorType::get(EltTy, NewNumElts);
1032 
1033  OverloadTys[0] = NewTy;
1034  Function *NewIntrin = Intrinsic::getDeclaration(M, IID, OverloadTys);
1035 
1037  for (unsigned I = 0, E = II->getNumArgOperands(); I != E; ++I)
1038  Args.push_back(II->getArgOperand(I));
1039 
1040  if (NewDMask)
1041  Args[DMaskIdx] = NewDMask;
1042 
1043  IRBuilderBase::InsertPointGuard Guard(Builder);
1044  Builder.SetInsertPoint(II);
1045 
1046  CallInst *NewCall = Builder.CreateCall(NewIntrin, Args);
1047  NewCall->takeName(II);
1048  NewCall->copyMetadata(*II);
1049 
1050  if (NewNumElts == 1) {
1051  return Builder.CreateInsertElement(UndefValue::get(II->getType()), NewCall,
1052  DemandedElts.countTrailingZeros());
1053  }
1054 
1055  SmallVector<uint32_t, 8> EltMask;
1056  unsigned NewLoadIdx = 0;
1057  for (unsigned OrigLoadIdx = 0; OrigLoadIdx < VWidth; ++OrigLoadIdx) {
1058  if (!!DemandedElts[OrigLoadIdx])
1059  EltMask.push_back(NewLoadIdx++);
1060  else
1061  EltMask.push_back(NewNumElts);
1062  }
1063 
1064  Value *Shuffle =
1065  Builder.CreateShuffleVector(NewCall, UndefValue::get(NewTy), EltMask);
1066 
1067  return Shuffle;
1068 }
1069 
1070 /// The specified value produces a vector with any number of elements.
1071 /// DemandedElts contains the set of elements that are actually used by the
1072 /// caller. This method analyzes which elements of the operand are undef and
1073 /// returns that information in UndefElts.
1074 ///
1075 /// If the information about demanded elements can be used to simplify the
1076 /// operation, the operation is simplified, then the resultant value is
1077 /// returned. This returns null if no change was made.
1078 Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
1079  APInt &UndefElts,
1080  unsigned Depth) {
1081  unsigned VWidth = V->getType()->getVectorNumElements();
1082  APInt EltMask(APInt::getAllOnesValue(VWidth));
1083  assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!");
1084 
1085  if (isa<UndefValue>(V)) {
1086  // If the entire vector is undefined, just return this info.
1087  UndefElts = EltMask;
1088  return nullptr;
1089  }
1090 
1091  if (DemandedElts.isNullValue()) { // If nothing is demanded, provide undef.
1092  UndefElts = EltMask;
1093  return UndefValue::get(V->getType());
1094  }
1095 
1096  UndefElts = 0;
1097 
1098  if (auto *C = dyn_cast<Constant>(V)) {
1099  // Check if this is identity. If so, return 0 since we are not simplifying
1100  // anything.
1101  if (DemandedElts.isAllOnesValue())
1102  return nullptr;
1103 
1104  Type *EltTy = cast<VectorType>(V->getType())->getElementType();
1105  Constant *Undef = UndefValue::get(EltTy);
1107  for (unsigned i = 0; i != VWidth; ++i) {
1108  if (!DemandedElts[i]) { // If not demanded, set to undef.
1109  Elts.push_back(Undef);
1110  UndefElts.setBit(i);
1111  continue;
1112  }
1113 
1114  Constant *Elt = C->getAggregateElement(i);
1115  if (!Elt) return nullptr;
1116 
1117  if (isa<UndefValue>(Elt)) { // Already undef.
1118  Elts.push_back(Undef);
1119  UndefElts.setBit(i);
1120  } else { // Otherwise, defined.
1121  Elts.push_back(Elt);
1122  }
1123  }
1124 
1125  // If we changed the constant, return it.
1126  Constant *NewCV = ConstantVector::get(Elts);
1127  return NewCV != C ? NewCV : nullptr;
1128  }
1129 
1130  // Limit search depth.
1131  if (Depth == 10)
1132  return nullptr;
1133 
1134  // If multiple users are using the root value, proceed with
1135  // simplification conservatively assuming that all elements
1136  // are needed.
1137  if (!V->hasOneUse()) {
1138  // Quit if we find multiple users of a non-root value though.
1139  // They'll be handled when it's their turn to be visited by
1140  // the main instcombine process.
1141  if (Depth != 0)
1142  // TODO: Just compute the UndefElts information recursively.
1143  return nullptr;
1144 
1145  // Conservatively assume that all elements are needed.
1146  DemandedElts = EltMask;
1147  }
1148 
1149  Instruction *I = dyn_cast<Instruction>(V);
1150  if (!I) return nullptr; // Only analyze instructions.
1151 
1152  bool MadeChange = false;
1153  auto simplifyAndSetOp = [&](Instruction *Inst, unsigned OpNum,
1154  APInt Demanded, APInt &Undef) {
1155  auto *II = dyn_cast<IntrinsicInst>(Inst);
1156  Value *Op = II ? II->getArgOperand(OpNum) : Inst->getOperand(OpNum);
1157  if (Value *V = SimplifyDemandedVectorElts(Op, Demanded, Undef, Depth + 1)) {
1158  if (II)
1159  II->setArgOperand(OpNum, V);
1160  else
1161  Inst->setOperand(OpNum, V);
1162  MadeChange = true;
1163  }
1164  };
1165 
1166  APInt UndefElts2(VWidth, 0);
1167  APInt UndefElts3(VWidth, 0);
1168  switch (I->getOpcode()) {
1169  default: break;
1170 
1171  case Instruction::GetElementPtr: {
1172  // The LangRef requires that struct geps have all constant indices. As
1173  // such, we can't convert any operand to partial undef.
1174  auto mayIndexStructType = [](GetElementPtrInst &GEP) {
1175  for (auto I = gep_type_begin(GEP), E = gep_type_end(GEP);
1176  I != E; I++)
1177  if (I.isStruct())
1178  return true;;
1179  return false;
1180  };
1181  if (mayIndexStructType(cast<GetElementPtrInst>(*I)))
1182  break;
1183 
1184  // Conservatively track the demanded elements back through any vector
1185  // operands we may have. We know there must be at least one, or we
1186  // wouldn't have a vector result to get here. Note that we intentionally
1187  // merge the undef bits here since gepping with either an undef base or
1188  // index results in undef.
1189  for (unsigned i = 0; i < I->getNumOperands(); i++) {
1190  if (isa<UndefValue>(I->getOperand(i))) {
1191  // If the entire vector is undefined, just return this info.
1192  UndefElts = EltMask;
1193  return nullptr;
1194  }
1195  if (I->getOperand(i)->getType()->isVectorTy()) {
1196  APInt UndefEltsOp(VWidth, 0);
1197  simplifyAndSetOp(I, i, DemandedElts, UndefEltsOp);
1198  UndefElts |= UndefEltsOp;
1199  }
1200  }
1201 
1202  break;
1203  }
1204  case Instruction::InsertElement: {
1205  // If this is a variable index, we don't know which element it overwrites.
1206  // demand exactly the same input as we produce.
1207  ConstantInt *Idx = dyn_cast<ConstantInt>(I->getOperand(2));
1208  if (!Idx) {
1209  // Note that we can't propagate undef elt info, because we don't know
1210  // which elt is getting updated.
1211  simplifyAndSetOp(I, 0, DemandedElts, UndefElts2);
1212  break;
1213  }
1214 
1215  // The element inserted overwrites whatever was there, so the input demanded
1216  // set is simpler than the output set.
1217  unsigned IdxNo = Idx->getZExtValue();
1218  APInt PreInsertDemandedElts = DemandedElts;
1219  if (IdxNo < VWidth)
1220  PreInsertDemandedElts.clearBit(IdxNo);
1221 
1222  simplifyAndSetOp(I, 0, PreInsertDemandedElts, UndefElts);
1223 
1224  // If this is inserting an element that isn't demanded, remove this
1225  // insertelement.
1226  if (IdxNo >= VWidth || !DemandedElts[IdxNo]) {
1227  Worklist.Add(I);
1228  return I->getOperand(0);
1229  }
1230 
1231  // The inserted element is defined.
1232  UndefElts.clearBit(IdxNo);
1233  break;
1234  }
1235  case Instruction::ShuffleVector: {
1236  ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1237  unsigned LHSVWidth =
1238  Shuffle->getOperand(0)->getType()->getVectorNumElements();
1239  APInt LeftDemanded(LHSVWidth, 0), RightDemanded(LHSVWidth, 0);
1240  for (unsigned i = 0; i < VWidth; i++) {
1241  if (DemandedElts[i]) {
1242  unsigned MaskVal = Shuffle->getMaskValue(i);
1243  if (MaskVal != -1u) {
1244  assert(MaskVal < LHSVWidth * 2 &&
1245  "shufflevector mask index out of range!");
1246  if (MaskVal < LHSVWidth)
1247  LeftDemanded.setBit(MaskVal);
1248  else
1249  RightDemanded.setBit(MaskVal - LHSVWidth);
1250  }
1251  }
1252  }
1253 
1254  APInt LHSUndefElts(LHSVWidth, 0);
1255  simplifyAndSetOp(I, 0, LeftDemanded, LHSUndefElts);
1256 
1257  APInt RHSUndefElts(LHSVWidth, 0);
1258  simplifyAndSetOp(I, 1, RightDemanded, RHSUndefElts);
1259 
1260  bool NewUndefElts = false;
1261  unsigned LHSIdx = -1u, LHSValIdx = -1u;
1262  unsigned RHSIdx = -1u, RHSValIdx = -1u;
1263  bool LHSUniform = true;
1264  bool RHSUniform = true;
1265  for (unsigned i = 0; i < VWidth; i++) {
1266  unsigned MaskVal = Shuffle->getMaskValue(i);
1267  if (MaskVal == -1u) {
1268  UndefElts.setBit(i);
1269  } else if (!DemandedElts[i]) {
1270  NewUndefElts = true;
1271  UndefElts.setBit(i);
1272  } else if (MaskVal < LHSVWidth) {
1273  if (LHSUndefElts[MaskVal]) {
1274  NewUndefElts = true;
1275  UndefElts.setBit(i);
1276  } else {
1277  LHSIdx = LHSIdx == -1u ? i : LHSVWidth;
1278  LHSValIdx = LHSValIdx == -1u ? MaskVal : LHSVWidth;
1279  LHSUniform = LHSUniform && (MaskVal == i);
1280  }
1281  } else {
1282  if (RHSUndefElts[MaskVal - LHSVWidth]) {
1283  NewUndefElts = true;
1284  UndefElts.setBit(i);
1285  } else {
1286  RHSIdx = RHSIdx == -1u ? i : LHSVWidth;
1287  RHSValIdx = RHSValIdx == -1u ? MaskVal - LHSVWidth : LHSVWidth;
1288  RHSUniform = RHSUniform && (MaskVal - LHSVWidth == i);
1289  }
1290  }
1291  }
1292 
1293  // Try to transform shuffle with constant vector and single element from
1294  // this constant vector to single insertelement instruction.
1295  // shufflevector V, C, <v1, v2, .., ci, .., vm> ->
1296  // insertelement V, C[ci], ci-n
1297  if (LHSVWidth == Shuffle->getType()->getNumElements()) {
1298  Value *Op = nullptr;
1299  Constant *Value = nullptr;
1300  unsigned Idx = -1u;
1301 
1302  // Find constant vector with the single element in shuffle (LHS or RHS).
1303  if (LHSIdx < LHSVWidth && RHSUniform) {
1304  if (auto *CV = dyn_cast<ConstantVector>(Shuffle->getOperand(0))) {
1305  Op = Shuffle->getOperand(1);
1306  Value = CV->getOperand(LHSValIdx);
1307  Idx = LHSIdx;
1308  }
1309  }
1310  if (RHSIdx < LHSVWidth && LHSUniform) {
1311  if (auto *CV = dyn_cast<ConstantVector>(Shuffle->getOperand(1))) {
1312  Op = Shuffle->getOperand(0);
1313  Value = CV->getOperand(RHSValIdx);
1314  Idx = RHSIdx;
1315  }
1316  }
1317  // Found constant vector with single element - convert to insertelement.
1318  if (Op && Value) {
1320  Op, Value, ConstantInt::get(Type::getInt32Ty(I->getContext()), Idx),
1321  Shuffle->getName());
1322  InsertNewInstWith(New, *Shuffle);
1323  return New;
1324  }
1325  }
1326  if (NewUndefElts) {
1327  // Add additional discovered undefs.
1329  for (unsigned i = 0; i < VWidth; ++i) {
1330  if (UndefElts[i])
1332  else
1334  Shuffle->getMaskValue(i)));
1335  }
1336  I->setOperand(2, ConstantVector::get(Elts));
1337  MadeChange = true;
1338  }
1339  break;
1340  }
1341  case Instruction::Select: {
1342  // If this is a vector select, try to transform the select condition based
1343  // on the current demanded elements.
1344  SelectInst *Sel = cast<SelectInst>(I);
1345  if (Sel->getCondition()->getType()->isVectorTy()) {
1346  // TODO: We are not doing anything with UndefElts based on this call.
1347  // It is overwritten below based on the other select operands. If an
1348  // element of the select condition is known undef, then we are free to
1349  // choose the output value from either arm of the select. If we know that
1350  // one of those values is undef, then the output can be undef.
1351  simplifyAndSetOp(I, 0, DemandedElts, UndefElts);
1352  }
1353 
1354  // Next, see if we can transform the arms of the select.
1355  APInt DemandedLHS(DemandedElts), DemandedRHS(DemandedElts);
1356  if (auto *CV = dyn_cast<ConstantVector>(Sel->getCondition())) {
1357  for (unsigned i = 0; i < VWidth; i++) {
1358  // isNullValue() always returns false when called on a ConstantExpr.
1359  // Skip constant expressions to avoid propagating incorrect information.
1360  Constant *CElt = CV->getAggregateElement(i);
1361  if (isa<ConstantExpr>(CElt))
1362  continue;
1363  // TODO: If a select condition element is undef, we can demand from
1364  // either side. If one side is known undef, choosing that side would
1365  // propagate undef.
1366  if (CElt->isNullValue())
1367  DemandedLHS.clearBit(i);
1368  else
1369  DemandedRHS.clearBit(i);
1370  }
1371  }
1372 
1373  simplifyAndSetOp(I, 1, DemandedLHS, UndefElts2);
1374  simplifyAndSetOp(I, 2, DemandedRHS, UndefElts3);
1375 
1376  // Output elements are undefined if the element from each arm is undefined.
1377  // TODO: This can be improved. See comment in select condition handling.
1378  UndefElts = UndefElts2 & UndefElts3;
1379  break;
1380  }
1381  case Instruction::BitCast: {
1382  // Vector->vector casts only.
1383  VectorType *VTy = dyn_cast<VectorType>(I->getOperand(0)->getType());
1384  if (!VTy) break;
1385  unsigned InVWidth = VTy->getNumElements();
1386  APInt InputDemandedElts(InVWidth, 0);
1387  UndefElts2 = APInt(InVWidth, 0);
1388  unsigned Ratio;
1389 
1390  if (VWidth == InVWidth) {
1391  // If we are converting from <4 x i32> -> <4 x f32>, we demand the same
1392  // elements as are demanded of us.
1393  Ratio = 1;
1394  InputDemandedElts = DemandedElts;
1395  } else if ((VWidth % InVWidth) == 0) {
1396  // If the number of elements in the output is a multiple of the number of
1397  // elements in the input then an input element is live if any of the
1398  // corresponding output elements are live.
1399  Ratio = VWidth / InVWidth;
1400  for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1401  if (DemandedElts[OutIdx])
1402  InputDemandedElts.setBit(OutIdx / Ratio);
1403  } else if ((InVWidth % VWidth) == 0) {
1404  // If the number of elements in the input is a multiple of the number of
1405  // elements in the output then an input element is live if the
1406  // corresponding output element is live.
1407  Ratio = InVWidth / VWidth;
1408  for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
1409  if (DemandedElts[InIdx / Ratio])
1410  InputDemandedElts.setBit(InIdx);
1411  } else {
1412  // Unsupported so far.
1413  break;
1414  }
1415 
1416  simplifyAndSetOp(I, 0, InputDemandedElts, UndefElts2);
1417 
1418  if (VWidth == InVWidth) {
1419  UndefElts = UndefElts2;
1420  } else if ((VWidth % InVWidth) == 0) {
1421  // If the number of elements in the output is a multiple of the number of
1422  // elements in the input then an output element is undef if the
1423  // corresponding input element is undef.
1424  for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1425  if (UndefElts2[OutIdx / Ratio])
1426  UndefElts.setBit(OutIdx);
1427  } else if ((InVWidth % VWidth) == 0) {
1428  // If the number of elements in the input is a multiple of the number of
1429  // elements in the output then an output element is undef if all of the
1430  // corresponding input elements are undef.
1431  for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) {
1432  APInt SubUndef = UndefElts2.lshr(OutIdx * Ratio).zextOrTrunc(Ratio);
1433  if (SubUndef.countPopulation() == Ratio)
1434  UndefElts.setBit(OutIdx);
1435  }
1436  } else {
1437  llvm_unreachable("Unimp");
1438  }
1439  break;
1440  }
1441  case Instruction::FPTrunc:
1442  case Instruction::FPExt:
1443  simplifyAndSetOp(I, 0, DemandedElts, UndefElts);
1444  break;
1445 
1446  case Instruction::Call: {
1448  if (!II) break;
1449  switch (II->getIntrinsicID()) {
1450  case Intrinsic::masked_gather: // fallthrough
1451  case Intrinsic::masked_load: {
1452  // Subtlety: If we load from a pointer, the pointer must be valid
1453  // regardless of whether the element is demanded. Doing otherwise risks
1454  // segfaults which didn't exist in the original program.
1455  APInt DemandedPtrs(APInt::getAllOnesValue(VWidth)),
1456  DemandedPassThrough(DemandedElts);
1457  if (auto *CV = dyn_cast<ConstantVector>(II->getOperand(2)))
1458  for (unsigned i = 0; i < VWidth; i++) {
1459  Constant *CElt = CV->getAggregateElement(i);
1460  if (CElt->isNullValue())
1461  DemandedPtrs.clearBit(i);
1462  else if (CElt->isAllOnesValue())
1463  DemandedPassThrough.clearBit(i);
1464  }
1465  if (II->getIntrinsicID() == Intrinsic::masked_gather)
1466  simplifyAndSetOp(II, 0, DemandedPtrs, UndefElts2);
1467  simplifyAndSetOp(II, 3, DemandedPassThrough, UndefElts3);
1468 
1469  // Output elements are undefined if the element from both sources are.
1470  // TODO: can strengthen via mask as well.
1471  UndefElts = UndefElts2 & UndefElts3;
1472  break;
1473  }
1474  case Intrinsic::x86_xop_vfrcz_ss:
1475  case Intrinsic::x86_xop_vfrcz_sd:
1476  // The instructions for these intrinsics are speced to zero upper bits not
1477  // pass them through like other scalar intrinsics. So we shouldn't just
1478  // use Arg0 if DemandedElts[0] is clear like we do for other intrinsics.
1479  // Instead we should return a zero vector.
1480  if (!DemandedElts[0]) {
1481  Worklist.Add(II);
1482  return ConstantAggregateZero::get(II->getType());
1483  }
1484 
1485  // Only the lower element is used.
1486  DemandedElts = 1;
1487  simplifyAndSetOp(II, 0, DemandedElts, UndefElts);
1488 
1489  // Only the lower element is undefined. The high elements are zero.
1490  UndefElts = UndefElts[0];
1491  break;
1492 
1493  // Unary scalar-as-vector operations that work column-wise.
1494  case Intrinsic::x86_sse_rcp_ss:
1495  case Intrinsic::x86_sse_rsqrt_ss:
1496  simplifyAndSetOp(II, 0, DemandedElts, UndefElts);
1497 
1498  // If lowest element of a scalar op isn't used then use Arg0.
1499  if (!DemandedElts[0]) {
1500  Worklist.Add(II);
1501  return II->getArgOperand(0);
1502  }
1503  // TODO: If only low elt lower SQRT to FSQRT (with rounding/exceptions
1504  // checks).
1505  break;
1506 
1507  // Binary scalar-as-vector operations that work column-wise. The high
1508  // elements come from operand 0. The low element is a function of both
1509  // operands.
1510  case Intrinsic::x86_sse_min_ss:
1511  case Intrinsic::x86_sse_max_ss:
1512  case Intrinsic::x86_sse_cmp_ss:
1513  case Intrinsic::x86_sse2_min_sd:
1514  case Intrinsic::x86_sse2_max_sd:
1515  case Intrinsic::x86_sse2_cmp_sd: {
1516  simplifyAndSetOp(II, 0, DemandedElts, UndefElts);
1517 
1518  // If lowest element of a scalar op isn't used then use Arg0.
1519  if (!DemandedElts[0]) {
1520  Worklist.Add(II);
1521  return II->getArgOperand(0);
1522  }
1523 
1524  // Only lower element is used for operand 1.
1525  DemandedElts = 1;
1526  simplifyAndSetOp(II, 1, DemandedElts, UndefElts2);
1527 
1528  // Lower element is undefined if both lower elements are undefined.
1529  // Consider things like undef&0. The result is known zero, not undef.
1530  if (!UndefElts2[0])
1531  UndefElts.clearBit(0);
1532 
1533  break;
1534  }
1535 
1536  // Binary scalar-as-vector operations that work column-wise. The high
1537  // elements come from operand 0 and the low element comes from operand 1.
1538  case Intrinsic::x86_sse41_round_ss:
1539  case Intrinsic::x86_sse41_round_sd: {
1540  // Don't use the low element of operand 0.
1541  APInt DemandedElts2 = DemandedElts;
1542  DemandedElts2.clearBit(0);
1543  simplifyAndSetOp(II, 0, DemandedElts2, UndefElts);
1544 
1545  // If lowest element of a scalar op isn't used then use Arg0.
1546  if (!DemandedElts[0]) {
1547  Worklist.Add(II);
1548  return II->getArgOperand(0);
1549  }
1550 
1551  // Only lower element is used for operand 1.
1552  DemandedElts = 1;
1553  simplifyAndSetOp(II, 1, DemandedElts, UndefElts2);
1554 
1555  // Take the high undef elements from operand 0 and take the lower element
1556  // from operand 1.
1557  UndefElts.clearBit(0);
1558  UndefElts |= UndefElts2[0];
1559  break;
1560  }
1561 
1562  // Three input scalar-as-vector operations that work column-wise. The high
1563  // elements come from operand 0 and the low element is a function of all
1564  // three inputs.
1565  case Intrinsic::x86_avx512_mask_add_ss_round:
1566  case Intrinsic::x86_avx512_mask_div_ss_round:
1567  case Intrinsic::x86_avx512_mask_mul_ss_round:
1568  case Intrinsic::x86_avx512_mask_sub_ss_round:
1569  case Intrinsic::x86_avx512_mask_max_ss_round:
1570  case Intrinsic::x86_avx512_mask_min_ss_round:
1571  case Intrinsic::x86_avx512_mask_add_sd_round:
1572  case Intrinsic::x86_avx512_mask_div_sd_round:
1573  case Intrinsic::x86_avx512_mask_mul_sd_round:
1574  case Intrinsic::x86_avx512_mask_sub_sd_round:
1575  case Intrinsic::x86_avx512_mask_max_sd_round:
1576  case Intrinsic::x86_avx512_mask_min_sd_round:
1577  simplifyAndSetOp(II, 0, DemandedElts, UndefElts);
1578 
1579  // If lowest element of a scalar op isn't used then use Arg0.
1580  if (!DemandedElts[0]) {
1581  Worklist.Add(II);
1582  return II->getArgOperand(0);
1583  }
1584 
1585  // Only lower element is used for operand 1 and 2.
1586  DemandedElts = 1;
1587  simplifyAndSetOp(II, 1, DemandedElts, UndefElts2);
1588  simplifyAndSetOp(II, 2, DemandedElts, UndefElts3);
1589 
1590  // Lower element is undefined if all three lower elements are undefined.
1591  // Consider things like undef&0. The result is known zero, not undef.
1592  if (!UndefElts2[0] || !UndefElts3[0])
1593  UndefElts.clearBit(0);
1594 
1595  break;
1596 
1597  case Intrinsic::x86_sse2_packssdw_128:
1598  case Intrinsic::x86_sse2_packsswb_128:
1599  case Intrinsic::x86_sse2_packuswb_128:
1600  case Intrinsic::x86_sse41_packusdw:
1601  case Intrinsic::x86_avx2_packssdw:
1602  case Intrinsic::x86_avx2_packsswb:
1603  case Intrinsic::x86_avx2_packusdw:
1604  case Intrinsic::x86_avx2_packuswb:
1605  case Intrinsic::x86_avx512_packssdw_512:
1606  case Intrinsic::x86_avx512_packsswb_512:
1607  case Intrinsic::x86_avx512_packusdw_512:
1608  case Intrinsic::x86_avx512_packuswb_512: {
1609  auto *Ty0 = II->getArgOperand(0)->getType();
1610  unsigned InnerVWidth = Ty0->getVectorNumElements();
1611  assert(VWidth == (InnerVWidth * 2) && "Unexpected input size");
1612 
1613  unsigned NumLanes = Ty0->getPrimitiveSizeInBits() / 128;
1614  unsigned VWidthPerLane = VWidth / NumLanes;
1615  unsigned InnerVWidthPerLane = InnerVWidth / NumLanes;
1616 
1617  // Per lane, pack the elements of the first input and then the second.
1618  // e.g.
1619  // v8i16 PACK(v4i32 X, v4i32 Y) - (X[0..3],Y[0..3])
1620  // v32i8 PACK(v16i16 X, v16i16 Y) - (X[0..7],Y[0..7]),(X[8..15],Y[8..15])
1621  for (int OpNum = 0; OpNum != 2; ++OpNum) {
1622  APInt OpDemandedElts(InnerVWidth, 0);
1623  for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
1624  unsigned LaneIdx = Lane * VWidthPerLane;
1625  for (unsigned Elt = 0; Elt != InnerVWidthPerLane; ++Elt) {
1626  unsigned Idx = LaneIdx + Elt + InnerVWidthPerLane * OpNum;
1627  if (DemandedElts[Idx])
1628  OpDemandedElts.setBit((Lane * InnerVWidthPerLane) + Elt);
1629  }
1630  }
1631 
1632  // Demand elements from the operand.
1633  APInt OpUndefElts(InnerVWidth, 0);
1634  simplifyAndSetOp(II, OpNum, OpDemandedElts, OpUndefElts);
1635 
1636  // Pack the operand's UNDEF elements, one lane at a time.
1637  OpUndefElts = OpUndefElts.zext(VWidth);
1638  for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
1639  APInt LaneElts = OpUndefElts.lshr(InnerVWidthPerLane * Lane);
1640  LaneElts = LaneElts.getLoBits(InnerVWidthPerLane);
1641  LaneElts <<= InnerVWidthPerLane * (2 * Lane + OpNum);
1642  UndefElts |= LaneElts;
1643  }
1644  }
1645  break;
1646  }
1647 
1648  // PSHUFB
1649  case Intrinsic::x86_ssse3_pshuf_b_128:
1650  case Intrinsic::x86_avx2_pshuf_b:
1651  case Intrinsic::x86_avx512_pshuf_b_512:
1652  // PERMILVAR
1653  case Intrinsic::x86_avx_vpermilvar_ps:
1654  case Intrinsic::x86_avx_vpermilvar_ps_256:
1655  case Intrinsic::x86_avx512_vpermilvar_ps_512:
1656  case Intrinsic::x86_avx_vpermilvar_pd:
1657  case Intrinsic::x86_avx_vpermilvar_pd_256:
1658  case Intrinsic::x86_avx512_vpermilvar_pd_512:
1659  // PERMV
1660  case Intrinsic::x86_avx2_permd:
1661  case Intrinsic::x86_avx2_permps: {
1662  simplifyAndSetOp(II, 1, DemandedElts, UndefElts);
1663  break;
1664  }
1665 
1666  // SSE4A instructions leave the upper 64-bits of the 128-bit result
1667  // in an undefined state.
1668  case Intrinsic::x86_sse4a_extrq:
1669  case Intrinsic::x86_sse4a_extrqi:
1670  case Intrinsic::x86_sse4a_insertq:
1671  case Intrinsic::x86_sse4a_insertqi:
1672  UndefElts.setHighBits(VWidth / 2);
1673  break;
1674  case Intrinsic::amdgcn_buffer_load:
1675  case Intrinsic::amdgcn_buffer_load_format:
1676  case Intrinsic::amdgcn_raw_buffer_load:
1677  case Intrinsic::amdgcn_raw_buffer_load_format:
1678  case Intrinsic::amdgcn_struct_buffer_load:
1679  case Intrinsic::amdgcn_struct_buffer_load_format:
1680  return simplifyAMDGCNMemoryIntrinsicDemanded(II, DemandedElts);
1681  default: {
1682  if (getAMDGPUImageDMaskIntrinsic(II->getIntrinsicID()))
1683  return simplifyAMDGCNMemoryIntrinsicDemanded(II, DemandedElts, 0);
1684 
1685  break;
1686  }
1687  } // switch on IntrinsicID
1688  break;
1689  } // case Call
1690  } // switch on Opcode
1691 
1692  // TODO: We bail completely on integer div/rem and shifts because they have
1693  // UB/poison potential, but that should be refined.
1694  BinaryOperator *BO;
1695  if (match(I, m_BinOp(BO)) && !BO->isIntDivRem() && !BO->isShift()) {
1696  simplifyAndSetOp(I, 0, DemandedElts, UndefElts);
1697  simplifyAndSetOp(I, 1, DemandedElts, UndefElts2);
1698 
1699  // Any change to an instruction with potential poison must clear those flags
1700  // because we can not guarantee those constraints now. Other analysis may
1701  // determine that it is safe to re-apply the flags.
1702  if (MadeChange)
1704 
1705  // Output elements are undefined if both are undefined. Consider things
1706  // like undef & 0. The result is known zero, not undef.
1707  UndefElts &= UndefElts2;
1708  }
1709 
1710  // If we've proven all of the lanes undef, return an undef value.
1711  // TODO: Intersect w/demanded lanes
1712  if (UndefElts.isAllOnesValue())
1713  return UndefValue::get(I->getType());;
1714 
1715  return MadeChange ? I : nullptr;
1716 }
void clearAllBits()
Set every bit to 0.
Definition: APInt.h:1451
Type * getVectorElementType() const
Definition: Type.h:370
uint64_t CallInst * C
void computeKnownBits(const Value *V, KnownBits &Known, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, OptimizationRemarkEmitter *ORE=nullptr, bool UseInstrInfo=true)
Determine which bits of V are known to be either zero or one and return them in the KnownZero/KnownOn...
BinOpPred_match< LHS, RHS, is_right_shift_op > m_Shr(const LHS &L, const RHS &R)
Matches logical shift operations.
Definition: PatternMatch.h:940
IntegerType * getType() const
getType - Specialize the getType() method to always return an IntegerType, which reduces the amount o...
Definition: Constants.h:171
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:70
void setSignBit()
Set the sign bit to 1.
Definition: APInt.h:1412
bool isSignMask() const
Check if the APInt&#39;s value is returned by getSignMask.
Definition: APInt.h:472
bool isAllOnesValue() const
Return true if this is the value that would be returned by getAllOnesValue.
Definition: Constants.cpp:99
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:561
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Type * getParamType(unsigned i) const
Parameter type accessors.
Definition: DerivedTypes.h:134
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
bool hasConflict() const
Returns true if there is conflicting information.
Definition: KnownBits.h:46
This class represents zero extension of integer types.
static ConstantAggregateZero * get(Type *Ty)
Definition: Constants.cpp:1341
APInt zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:857
This class represents a function call, abstracting a target machine&#39;s calling convention.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:647
gep_type_iterator gep_type_end(const User *GEP)
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
Definition: APInt.h:1328
This instruction constructs a fixed permutation of two input vectors.
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:709
const Use & getOperandUse(unsigned i) const
Definition: User.h:182
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:810
void setAllBits()
Set every bit to 1.
Definition: APInt.h:1389
void setArgOperand(unsigned i, Value *v)
Definition: InstrTypes.h:1223
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
Definition: APInt.cpp:875
Hexagon Common GEP
void setBitsFrom(unsigned loBit)
Set the top bits starting from loBit.
Definition: APInt.h:1436
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:229
unsigned getBitWidth() const
Get the bit width of this value.
Definition: KnownBits.h:39
bool hasNoSignedWrap() const
Determine whether the no signed wrap flag is set.
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1508
Signed maximum.
Value * get() const
Definition: Use.h:107
static Constant * getNullValue(Type *Ty)
Constructor to create a &#39;0&#39; constant of arbitrary type.
Definition: Constants.cpp:274
Value * getArgOperand(unsigned i) const
Definition: InstrTypes.h:1218
SI optimize exec mask operations pre RA
unsigned countTrailingZeros() const
Count the number of trailing zero bits.
Definition: APInt.h:1631
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:47
static InsertElementInst * Create(Value *Vec, Value *NewElt, Value *Idx, const Twine &NameStr="", Instruction *InsertBefore=nullptr)
APInt getLoBits(unsigned numBits) const
Compute an APInt containing numBits lowbits from this APInt.
Definition: APInt.cpp:515
void setBit(unsigned BitPosition)
Set a given bit to 1.
Definition: APInt.h:1402
This class represents the LLVM &#39;select&#39; instruction.
void setHighBits(unsigned hiBits)
Set the top hiBits bits.
Definition: APInt.h:1446
This is the base class for all instructions that perform data casts.
Definition: InstrTypes.h:416
static KnownBits computeForAddSub(bool Add, bool NSW, const KnownBits &LHS, KnownBits RHS)
Compute known bits resulting from adding LHS and RHS.
Definition: KnownBits.cpp:54
APInt shl(unsigned shiftAmt) const
Left-shift function.
Definition: APInt.h:992
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
void dropPoisonGeneratingFlags()
Drops flags that may cause this instruction to evaluate to poison despite having non-poison inputs...
unsigned Intr
uint64_t getNumElements() const
Definition: DerivedTypes.h:390
void lshrInPlace(unsigned ShiftAmt)
Logical right-shift this APInt by ShiftAmt in place.
Definition: APInt.h:977
KnownBits zextOrTrunc(unsigned BitWidth, bool ExtendedBitsAreKnownZero) const
Extends or truncates the underlying known Zero and One bits.
Definition: KnownBits.h:138
unsigned getActiveBits() const
Compute the number of active bits in the value.
Definition: APInt.h:1532
bool isNullValue() const
Return true if this is the value that would be returned by getNullValue.
Definition: Constants.cpp:84
Class to represent function types.
Definition: DerivedTypes.h:102
void setIsExact(bool b=true)
Set or clear the exact flag on this instruction, which must be an operator which supports this flag...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
void clearBit(unsigned BitPosition)
Set a given bit to 0.
Definition: APInt.h:1461
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:137
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
bool isIntOrIntVectorTy() const
Return true if this is an integer type or a vector of integer types.
Definition: Type.h:202
void takeName(Value *V)
Transfer the name from V to this value.
Definition: Value.cpp:291
Function * getDeclaration(Module *M, ID id, ArrayRef< Type *> Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
Definition: Function.cpp:1022
Value * getOperand(unsigned i) const
Definition: User.h:169
Constant * getAggregateElement(unsigned Elt) const
For aggregates (struct/array/vector) return the constant that corresponds to the specified element if...
Definition: Constants.cpp:344
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:635
an instruction for type-safe pointer arithmetic to access elements of arrays and structs ...
Definition: Instructions.h:873
unsigned ComputeNumSignBits(const Value *Op, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return the number of times the sign bit of the register is replicated into the other bits...
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:395
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:148
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
apint_match m_APInt(const APInt *&Res)
Match a ConstantInt or splatted ConstantVector, binding the specified pointer to the contained APInt...
Definition: PatternMatch.h:175
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
Definition: APInt.cpp:1612
unsigned countPopulation() const
Count the number of bits set.
Definition: APInt.h:1657
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
bool ult(const APInt &RHS) const
Unsigned less than comparison.
Definition: APInt.h:1184
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
void resetAll()
Resets the known state of all bits.
Definition: KnownBits.h:65
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:138
bool isMask(unsigned numBits) const
Definition: APInt.h:494
bool isOneValue() const
Determine if this is a value of 1.
Definition: APInt.h:410
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
class_match< BinaryOperator > m_BinOp()
Match an arbitrary binary operation and ignore it.
Definition: PatternMatch.h:73
const Value * getCondition() const
static UndefValue * get(Type *T)
Static factory methods - Return an &#39;undef&#39; object of the specified type.
Definition: Constants.cpp:1424
static int getMaskValue(const Constant *Mask, unsigned Elt)
Return the shuffle mask value for the specified element of the mask.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:970
static Constant * getIntegerValue(Type *Ty, const APInt &V)
Return the value for an integer or pointer constant, or a vector thereof, with the given scalar value...
Definition: Constants.cpp:311
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:50
void makeNonNegative()
Make this value non-negative.
Definition: KnownBits.h:106
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
Definition: APInt.h:554
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
Definition: APInt.h:946
void setHasNoSignedWrap(bool b=true)
Set or clear the nsw flag on this instruction, which must be an operator which supports this flag...
unsigned getNumOperands() const
Definition: User.h:191
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:519
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
SelectPatternFlavor Flavor
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type...
Definition: Type.cpp:129
void getIntrinsicInfoTableEntries(ID id, SmallVectorImpl< IITDescriptor > &T)
Return the IIT table descriptor for the specified intrinsic into an array of IITDescriptors.
Definition: Function.cpp:867
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
SelectPatternFlavor
Specific patterns of select instructions we can match.
Type * getReturnType() const
Definition: DerivedTypes.h:123
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:631
bool uge(const APInt &RHS) const
Unsigned greater or equal comparison.
Definition: APInt.h:1292
KnownBits sext(unsigned BitWidth) const
Sign extends the underlying known Zero and One bits.
Definition: KnownBits.h:130
void setOperand(unsigned i, Value *Val)
Definition: User.h:174
unsigned getVectorNumElements() const
Definition: DerivedTypes.h:493
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:163
Class to represent vector types.
Definition: DerivedTypes.h:424
Class for arbitrary precision integers.
Definition: APInt.h:69
bool isPowerOf2() const
Check if this APInt&#39;s value is a power of two greater than zero.
Definition: APInt.h:463
unsigned getNumArgOperands() const
Definition: InstrTypes.h:1216
bool intersects(const APInt &RHS) const
This operation tests if there are any pairs of corresponding bits between this APInt and RHS that are...
Definition: APInt.h:1320
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:175
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value...
Definition: APInt.h:481
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:214
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation.
Definition: InstrTypes.h:1264
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
bool matchIntrinsicType(Type *Ty, ArrayRef< IITDescriptor > &Infos, SmallVectorImpl< Type *> &ArgTys)
Match the specified type (which comes from an intrinsic argument or return value) with the type const...
Definition: Function.cpp:1041
#define I(x, y, z)
Definition: MD5.cpp:58
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
bool hasNoUnsignedWrap() const
Determine whether the no unsigned wrap flag is set.
Signed minimum.
void setHasNoUnsignedWrap(bool b=true)
Set or clear the nuw flag on this instruction, which must be an operator which supports this flag...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:565
LLVM Value Representation.
Definition: Value.h:72
This file provides internal interfaces used to implement the InstCombine.
SelectPatternResult matchSelectPattern(Value *V, Value *&LHS, Value *&RHS, Instruction::CastOps *CastOp=nullptr, unsigned Depth=0)
Pattern match integer [SU]MIN, [SU]MAX and ABS idioms, returning the kind and providing the out param...
void copyMetadata(const Instruction &SrcInst, ArrayRef< unsigned > WL=ArrayRef< unsigned >())
Copy metadata from SrcInst to this instruction.
static VectorType * get(Type *ElementType, unsigned NumElements)
This static method is the primary way to construct an VectorType.
Definition: Type.cpp:605
static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo, const APInt &Demanded)
Check to see if the specified operand of the specified instruction is a constant integer.
bool isSignBitSet() const
Determine if sign bit of this APInt is set.
Definition: APInt.h:375
unsigned countMinLeadingZeros() const
Returns the minimum number of leading zero bits.
Definition: KnownBits.h:156
bool hasOneUse() const
Return true if there is exactly one user of this value.
Definition: Value.h:412
bool isIntDivRem() const
Definition: Instruction.h:131
unsigned countLeadingOnes() const
Count the number of leading one bits.
Definition: APInt.h:1611
bool isNonNegative() const
Returns true if this value is known to be non-negative.
Definition: KnownBits.h:98
unsigned countLeadingZeros() const
The APInt version of the countLeadingZeros functions in MathExtras.h.
Definition: APInt.h:1595
VectorType * getType() const
Overload to return most specific vector type.
static Constant * get(ArrayRef< Constant *> V)
Definition: Constants.cpp:1088
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
void setLowBits(unsigned loBits)
Set the bottom loBits bits.
Definition: APInt.h:1441
bool isNullValue() const
Determine if all bits are clear.
Definition: APInt.h:405
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:43
const BasicBlock * getParent() const
Definition: Instruction.h:66
gep_type_iterator gep_type_begin(const User *GEP)