27#define DEBUG_TYPE "instcombine"
31 cl::desc(
"Verify that computeKnownBits() and "
32 "SimplifyDemandedBits() are consistent"),
36 "instcombine-simplify-vector-elts-depth",
38 "Depth limit when simplifying vector instructions and their operands"),
45 const APInt &Demanded) {
47 assert(OpNo < I->getNumOperands() &&
"Operand index too large");
56 if (
C->isSubsetOf(Demanded))
60 I->setOperand(OpNo, ConstantInt::get(
Op->getType(), *
C & Demanded));
72 const APInt &DemandedMask,
75 assert(
I->getOpcode() == Instruction::LShr &&
76 "Only lshr instruction supported");
80 if (!
match(
I->getOperand(0),
90 if (DemandedBitWidth > ShlAmt)
94 if (
Upper->getType()->getScalarSizeInBits() < ShlAmt + DemandedBitWidth)
101 Value *ShrAmt =
I->getOperand(1);
106 if (~KnownShrBits.
Zero != ShlAmt)
125 if (
unsigned BitWidth = Ty->getScalarSizeInBits())
128 return DL.getPointerTypeSizeInBits(Ty);
137 SQ.getWithInstruction(&Inst));
138 if (!V)
return false;
139 if (V == &Inst)
return true;
155 const APInt &DemandedMask,
159 Use &U =
I->getOperandUse(OpNo);
167 if (DemandedMask.
isZero()) {
192 if (!NewVal)
return false;
224 const APInt &DemandedMask,
228 assert(
I !=
nullptr &&
"Null pointer of Value???");
231 Type *VTy =
I->getType();
235 "Value *V, DemandedMask and Known must have same BitWidth");
241 auto disableWrapFlagsBasedOnUnusedHighBits = [](
Instruction *
I,
247 I->setHasNoSignedWrap(
false);
248 I->setHasNoUnsignedWrap(
false);
255 auto simplifyOperandsBasedOnUnusedHighBits = [&](
APInt &DemandedFromOps) {
264 disableWrapFlagsBasedOnUnusedHighBits(
I, NLZ);
270 switch (
I->getOpcode()) {
274 case Instruction::And: {
292 return I->getOperand(0);
294 return I->getOperand(1);
302 case Instruction::Or: {
308 I->dropPoisonGeneratingFlags();
323 return I->getOperand(0);
325 return I->getOperand(1);
334 RHSCache(
I->getOperand(1), RHSKnown);
343 case Instruction::Xor: {
348 if (DemandedMask == 1 &&
355 return Builder.CreateUnaryIntrinsic(Intrinsic::ctpop,
Xor);
369 return I->getOperand(0);
371 return I->getOperand(1);
378 BinaryOperator::CreateOr(
I->getOperand(0),
I->getOperand(1));
392 ~RHSKnown.
One & DemandedMask);
402 if ((*
C | ~DemandedMask).isAllOnes()) {
418 if (LHSInst->getOpcode() == Instruction::And && LHSInst->hasOneUse() &&
421 (LHSKnown.One & RHSKnown.
One & DemandedMask) != 0) {
422 APInt NewMask = ~(LHSKnown.One & RHSKnown.
One & DemandedMask);
425 Instruction *NewAnd = BinaryOperator::CreateAnd(
I->getOperand(0), AndC);
429 Instruction *NewXor = BinaryOperator::CreateXor(NewAnd, XorC);
435 case Instruction::Select: {
445 auto CanonicalizeSelectConstant = [](
Instruction *
I,
unsigned OpNo,
446 const APInt &DemandedMask) {
466 if ((*CmpC & DemandedMask) == (*SelC & DemandedMask)) {
467 I->setOperand(OpNo, ConstantInt::get(
I->getType(), *CmpC));
472 if (CanonicalizeSelectConstant(
I, 1, DemandedMask) ||
473 CanonicalizeSelectConstant(
I, 2, DemandedMask))
484 case Instruction::Trunc: {
498 return Builder.CreateLShr(Trunc,
C->getZExtValue());
503 case Instruction::ZExt: {
504 unsigned SrcBitWidth =
I->getOperand(0)->getType()->getScalarSizeInBits();
512 I->dropPoisonGeneratingFlags();
516 if (
I->getOpcode() == Instruction::ZExt &&
I->hasNonNeg() &&
523 case Instruction::SExt: {
525 unsigned SrcBitWidth =
I->getOperand(0)->getType()->getScalarSizeInBits();
527 APInt InputDemandedBits = DemandedMask.
trunc(SrcBitWidth);
532 InputDemandedBits.
setBit(SrcBitWidth-1);
553 case Instruction::Add: {
554 if ((DemandedMask & 1) == 0) {
560 X->getType()->isIntOrIntVectorTy(1) &&
X->getType() ==
Y->getType()) {
570 return Builder.CreateSExt(AndNot, VTy);
575 X->getType()->isIntOrIntVectorTy(1) &&
X->getType() ==
Y->getType() &&
576 (
I->getOperand(0)->hasOneUse() ||
I->getOperand(1)->hasOneUse())) {
597 return disableWrapFlagsBasedOnUnusedHighBits(
I, NLZ);
603 APInt DemandedFromLHS = DemandedFromOps;
607 return disableWrapFlagsBasedOnUnusedHighBits(
I, NLZ);
612 return I->getOperand(0);
613 if (DemandedFromOps.
isSubsetOf(LHSKnown.Zero))
614 return I->getOperand(1);
623 return Builder.CreateXor(
I->getOperand(0), ConstantInt::get(VTy, *
C));
633 case Instruction::Sub: {
640 return disableWrapFlagsBasedOnUnusedHighBits(
I, NLZ);
646 APInt DemandedFromLHS = DemandedFromOps;
650 return disableWrapFlagsBasedOnUnusedHighBits(
I, NLZ);
655 return I->getOperand(0);
658 if (DemandedFromOps.
isOne() && DemandedFromOps.
isSubsetOf(LHSKnown.Zero))
659 return I->getOperand(1);
667 return Builder.CreateNot(
I->getOperand(1));
676 case Instruction::Mul: {
677 APInt DemandedFromOps;
678 if (simplifyOperandsBasedOnUnusedHighBits(DemandedFromOps))
688 Constant *ShiftC = ConstantInt::get(VTy, CTZ);
689 Instruction *Shl = BinaryOperator::CreateShl(
I->getOperand(0), ShiftC);
696 if (
I->getOperand(0) ==
I->getOperand(1) && DemandedMask.
ult(4)) {
697 Constant *One = ConstantInt::get(VTy, 1);
698 Instruction *And1 = BinaryOperator::CreateAnd(
I->getOperand(0), One);
705 case Instruction::Shl: {
712 DemandedMask, Known))
716 if (
I->hasOneUse()) {
718 if (Inst && Inst->getOpcode() == BinaryOperator::Or) {
720 auto [IID, FShiftArgs] = *Opt;
721 if ((IID == Intrinsic::fshl || IID == Intrinsic::fshr) &&
722 FShiftArgs[0] == FShiftArgs[1]) {
734 if (
I->hasNoSignedWrap()) {
738 if (SignBits > ShiftAmt && SignBits - ShiftAmt >= NumHiDemandedBits)
739 return I->getOperand(0);
749 Constant *LeftShiftAmtC = ConstantInt::get(VTy, ShiftAmt);
753 LeftShiftAmtC,
DL) ==
C) {
754 Instruction *Lshr = BinaryOperator::CreateLShr(NewC,
X);
760 APInt DemandedMaskIn(DemandedMask.
lshr(ShiftAmt));
784 I->dropPoisonGeneratingFlags();
792 case Instruction::LShr: {
798 if (
I->hasOneUse()) {
800 if (Inst && Inst->getOpcode() == BinaryOperator::Or) {
802 auto [IID, FShiftArgs] = *Opt;
803 if ((IID == Intrinsic::fshl || IID == Intrinsic::fshr) &&
804 FShiftArgs[0] == FShiftArgs[1]) {
820 if (SignBits >= NumHiDemandedBits)
821 return I->getOperand(0);
830 Constant *RightShiftAmtC = ConstantInt::get(VTy, ShiftAmt);
834 RightShiftAmtC,
DL) ==
C) {
841 if (
match(
I->getOperand(0),
845 X, ConstantInt::get(
X->getType(), Factor->
lshr(ShiftAmt)));
851 APInt DemandedMaskIn(DemandedMask.
shl(ShiftAmt));
854 I->dropPoisonGeneratingFlags();
869 case Instruction::AShr: {
875 if (SignBits >= NumHiDemandedBits)
876 return I->getOperand(0);
882 if (DemandedMask.
isOne()) {
885 I->getOperand(0),
I->getOperand(1),
I->getName());
894 APInt DemandedMaskIn(DemandedMask.
shl(ShiftAmt));
897 bool ShiftedInBitsDemanded = DemandedMask.
countl_zero() < ShiftAmt;
898 if (ShiftedInBitsDemanded)
902 I->dropPoisonGeneratingFlags();
908 if (Known.
Zero[
BitWidth - 1] || !ShiftedInBitsDemanded) {
918 ShiftAmt != 0,
I->isExact());
924 case Instruction::UDiv: {
930 APInt DemandedMaskIn =
935 I->dropPoisonGeneratingFlags();
946 case Instruction::SRem: {
949 if (DemandedMask.
ult(*Rem))
950 return I->getOperand(0);
952 APInt LowBits = *Rem - 1;
963 case Instruction::Call: {
964 bool KnownBitsComputed =
false;
966 switch (
II->getIntrinsicID()) {
967 case Intrinsic::abs: {
968 if (DemandedMask == 1)
969 return II->getArgOperand(0);
972 case Intrinsic::ctpop: {
980 II->getModule(), Intrinsic::ctpop, VTy);
985 case Intrinsic::bswap: {
1002 NewVal = BinaryOperator::CreateLShr(
1003 II->getArgOperand(0), ConstantInt::get(VTy, NLZ - NTZ));
1005 NewVal = BinaryOperator::CreateShl(
1006 II->getArgOperand(0), ConstantInt::get(VTy, NTZ - NLZ));
1012 case Intrinsic::ptrmask: {
1013 unsigned MaskWidth =
I->getOperand(1)->getType()->getScalarSizeInBits();
1018 I, 1, (DemandedMask & ~LHSKnown.Zero).zextOrTrunc(MaskWidth),
1019 RHSKnown, Q,
Depth + 1))
1025 Known = LHSKnown & RHSKnown;
1026 KnownBitsComputed =
true;
1041 if (DemandedMask.
isSubsetOf(RHSKnown.One | LHSKnown.Zero))
1042 return I->getOperand(0);
1046 I, 1, (DemandedMask & ~LHSKnown.Zero).zextOrTrunc(MaskWidth)))
1061 if (!LHSKnown.isZero()) {
1062 const unsigned trailingZeros = LHSKnown.countMinTrailingZeros();
1065 uint64_t HighBitsGEPIndex = GEPIndex & ~PointerAlignBits;
1067 GEPIndex & PointerAlignBits & PtrMaskImmediate;
1069 uint64_t MaskedGEPIndex = HighBitsGEPIndex | MaskedLowBitsGEPIndex;
1071 if (MaskedGEPIndex != GEPIndex) {
1074 Type *GEPIndexType =
1075 DL.getIndexType(
GEP->getPointerOperand()->getType());
1077 GEP->getSourceElementType(), InnerPtr,
1078 ConstantInt::get(GEPIndexType, MaskedGEPIndex),
1079 GEP->getName(),
GEP->isInBounds());
1090 case Intrinsic::fshr:
1091 case Intrinsic::fshl: {
1099 if (
II->getIntrinsicID() == Intrinsic::fshr)
1102 APInt DemandedMaskLHS(DemandedMask.
lshr(ShiftAmt));
1104 if (
I->getOperand(0) !=
I->getOperand(1)) {
1110 I->dropPoisonGeneratingAnnotations();
1117 if (DemandedMaskLHS.
isSubsetOf(LHSKnown.Zero | LHSKnown.One) &&
1131 LHSKnown <<= ShiftAmt;
1134 KnownBitsComputed =
true;
1137 case Intrinsic::umax: {
1144 CTZ >=
C->getActiveBits())
1145 return II->getArgOperand(0);
1148 case Intrinsic::umin: {
1156 CTZ >=
C->getBitWidth() -
C->countl_one())
1157 return II->getArgOperand(0);
1163 *
II, DemandedMask, Known, KnownBitsComputed);
1171 if (!KnownBitsComputed)
1177 if (
I->getType()->isPointerTy()) {
1178 Align Alignment =
I->getPointerAlignment(
DL);
1186 if (!
I->getType()->isPointerTy() &&
1192 if (Known != ReferenceKnown) {
1193 errs() <<
"Mismatched known bits for " << *
I <<
" in "
1194 <<
I->getFunction()->getName() <<
"\n";
1195 errs() <<
"computeKnownBits(): " << ReferenceKnown <<
"\n";
1196 errs() <<
"SimplifyDemandedBits(): " << Known <<
"\n";
1211 Type *ITy =
I->getType();
1220 switch (
I->getOpcode()) {
1221 case Instruction::And: {
1236 return I->getOperand(0);
1238 return I->getOperand(1);
1242 case Instruction::Or: {
1259 return I->getOperand(0);
1261 return I->getOperand(1);
1265 case Instruction::Xor: {
1281 return I->getOperand(0);
1283 return I->getOperand(1);
1287 case Instruction::Add: {
1295 return I->getOperand(0);
1299 return I->getOperand(1);
1307 case Instruction::Sub: {
1315 return I->getOperand(0);
1324 case Instruction::AShr: {
1337 const APInt *ShiftRC;
1338 const APInt *ShiftLC;
1386 if (!ShlOp1 || !ShrOp1)
1391 unsigned BitWidth = Ty->getScalarSizeInBits();
1400 Known.
Zero &= DemandedMask;
1405 bool isLshr = (Shr->
getOpcode() == Instruction::LShr);
1406 BitMask1 = isLshr ? (BitMask1.
lshr(ShrAmt) << ShlAmt) :
1407 (BitMask1.
ashr(ShrAmt) << ShlAmt);
1409 if (ShrAmt <= ShlAmt) {
1410 BitMask2 <<= (ShlAmt - ShrAmt);
1412 BitMask2 = isLshr ? BitMask2.
lshr(ShrAmt - ShlAmt):
1413 BitMask2.
ashr(ShrAmt - ShlAmt);
1417 if ((BitMask1 & DemandedMask) == (BitMask2 & DemandedMask)) {
1418 if (ShrAmt == ShlAmt)
1425 if (ShrAmt < ShlAmt) {
1427 New = BinaryOperator::CreateShl(VarX, Amt);
1433 New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) :
1434 BinaryOperator::CreateAShr(VarX, Amt);
1436 New->setIsExact(
true);
1462 bool AllowMultipleUsers) {
1470 assert((DemandedElts & ~EltMask) == 0 &&
"Invalid DemandedElts!");
1474 PoisonElts = EltMask;
1478 if (DemandedElts.
isZero()) {
1479 PoisonElts = EltMask;
1494 for (
unsigned i = 0; i != VWidth; ++i) {
1495 if (!DemandedElts[i]) {
1501 Constant *Elt =
C->getAggregateElement(i);
1502 if (!Elt)
return nullptr;
1511 return NewCV !=
C ? NewCV :
nullptr;
1518 if (!AllowMultipleUsers) {
1522 if (!V->hasOneUse()) {
1531 DemandedElts = EltMask;
1536 if (!
I)
return nullptr;
1538 bool MadeChange =
false;
1539 auto simplifyAndSetOp = [&](
Instruction *Inst,
unsigned OpNum,
1549 APInt PoisonElts2(VWidth, 0);
1550 APInt PoisonElts3(VWidth, 0);
1551 switch (
I->getOpcode()) {
1554 case Instruction::GetElementPtr: {
1572 for (
unsigned i = 0; i <
I->getNumOperands(); i++) {
1576 PoisonElts = EltMask;
1579 if (
I->getOperand(i)->getType()->isVectorTy()) {
1580 APInt PoisonEltsOp(VWidth, 0);
1581 simplifyAndSetOp(
I, i, DemandedElts, PoisonEltsOp);
1586 PoisonElts |= PoisonEltsOp;
1592 case Instruction::InsertElement: {
1599 simplifyAndSetOp(
I, 0, DemandedElts, PoisonElts2);
1606 APInt PreInsertDemandedElts = DemandedElts;
1608 PreInsertDemandedElts.
clearBit(IdxNo);
1616 if (PreInsertDemandedElts == 0 &&
1623 simplifyAndSetOp(
I, 0, PreInsertDemandedElts, PoisonElts);
1627 if (IdxNo >= VWidth || !DemandedElts[IdxNo]) {
1629 return I->getOperand(0);
1636 case Instruction::ShuffleVector: {
1638 assert(Shuffle->getOperand(0)->getType() ==
1639 Shuffle->getOperand(1)->getType() &&
1640 "Expected shuffle operands to have same type");
1651 APInt LeftDemanded(OpWidth, 1);
1652 APInt LHSPoisonElts(OpWidth, 0);
1653 simplifyAndSetOp(
I, 0, LeftDemanded, LHSPoisonElts);
1654 if (LHSPoisonElts[0])
1655 PoisonElts = EltMask;
1661 APInt LeftDemanded(OpWidth, 0), RightDemanded(OpWidth, 0);
1662 for (
unsigned i = 0; i < VWidth; i++) {
1663 if (DemandedElts[i]) {
1664 unsigned MaskVal = Shuffle->getMaskValue(i);
1665 if (MaskVal != -1u) {
1666 assert(MaskVal < OpWidth * 2 &&
1667 "shufflevector mask index out of range!");
1668 if (MaskVal < OpWidth)
1669 LeftDemanded.setBit(MaskVal);
1671 RightDemanded.
setBit(MaskVal - OpWidth);
1676 APInt LHSPoisonElts(OpWidth, 0);
1677 simplifyAndSetOp(
I, 0, LeftDemanded, LHSPoisonElts);
1679 APInt RHSPoisonElts(OpWidth, 0);
1680 simplifyAndSetOp(
I, 1, RightDemanded, RHSPoisonElts);
1693 if (VWidth == OpWidth) {
1694 bool IsIdentityShuffle =
true;
1695 for (
unsigned i = 0; i < VWidth; i++) {
1696 unsigned MaskVal = Shuffle->getMaskValue(i);
1697 if (DemandedElts[i] && i != MaskVal) {
1698 IsIdentityShuffle =
false;
1702 if (IsIdentityShuffle)
1703 return Shuffle->getOperand(0);
1706 bool NewPoisonElts =
false;
1707 unsigned LHSIdx = -1u, LHSValIdx = -1u;
1708 unsigned RHSIdx = -1u, RHSValIdx = -1u;
1709 bool LHSUniform =
true;
1710 bool RHSUniform =
true;
1711 for (
unsigned i = 0; i < VWidth; i++) {
1712 unsigned MaskVal = Shuffle->getMaskValue(i);
1713 if (MaskVal == -1u) {
1715 }
else if (!DemandedElts[i]) {
1716 NewPoisonElts =
true;
1718 }
else if (MaskVal < OpWidth) {
1719 if (LHSPoisonElts[MaskVal]) {
1720 NewPoisonElts =
true;
1723 LHSIdx = LHSIdx == -1u ? i : OpWidth;
1724 LHSValIdx = LHSValIdx == -1u ? MaskVal : OpWidth;
1725 LHSUniform = LHSUniform && (MaskVal == i);
1728 if (RHSPoisonElts[MaskVal - OpWidth]) {
1729 NewPoisonElts =
true;
1732 RHSIdx = RHSIdx == -1u ? i : OpWidth;
1733 RHSValIdx = RHSValIdx == -1u ? MaskVal - OpWidth : OpWidth;
1734 RHSUniform = RHSUniform && (MaskVal - OpWidth == i);
1750 if (LHSIdx < OpWidth && RHSUniform) {
1752 Op = Shuffle->getOperand(1);
1753 Value = CV->getOperand(LHSValIdx);
1757 if (RHSIdx < OpWidth && LHSUniform) {
1759 Op = Shuffle->getOperand(0);
1760 Value = CV->getOperand(RHSValIdx);
1773 if (NewPoisonElts) {
1776 for (
unsigned i = 0; i < VWidth; ++i) {
1780 Elts.
push_back(Shuffle->getMaskValue(i));
1782 Shuffle->setShuffleMask(Elts);
1787 case Instruction::Select: {
1797 simplifyAndSetOp(
I, 0, DemandedElts, PoisonElts);
1801 APInt DemandedLHS(DemandedElts), DemandedRHS(DemandedElts);
1803 for (
unsigned i = 0; i < VWidth; i++) {
1808 DemandedLHS.clearBit(i);
1814 simplifyAndSetOp(
I, 1, DemandedLHS, PoisonElts2);
1815 simplifyAndSetOp(
I, 2, DemandedRHS, PoisonElts3);
1819 PoisonElts = PoisonElts2 & PoisonElts3;
1822 case Instruction::BitCast: {
1827 APInt InputDemandedElts(InVWidth, 0);
1828 PoisonElts2 =
APInt(InVWidth, 0);
1831 if (VWidth == InVWidth) {
1835 InputDemandedElts = DemandedElts;
1836 }
else if ((VWidth % InVWidth) == 0) {
1840 Ratio = VWidth / InVWidth;
1841 for (
unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1842 if (DemandedElts[OutIdx])
1843 InputDemandedElts.
setBit(OutIdx / Ratio);
1844 }
else if ((InVWidth % VWidth) == 0) {
1848 Ratio = InVWidth / VWidth;
1849 for (
unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
1850 if (DemandedElts[InIdx / Ratio])
1851 InputDemandedElts.
setBit(InIdx);
1857 simplifyAndSetOp(
I, 0, InputDemandedElts, PoisonElts2);
1859 if (VWidth == InVWidth) {
1860 PoisonElts = PoisonElts2;
1861 }
else if ((VWidth % InVWidth) == 0) {
1865 for (
unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1866 if (PoisonElts2[OutIdx / Ratio])
1867 PoisonElts.
setBit(OutIdx);
1868 }
else if ((InVWidth % VWidth) == 0) {
1872 for (
unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) {
1875 PoisonElts.
setBit(OutIdx);
1882 case Instruction::FPTrunc:
1883 case Instruction::FPExt:
1884 simplifyAndSetOp(
I, 0, DemandedElts, PoisonElts);
1887 case Instruction::Call: {
1890 switch (
II->getIntrinsicID()) {
1891 case Intrinsic::masked_gather:
1892 case Intrinsic::masked_load: {
1897 DemandedPassThrough(DemandedElts);
1899 for (
unsigned i = 0; i < VWidth; i++) {
1901 if (CElt->isNullValue())
1902 DemandedPtrs.clearBit(i);
1903 else if (CElt->isAllOnesValue())
1909 if (
II->getIntrinsicID() == Intrinsic::masked_gather)
1910 simplifyAndSetOp(
II, 0, DemandedPtrs, PoisonElts2);
1911 simplifyAndSetOp(
II, 2, DemandedPassThrough, PoisonElts3);
1915 PoisonElts = PoisonElts2 & PoisonElts3;
1921 *
II, DemandedElts, PoisonElts, PoisonElts2, PoisonElts3,
1955 if (DemandedElts == 1 && !
X->hasOneUse() && !
Y->hasOneUse() &&
1958 auto findShufBO = [&](
bool MatchShufAsOp0) ->
User * {
1963 Value *OtherOp = MatchShufAsOp0 ?
Y :
X;
1968 Value *ShufOp = MatchShufAsOp0 ?
X :
Y;
1979 if (
DT.dominates(U,
I))
1985 if (
User *ShufBO = findShufBO(
true))
1987 if (
User *ShufBO = findShufBO(
false))
1991 simplifyAndSetOp(
I, 0, DemandedElts, PoisonElts);
1992 simplifyAndSetOp(
I, 1, DemandedElts, PoisonElts2);
1996 PoisonElts &= PoisonElts2;
2004 return MadeChange ?
I :
nullptr;
2010 bool IsCanonicalizing =
false) {
2018 if (Mask ==
fcNan && IsCanonicalizing)
2022 if (Ty->isAggregateType())
2048 if (KnownSrc.
SignBit ==
false ||
2066 const bool PropagateNaN =
2067 IID == Intrinsic::maximum || IID == Intrinsic::minimum;
2070 if (PropagateNaN && (DemandedMask &
fcNan) ==
fcNone) {
2075 bool OrderedZeroSign = !NSZ;
2079 case Intrinsic::maximum: {
2096 case Intrinsic::minimum: {
2113 case Intrinsic::maximumnum: {
2128 case Intrinsic::minimumnum: {
2182 return DemandedMask;
2192 assert(
I->hasOneUse() &&
"wrong version called");
2194 Type *VTy =
I->getType();
2198 FMF = FPOp->getFastMathFlags();
2204 [=, &Known]() { Known.
knownNot(~DemandedMask); });
2206 switch (
I->getOpcode()) {
2207 case Instruction::FNeg: {
2214 case Instruction::FAdd: {
2220 if (
I->getOperand(0) ==
I->getOperand(1) &&
2239 if (Mode.inputsMayBePositiveZero() || Mode.outputsMayBePositiveZero())
2257 KnownRHS = KnownLHS;
2262 if (DemandedMask &
fcNan)
2265 if (DemandedMask &
fcInf)
2266 SrcDemandedMask |=
fcInf;
2283 bool ResultNotNan = (DemandedMask &
fcNan) ==
fcNone;
2292 return I->getOperand(1);
2297 return I->getOperand(0);
2301 if (InferredFMF != FMF) {
2302 I->setFastMathFlags(InferredFMF);
2308 case Instruction::FMul: {
2317 if (DemandedMask &
fcInf) {
2323 if (DemandedMask &
fcNan) {
2337 if (DemandedMask &
fcZero)
2371 Value *Fabs =
Builder.CreateUnaryIntrinsic(Intrinsic::fabs,
X, FMF);
2395 bool NonNanResult = (DemandedMask &
fcNan) ==
fcNone;
2468 if (InferredFMF != FMF) {
2469 I->setFastMathFlags(InferredFMF);
2475 case Instruction::FPExt: {
2490 I->getOperand(0)->getType()->getScalarType()->getFltSemantics();
2497 case Instruction::Call: {
2501 case Intrinsic::fabs: {
2504 KnownSrc,
Depth + 1))
2513 case Intrinsic::arithmetic_fence:
2517 case Intrinsic::copysign: {
2523 if ((DemandedMask &
fcNegative) == DemandedMask) {
2525 CI->
setOperand(1, ConstantFP::get(VTy, -1.0));
2529 if ((DemandedMask &
fcPositive) == DemandedMask) {
2547 if (KnownSign.
SignBit ==
false) {
2553 if (KnownSign.
SignBit ==
true) {
2555 CI->
setOperand(1, ConstantFP::get(VTy, -1.0));
2562 case Intrinsic::maximum:
2563 case Intrinsic::minimum:
2564 case Intrinsic::maximumnum:
2565 case Intrinsic::minimumnum: {
2566 const bool PropagateNaN =
2567 IID == Intrinsic::maximum || IID == Intrinsic::minimum;
2602 bool ResultNotLogical0 = (ValidResults & ZeroMask) ==
fcNone;
2611 ((PropagateNaN && (ValidResults &
fcNan) ==
fcNone) ||
2617 if (InferredFMF != FMF) {
2624 case Intrinsic::exp:
2625 case Intrinsic::exp2:
2626 case Intrinsic::exp10: {
2641 if (DemandedMask &
fcZero) {
2684 return ConstantFP::get(VTy, 1.0);
2699 ConstantFP::get(VTy, 1.0), FMF);
2714 Value *ZeroOrInf =
Builder.CreateSelectFMFWithUnknownProfile(
2724 case Intrinsic::log:
2725 case Intrinsic::log2:
2726 case Intrinsic::log10: {
2730 DenormalMode Mode =
F.getDenormalMode(EltTy->getFltSemantics());
2733 if (DemandedMask &
fcNan)
2738 DemandedSrcMask |=
fcZero;
2741 if (Mode.inputsMayBeZero())
2749 if (DemandedMask &
fcZero)
2761 case Intrinsic::sqrt: {
2765 if (DemandedMask &
fcNan)
2787 if (ValidResults ==
fcZero) {
2799 case Intrinsic::trunc:
2800 case Intrinsic::floor:
2801 case Intrinsic::ceil:
2802 case Intrinsic::rint:
2803 case Intrinsic::nearbyint:
2804 case Intrinsic::round:
2805 case Intrinsic::roundeven: {
2827 bool IsRoundNearestOrTrunc =
2828 IID == Intrinsic::round || IID == Intrinsic::roundeven ||
2829 IID == Intrinsic::nearbyint || IID == Intrinsic::rint ||
2830 IID == Intrinsic::trunc;
2833 if ((IID == Intrinsic::floor || IsRoundNearestOrTrunc) &&
2837 if ((IID == Intrinsic::ceil || IsRoundNearestOrTrunc) &&
2842 return ConstantFP::get(VTy, -1.0);
2845 return ConstantFP::get(VTy, 1.0);
2848 KnownSrc, IID == Intrinsic::trunc,
2856 if ((IID == Intrinsic::trunc || IsRoundNearestOrTrunc) &&
2866 case Intrinsic::canonicalize: {
2879 SrcDemandedMask |=
fcSNan;
2934 case Instruction::Select: {
2941 return I->getOperand(2);
2943 return I->getOperand(1);
2953 case Instruction::ExtractElement: {
2959 case Instruction::InsertElement: {
2966 Known = KnownVec | KnownInserted;
2969 case Instruction::ShuffleVector: {
2977 Known = KnownLHS | KnownRHS;
2996 FMF = FPOp->getFastMathFlags();
3002 [=, &Known]() { Known.
knownNot(~DemandedMask); });
3004 switch (
I->getOpcode()) {
3005 case Instruction::Select: {
3011 return I->getOperand(1);
3016 return I->getOperand(2);
3026 case Instruction::FNeg: {
3030 Value *FNegSrc =
I->getOperand(0);
3060 case Instruction::Call: {
3064 case Intrinsic::fabs: {
3075 case Intrinsic::maximum:
3076 case Intrinsic::minimum:
3077 case Intrinsic::maximumnum:
3078 case Intrinsic::minimumnum: {
3088 Known, IID, CI, DemandedMask, KnownLHS, KnownRHS,
F,
3109 Use &U =
I->getOperandUse(OpNo);
3111 Type *VTy = V->getType();
3113 if (DemandedMask ==
fcNone) {
3141 if (!FoldedToConst || FoldedToConst == V)
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
AMDGPU Register Bank Select
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file provides internal interfaces used to implement the InstCombine.
static cl::opt< unsigned > SimplifyDemandedVectorEltsDepthLimit("instcombine-simplify-vector-elts-depth", cl::desc("Depth limit when simplifying vector instructions and their operands"), cl::Hidden, cl::init(10))
static FastMathFlags inferFastMathValueFlagsBinOp(FastMathFlags FMF, FPClassTest ValidResults, const KnownFPClass &KnownLHS, const KnownFPClass &KnownRHS)
Try to set an inferred no-nans or no-infs in FMF.
static Constant * getFPClassConstant(Type *Ty, FPClassTest Mask, bool IsCanonicalizing=false)
For floating-point classes that resolve to a single bit pattern, return that value.
static cl::opt< bool > VerifyKnownBits("instcombine-verify-known-bits", cl::desc("Verify that computeKnownBits() and " "SimplifyDemandedBits() are consistent"), cl::Hidden, cl::init(false))
static unsigned getBitWidth(Type *Ty, const DataLayout &DL)
Returns the bitwidth of the given scalar or pointer type.
static Value * simplifyDemandedFPClassFabs(KnownFPClass &Known, Value *Src, FPClassTest DemandedMask, KnownFPClass KnownSrc, bool NSZ)
Perform multiple-use aware simplfications for fabs(Src).
static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo, const APInt &Demanded)
Check to see if the specified operand of the specified instruction is a constant integer.
static Value * simplifyShiftSelectingPackedElement(Instruction *I, const APInt &DemandedMask, InstCombinerImpl &IC, unsigned Depth)
Let N = 2 * M.
static Value * simplifyDemandedFPClassMinMax(KnownFPClass &Known, Intrinsic::ID IID, const CallInst *CI, FPClassTest DemandedMask, KnownFPClass KnownLHS, KnownFPClass KnownRHS, const Function &F, bool NSZ)
static FPClassTest adjustDemandedMaskFromFlags(FPClassTest DemandedMask, FastMathFlags FMF)
This file provides the interface for the instcombine pass implementation.
uint64_t IntrinsicInst * II
This file contains the declarations for profiling metadata utility functions.
static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))
This file defines the make_scope_exit function, which executes user-defined cleanup logic at scope ex...
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")
static unsigned getBitWidth(Type *Ty, const DataLayout &DL)
Returns the bitwidth of the given scalar or pointer type.
Class for arbitrary precision integers.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
void clearBit(unsigned BitPosition)
Set a given bit to 0.
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
uint64_t getZExtValue() const
Get zero extended value.
void setHighBits(unsigned hiBits)
Set the top hiBits bits.
unsigned popcount() const
Count the number of bits set.
LLVM_ABI APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
unsigned getActiveBits() const
Compute the number of active bits in the value.
LLVM_ABI APInt trunc(unsigned width) const
Truncate to new width.
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
bool isAllOnes() const
Determine if all bits are set. This is true for zero-width values.
bool isZero() const
Determine if this value is zero, i.e. all bits are clear.
LLVM_ABI APInt urem(const APInt &RHS) const
Unsigned remainder operation.
void setSignBit()
Set the sign bit to 1.
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool ult(const APInt &RHS) const
Unsigned less than comparison.
void clearAllBits()
Set every bit to 0.
unsigned countr_zero() const
Count the number of trailing zero bits.
unsigned countl_zero() const
The APInt version of std::countl_zero.
void clearLowBits(unsigned loBits)
Set bottom loBits bits to 0.
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
APInt shl(unsigned shiftAmt) const
Left-shift function.
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
void setLowBits(unsigned loBits)
Set the bottom loBits bits.
bool isIntN(unsigned N) const
Check if this APInt has an N-bits unsigned integer value.
bool isOne() const
Determine if this is a value of 1.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
bool uge(const APInt &RHS) const
Unsigned greater or equal comparison.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
BinaryOps getOpcode() const
Value * getArgOperand(unsigned i) const
LLVM_ABI Intrinsic::ID getIntrinsicID() const
Returns the intrinsic ID of the intrinsic called or Intrinsic::not_intrinsic if the called function i...
This class represents a function call, abstracting a target machine's calling convention.
static CallInst * Create(FunctionType *Ty, Value *F, const Twine &NameStr="", InsertPosition InsertBefore=nullptr)
This is the base class for all instructions that perform data casts.
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
static LLVM_ABI Constant * getInfinity(Type *Ty, bool Negative=false)
static LLVM_ABI Constant * getZero(Type *Ty, bool Negative=false)
static LLVM_ABI Constant * getQNaN(Type *Ty, bool Negative=false, APInt *Payload=nullptr)
This is the shared class of boolean and integer constants.
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
const APInt & getValue() const
Return the constant as an APInt value reference.
static LLVM_ABI Constant * get(ArrayRef< Constant * > V)
This is an important base class in LLVM.
static LLVM_ABI Constant * getIntegerValue(Type *Ty, const APInt &V)
Return the value for an integer or pointer constant, or a vector thereof, with the given scalar value...
static LLVM_ABI Constant * getAllOnesValue(Type *Ty)
LLVM_ABI bool isOneValue() const
Returns true if the value is one.
static LLVM_ABI Constant * getNullValue(Type *Ty)
Constructor to create a '0' constant of arbitrary type.
LLVM_ABI Constant * getAggregateElement(unsigned Elt) const
For aggregates (struct/array/vector) return the constant that corresponds to the specified element if...
LLVM_ABI bool isNullValue() const
Return true if this is the value that would be returned by getNullValue.
A parsed version of the target data layout string in and methods for querying it.
Convenience struct for specifying and reasoning about fast-math flags.
bool noSignedZeros() const
void setNoSignedZeros(bool B=true)
void setNoNaNs(bool B=true)
void setNoInfs(bool B=true)
an instruction for type-safe pointer arithmetic to access elements of arrays and structs
Value * CreateICmpEQ(Value *LHS, Value *RHS, const Twine &Name="")
LLVM_ABI Value * CreateSelectWithUnknownProfile(Value *C, Value *True, Value *False, StringRef PassName, const Twine &Name="")
void SetInsertPoint(BasicBlock *TheBB)
This specifies that created instructions should be appended to the end of the specified block.
static InsertElementInst * Create(Value *Vec, Value *NewElt, Value *Idx, const Twine &NameStr="", InsertPosition InsertBefore=nullptr)
KnownFPClass computeKnownFPClass(Value *Val, FastMathFlags FMF, FPClassTest Interested=fcAllFlags, const Instruction *CtxI=nullptr, unsigned Depth=0) const
Value * SimplifyDemandedUseFPClass(Instruction *I, FPClassTest DemandedMask, KnownFPClass &Known, Instruction *CxtI, unsigned Depth=0)
Attempts to replace V with a simpler value based on the demanded floating-point classes.
Value * SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, APInt &PoisonElts, unsigned Depth=0, bool AllowMultipleUsers=false) override
The specified value produces a vector with any number of elements.
Value * SimplifyMultipleUseDemandedFPClass(Instruction *I, FPClassTest DemandedMask, KnownFPClass &Known, Instruction *CxtI, unsigned Depth)
Helper routine of SimplifyDemandedUseFPClass.
bool SimplifyDemandedBits(Instruction *I, unsigned Op, const APInt &DemandedMask, KnownBits &Known, const SimplifyQuery &Q, unsigned Depth=0) override
This form of SimplifyDemandedBits simplifies the specified instruction operand if possible,...
std::optional< std::pair< Intrinsic::ID, SmallVector< Value *, 3 > > > convertOrOfShiftsToFunnelShift(Instruction &Or)
Value * simplifyShrShlDemandedBits(Instruction *Shr, const APInt &ShrOp1, Instruction *Shl, const APInt &ShlOp1, const APInt &DemandedMask, KnownBits &Known)
Helper routine of SimplifyDemandedUseBits.
Value * SimplifyDemandedUseBits(Instruction *I, const APInt &DemandedMask, KnownBits &Known, const SimplifyQuery &Q, unsigned Depth=0)
Attempts to replace I with a simpler value based on the demanded bits.
bool SimplifyDemandedFPClass(Instruction *I, unsigned Op, FPClassTest DemandedMask, KnownFPClass &Known, unsigned Depth=0)
bool SimplifyDemandedInstructionBits(Instruction &Inst)
Tries to simplify operands to an integer instruction based on its demanded bits.
Value * SimplifyMultipleUseDemandedBits(Instruction *I, const APInt &DemandedMask, KnownBits &Known, const SimplifyQuery &Q, unsigned Depth=0)
Helper routine of SimplifyDemandedUseBits.
unsigned ComputeNumSignBits(const Value *Op, const Instruction *CxtI=nullptr, unsigned Depth=0) const
Instruction * replaceInstUsesWith(Instruction &I, Value *V)
A combiner-aware RAUW-like routine.
void replaceUse(Use &U, Value *NewValue)
Replace use and add the previously used value to the worklist.
InstructionWorklist & Worklist
A worklist of the instructions that need to be simplified.
Instruction * InsertNewInstWith(Instruction *New, BasicBlock::iterator Old)
Same as InsertNewInstBefore, but also sets the debug loc.
void computeKnownBits(const Value *V, KnownBits &Known, const Instruction *CxtI, unsigned Depth=0) const
std::optional< Value * > targetSimplifyDemandedVectorEltsIntrinsic(IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp)
Instruction * replaceOperand(Instruction &I, unsigned OpNum, Value *V)
Replace operand of instruction and add old operand to the worklist.
std::optional< Value * > targetSimplifyDemandedUseBitsIntrinsic(IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed)
const SimplifyQuery & getSimplifyQuery() const
LLVM_ABI void dropUBImplyingAttrsAndMetadata(ArrayRef< unsigned > Keep={})
Drop any attributes or metadata that can cause immediate undefined behavior.
LLVM_ABI bool hasNoUnsignedWrap() const LLVM_READONLY
Determine whether the no unsigned wrap flag is set.
LLVM_ABI bool hasNoSignedWrap() const LLVM_READONLY
Determine whether the no signed wrap flag is set.
LLVM_ABI bool isCommutative() const LLVM_READONLY
Return true if the instruction is commutative:
LLVM_ABI void setFastMathFlags(FastMathFlags FMF)
Convenience function for setting multiple fast-math flags on this instruction, which must be an opera...
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
LLVM_ABI void setIsExact(bool b=true)
Set or clear the exact flag on this instruction, which must be an operator which supports this flag.
A wrapper class for inspecting calls to intrinsic functions.
bool hasNoSignedWrap() const
Test whether this operation is known to never undergo signed overflow, aka the nsw property.
bool hasNoUnsignedWrap() const
Test whether this operation is known to never undergo unsigned overflow, aka the nuw property.
static LLVM_ABI PoisonValue * get(Type *T)
Static factory methods - Return an 'poison' object of the specified type.
This class represents the LLVM 'select' instruction.
const Value * getCondition() const
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
The instances of the Type class are immutable: once they are created, they are never changed.
static LLVM_ABI IntegerType * getInt64Ty(LLVMContext &C)
bool isVectorTy() const
True if this is an instance of VectorType.
bool isIntOrIntVectorTy() const
Return true if this is an integer type or a vector of integer types.
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
bool isMultiUnitFPType() const
Returns true if this is a floating-point type that is an unevaluated sum of multiple floating-point u...
LLVM_ABI unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
bool isIEEELikeFPTy() const
Return true if this is a well-behaved IEEE-like type, which has a IEEE compatible layout,...
LLVM_ABI const fltSemantics & getFltSemantics() const
static LLVM_ABI UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
A Use represents the edge between a Value definition and its users.
void setOperand(unsigned i, Value *Val)
Value * getOperand(unsigned i) const
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
bool hasOneUse() const
Return true if there is exactly one use of this value.
iterator_range< user_iterator > users()
bool hasUseList() const
Check if this Value has a use-list.
LLVM_ABI StringRef getName() const
Return a constant reference to the value's name.
LLVM_ABI void takeName(Value *V)
Transfer the name from V to this value.
Base class of all SIMD vector types.
This class represents zero extension of integer types.
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
LLVM_ABI Function * getOrInsertDeclaration(Module *M, ID id, ArrayRef< Type * > Tys={})
Look up the Function declaration of the intrinsic id in the Module M.
BinaryOp_match< SrcTy, SpecificConstantMatch, TargetOpcode::G_XOR, true > m_Not(const SrcTy &&Src)
Matches a register not-ed by a G_XOR.
OneUse_match< SubPat > m_OneUse(const SubPat &SP)
class_match< PoisonValue > m_Poison()
Match an arbitrary poison constant.
cst_pred_ty< is_lowbit_mask > m_LowBitMask()
Match an integer or vector with only the low bit(s) set.
PtrAdd_match< PointerOpTy, OffsetOpTy > m_PtrAdd(const PointerOpTy &PointerOp, const OffsetOpTy &OffsetOp)
Matches GEP with i8 source element type.
BinaryOp_match< LHS, RHS, Instruction::Add > m_Add(const LHS &L, const RHS &R)
class_match< BinaryOperator > m_BinOp()
Match an arbitrary binary operation and ignore it.
BinaryOp_match< LHS, RHS, Instruction::AShr > m_AShr(const LHS &L, const RHS &R)
ap_match< APInt > m_APInt(const APInt *&Res)
Match a ConstantInt or splatted ConstantVector, binding the specified pointer to the contained APInt.
specific_intval< false > m_SpecificInt(const APInt &V)
Match a specific integer value or vector with all elements equal to the value.
bool match(Val *V, const Pattern &P)
specificval_ty m_Specific(const Value *V)
Match if we have a specific specified value.
BinOpPred_match< LHS, RHS, is_right_shift_op > m_Shr(const LHS &L, const RHS &R)
Matches logical shift operations.
TwoOps_match< Val_t, Idx_t, Instruction::ExtractElement > m_ExtractElt(const Val_t &Val, const Idx_t &Idx)
Matches ExtractElementInst.
class_match< ConstantInt > m_ConstantInt()
Match an arbitrary ConstantInt and ignore it.
IntrinsicID_match m_Intrinsic()
Match intrinsic calls like this: m_Intrinsic<Intrinsic::fabs>(m_Value(X))
BinaryOp_match< LHS, RHS, Instruction::Mul > m_Mul(const LHS &L, const RHS &R)
TwoOps_match< V1_t, V2_t, Instruction::ShuffleVector > m_Shuffle(const V1_t &v1, const V2_t &v2)
Matches ShuffleVectorInst independently of mask value.
CastInst_match< OpTy, ZExtInst > m_ZExt(const OpTy &Op)
Matches ZExt.
match_immconstant_ty m_ImmConstant()
Match an arbitrary immediate Constant and ignore it.
DisjointOr_match< LHS, RHS, true > m_c_DisjointOr(const LHS &L, const RHS &R)
BinaryOp_match< LHS, RHS, Instruction::Add, true > m_c_Add(const LHS &L, const RHS &R)
Matches a Add with LHS and RHS in either order.
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
AnyBinaryOp_match< LHS, RHS, true > m_c_BinOp(const LHS &L, const RHS &R)
Matches a BinaryOperator with LHS and RHS in either order.
BinaryOp_match< LHS, RHS, Instruction::LShr > m_LShr(const LHS &L, const RHS &R)
CmpClass_match< LHS, RHS, ICmpInst > m_ICmp(CmpPredicate &Pred, const LHS &L, const RHS &R)
BinaryOp_match< LHS, RHS, Instruction::Shl > m_Shl(const LHS &L, const RHS &R)
auto m_Undef()
Match an arbitrary undef constant.
CastInst_match< OpTy, SExtInst > m_SExt(const OpTy &Op)
Matches SExt.
is_zero m_Zero()
Match any null constant or a vector with all elements equal to 0.
m_Intrinsic_Ty< Opnd0 >::Ty m_FAbs(const Opnd0 &Op0)
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ABI bool haveNoCommonBitsSet(const WithCache< const Value * > &LHSCache, const WithCache< const Value * > &RHSCache, const SimplifyQuery &SQ)
Return true if LHS and RHS have no common bits set.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
LLVM_ABI void computeKnownBitsFromContext(const Value *V, KnownBits &Known, const SimplifyQuery &Q, unsigned Depth=0)
Merge bits known from context-dependent facts into Known.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
LLVM_ABI void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
constexpr T alignDown(U Value, V Align, W Skew=0)
Returns the largest unsigned integer less than or equal to Value and is Skew mod Align.
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
gep_type_iterator gep_type_end(const User *GEP)
constexpr auto equal_to(T &&Arg)
Functor variant of std::equal_to that can be used as a UnaryPredicate in functional algorithms like a...
LLVM_ABI bool isGuaranteedNotToBeUndef(const Value *V, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, unsigned Depth=0)
Returns true if V cannot be undef, but may be poison.
LLVM_ABI bool cannotOrderStrictlyLess(FPClassTest LHS, FPClassTest RHS, bool OrderedZeroSign=false)
Returns true if all values in LHS must be greater than or equal to those in RHS.
LLVM_ABI bool cannotOrderStrictlyGreater(FPClassTest LHS, FPClassTest RHS, bool OrderedZeroSign=false)
Returns true if all values in LHS must be less than or equal to those in RHS.
constexpr unsigned MaxAnalysisRecursionDepth
LLVM_ABI void adjustKnownBitsForSelectArm(KnownBits &Known, Value *Cond, Value *Arm, bool Invert, const SimplifyQuery &Q, unsigned Depth=0)
Adjust Known for the given select Arm to include information from the select Cond.
LLVM_ABI FPClassTest fneg(FPClassTest Mask)
Return the test mask which returns true if the value's sign bit is flipped.
FPClassTest
Floating-point class tests, supported by 'is_fpclass' intrinsic.
LLVM_ABI void computeKnownBits(const Value *V, KnownBits &Known, const DataLayout &DL, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true, unsigned Depth=0)
Determine which bits of V are known to be either zero or one and return them in the KnownZero/KnownOn...
LLVM_ABI void adjustKnownFPClassForSelectArm(KnownFPClass &Known, Value *Cond, Value *Arm, bool Invert, const SimplifyQuery &Q, unsigned Depth=0)
Adjust Known for the given select Arm to include information from the select Cond.
LLVM_ABI FPClassTest inverse_fabs(FPClassTest Mask)
Return the test mask which returns true after fabs is applied to the value.
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
LLVM_ABI Constant * ConstantFoldBinaryOpOperands(unsigned Opcode, Constant *LHS, Constant *RHS, const DataLayout &DL)
Attempt to constant fold a binary operation with the specified operands.
constexpr int PoisonMaskElem
LLVM_ABI raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
@ Mul
Product of integers.
@ Xor
Bitwise or logical XOR of integers.
LLVM_ABI FPClassTest unknown_sign(FPClassTest Mask)
Return the test mask which returns true if the value could have the same set of classes,...
DWARFExpression::Operation Op
constexpr unsigned BitWidth
LLVM_ABI KnownBits analyzeKnownBitsFromAndXorOr(const Operator *I, const KnownBits &KnownLHS, const KnownBits &KnownRHS, const SimplifyQuery &SQ, unsigned Depth=0)
Using KnownBits LHS/RHS produce the known bits for logic op (and/xor/or).
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
gep_type_iterator gep_type_begin(const User *GEP)
unsigned Log2(Align A)
Returns the log2 of the alignment.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Represent subnormal handling kind for floating point instruction inputs and outputs.
static constexpr DenormalMode getPreserveSign()
static constexpr DenormalMode getIEEE()
static KnownBits makeConstant(const APInt &C)
Create known bits from a known constant.
KnownBits anyextOrTrunc(unsigned BitWidth) const
Return known bits for an "any" extension or truncation of the value we're tracking.
bool isNonNegative() const
Returns true if this value is known to be non-negative.
void makeNonNegative()
Make this value non-negative.
static LLVM_ABI KnownBits ashr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)
Compute known bits for ashr(LHS, RHS).
unsigned getBitWidth() const
Get the bit width of this value.
void resetAll()
Resets the known state of all bits.
KnownBits unionWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for either this or RHS or both.
KnownBits intersectWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for both this and RHS.
KnownBits sext(unsigned BitWidth) const
Return known bits for a sign extension of the value we're tracking.
static KnownBits add(const KnownBits &LHS, const KnownBits &RHS, bool NSW=false, bool NUW=false)
Compute knownbits resulting from addition of LHS and RHS.
KnownBits zextOrTrunc(unsigned BitWidth) const
Return known bits for a zero extension or truncation of the value we're tracking.
APInt getMaxValue() const
Return the maximal unsigned value possible given these KnownBits.
static LLVM_ABI KnownBits srem(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for srem(LHS, RHS).
static LLVM_ABI KnownBits udiv(const KnownBits &LHS, const KnownBits &RHS, bool Exact=false)
Compute known bits for udiv(LHS, RHS).
bool isNegative() const
Returns true if this value is known to be negative.
static KnownBits sub(const KnownBits &LHS, const KnownBits &RHS, bool NSW=false, bool NUW=false)
Compute knownbits resulting from subtraction of LHS and RHS.
static LLVM_ABI KnownBits shl(const KnownBits &LHS, const KnownBits &RHS, bool NUW=false, bool NSW=false, bool ShAmtNonZero=false)
Compute known bits for shl(LHS, RHS).
bool isKnownNeverInfOrNaN() const
Return true if it's known this can never be an infinity or nan.
FPClassTest KnownFPClasses
Floating-point classes the value could be one of.
bool isKnownNeverInfinity() const
Return true if it's known this can never be an infinity.
static constexpr FPClassTest OrderedGreaterThanZeroMask
static constexpr FPClassTest OrderedLessThanZeroMask
void knownNot(FPClassTest RuleOut)
static LLVM_ABI KnownFPClass fmul(const KnownFPClass &LHS, const KnownFPClass &RHS, DenormalMode Mode=DenormalMode::getDynamic())
Report known values for fmul.
static LLVM_ABI KnownFPClass fadd_self(const KnownFPClass &Src, DenormalMode Mode=DenormalMode::getDynamic())
Report known values for fadd x, x.
void copysign(const KnownFPClass &Sign)
static KnownFPClass square(const KnownFPClass &Src, DenormalMode Mode=DenormalMode::getDynamic())
bool isKnownNeverSubnormal() const
Return true if it's known this can never be a subnormal.
bool isKnownAlways(FPClassTest Mask) const
static LLVM_ABI KnownFPClass canonicalize(const KnownFPClass &Src, DenormalMode DenormMode=DenormalMode::getDynamic())
Apply the canonicalize intrinsic to this value.
LLVM_ABI bool isKnownNeverLogicalZero(DenormalMode Mode) const
Return true if it's known this can never be interpreted as a zero.
static LLVM_ABI KnownFPClass log(const KnownFPClass &Src, DenormalMode Mode=DenormalMode::getDynamic())
Propagate known class for log/log2/log10.
static LLVM_ABI KnownFPClass roundToIntegral(const KnownFPClass &Src, bool IsTrunc, bool IsMultiUnitFPType)
Propagate known class for rounding intrinsics (trunc, floor, ceil, rint, nearbyint,...
static LLVM_ABI KnownFPClass minMaxLike(const KnownFPClass &LHS, const KnownFPClass &RHS, MinMaxKind Kind, DenormalMode DenormMode=DenormalMode::getDynamic())
KnownFPClass intersectWith(const KnownFPClass &RHS) const
static LLVM_ABI KnownFPClass exp(const KnownFPClass &Src)
Report known values for exp, exp2 and exp10.
std::optional< bool > SignBit
std::nullopt if the sign bit is unknown, true if the sign bit is definitely set or false if the sign ...
bool isKnownNeverNaN() const
Return true if it's known this can never be a nan.
bool isKnownNever(FPClassTest Mask) const
Return true if it's known this can never be one of the mask entries.
static LLVM_ABI KnownFPClass fpext(const KnownFPClass &KnownSrc, const fltSemantics &DstTy, const fltSemantics &SrcTy)
Propagate known class for fpext.
static LLVM_ABI KnownFPClass sqrt(const KnownFPClass &Src, DenormalMode Mode=DenormalMode::getDynamic())
Propagate known class for sqrt.
LLVM_ABI bool isKnownNeverLogicalPosZero(DenormalMode Mode) const
Return true if it's known this can never be interpreted as a positive zero.
bool cannotBeOrderedGreaterEqZero(DenormalMode Mode) const
Return true if it's know this can never be a negative value or a logical 0.
static LLVM_ABI KnownFPClass fadd(const KnownFPClass &LHS, const KnownFPClass &RHS, DenormalMode Mode=DenormalMode::getDynamic())
Report known values for fadd.
LLVM_ABI bool isKnownNeverLogicalNegZero(DenormalMode Mode) const
Return true if it's known this can never be interpreted as a negative zero.