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TargetPassConfig.h
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1 //===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// Target-Independent Code Generator Pass Configuration Options pass.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H
14 #define LLVM_CODEGEN_TARGETPASSCONFIG_H
15 
16 #include "llvm/Pass.h"
17 #include "llvm/Support/CodeGen.h"
18 #include <cassert>
19 #include <string>
20 
21 namespace llvm {
22 
23 class LLVMTargetMachine;
24 struct MachineSchedContext;
25 class PassConfigImpl;
26 class ScheduleDAGInstrs;
27 class CSEConfigBase;
28 
29 // The old pass manager infrastructure is hidden in a legacy namespace now.
30 namespace legacy {
31 
32 class PassManagerBase;
33 
34 } // end namespace legacy
35 
37 
38 /// Discriminated union of Pass ID types.
39 ///
40 /// The PassConfig API prefers dealing with IDs because they are safer and more
41 /// efficient. IDs decouple configuration from instantiation. This way, when a
42 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
43 /// refer to a Pass pointer after adding it to a pass manager, which deletes
44 /// redundant pass instances.
45 ///
46 /// However, it is convient to directly instantiate target passes with
47 /// non-default ctors. These often don't have a registered PassInfo. Rather than
48 /// force all target passes to implement the pass registry boilerplate, allow
49 /// the PassConfig API to handle either type.
50 ///
51 /// AnalysisID is sadly char*, so PointerIntPair won't work.
53  union {
55  Pass *P;
56  };
57  bool IsInstance = false;
58 
59 public:
60  IdentifyingPassPtr() : P(nullptr) {}
61  IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {}
62  IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
63 
64  bool isValid() const { return P; }
65  bool isInstance() const { return IsInstance; }
66 
67  AnalysisID getID() const {
68  assert(!IsInstance && "Not a Pass ID");
69  return ID;
70  }
71 
72  Pass *getInstance() const {
73  assert(IsInstance && "Not a Pass Instance");
74  return P;
75  }
76 };
77 
78 
79 /// Target-Independent Code Generator Pass Configuration Options.
80 ///
81 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
82 /// to the internals of other CodeGen passes.
84 private:
85  PassManagerBase *PM = nullptr;
86  AnalysisID StartBefore = nullptr;
87  AnalysisID StartAfter = nullptr;
88  AnalysisID StopBefore = nullptr;
89  AnalysisID StopAfter = nullptr;
90 
91  unsigned StartBeforeInstanceNum = 0;
92  unsigned StartBeforeCount = 0;
93 
94  unsigned StartAfterInstanceNum = 0;
95  unsigned StartAfterCount = 0;
96 
97  unsigned StopBeforeInstanceNum = 0;
98  unsigned StopBeforeCount = 0;
99 
100  unsigned StopAfterInstanceNum = 0;
101  unsigned StopAfterCount = 0;
102 
103  bool Started = true;
104  bool Stopped = false;
105  bool AddingMachinePasses = false;
106 
107  /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
108  /// a portion of the normal code-gen pass sequence.
109  ///
110  /// If the StartAfter and StartBefore pass ID is zero, then compilation will
111  /// begin at the normal point; otherwise, clear the Started flag to indicate
112  /// that passes should not be added until the starting pass is seen. If the
113  /// Stop pass ID is zero, then compilation will continue to the end.
114  ///
115  /// This function expects that at least one of the StartAfter or the
116  /// StartBefore pass IDs is null.
117  void setStartStopPasses();
118 
119 protected:
121  PassConfigImpl *Impl = nullptr; // Internal data structures
122  bool Initialized = false; // Flagged after all passes are configured.
123 
124  // Target Pass Options
125  // Targets provide a default setting, user flags override.
126  bool DisableVerify = false;
127 
128  /// Default setting for -enable-tail-merge on this target.
129  bool EnableTailMerge = true;
130 
131  /// Require processing of functions such that callees are generated before
132  /// callers.
133  bool RequireCodeGenSCCOrder = false;
134 
135  /// Add the actual instruction selection passes. This does not include
136  /// preparation passes on IR.
137  bool addCoreISelPasses();
138 
139 public:
141  // Dummy constructor.
143 
144  ~TargetPassConfig() override;
145 
146  static char ID;
147 
148  /// Get the right type of TargetMachine for this target.
149  template<typename TMC> TMC &getTM() const {
150  return *static_cast<TMC*>(TM);
151  }
152 
153  //
154  void setInitialized() { Initialized = true; }
155 
156  CodeGenOpt::Level getOptLevel() const;
157 
158  /// Returns true if one of the `-start-after`, `-start-before`, `-stop-after`
159  /// or `-stop-before` options is set.
160  static bool hasLimitedCodeGenPipeline();
161 
162  /// Returns true if none of the `-stop-before` and `-stop-after` options is
163  /// set.
164  static bool willCompleteCodeGenPipeline();
165 
166  /// If hasLimitedCodeGenPipeline is true, this method
167  /// returns a string with the name of the options, separated
168  /// by \p Separator that caused this pipeline to be limited.
169  std::string
170  getLimitedCodeGenPipelineReason(const char *Separator = "/") const;
171 
172  void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
173 
174  bool getEnableTailMerge() const { return EnableTailMerge; }
175  void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
176 
177  bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
178  void setRequiresCodeGenSCCOrder(bool Enable = true) {
179  setOpt(RequireCodeGenSCCOrder, Enable);
180  }
181 
182  /// Allow the target to override a specific pass without overriding the pass
183  /// pipeline. When passes are added to the standard pipeline at the
184  /// point where StandardID is expected, add TargetID in its place.
185  void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
186 
187  /// Insert InsertedPassID pass after TargetPassID pass.
188  void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
189  bool VerifyAfter = true, bool PrintAfter = true);
190 
191  /// Allow the target to enable a specific standard pass by default.
192  void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
193 
194  /// Allow the target to disable a specific standard pass by default.
195  void disablePass(AnalysisID PassID) {
196  substitutePass(PassID, IdentifyingPassPtr());
197  }
198 
199  /// Return the pass substituted for StandardID by the target.
200  /// If no substitution exists, return StandardID.
201  IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
202 
203  /// Return true if the pass has been substituted by the target or
204  /// overridden on the command line.
205  bool isPassSubstitutedOrOverridden(AnalysisID ID) const;
206 
207  /// Return true if the optimized regalloc pipeline is enabled.
208  bool getOptimizeRegAlloc() const;
209 
210  /// Return true if the default global register allocator is in use and
211  /// has not be overriden on the command line with '-regalloc=...'
212  bool usingDefaultRegAlloc() const;
213 
214  /// High level function that adds all passes necessary to go from llvm IR
215  /// representation to the MI representation.
216  /// Adds IR based lowering and target specific optimization passes and finally
217  /// the core instruction selection passes.
218  /// \returns true if an error occurred, false otherwise.
219  bool addISelPasses();
220 
221  /// Add common target configurable passes that perform LLVM IR to IR
222  /// transforms following machine independent optimization.
223  virtual void addIRPasses();
224 
225  /// Add passes to lower exception handling for the code generator.
226  void addPassesToHandleExceptions();
227 
228  /// Add pass to prepare the LLVM IR for code generation. This should be done
229  /// before exception handling preparation passes.
230  virtual void addCodeGenPrepare();
231 
232  /// Add common passes that perform LLVM IR to IR transforms in preparation for
233  /// instruction selection.
234  virtual void addISelPrepare();
235 
236  /// addInstSelector - This method should install an instruction selector pass,
237  /// which converts from LLVM code to machine instructions.
238  virtual bool addInstSelector() {
239  return true;
240  }
241 
242  /// This method should install an IR translator pass, which converts from
243  /// LLVM code to machine instructions with possibly generic opcodes.
244  virtual bool addIRTranslator() { return true; }
245 
246  /// This method may be implemented by targets that want to run passes
247  /// immediately before legalization.
248  virtual void addPreLegalizeMachineIR() {}
249 
250  /// This method should install a legalize pass, which converts the instruction
251  /// sequence into one that can be selected by the target.
252  virtual bool addLegalizeMachineIR() { return true; }
253 
254  /// This method may be implemented by targets that want to run passes
255  /// immediately before the register bank selection.
256  virtual void addPreRegBankSelect() {}
257 
258  /// This method should install a register bank selector pass, which
259  /// assigns register banks to virtual registers without a register
260  /// class or register banks.
261  virtual bool addRegBankSelect() { return true; }
262 
263  /// This method may be implemented by targets that want to run passes
264  /// immediately before the (global) instruction selection.
266 
267  /// This method should install a (global) instruction selector pass, which
268  /// converts possibly generic instructions to fully target-specific
269  /// instructions, thereby constraining all generic virtual registers to
270  /// register classes.
271  virtual bool addGlobalInstructionSelect() { return true; }
272 
273  /// Add the complete, standard set of LLVM CodeGen passes.
274  /// Fully developed targets will not generally override this.
275  virtual void addMachinePasses();
276 
277  /// Create an instance of ScheduleDAGInstrs to be run within the standard
278  /// MachineScheduler pass for this function and target at the current
279  /// optimization level.
280  ///
281  /// This can also be used to plug a new MachineSchedStrategy into an instance
282  /// of the standard ScheduleDAGMI:
283  /// return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /*RemoveKillFlags=*/false)
284  ///
285  /// Return NULL to select the default (generic) machine scheduler.
286  virtual ScheduleDAGInstrs *
287  createMachineScheduler(MachineSchedContext *C) const {
288  return nullptr;
289  }
290 
291  /// Similar to createMachineScheduler but used when postRA machine scheduling
292  /// is enabled.
293  virtual ScheduleDAGInstrs *
295  return nullptr;
296  }
297 
298  /// printAndVerify - Add a pass to dump then verify the machine function, if
299  /// those steps are enabled.
300  void printAndVerify(const std::string &Banner);
301 
302  /// Add a pass to print the machine function if printing is enabled.
303  void addPrintPass(const std::string &Banner);
304 
305  /// Add a pass to perform basic verification of the machine function if
306  /// verification is enabled.
307  void addVerifyPass(const std::string &Banner);
308 
309  /// Check whether or not GlobalISel should abort on error.
310  /// When this is disabled, GlobalISel will fall back on SDISel instead of
311  /// erroring out.
312  bool isGlobalISelAbortEnabled() const;
313 
314  /// Check whether or not a diagnostic should be emitted when GlobalISel
315  /// uses the fallback path. In other words, it will emit a diagnostic
316  /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
317  virtual bool reportDiagnosticWhenGlobalISelFallback() const;
318 
319  /// Check whether continuous CSE should be enabled in GISel passes.
320  /// By default, it's enabled for non O0 levels.
321  virtual bool isGISelCSEEnabled() const;
322 
323  /// Returns the CSEConfig object to use for the current optimization level.
324  virtual std::unique_ptr<CSEConfigBase> getCSEConfig() const;
325 
326 protected:
327  // Helper to verify the analysis is really immutable.
328  void setOpt(bool &Opt, bool Val);
329 
330  /// Methods with trivial inline returns are convenient points in the common
331  /// codegen pass pipeline where targets may insert passes. Methods with
332  /// out-of-line standard implementations are major CodeGen stages called by
333  /// addMachinePasses. Some targets may override major stages when inserting
334  /// passes is insufficient, but maintaining overriden stages is more work.
335  ///
336 
337  /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
338  /// passes (which are run just before instruction selector).
339  virtual bool addPreISel() {
340  return true;
341  }
342 
343  /// addMachineSSAOptimization - Add standard passes that optimize machine
344  /// instructions in SSA form.
345  virtual void addMachineSSAOptimization();
346 
347  /// Add passes that optimize instruction level parallelism for out-of-order
348  /// targets. These passes are run while the machine code is still in SSA
349  /// form, so they can use MachineTraceMetrics to control their heuristics.
350  ///
351  /// All passes added here should preserve the MachineDominatorTree,
352  /// MachineLoopInfo, and MachineTraceMetrics analyses.
353  virtual bool addILPOpts() {
354  return false;
355  }
356 
357  /// This method may be implemented by targets that want to run passes
358  /// immediately before register allocation.
359  virtual void addPreRegAlloc() { }
360 
361  /// createTargetRegisterAllocator - Create the register allocator pass for
362  /// this target at the current optimization level.
363  virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
364 
365  /// addFastRegAlloc - Add the minimum set of target-independent passes that
366  /// are required for fast register allocation.
367  virtual void addFastRegAlloc();
368 
369  /// addOptimizedRegAlloc - Add passes related to register allocation.
370  /// LLVMTargetMachine provides standard regalloc passes for most targets.
371  virtual void addOptimizedRegAlloc();
372 
373  /// addPreRewrite - Add passes to the optimized register allocation pipeline
374  /// after register allocation is complete, but before virtual registers are
375  /// rewritten to physical registers.
376  ///
377  /// These passes must preserve VirtRegMap and LiveIntervals, and when running
378  /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
379  /// When these passes run, VirtRegMap contains legal physreg assignments for
380  /// all virtual registers.
381  ///
382  /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
383  /// be honored. This is also not generally used for the the fast variant,
384  /// where the allocation and rewriting are done in one pass.
385  virtual bool addPreRewrite() {
386  return false;
387  }
388 
389  /// Add passes to be run immediately after virtual registers are rewritten
390  /// to physical registers.
391  virtual void addPostRewrite() { }
392 
393  /// This method may be implemented by targets that want to run passes after
394  /// register allocation pass pipeline but before prolog-epilog insertion.
395  virtual void addPostRegAlloc() { }
396 
397  /// Add passes that optimize machine instructions after register allocation.
398  virtual void addMachineLateOptimization();
399 
400  /// This method may be implemented by targets that want to run passes after
401  /// prolog-epilog insertion and before the second instruction scheduling pass.
402  virtual void addPreSched2() { }
403 
404  /// addGCPasses - Add late codegen passes that analyze code for garbage
405  /// collection. This should return true if GC info should be printed after
406  /// these passes.
407  virtual bool addGCPasses();
408 
409  /// Add standard basic block placement passes.
410  virtual void addBlockPlacement();
411 
412  /// This pass may be implemented by targets that want to run passes
413  /// immediately before machine code is emitted.
414  virtual void addPreEmitPass() { }
415 
416  /// Targets may add passes immediately before machine code is emitted in this
417  /// callback. This is called even later than `addPreEmitPass`.
418  // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
419  // position and remove the `2` suffix here as this callback is what
420  // `addPreEmitPass` *should* be but in reality isn't.
421  virtual void addPreEmitPass2() {}
422 
423  /// Utilities for targets to add passes to the pass manager.
424  ///
425 
426  /// Add a CodeGen pass at this point in the pipeline after checking overrides.
427  /// Return the pass that was added, or zero if no pass was added.
428  /// @p printAfter if true and adding a machine function pass add an extra
429  /// machine printer pass afterwards
430  /// @p verifyAfter if true and adding a machine function pass add an extra
431  /// machine verification pass afterwards.
432  AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
433  bool printAfter = true);
434 
435  /// Add a pass to the PassManager if that pass is supposed to be run, as
436  /// determined by the StartAfter and StopAfter options. Takes ownership of the
437  /// pass.
438  /// @p printAfter if true and adding a machine function pass add an extra
439  /// machine printer pass afterwards
440  /// @p verifyAfter if true and adding a machine function pass add an extra
441  /// machine verification pass afterwards.
442  void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
443 
444  /// addMachinePasses helper to create the target-selected or overriden
445  /// regalloc pass.
446  virtual FunctionPass *createRegAllocPass(bool Optimized);
447 
448  /// Add core register alloator passes which do the actual register assignment
449  /// and rewriting. \returns true if any passes were added.
450  virtual bool addRegAssignmentFast();
451  virtual bool addRegAssignmentOptimized();
452 };
453 
454 } // end namespace llvm
455 
456 #endif // LLVM_CODEGEN_TARGETPASSCONFIG_H
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:80
uint64_t CallInst * C
void enablePass(AnalysisID PassID)
Allow the target to enable a specific standard pass by default.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
virtual void addPostRewrite()
Add passes to be run immediately after virtual registers are rewritten to physical registers...
void setDisableVerify(bool Disable)
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
bool requiresCodeGenSCCOrder() const
TMC & getTM() const
Get the right type of TargetMachine for this target.
block Block Frequency true
void setRequiresCodeGenSCCOrder(bool Enable=true)
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
IdentifyingPassPtr(Pass *InstancePtr)
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Target-Independent Code Generator Pass Configuration Options.
AnalysisID getID() const
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization...
LLVMTargetMachine * TM
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
bool getEnableTailMerge() const
static PassOptionList PrintAfter("print-after", llvm::cl::desc("Print IR after specified passes"), cl::Hidden)
#define P(N)
void disablePass(AnalysisID PassID)
Allow the target to disable a specific standard pass by default.
void setEnableTailMerge(bool Enable)
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
This class describes a target machine that is implemented with the LLVM target-independent code gener...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
virtual ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const
Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
void pm(uint64_t &Value)
Adjusts a program memory address.
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:255
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
const void * AnalysisID
Definition: Pass.h:48
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Discriminated union of Pass ID types.
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
A ScheduleDAG for scheduling lists of MachineInstr.
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IdentifyingPassPtr(AnalysisID IDPtr)
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...