Define some predicates that are used for node matching. More...
Typedefs | |
| using | Specifier = uint16_t |
Functions | |
| LLVM_ABI CPUKind | parseArchX86 (StringRef CPU, bool Only64Bit=false) |
Parse CPU string into a CPUKind. | |
| LLVM_ABI CPUKind | parseTuneCPU (StringRef CPU, bool Only64Bit=false) |
| LLVM_ABI void | fillValidCPUArchList (SmallVectorImpl< StringRef > &Values, bool Only64Bit=false) |
| Provide a list of valid CPU names. | |
| LLVM_ABI void | fillValidTuneCPUList (SmallVectorImpl< StringRef > &Values, bool Only64Bit=false) |
| Provide a list of valid -mtune names. | |
| LLVM_ABI ProcessorFeatures | getKeyFeature (CPUKind Kind) |
| Get the key feature prioritizing target multiversioning. | |
| LLVM_ABI void | getFeaturesForCPU (StringRef CPU, SmallVectorImpl< StringRef > &Features, bool NeedPlus=false) |
Fill in the features that CPU supports into Features. | |
| LLVM_ABI void | updateImpliedFeatures (StringRef Feature, bool Enabled, StringMap< bool > &Features) |
Set or clear entries in Features that are implied to be enabled/disabled by the provided Feature. | |
| LLVM_ABI char | getCPUDispatchMangling (StringRef Name) |
| LLVM_ABI bool | validateCPUSpecificCPUDispatch (StringRef Name) |
| LLVM_ABI std::array< uint32_t, 4 > | getCpuSupportsMask (ArrayRef< StringRef > FeatureStrs) |
| LLVM_ABI unsigned | getFeaturePriority (ProcessorFeatures Feat) |
| FirstMacroFusionInstKind | classifyFirstOpcodeInMacroFusion (unsigned Opcode) |
| SecondMacroFusionInstKind | classifySecondCondCodeInMacroFusion (X86::CondCode CC) |
| bool | isMacroFused (FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind) |
| EncodingOfSegmentOverridePrefix | getSegmentOverridePrefixForReg (MCRegister Reg) |
| Given a segment register, return the encoding of the segment override prefix for it. | |
| bool | optimizeInstFromVEX3ToVEX2 (MCInst &MI, const MCInstrDesc &Desc) |
| bool | optimizeShiftRotateWithImmediateOne (MCInst &MI) |
| bool | optimizeVPCMPWithImmediateOneOrSix (MCInst &MI) |
| bool | optimizeMOVSX (MCInst &MI) |
| bool | optimizeINCDEC (MCInst &MI, bool In64BitMode) |
| bool | optimizeMOV (MCInst &MI, bool In64BitMode) |
| Simplify things like MOV32rm to MOV32o32a. | |
| bool | optimizeToFixedRegisterOrShortImmediateForm (MCInst &MI) |
| unsigned | getOpcodeForShortImmediateForm (unsigned Opcode) |
| unsigned | getOpcodeForLongImmediateForm (unsigned Opcode) |
| std::pair< CondCode, bool > | getX86ConditionCode (CmpInst::Predicate Predicate) |
| Return a pair of condition code for the given predicate and whether the instruction operands should be swaped to match the condition code. | |
| unsigned | getCMovOpcode (unsigned RegBytes, bool HasMemoryOperand=false, bool HasNDD=false) |
| Return a cmov opcode for the given register size in bytes, and operand type. | |
| int | getCondSrcNoFromDesc (const MCInstrDesc &MCID) |
Return the source operand # for condition code by MCID. | |
| CondCode | getCondFromMI (const MachineInstr &MI) |
| Return the condition code of the instruction. | |
| CondCode | getCondFromBranch (const MachineInstr &MI) |
| CondCode | getCondFromSETCC (const MachineInstr &MI) |
| CondCode | getCondFromCMov (const MachineInstr &MI) |
| CondCode | getCondFromCFCMov (const MachineInstr &MI) |
| CondCode | getCondFromCCMP (const MachineInstr &MI) |
| int | getCCMPCondFlagsFromCondCode (CondCode CC) |
| unsigned | getNFVariant (unsigned Opc) |
| unsigned | getNonNDVariant (unsigned Opc) |
| CondCode | GetOppositeBranchCondition (CondCode CC) |
| GetOppositeBranchCondition - Return the inverse of the specified cond, e.g. | |
| unsigned | getVPCMPImmForCond (ISD::CondCode CC) |
| Get the VPCMP immediate for the given condition. | |
| unsigned | getSwappedVPCMPImm (unsigned Imm) |
| Get the VPCMP immediate if the opcodes are swapped. | |
| unsigned | getSwappedVPCOMImm (unsigned Imm) |
| Get the VPCOM immediate if the opcodes are swapped. | |
| unsigned | getSwappedVCMPImm (unsigned Imm) |
| Get the VCMP immediate if the opcodes are swapped. | |
| unsigned | getVectorRegisterWidth (const MCOperandInfo &Info) |
| Get the width of the vector register operand. | |
| bool | isX87Instruction (MachineInstr &MI) |
| Check if the instruction is X87 instruction. | |
| int | getFirstAddrOperandIdx (const MachineInstr &MI) |
| Return the index of the instruction's first address operand, if it has a memory reference, or -1 if it has none. | |
| const Constant * | getConstantFromPool (const MachineInstr &MI, unsigned OpNo) |
| Find any constant pool entry associated with a specific instruction operand. | |
| bool | isConstantSplat (SDValue Op, APInt &SplatVal, bool AllowPartialUndefs=true) |
If Op is a constant whose elements are all the same constant or undefined, return true and return the constant value in SplatVal. | |
| int | getRoundingModeX86 (unsigned RM) |
| Convert LLVM rounding mode to X86 rounding mode. | |
| bool | isZeroNode (SDValue Elt) |
| Returns true if Elt is a constant zero or floating point constant +0.0. | |
| bool | isOffsetSuitableForCodeModel (int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement) |
| Returns true of the given offset can be fit into displacement field of the instruction. | |
| bool | isCalleePop (CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO) |
| Determines whether the callee is required to pop its own arguments. | |
| bool | mayFoldLoad (SDValue Op, const X86Subtarget &Subtarget, bool AssumeSingleUse=false) |
| Check if Op is a load operation that could be folded into some other x86 instruction as a memory operand. | |
| bool | mayFoldLoadIntoBroadcastFromMem (SDValue Op, MVT EltVT, const X86Subtarget &Subtarget, bool AssumeSingleUse=false) |
| Check if Op is a load operation that could be folded into a vector splat instruction as a memory operand. | |
| bool | mayFoldIntoStore (SDValue Op) |
| Check if Op is a value that could be used to fold a store into some other x86 instruction as a memory operand. | |
| bool | mayFoldIntoZeroExtend (SDValue Op) |
| Check if Op is an operation that could be folded into a zero extend x86 instruction. | |
| bool | isExtendedSwiftAsyncFrameSupported (const X86Subtarget &Subtarget, const MachineFunction &MF) |
| True if the target supports the extended frame for async Swift functions. | |
| FastISel * | createFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) |
Detailed Description
Define some predicates that are used for node matching.
Typedef Documentation
◆ Specifier
| using llvm::X86::Specifier = uint16_t |
Definition at line 68 of file X86MCAsmInfo.h.
Enumeration Type Documentation
◆ anonymous enum
| anonymous enum |
| Enumerator | |
|---|---|
| AddrBaseReg | |
| AddrScaleAmt | |
| AddrIndexReg | |
| AddrDisp | |
| AddrSegmentReg | |
| AddrNumOperands | |
Definition at line 28 of file X86BaseInfo.h.
◆ anonymous enum
| anonymous enum |
| Enumerator | |
|---|---|
| BX_SI | |
| BX_DI | |
| BP_SI | |
| BP_DI | |
| sib | |
| sib64 | |
Definition at line 1818 of file X86Disassembler.cpp.
◆ anonymous enum
| anonymous enum |
| Enumerator | |
|---|---|
| MaxShuffleCombineDepth | |
Definition at line 41184 of file X86ISelLowering.cpp.
◆ anonymous enum
| anonymous enum |
Definition at line 70 of file X86MCAsmInfo.h.
◆ AlignBranchBoundaryKind
Defines the possible values of the branch boundary alignment mask.
| Enumerator | |
|---|---|
| AlignBranchNone | |
| AlignBranchFused | |
| AlignBranchJcc | |
| AlignBranchJmp | |
| AlignBranchCall | |
| AlignBranchRet | |
| AlignBranchIndirect | |
Definition at line 309 of file X86BaseInfo.h.
◆ AsmComments
| Enumerator | |
|---|---|
| AC_EVEX_2_LEGACY | |
| AC_EVEX_2_VEX | |
| AC_EVEX_2_EVEX | |
Definition at line 37 of file X86InstrInfo.h.
◆ CondCode
| enum llvm::X86::CondCode |
| Enumerator | |
|---|---|
| COND_O | |
| COND_NO | |
| COND_B | |
| COND_AE | |
| COND_E | |
| COND_NE | |
| COND_BE | |
| COND_A | |
| COND_S | |
| COND_NS | |
| COND_P | |
| COND_NP | |
| COND_L | |
| COND_GE | |
| COND_LE | |
| COND_G | |
| LAST_VALID_COND | |
| COND_NE_OR_P | |
| COND_E_AND_NP | |
| COND_INVALID | |
Definition at line 77 of file X86BaseInfo.h.
◆ CPUKind
| enum llvm::X86::CPUKind |
Definition at line 68 of file X86TargetParser.h.
◆ EncodingOfSegmentOverridePrefix
Defines the encoding values for segment override prefix.
| Enumerator | |
|---|---|
| CS_Encoding | |
| DS_Encoding | |
| ES_Encoding | |
| FS_Encoding | |
| GS_Encoding | |
| SS_Encoding | |
Definition at line 320 of file X86BaseInfo.h.
◆ FirstMacroFusionInstKind
|
strong |
| Enumerator | |
|---|---|
| Test | |
| Cmp | |
| And | |
| AddSub | |
| IncDec | |
| Invalid | |
Definition at line 107 of file X86BaseInfo.h.
◆ Fixups
| enum llvm::X86::Fixups |
Definition at line 16 of file X86FixupKinds.h.
◆ IPREFIXES
| enum llvm::X86::IPREFIXES |
The constants to describe instr prefixes if there are.
Definition at line 51 of file X86BaseInfo.h.
◆ OperandType
| enum llvm::X86::OperandType : unsigned |
| Enumerator | |
|---|---|
| OPERAND_ROUNDING_CONTROL | |
| OPERAND_COND_CODE | |
Definition at line 69 of file X86BaseInfo.h.
◆ ProcessorFeatures
| Enumerator | |
|---|---|
| CPU_FEATURE_MAX | |
Definition at line 59 of file X86TargetParser.h.
◆ ProcessorSubtypes
| Enumerator | |
|---|---|
| CPU_SUBTYPE_DUMMY | |
| CPU_SUBTYPE_MAX | |
Definition at line 49 of file X86TargetParser.h.
◆ ProcessorTypes
| Enumerator | |
|---|---|
| CPU_TYPE_DUMMY | |
| CPU_TYPE_MAX | |
Definition at line 39 of file X86TargetParser.h.
◆ ProcessorVendors
| Enumerator | |
|---|---|
| VENDOR_DUMMY | |
| VENDOR_OTHER | |
Definition at line 29 of file X86TargetParser.h.
◆ RoundingMode
Current rounding mode is represented in bits 11:10 of FPSR.
These values are same as corresponding constants for rounding mode used in glibc.
| Enumerator | |
|---|---|
| rmInvalid | |
| rmToNearest | |
| rmDownward | |
| rmUpward | |
| rmTowardZero | |
| rmMask | |
Definition at line 1007 of file X86ISelLowering.h.
◆ SecondMacroFusionInstKind
|
strong |
| Enumerator | |
|---|---|
| AB | |
| ELG | |
| SPO | |
| Invalid | |
Definition at line 116 of file X86BaseInfo.h.
◆ STATIC_ROUNDING
AVX512 static rounding constants.
These need to match the values in avx512fintrin.h.
| Enumerator | |
|---|---|
| TO_NEAREST_INT | |
| TO_NEG_INF | |
| TO_POS_INF | |
| TO_ZERO | |
| CUR_DIRECTION | |
| NO_EXC | |
Definition at line 41 of file X86BaseInfo.h.
Function Documentation
◆ classifyFirstOpcodeInMacroFusion()
|
inline |
- Returns
- the type of the first instruction in macro-fusion.
Definition at line 126 of file X86BaseInfo.h.
References AddSub, And, Cmp, IncDec, Invalid, and Test.
Referenced by classifyFirst(), and isFirstMacroFusibleInst().
◆ classifySecondCondCodeInMacroFusion()
|
inline |
- Returns
- the type of the second instruction in macro-fusion.
Definition at line 258 of file X86BaseInfo.h.
References AB, COND_A, COND_AE, COND_B, COND_BE, COND_E, COND_G, COND_GE, COND_INVALID, COND_L, COND_LE, COND_NE, COND_NO, COND_NP, COND_NS, COND_O, COND_P, COND_S, ELG, Invalid, and SPO.
Referenced by classifySecond().
◆ createFastISel()
| FastISel * llvm::X86::createFastISel | ( | FunctionLoweringInfo & | funcInfo, |
| const TargetLibraryInfo * | libInfo ) |
Definition at line 4094 of file X86FastISel.cpp.
Referenced by llvm::X86TargetLowering::createFastISel().
◆ fillValidCPUArchList()
| void llvm::X86::fillValidCPUArchList | ( | SmallVectorImpl< StringRef > & | Values, |
| bool | Only64Bit = false ) |
Provide a list of valid CPU names.
If Only64Bit is true, the list will only contain 64-bit capable CPUs.
Definition at line 464 of file X86TargetParser.cpp.
References llvm::SmallVectorImpl< T >::emplace_back(), P, and Processors.
◆ fillValidTuneCPUList()
| void llvm::X86::fillValidTuneCPUList | ( | SmallVectorImpl< StringRef > & | Values, |
| bool | Only64Bit = false ) |
Provide a list of valid -mtune names.
Definition at line 472 of file X86TargetParser.cpp.
References llvm::SmallVectorImpl< T >::emplace_back(), llvm::is_contained(), NoTuneList, P, and Processors.
◆ getCCMPCondFlagsFromCondCode()
| int llvm::X86::getCCMPCondFlagsFromCondCode | ( | X86::CondCode | CC | ) |
◆ getCMovOpcode()
| unsigned llvm::X86::getCMovOpcode | ( | unsigned | RegBytes, |
| bool | HasMemoryOperand = false, | ||
| bool | HasNDD = false ) |
Return a cmov opcode for the given register size in bytes, and operand type.
Definition at line 3468 of file X86InstrInfo.cpp.
References GET_ND_IF_ENABLED, and llvm_unreachable.
Referenced by llvm::X86InstrInfo::insertSelect().
◆ getCondFromBranch()
| X86::CondCode llvm::X86::getCondFromBranch | ( | const MachineInstr & | MI | ) |
Definition at line 3188 of file X86InstrInfo.cpp.
References COND_INVALID, getCondFromMI(), and MI.
Referenced by classifySecond(), llvm::X86InstrInfo::removeBranch(), llvm::X86InstrInfo::replaceBranchWithTailCall(), and splitBlock().
◆ getCondFromCCMP()
| X86::CondCode llvm::X86::getCondFromCCMP | ( | const MachineInstr & | MI | ) |
Definition at line 3209 of file X86InstrInfo.cpp.
References COND_INVALID, getCondFromMI(), and MI.
◆ getCondFromCFCMov()
| X86::CondCode llvm::X86::getCondFromCFCMov | ( | const MachineInstr & | MI | ) |
Definition at line 3204 of file X86InstrInfo.cpp.
References COND_INVALID, getCondFromMI(), and MI.
◆ getCondFromCMov()
| X86::CondCode llvm::X86::getCondFromCMov | ( | const MachineInstr & | MI | ) |
Definition at line 3199 of file X86InstrInfo.cpp.
References COND_INVALID, getCondFromMI(), and MI.
Referenced by packCmovGroup().
◆ getCondFromMI()
| X86::CondCode llvm::X86::getCondFromMI | ( | const MachineInstr & | MI | ) |
Return the condition code of the instruction.
If the instruction doesn't have a condition code, return X86::COND_INVALID.
Definition at line 3179 of file X86InstrInfo.cpp.
References COND_INVALID, getCondSrcNoFromDesc(), llvm::getImm(), and MI.
Referenced by getCondFromBranch(), getCondFromCCMP(), getCondFromCFCMov(), getCondFromCMov(), getCondFromSETCC(), and llvm::X86InstrInfo::optimizeCompareInstr().
◆ getCondFromSETCC()
| X86::CondCode llvm::X86::getCondFromSETCC | ( | const MachineInstr & | MI | ) |
Definition at line 3193 of file X86InstrInfo.cpp.
References COND_INVALID, getCondFromMI(), and MI.
◆ getCondSrcNoFromDesc()
| int llvm::X86::getCondSrcNoFromDesc | ( | const MCInstrDesc & | MCID | ) |
Return the source operand # for condition code by MCID.
If the instruction doesn't have a condition code, return -1.
Definition at line 3168 of file X86InstrInfo.cpp.
Referenced by getCondFromMI().
◆ getConstantFromPool()
| const Constant * llvm::X86::getConstantFromPool | ( | const MachineInstr & | MI, |
| unsigned | OpNo ) |
Find any constant pool entry associated with a specific instruction operand.
Definition at line 3669 of file X86InstrInfo.cpp.
References AddrDisp, AddrIndexReg, AddrNumOperands, assert(), llvm::MachineConstantPoolEntry::ConstVal, llvm::MachineOperand::getIndex(), llvm::MachineOperand::getOffset(), llvm::MachineOperand::isCPI(), llvm::MachineConstantPoolEntry::isMachineConstantPoolEntry(), MI, and llvm::MachineConstantPoolEntry::Val.
Referenced by addConstantComments(), printBroadcast(), printExtend(), and printZeroUpperMove().
◆ getCPUDispatchMangling()
Definition at line 739 of file X86TargetParser.cpp.
References assert(), llvm::find_if(), I, P, and Processors.
◆ getCpuSupportsMask()
Definition at line 754 of file X86TargetParser.cpp.
References assert().
◆ getFeaturePriority()
| unsigned llvm::X86::getFeaturePriority | ( | ProcessorFeatures | Feat | ) |
Definition at line 771 of file X86TargetParser.cpp.
References assert(), and llvm_unreachable.
◆ getFeaturesForCPU()
| void llvm::X86::getFeaturesForCPU | ( | StringRef | CPU, |
| SmallVectorImpl< StringRef > & | Features, | ||
| bool | NeedPlus = false ) |
Fill in the features that CPU supports into Features.
"+" will be append in front of each feature if NeedPlus is true.
Definition at line 664 of file X86TargetParser.cpp.
References assert(), CPU_FEATURE_MAX, FeatureInfos, llvm::find_if(), getName(), I, P, Processors, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
◆ getFirstAddrOperandIdx()
| int llvm::X86::getFirstAddrOperandIdx | ( | const MachineInstr & | MI | ) |
Return the index of the instruction's first address operand, if it has a memory reference, or -1 if it has none.
Unlike X86II::getMemoryOperandNo(), this also works for both pseudo instructions (e.g., TCRETURNmi) as well as real instructions (e.g., JMP64m).
Definition at line 3618 of file X86InstrInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::NumOps, AddrNumOperands, assert(), llvm::X86II::getMemoryOperandNo(), llvm::X86II::getOperandBias(), I, llvm::X86II::isPseudo(), MI, llvm::none_of(), and llvm::MCOI::OPERAND_MEMORY.
Referenced by CompressEVEXImpl().
◆ getKeyFeature()
| ProcessorFeatures llvm::X86::getKeyFeature | ( | X86::CPUKind | Kind | ) |
Get the key feature prioritizing target multiversioning.
Definition at line 481 of file X86TargetParser.cpp.
References assert(), llvm_unreachable, P, and Processors.
◆ getNFVariant()
Definition at line 3281 of file X86InstrInfo.cpp.
References assert(), getNewOpcFromTable(), llvm::is_sorted(), and Opc.
Referenced by CompressEVEXImpl(), getClobberType(), and llvm::X86InstrInfo::optimizeCompareInstr().
◆ getNonNDVariant()
Definition at line 3294 of file X86InstrInfo.cpp.
References assert(), getNewOpcFromTable(), llvm::is_sorted(), and Opc.
Referenced by CompressEVEXImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), and llvm::X86RegisterInfo::getRegAllocationHints().
◆ getOpcodeForLongImmediateForm()
Definition at line 463 of file X86EncodingOptimization.cpp.
Referenced by getRelaxedOpcode().
◆ getOpcodeForShortImmediateForm()
Definition at line 452 of file X86EncodingOptimization.cpp.
◆ GetOppositeBranchCondition()
| X86::CondCode llvm::X86::GetOppositeBranchCondition | ( | X86::CondCode | CC | ) |
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
Return the inverse of the specified condition, e.g.
turning COND_E to COND_NE.
Definition at line 3309 of file X86InstrInfo.cpp.
References COND_A, COND_AE, COND_B, COND_BE, COND_E, COND_E_AND_NP, COND_G, COND_GE, COND_L, COND_LE, COND_NE, COND_NE_OR_P, COND_NO, COND_NP, COND_NS, COND_O, COND_P, COND_S, and llvm_unreachable.
Referenced by checkBoolTestSetCCCombine(), combineAndOrForCcmpCtest(), combineCMov(), combineOr(), combineSubSetcc(), combineX86SubCmpForFlags(), llvm::X86InstrInfo::commuteInstructionImpl(), createPHIsForCMOVsInSinkBB(), and foldXor1SetCC().
◆ getRoundingModeX86()
| int llvm::X86::getRoundingModeX86 | ( | unsigned | RM | ) |
Convert LLVM rounding mode to X86 rounding mode.
Definition at line 5351 of file X86ISelLowering.cpp.
References rmDownward, rmInvalid, rmToNearest, rmTowardZero, and rmUpward.
◆ getSegmentOverridePrefixForReg()
|
inline |
Given a segment register, return the encoding of the segment override prefix for it.
Definition at line 332 of file X86BaseInfo.h.
References CS_Encoding, DS_Encoding, ES_Encoding, FS_Encoding, GS_Encoding, llvm_unreachable, Reg, and SS_Encoding.
◆ getSwappedVCMPImm()
Get the VCMP immediate if the opcodes are swapped.
Get the VCMP immediate if the operands are swapped.
Definition at line 3565 of file X86InstrInfo.cpp.
References llvm_unreachable.
Referenced by llvm::X86InstrInfo::commuteInstructionImpl().
◆ getSwappedVPCMPImm()
Get the VPCMP immediate if the opcodes are swapped.
Get the VPCMP immediate if the operands are swapped.
Definition at line 3511 of file X86InstrInfo.cpp.
References llvm_unreachable.
Referenced by llvm::X86InstrInfo::commuteInstructionImpl().
◆ getSwappedVPCOMImm()
Get the VPCOM immediate if the opcodes are swapped.
Get the VPCOM immediate if the operands are swapped.
Definition at line 3538 of file X86InstrInfo.cpp.
References llvm_unreachable.
Referenced by llvm::X86InstrInfo::commuteInstructionImpl().
◆ getVectorRegisterWidth()
| unsigned llvm::X86::getVectorRegisterWidth | ( | const MCOperandInfo & | Info | ) |
Get the width of the vector register operand.
Definition at line 3584 of file X86InstrInfo.cpp.
References llvm_unreachable.
Referenced by addConstantComments(), and printZeroExtend().
◆ getVPCMPImmForCond()
| unsigned llvm::X86::getVPCMPImmForCond | ( | ISD::CondCode | CC | ) |
Get the VPCMP immediate for the given condition.
Definition at line 3487 of file X86InstrInfo.cpp.
References llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.
◆ getX86ConditionCode()
| std::pair< X86::CondCode, bool > llvm::X86::getX86ConditionCode | ( | CmpInst::Predicate | Predicate | ) |
Return a pair of condition code for the given predicate and whether the instruction operands should be swaped to match the condition code.
Definition at line 3382 of file X86InstrInfo.cpp.
References COND_A, COND_AE, COND_B, COND_BE, COND_E, COND_G, COND_GE, COND_INVALID, COND_L, COND_LE, COND_NE, COND_NP, COND_P, llvm::CmpInst::FCMP_OEQ, llvm::CmpInst::FCMP_OGE, llvm::CmpInst::FCMP_OGT, llvm::CmpInst::FCMP_OLE, llvm::CmpInst::FCMP_OLT, llvm::CmpInst::FCMP_ONE, llvm::CmpInst::FCMP_ORD, llvm::CmpInst::FCMP_UEQ, llvm::CmpInst::FCMP_UGE, llvm::CmpInst::FCMP_UGT, llvm::CmpInst::FCMP_ULE, llvm::CmpInst::FCMP_ULT, llvm::CmpInst::FCMP_UNE, llvm::CmpInst::FCMP_UNO, llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::CmpInst::ICMP_SGE, llvm::CmpInst::ICMP_SGT, llvm::CmpInst::ICMP_SLE, llvm::CmpInst::ICMP_SLT, llvm::CmpInst::ICMP_UGE, llvm::CmpInst::ICMP_UGT, llvm::CmpInst::ICMP_ULE, and llvm::CmpInst::ICMP_ULT.
◆ isCalleePop()
| bool llvm::X86::isCalleePop | ( | CallingConv::ID | CallingConv, |
| bool | is64Bit, | ||
| bool | IsVarArg, | ||
| bool | GuaranteeTCO ) |
Determines whether the callee is required to pop its own arguments.
Callee pop is necessary to support tail calls.
Definition at line 3010 of file X86ISelLoweringCall.cpp.
References is64Bit(), shouldGuaranteeTCO(), llvm::CallingConv::X86_FastCall, llvm::CallingConv::X86_StdCall, llvm::CallingConv::X86_ThisCall, and llvm::CallingConv::X86_VectorCall.
◆ isConstantSplat()
If Op is a constant whose elements are all the same constant or undefined, return true and return the constant value in SplatVal.
If we have undef bits that don't cover an entire element, we treat these as zero if AllowPartialUndefs is set, else we fail and return false.
Definition at line 5326 of file X86ISelLowering.cpp.
References getTargetConstantBitsFromNode(), and llvm::SmallVectorTemplateCommon< T, typename >::size().
Referenced by combineAndMaskToShift(), combineVPMADD52LH(), LowerFunnelShift(), LowerRotate(), LowerShift(), and LowerShiftByScalarImmediate().
◆ isExtendedSwiftAsyncFrameSupported()
| bool llvm::X86::isExtendedSwiftAsyncFrameSupported | ( | const X86Subtarget & | Subtarget, |
| const MachineFunction & | MF ) |
True if the target supports the extended frame for async Swift functions.
Definition at line 27713 of file X86ISelLowering.cpp.
References llvm::TargetMachine::getMCAsmInfo(), llvm::MachineFunction::getTarget(), and llvm::MCAsmInfo::usesWindowsCFI().
Referenced by LowerINTRINSIC_W_CHAIN().
◆ isMacroFused()
|
inline |
- Parameters
-
FirstKind kind of the first instruction in macro fusion. SecondKind kind of the second instruction in macro fusion.
- Returns
- true if the two instruction can be macro fused.
Definition at line 290 of file X86BaseInfo.h.
References AB, AddSub, And, Cmp, ELG, IncDec, Invalid, llvm_unreachable, and Test.
Referenced by shouldScheduleAdjacent().
◆ isOffsetSuitableForCodeModel()
| bool llvm::X86::isOffsetSuitableForCodeModel | ( | int64_t | Offset, |
| CodeModel::Model | M, | ||
| bool | hasSymbolicDisplacement ) |
Returns true of the given offset can be fit into displacement field of the instruction.
Definition at line 2915 of file X86ISelLowering.cpp.
References llvm::isInt(), llvm::CodeModel::Kernel, llvm::CodeModel::Large, and llvm::Offset.
Referenced by llvm::X86TargetLowering::isLegalAddressingMode().
◆ isX87Instruction()
| bool llvm::X86::isX87Instruction | ( | MachineInstr & | MI | ) |
Check if the instruction is X87 instruction.
check if the instruction is X87 instruction
Definition at line 3603 of file X86InstrInfo.cpp.
References isX87Reg(), and MI.
Referenced by getNextFPInstruction().
◆ isZeroNode()
Returns true if Elt is a constant zero or floating point constant +0.0.
Returns true if Elt is a constant zero or a floating point constant +0.0.
Definition at line 3977 of file X86ISelLowering.cpp.
References llvm::isNullConstant(), and llvm::isNullFPConstant().
Referenced by combineAdd(), combineAddOrSubToADCOrSBB(), combineSub(), combineX86CloadCstore(), computeZeroableShuffleElements(), EltsFromConsecutiveLoads(), getFauxShuffleMask(), getMaskNode(), getTargetShuffleAndZeroables(), LowerBuildVectorv4x32(), LowerSCALAR_TO_VECTOR(), and widenSubVector().
◆ mayFoldIntoStore()
Check if Op is a value that could be used to fold a store into some other x86 instruction as a memory operand.
Ex: pextrb $0, xmm0, (rdi).
Definition at line 2811 of file X86ISelLowering.cpp.
References llvm::Value::hasOneUse(), llvm::ISD::isNormalStore(), and llvm::Value::user_begin().
Referenced by LowerEXTRACT_VECTOR_ELT_SSE4().
◆ mayFoldIntoZeroExtend()
Check if Op is an operation that could be folded into a zero extend x86 instruction.
Definition at line 2824 of file X86ISelLowering.cpp.
References llvm::ISD::ZERO_EXTEND.
Referenced by LowerEXTRACT_VECTOR_ELT_SSE4().
◆ mayFoldLoad()
| bool llvm::X86::mayFoldLoad | ( | SDValue | Op, |
| const X86Subtarget & | Subtarget, | ||
| bool | AssumeSingleUse = false ) |
Check if Op is a load operation that could be folded into some other x86 instruction as a memory operand.
Example: vpaddd (rdi), xmm0, xmm0.
Definition at line 2778 of file X86ISelLowering.cpp.
References llvm::cast(), llvm::X86Subtarget::hasAVX(), and llvm::ISD::isNormalLoad().
Referenced by combineCommutableSHUFP(), combineConcatVectorOps(), combineTargetShuffle(), combineX86ShuffleChain(), EmitCmp(), llvm::X86TargetLowering::IsDesirableToPromoteOp(), lowerShuffleAsDecomposedShuffleMerge(), lowerV2X128Shuffle(), mayFoldLoadIntoBroadcastFromMem(), and pushAddIntoCmovOfConsts().
◆ mayFoldLoadIntoBroadcastFromMem()
| bool llvm::X86::mayFoldLoadIntoBroadcastFromMem | ( | SDValue | Op, |
| MVT | EltVT, | ||
| const X86Subtarget & | Subtarget, | ||
| bool | AssumeSingleUse = false ) |
Check if Op is a load operation that could be folded into a vector splat instruction as a memory operand.
Example: vbroadcastss 16(rdi), xmm2.
Definition at line 2797 of file X86ISelLowering.cpp.
References assert(), llvm::cast(), llvm::MVT::getScalarSizeInBits(), llvm::X86Subtarget::hasAVX(), and mayFoldLoad().
Referenced by combineConcatVectorOps(), and EltsFromConsecutiveLoads().
◆ optimizeINCDEC()
Definition at line 312 of file X86EncodingOptimization.cpp.
◆ optimizeInstFromVEX3ToVEX2()
| bool llvm::X86::optimizeInstFromVEX3ToVEX2 | ( | MCInst & | MI, |
| const MCInstrDesc & | Desc ) |
Definition at line 23 of file X86EncodingOptimization.cpp.
References llvm::X86II::EncodingMask, llvm::X86II::FormMask, FROM_TO, llvm::X86II::isX86_64ExtendedReg(), MI, llvm::X86II::MRMSrcReg, llvm::X86II::OpMapMask, llvm::X86II::REX_W, std::swap(), llvm::X86II::TB, TO_REV, llvm::X86II::VEX, and llvm::X86II::VEX_4V.
◆ optimizeMOV()
Simplify things like MOV32rm to MOV32o32a.
Definition at line 338 of file X86EncodingOptimization.cpp.
References AddrBaseReg, AddrIndexReg, AddrScaleAmt, AddrSegmentReg, llvm::dyn_cast(), FROM_TO, isARegister(), MI, S_TLVP, and Saved.
◆ optimizeMOVSX()
Definition at line 290 of file X86EncodingOptimization.cpp.
◆ optimizeShiftRotateWithImmediateOne()
Definition at line 105 of file X86EncodingOptimization.cpp.
References llvm::MCOperand::getImm(), llvm::MCOperand::isImm(), MI, and TO_IMM1.
◆ optimizeToFixedRegisterOrShortImmediateForm()
Definition at line 499 of file X86EncodingOptimization.cpp.
References MI, optimizeToFixedRegisterForm(), and optimizeToShortImmediateForm().
◆ optimizeVPCMPWithImmediateOneOrSix()
Definition at line 203 of file X86EncodingOptimization.cpp.
References FROM_TO, llvm::MCOperand::getImm(), and MI.
◆ parseArchX86()
| X86::CPUKind llvm::X86::parseArchX86 | ( | StringRef | CPU, |
| bool | Only64Bit = false ) |
Parse CPU string into a CPUKind.
Will only accept 64-bit capable CPUs if Only64Bit is true.
Definition at line 449 of file X86TargetParser.cpp.
References CK_None, P, and Processors.
Referenced by parseTuneCPU().
◆ parseTuneCPU()
| X86::CPUKind llvm::X86::parseTuneCPU | ( | StringRef | CPU, |
| bool | Only64Bit = false ) |
Definition at line 458 of file X86TargetParser.cpp.
References CK_None, llvm::is_contained(), NoTuneList, and parseArchX86().
◆ updateImpliedFeatures()
| void llvm::X86::updateImpliedFeatures | ( | StringRef | Feature, |
| bool | Enabled, | ||
| StringMap< bool > & | Features ) |
Set or clear entries in Features that are implied to be enabled/disabled by the provided Feature.
Definition at line 714 of file X86TargetParser.cpp.
References CPU_FEATURE_MAX, Enabled, FeatureInfos, llvm::find_if(), getImpliedDisabledFeatures(), getImpliedEnabledFeatures(), getName(), and I.
◆ validateCPUSpecificCPUDispatch()
Definition at line 747 of file X86TargetParser.cpp.
References llvm::find_if(), I, P, and Processors.
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