40class X86AlignBranchKind {
45 void operator=(
const std::string &Val) {
50 for (
auto BranchType : BranchTypes) {
51 if (BranchType ==
"fused")
53 else if (BranchType ==
"jcc")
55 else if (BranchType ==
"jmp")
57 else if (BranchType ==
"call")
59 else if (BranchType ==
"ret")
61 else if (BranchType ==
"indirect")
65 <<
" to -x86-align-branch=; each element must be one of: fused, "
66 "jcc, jmp, call, ret, indirect.(plus separated)\n";
71 operator uint8_t()
const {
return AlignBranchKind; }
75X86AlignBranchKind X86AlignBranchKindLoc;
78 "x86-align-branch-boundary",
cl::init(0),
80 "Control how the assembler should align branches with NOP. If the "
81 "boundary's size is not 0, it should be a power of 2 and no less "
82 "than 32. Branches will be aligned to prevent from being across or "
83 "against the boundary of specified size. The default value 0 does not "
89 "Specify types of branches to align (plus separated list of types):"
90 "\njcc indicates conditional jumps"
91 "\nfused indicates fused conditional jumps"
92 "\njmp indicates direct unconditional jumps"
93 "\ncall indicates direct and indirect calls"
94 "\nret indicates rets"
95 "\nindirect indicates indirect unconditional jumps"),
99 "x86-branches-within-32B-boundaries",
cl::init(
false),
101 "Align selected instructions to mitigate negative performance impact "
102 "of Intel's micro code update for errata skx102. May break "
103 "assumptions about labels corresponding to particular instructions, "
104 "and should be used with caution."));
107 "x86-pad-max-prefix-size",
cl::init(0),
108 cl::desc(
"Maximum number of prefixes to use for padding"));
112 cl::desc(
"Pad previous instructions to implement align directives"));
116 cl::desc(
"Pad previous instructions to implement branch alignment"));
120 std::unique_ptr<const MCInstrInfo> MCII;
121 X86AlignBranchKind AlignBranchType;
123 unsigned TargetPrefixMax = 0;
126 unsigned PrevInstOpcode = 0;
128 std::pair<MCFragment *, size_t> PrevInstPosition;
129 bool IsRightAfterData =
false;
133 bool needAlign(
const MCInst &Inst)
const;
141 if (X86AlignBranchWithin32BBoundaries) {
152 if (X86AlignBranchBoundary.getNumOccurrences())
154 if (X86AlignBranch.getNumOccurrences())
155 AlignBranchType = X86AlignBranchKindLoc;
156 if (X86PadMaxPrefixSize.getNumOccurrences())
157 TargetPrefixMax = X86PadMaxPrefixSize;
194 unsigned &RemainingSize)
const;
197 unsigned &RemainingSize)
const;
200 unsigned &RemainingSize)
const;
212 return Opcode == X86::JCC_1 || Opcode == X86::JMP_1;
216 bool Is16BitMode =
false) {
221 return (Is16BitMode) ? X86::JCC_2 : X86::JCC_4;
223 return (Is16BitMode) ? X86::JMP_2 : X86::JMP_4;
228 unsigned Opcode =
MI.getOpcode();
235 unsigned Opcode =
MI.getOpcode();
242 MI.getOperand(
Desc.getNumOperands() - 1).getImm());
250 return classifySecondCondCodeInMacroFusion(
CC);
255 unsigned Opcode =
MI.getOpcode();
260 if (MemoryOperand < 0)
263 MCRegister BaseReg =
MI.getOperand(BaseRegNum).getReg();
264 return (BaseReg == X86::RIP);
280 return FIK != X86::FirstMacroFusionInstKind::Invalid;
292uint8_t X86AsmBackend::determinePaddingPrefix(
const MCInst &Inst)
const {
294 "Prefixes can be added only in 32-bit or 64-bit mode.");
300 if (MemoryOperand != -1)
304 if (MemoryOperand >= 0) {
337 if (MemoryOperand >= 0) {
340 if (BaseReg == X86::ESP || BaseReg == X86::EBP)
347bool X86AsmBackend::isMacroFused(
const MCInst &Cmp,
const MCInst &Jcc)
const {
362 for (
auto &Operand :
MI) {
363 if (!Operand.isExpr())
365 const MCExpr &Expr = *Operand.getExpr();
373bool X86AsmBackend::allowAutoPadding()
const {
377bool X86AsmBackend::allowEnhancedRelaxation()
const {
378 return allowAutoPadding() && TargetPrefixMax != 0 && X86PadForBranchAlign;
385 switch (InstOpcode) {
405 const std::pair<MCFragment *, size_t> &PrevInstPosition) {
418 if (
auto *
DF = dyn_cast_or_null<MCDataFragment>(
F))
419 return DF->getContents().size() &&
420 (
DF != PrevInstPosition.first ||
421 DF->getContents().size() != PrevInstPosition.second);
428 if (!
F || !
F->hasInstructions())
431 switch (
F->getKind()) {
435 return cast<MCDataFragment>(*F).getContents().size();
437 return cast<MCRelaxableFragment>(*F).getContents().size();
454 if (
isPrefix(PrevInstOpcode, *MCII))
464 if (IsRightAfterData)
473 if (!
OS.getAllowAutoPadding())
475 assert(allowAutoPadding() &&
"incorrect initialization!");
478 if (!
OS.getCurrentSectionOnly()->isText())
482 if (
OS.getAssembler().isBundlingEnabled())
493bool X86AsmBackend::needAlign(
const MCInst &Inst)
const {
495 return (
Desc.isConditionalBranch() &&
497 (
Desc.isUnconditionalBranch() &&
501 (
Desc.isIndirectBranch() &&
513 if (!canPadBranches(
OS))
525 if (!canPadInst(Inst,
OS))
528 if (PendingBA && PendingBA->
getNext() ==
OS.getCurrentFragment()) {
556 OS.insert(PendingBA);
564 if (
auto *
F = dyn_cast_or_null<MCRelaxableFragment>(CF))
565 F->setAllowAutoPadding(canPadInst(Inst,
OS));
571 if (!canPadBranches(
OS))
577 if (!needAlign(Inst) || !PendingBA)
588 if (isa_and_nonnull<MCDataFragment>(CF))
596std::optional<MCFixupKind> X86AsmBackend::getFixupKind(
StringRef Name)
const {
601#define ELF_RELOC(X, Y) .Case(#X, Y)
602#include "llvm/BinaryFormat/ELFRelocs/x86_64.def"
604 .
Case(
"BFD_RELOC_NONE", ELF::R_X86_64_NONE)
605 .
Case(
"BFD_RELOC_8", ELF::R_X86_64_8)
606 .
Case(
"BFD_RELOC_16", ELF::R_X86_64_16)
607 .
Case(
"BFD_RELOC_32", ELF::R_X86_64_32)
608 .
Case(
"BFD_RELOC_64", ELF::R_X86_64_64)
612#define ELF_RELOC(X, Y) .Case(#X, Y)
613#include "llvm/BinaryFormat/ELFRelocs/i386.def"
615 .
Case(
"BFD_RELOC_NONE", ELF::R_386_NONE)
616 .
Case(
"BFD_RELOC_8", ELF::R_386_8)
617 .
Case(
"BFD_RELOC_16", ELF::R_386_16)
618 .
Case(
"BFD_RELOC_32", ELF::R_386_32)
638 {
"reloc_signed_4byte", 0, 32, 0},
639 {
"reloc_signed_4byte_relax", 0, 32, 0},
640 {
"reloc_global_offset_table", 0, 32, 0},
641 {
"reloc_global_offset_table8", 0, 64, 0},
660bool X86AsmBackend::shouldForceRelocation(
const MCAssembler &,
714 assert(
Fixup.getOffset() +
Size <= Data.size() &&
"Invalid fixup offset!");
716 int64_t SignedValue =
static_cast<int64_t
>(
Value);
717 if ((
Target.isAbsolute() || IsResolved) &&
718 getFixupKindInfo(
Fixup.getKind()).Flags &
722 Asm.getContext().reportError(
723 Fixup.getLoc(),
"value of " +
Twine(SignedValue) +
724 " is too large for field of " +
Twine(
Size) +
725 ((
Size == 1) ?
" byte." :
" bytes."));
732 "Value does not fit in the Fixup field");
735 for (
unsigned i = 0; i !=
Size; ++i)
739bool X86AsmBackend::mayNeedRelaxation(
const MCInst &
MI,
741 unsigned Opcode =
MI.getOpcode();
742 unsigned SkipOperands = X86::isCCMPCC(Opcode) ? 2 : 0;
745 MI.getOperand(
MI.getNumOperands() - 1 - SkipOperands).isExpr());
748bool X86AsmBackend::fixupNeedsRelaxation(
const MCFixup &
Fixup,
751 return !isInt<8>(
Value);
756void X86AsmBackend::relaxInstruction(
MCInst &Inst,
759 bool Is16BitMode = STI.
hasFeature(X86::Is16Bit);
775 unsigned &RemainingSize)
const {
789 const unsigned MaxPossiblePad = std::min(15 - OldSize, RemainingSize);
790 const unsigned RemainingPrefixSize = [&]() ->
unsigned {
793 assert(
Code.size() < 15 &&
"The number of prefixes must be less than 15.");
800 unsigned ExistingPrefixSize =
Code.size();
801 if (TargetPrefixMax <= ExistingPrefixSize)
803 return TargetPrefixMax - ExistingPrefixSize;
805 const unsigned PrefixBytesToAdd =
806 std::min(MaxPossiblePad, RemainingPrefixSize);
807 if (PrefixBytesToAdd == 0)
813 Code.append(PrefixBytesToAdd, Prefix);
819 F.setOffset(
F.getOffset() + PrefixBytesToAdd);
822 RemainingSize -= PrefixBytesToAdd;
828 unsigned &RemainingSize)
const {
841 const unsigned NewSize =
Code.size();
842 assert(NewSize >= OldSize &&
"size decrease during relaxation?");
843 unsigned Delta = NewSize - OldSize;
844 if (Delta > RemainingSize)
849 RemainingSize -= Delta;
855 unsigned &RemainingSize)
const {
856 bool Changed =
false;
857 if (RemainingSize != 0)
858 Changed |= padInstructionViaRelaxation(RF,
Emitter, RemainingSize);
859 if (RemainingSize != 0)
860 Changed |= padInstructionViaPrefix(RF,
Emitter, RemainingSize);
864void X86AsmBackend::finishLayout(
MCAssembler const &Asm)
const {
871 if (!X86PadForAlign && !X86PadForBranchAlign)
879 LabeledFragments.
insert(S.getFragment(
false));
889 if (LabeledFragments.
count(&
F))
896 auto &RF = cast<MCRelaxableFragment>(*
I);
902 switch (
F.getKind()) {
906 return X86PadForAlign;
908 return X86PadForBranchAlign;
926 unsigned RemainingSize = OrigSize;
927 while (!Relaxable.
empty() && RemainingSize != 0) {
932 if (padInstructionEncoding(RF,
Asm.getEmitter(), RemainingSize))
948 cast<MCBoundaryAlignFragment>(
F).setSize(RemainingSize);
953 assert(OrigOffset + OrigSize == FinalOffset + FinalSize &&
954 "can't move start of next fragment!");
955 assert(FinalSize == RemainingSize &&
"inconsistent size computation?");
961 if (
auto *BF = dyn_cast<MCBoundaryAlignFragment>(&
F)) {
962 const MCFragment *LastFragment = BF->getLastFragment();
965 while (&*
I != LastFragment)
973 Asm.getFragmentOffset(*
Section.curFragList()->Tail);
974 Asm.computeFragmentSize(*
Section.curFragList()->Tail);
978unsigned X86AsmBackend::getMaximumNopSize(
const MCSubtargetInfo &STI)
const {
1000 static const char Nops32Bit[10][11] = {
1010 "\x0f\x1f\x44\x00\x00",
1012 "\x66\x0f\x1f\x44\x00\x00",
1014 "\x0f\x1f\x80\x00\x00\x00\x00",
1016 "\x0f\x1f\x84\x00\x00\x00\x00\x00",
1018 "\x66\x0f\x1f\x84\x00\x00\x00\x00\x00",
1020 "\x66\x2e\x0f\x1f\x84\x00\x00\x00\x00\x00",
1024 static const char Nops16Bit[4][11] = {
1035 const char(*Nops)[11] =
1036 STI->
hasFeature(X86::Is16Bit) ? Nops16Bit : Nops32Bit;
1043 const uint8_t ThisNopLength = (
uint8_t) std::min(Count, MaxNopLength);
1044 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
1045 for (
uint8_t i = 0; i < Prefixes; i++)
1047 const uint8_t Rest = ThisNopLength - Prefixes;
1049 OS.
write(Nops[Rest - 1], Rest);
1050 Count -= ThisNopLength;
1051 }
while (Count != 0);
1060class ELFX86AsmBackend :
public X86AsmBackend {
1064 : X86AsmBackend(
T, STI), OSABI(OSABI) {}
1067class ELFX86_32AsmBackend :
public ELFX86AsmBackend {
1071 : ELFX86AsmBackend(
T, OSABI, STI) {}
1073 std::unique_ptr<MCObjectTargetWriter>
1074 createObjectTargetWriter()
const override {
1079class ELFX86_X32AsmBackend :
public ELFX86AsmBackend {
1083 : ELFX86AsmBackend(
T, OSABI, STI) {}
1085 std::unique_ptr<MCObjectTargetWriter>
1086 createObjectTargetWriter()
const override {
1092class ELFX86_IAMCUAsmBackend :
public ELFX86AsmBackend {
1096 : ELFX86AsmBackend(
T, OSABI, STI) {}
1098 std::unique_ptr<MCObjectTargetWriter>
1099 createObjectTargetWriter()
const override {
1105class ELFX86_64AsmBackend :
public ELFX86AsmBackend {
1109 : ELFX86AsmBackend(
T, OSABI, STI) {}
1111 std::unique_ptr<MCObjectTargetWriter>
1112 createObjectTargetWriter()
const override {
1117class WindowsX86AsmBackend :
public X86AsmBackend {
1123 : X86AsmBackend(
T, STI)
1127 std::optional<MCFixupKind> getFixupKind(
StringRef Name)
const override {
1135 std::unique_ptr<MCObjectTargetWriter>
1136 createObjectTargetWriter()
const override {
1147 UNWIND_MODE_BP_FRAME = 0x01000000,
1150 UNWIND_MODE_STACK_IMMD = 0x02000000,
1153 UNWIND_MODE_STACK_IND = 0x03000000,
1156 UNWIND_MODE_DWARF = 0x04000000,
1159 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
1162 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
1167class DarwinX86AsmBackend :
public X86AsmBackend {
1171 enum { CU_NUM_SAVED_REGS = 6 };
1173 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
1177 unsigned OffsetSize;
1178 unsigned MoveInstrSize;
1179 unsigned StackDivide;
1182 unsigned PushInstrSize(
unsigned Reg)
const {
1205 int getCompactUnwindRegNum(
unsigned Reg)
const {
1206 static const MCPhysReg CU32BitRegs[7] = {
1207 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
1209 static const MCPhysReg CU64BitRegs[] = {
1210 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
1212 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
1213 for (
int Idx = 1; *CURegs; ++CURegs, ++
Idx)
1222 uint32_t encodeCompactUnwindRegistersWithFrame()
const {
1227 for (
int i = 0,
Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
1228 unsigned Reg = SavedRegs[i];
1229 if (Reg == 0)
break;
1231 int CURegNum = getCompactUnwindRegNum(Reg);
1232 if (CURegNum == -1)
return ~0
U;
1236 RegEnc |= (CURegNum & 0x7) << (
Idx++ * 3);
1239 assert((RegEnc & 0x3FFFF) == RegEnc &&
1240 "Invalid compact register encoding!");
1247 uint32_t encodeCompactUnwindRegistersWithoutFrame(
unsigned RegCount)
const {
1261 for (
unsigned i = 0; i < RegCount; ++i) {
1262 int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
1263 if (CUReg == -1)
return ~0
U;
1264 SavedRegs[i] = CUReg;
1268 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
1270 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
1271 for (
unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
1272 unsigned Countless = 0;
1273 for (
unsigned j = CU_NUM_SAVED_REGS - RegCount;
j < i; ++
j)
1274 if (SavedRegs[j] < SavedRegs[i])
1277 RenumRegs[i] = SavedRegs[i] - Countless - 1;
1284 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
1285 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
1289 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
1290 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
1294 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
1295 + 3 * RenumRegs[4] + RenumRegs[5];
1298 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
1302 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
1305 permutationEncoding |= RenumRegs[5];
1309 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
1310 "Invalid compact register encoding!");
1311 return permutationEncoding;
1317 : X86AsmBackend(
T, STI),
MRI(
MRI),
TT(STI.getTargetTriple()),
1318 Is64Bit(
TT.isArch64Bit()) {
1319 memset(SavedRegs, 0,
sizeof(SavedRegs));
1320 OffsetSize = Is64Bit ? 8 : 4;
1321 MoveInstrSize = Is64Bit ? 3 : 2;
1322 StackDivide = Is64Bit ? 8 : 4;
1325 std::unique_ptr<MCObjectTargetWriter>
1326 createObjectTargetWriter()
const override {
1337 if (Instrs.
empty())
return 0;
1338 if (!isDarwinCanonicalPersonality(FI->
Personality) &&
1340 return CU::UNWIND_MODE_DWARF;
1343 unsigned SavedRegIdx = 0;
1344 memset(SavedRegs, 0,
sizeof(SavedRegs));
1349 uint64_t CompactUnwindEncoding = 0;
1351 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
1352 unsigned InstrOffset = 0;
1353 unsigned StackAdjust = 0;
1355 int64_t MinAbsOffset = std::numeric_limits<int64_t>::max();
1358 switch (Inst.getOperation()) {
1362 return CU::UNWIND_MODE_DWARF;
1374 if (*
MRI.getLLVMRegNum(Inst.getRegister(),
true) !=
1375 (Is64Bit ? X86::RBP : X86::EBP))
1376 return CU::UNWIND_MODE_DWARF;
1379 memset(SavedRegs, 0,
sizeof(SavedRegs));
1382 MinAbsOffset = std::numeric_limits<int64_t>::max();
1383 InstrOffset += MoveInstrSize;
1401 StackSize = Inst.getOffset() / StackDivide;
1417 if (SavedRegIdx == CU_NUM_SAVED_REGS)
1420 return CU::UNWIND_MODE_DWARF;
1423 SavedRegs[SavedRegIdx++] =
Reg;
1424 StackAdjust += OffsetSize;
1425 MinAbsOffset = std::min(MinAbsOffset, std::abs(Inst.getOffset()));
1426 InstrOffset += PushInstrSize(Reg);
1432 StackAdjust /= StackDivide;
1435 if ((StackAdjust & 0xFF) != StackAdjust)
1437 return CU::UNWIND_MODE_DWARF;
1441 if (SavedRegIdx != 0 && MinAbsOffset != 3 * (
int)OffsetSize)
1442 return CU::UNWIND_MODE_DWARF;
1445 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
1446 if (RegEnc == ~0U)
return CU::UNWIND_MODE_DWARF;
1448 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
1449 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
1450 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
1452 SubtractInstrIdx += InstrOffset;
1455 if ((StackSize & 0xFF) == StackSize) {
1457 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
1460 CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
1462 if ((StackAdjust & 0x7) != StackAdjust)
1464 return CU::UNWIND_MODE_DWARF;
1467 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
1471 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
1474 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
1478 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
1479 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
1483 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
1484 if (RegEnc == ~0U)
return CU::UNWIND_MODE_DWARF;
1487 CompactUnwindEncoding |=
1488 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
1491 return CompactUnwindEncoding;
1503 return new DarwinX86AsmBackend(
T,
MRI, STI);
1506 return new WindowsX86AsmBackend(
T,
false, STI);
1511 return new ELFX86_IAMCUAsmBackend(
T, OSABI, STI);
1513 return new ELFX86_32AsmBackend(
T, OSABI, STI);
1522 return new DarwinX86AsmBackend(
T,
MRI, STI);
1525 return new WindowsX86AsmBackend(
T,
true, STI);
1527 if (TheTriple.
isUEFI()) {
1529 "Only COFF format is supported in UEFI environment.");
1530 return new WindowsX86AsmBackend(
T,
true, STI);
1535 if (TheTriple.
isX32())
1536 return new ELFX86_X32AsmBackend(
T, OSABI, STI);
1537 return new ELFX86_64AsmBackend(
T, OSABI, STI);
1543 X86ELFStreamer(
MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
1544 std::unique_ptr<MCObjectWriter> OW,
1545 std::unique_ptr<MCCodeEmitter>
Emitter)
1556 Backend.emitInstructionBegin(S, Inst, STI);
1557 S.MCObjectStreamer::emitInstruction(Inst, STI);
1558 Backend.emitInstructionEnd(S, Inst);
1561void X86ELFStreamer::emitInstruction(
const MCInst &Inst,
1567 std::unique_ptr<MCAsmBackend> &&MAB,
1568 std::unique_ptr<MCObjectWriter> &&MOW,
1569 std::unique_ptr<MCCodeEmitter> &&MCE) {
1570 return new X86ELFStreamer(Context, std::move(MAB), std::move(MOW),
unsigned const MachineRegisterInfo * MRI
dxil DXContainer Global Emitter
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static MCInstrInfo * createMCInstrInfo()
static unsigned getRelaxedOpcodeBranch(unsigned Opcode, bool Is16BitMode=false)
static X86::SecondMacroFusionInstKind classifySecondInstInMacroFusion(const MCInst &MI, const MCInstrInfo &MCII)
static size_t getSizeForInstFragment(const MCFragment *F)
static bool isRIPRelative(const MCInst &MI, const MCInstrInfo &MCII)
Check if the instruction uses RIP relative addressing.
static bool isRightAfterData(MCFragment *CurrentFragment, const std::pair< MCFragment *, size_t > &PrevInstPosition)
Check if the instruction to be emitted is right after any data.
static bool mayHaveInterruptDelaySlot(unsigned InstOpcode)
X86 has certain instructions which enable interrupts exactly one instruction after the instruction wh...
static bool isFirstMacroFusibleInst(const MCInst &Inst, const MCInstrInfo &MCII)
Check if the instruction is valid as the first instruction in macro fusion.
static X86::CondCode getCondFromBranch(const MCInst &MI, const MCInstrInfo &MCII)
static unsigned getRelaxedOpcode(const MCInst &MI, bool Is16BitMode)
static unsigned getFixupKindSize(unsigned Kind)
static bool isRelaxableBranch(unsigned Opcode)
static bool isPrefix(unsigned Opcode, const MCInstrInfo &MCII)
Check if the instruction is a prefix.
static bool hasVariantSymbol(const MCInst &MI)
Check if the instruction has a variant symbol operand.
static bool is64Bit(const char *name)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool empty() const
empty - Check if the array is empty.
Implements a dense probed hash-table based set.
Generic interface to target specific assembler backends.
virtual bool allowEnhancedRelaxation() const
Return true if this target allows an unrelaxable instruction to be emitted into RelaxableFragment and...
virtual unsigned getMaximumNopSize(const MCSubtargetInfo &STI) const
Returns the maximum size of a nop in bytes on this target.
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
virtual bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const
Check whether the given instruction may need relaxation.
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const uint64_t Value, const MCSubtargetInfo *STI)
Hook to check if a relocation is needed for some target specific reason.
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value) const
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual void finishLayout(MCAssembler const &Asm) const
Give backend an opportunity to finish layout after relaxation.
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual std::optional< MCFixupKind > getFixupKind(StringRef Name) const
Map a relocation name used in .reloc to a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
virtual bool allowAutoPadding() const
Return true if this target might automatically pad instructions and thus need to emit padding enable/...
MCAsmBackend & getBackend() const
Represents required padding such that a particular other set of fragments does not cross a particular...
void setLastFragment(const MCFragment *F)
MCCodeEmitter - Generic instruction encoding interface.
Context object for machine code objects.
bool emitCompactUnwindNonCanonical() const
Fragment for data and encoded instructions.
void setContents(ArrayRef< char > C)
SmallVectorImpl< MCFixup > & getFixups()
SmallVectorImpl< char > & getContents()
const MCSubtargetInfo * getSubtargetInfo() const
Retrieve the MCSubTargetInfo in effect when the instruction was encoded.
Base class for the full range of assembler expressions which are needed for parsing.
@ SymbolRef
References to labels and assigned expressions.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
MCFragment * getNext() const
Instances of this class represent a single low-level machine instruction.
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ", const MCRegisterInfo *RegInfo=nullptr) const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
unsigned getOpcode() const
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Streaming object file generation interface.
MCAssembler & getAssembler()
void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override
Emit the given Instruction into the current section.
MCRegister getReg() const
Returns the register number.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
bool getAllowAutoPadding() const
const MCInst & getInst() const
void setInst(const MCInst &Value)
Instances of this class represent a uniqued identifier for a section in the current translation unit.
void ensureMinAlignment(Align MinAlignment)
Makes sure that Alignment is at least MinAlignment.
void setHasLayout(bool Value)
Streaming machine code generation interface.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
This represents an "assembler immediate".
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isX32() const
Tests whether the target is X32.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
OSType getOS() const
Get the parsed operating system type of this triple.
ArchType getArch() const
Get the parsed architecture type of this triple.
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
bool isUEFI() const
Tests whether the OS is UEFI.
bool isOSWindows() const
Tests whether the OS is Windows.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
std::pair< iterator, bool > insert(const ValueT &V)
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & write(unsigned char C)
A raw_ostream that writes to an SmallVector or SmallString.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CompactUnwindEncodings
Compact unwind encoding values.
Expected< uint32_t > getCPUSubType(const Triple &T)
Expected< uint32_t > getCPUType(const Triple &T)
Reg
All possible values of the reg field in the ModR/M byte.
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
@ RawFrmMemOffs
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
bool isPrefix(uint64_t TSFlags)
int getMemoryOperandNo(uint64_t TSFlags)
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
void emitPrefix(MCCodeEmitter &MCE, const MCInst &MI, SmallVectorImpl< char > &CB, const MCSubtargetInfo &STI)
void emitInstruction(MCObjectStreamer &, const MCInst &Inst, const MCSubtargetInfo &STI)
FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion(unsigned Opcode)
AlignBranchBoundaryKind
Defines the possible values of the branch boundary alignment mask.
SecondMacroFusionInstKind
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(MCRegister Reg)
Given a segment register, return the encoding of the segment override prefix for it.
unsigned getOpcodeForLongImmediateForm(unsigned Opcode)
bool isMacroFused(FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind)
@ reloc_global_offset_table8
@ reloc_riprel_4byte_movq_load_rex2
@ reloc_signed_4byte_relax
@ reloc_branch_4byte_pcrel
@ reloc_riprel_4byte_relax
@ reloc_riprel_4byte_relax_evex
@ reloc_riprel_4byte_relax_rex
@ reloc_global_offset_table
@ reloc_riprel_4byte_movq_load
@ reloc_riprel_4byte_relax_rex2
initializer< Ty > init(const Ty &Val)
LocationClass< Ty > location(Ty &L)
NodeAddr< CodeNode * > Code
This is an optimization pass for GlobalISel generic memory operations.
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createX86WinCOFFObjectWriter(bool Is64Bit)
Construct an X86 Win COFF object writer.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MCStreamer * createX86ELFStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&MOW, std::unique_ptr< MCCodeEmitter > &&MCE)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_PCRel_4
A four-byte pc relative fixup.
@ FK_PCRel_2
A two-byte pc relative fixup.
@ FK_SecRel_2
A two-byte section relative fixup.
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
@ FK_Data_8
A eight-byte fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_SecRel_8
A eight-byte section relative fixup.
@ FK_PCRel_8
A eight-byte pc relative fixup.
@ FK_SecRel_4
A four-byte section relative fixup.
@ FK_PCRel_1
A one-byte pc relative fixup.
@ FK_SecRel_1
A one-byte section relative fixup.
@ FK_Data_2
A two-byte fixup.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
std::unique_ptr< MCObjectTargetWriter > createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an X86 Mach-O object writer.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
std::unique_ptr< MCObjectTargetWriter > createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine)
Construct an X86 ELF object writer.
Align assumeAligned(uint64_t Value)
Treats the value 0 as a 1, so Align is always at least 1.
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Implement std::hash so that hash_code can be used in STL containers.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Description of the encoding of one expression Op.
const MCSymbol * Personality
std::vector< MCCFIInstruction > Instructions
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...