42class X86AlignBranchKind {
44 uint8_t AlignBranchKind = 0;
47 void operator=(
const std::string &Val) {
52 for (
auto BranchType : BranchTypes) {
53 if (BranchType ==
"fused")
55 else if (BranchType ==
"jcc")
57 else if (BranchType ==
"jmp")
59 else if (BranchType ==
"call")
61 else if (BranchType ==
"ret")
63 else if (BranchType ==
"indirect")
67 <<
" to -x86-align-branch=; each element must be one of: fused, "
68 "jcc, jmp, call, ret, indirect.(plus separated)\n";
73 operator uint8_t()
const {
return AlignBranchKind; }
77X86AlignBranchKind X86AlignBranchKindLoc;
80 "x86-align-branch-boundary",
cl::init(0),
82 "Control how the assembler should align branches with NOP. If the "
83 "boundary's size is not 0, it should be a power of 2 and no less "
84 "than 32. Branches will be aligned to prevent from being across or "
85 "against the boundary of specified size. The default value 0 does not "
91 "Specify types of branches to align (plus separated list of types):"
92 "\njcc indicates conditional jumps"
93 "\nfused indicates fused conditional jumps"
94 "\njmp indicates direct unconditional jumps"
95 "\ncall indicates direct and indirect calls"
96 "\nret indicates rets"
97 "\nindirect indicates indirect unconditional jumps"),
101 "x86-branches-within-32B-boundaries",
cl::init(
false),
103 "Align selected instructions to mitigate negative performance impact "
104 "of Intel's micro code update for errata skx102. May break "
105 "assumptions about labels corresponding to particular instructions, "
106 "and should be used with caution."));
109 "x86-pad-max-prefix-size",
cl::init(0),
110 cl::desc(
"Maximum number of prefixes to use for padding"));
114 cl::desc(
"Pad previous instructions to implement align directives"));
118 cl::desc(
"Pad previous instructions to implement branch alignment"));
122 std::unique_ptr<const MCInstrInfo> MCII;
123 X86AlignBranchKind AlignBranchType;
125 unsigned TargetPrefixMax = 0;
129 std::pair<MCFragment *, size_t> PrevInstPosition;
130 bool CanPadInst =
false;
132 uint8_t determinePaddingPrefix(
const MCInst &Inst)
const;
134 bool needAlign(
const MCInst &Inst)
const;
142 if (X86AlignBranchWithin32BBoundaries) {
153 if (X86AlignBranchBoundary.getNumOccurrences())
155 if (X86AlignBranch.getNumOccurrences())
156 AlignBranchType = X86AlignBranchKindLoc;
157 if (X86PadMaxPrefixSize.getNumOccurrences())
158 TargetPrefixMax = X86PadMaxPrefixSize;
195 unsigned &RemainingSize)
const;
198 unsigned &RemainingSize)
const;
201 unsigned &RemainingSize)
const;
213 return Opcode == X86::JCC_1 || Opcode == X86::JMP_1;
217 bool Is16BitMode =
false) {
222 return (Is16BitMode) ? X86::JCC_2 : X86::JCC_4;
224 return (Is16BitMode) ? X86::JMP_2 : X86::JMP_4;
229 unsigned Opcode =
MI.getOpcode();
236 unsigned Opcode =
MI.getOpcode();
243 MI.getOperand(
Desc.getNumOperands() - 1).getImm());
251 return classifySecondCondCodeInMacroFusion(
CC);
256 unsigned Opcode =
MI.getOpcode();
261 if (MemoryOperand < 0)
264 unsigned BaseReg =
MI.getOperand(BaseRegNum).getReg();
265 return (BaseReg == X86::RIP);
281 return FIK != X86::FirstMacroFusionInstKind::Invalid;
293uint8_t X86AsmBackend::determinePaddingPrefix(
const MCInst &Inst)
const {
295 "Prefixes can be added only in 32-bit or 64-bit mode.");
301 if (MemoryOperand != -1)
304 unsigned SegmentReg = 0;
305 if (MemoryOperand >= 0) {
338 if (MemoryOperand >= 0) {
341 if (BaseReg == X86::ESP || BaseReg == X86::EBP)
348bool X86AsmBackend::isMacroFused(
const MCInst &Cmp,
const MCInst &Jcc)
const {
363 for (
auto &Operand :
MI) {
364 if (!Operand.isExpr())
366 const MCExpr &Expr = *Operand.getExpr();
374bool X86AsmBackend::allowAutoPadding()
const {
378bool X86AsmBackend::allowEnhancedRelaxation()
const {
379 return allowAutoPadding() && TargetPrefixMax != 0 && X86PadForBranchAlign;
406 const std::pair<MCFragment *, size_t> &PrevInstPosition) {
411 for (; isa_and_nonnull<MCDataFragment>(
F);
F =
F->getPrevNode())
412 if (cast<MCDataFragment>(
F)->getContents().size() != 0)
425 if (
auto *
DF = dyn_cast_or_null<MCDataFragment>(
F))
426 return DF != PrevInstPosition.first ||
427 DF->getContents().size() != PrevInstPosition.second;
434 if (!
F || !
F->hasInstructions())
437 switch (
F->getKind()) {
441 return cast<MCDataFragment>(*F).getContents().size();
443 return cast<MCRelaxableFragment>(*F).getContents().size();
445 return cast<MCCompactEncodedInstFragment>(*F).getContents().size();
481 if (!
OS.getAllowAutoPadding())
483 assert(allowAutoPadding() &&
"incorrect initialization!");
486 if (!
OS.getCurrentSectionOnly()->getKind().isText())
490 if (
OS.getAssembler().isBundlingEnabled())
501bool X86AsmBackend::needAlign(
const MCInst &Inst)
const {
503 return (
Desc.isConditionalBranch() &&
505 (
Desc.isUnconditionalBranch() &&
509 (
Desc.isIndirectBranch() &&
516 CanPadInst = canPadInst(Inst,
OS);
518 if (!canPadBranches(
OS))
528 if (PendingBA &&
OS.getCurrentFragment()->getPrevNode() == PendingBA) {
563 if (
auto *
F = dyn_cast_or_null<MCRelaxableFragment>(CF))
564 F->setAllowAutoPadding(CanPadInst);
566 if (!canPadBranches(
OS))
569 if (!needAlign(Inst) || !PendingBA)
580 if (isa_and_nonnull<MCDataFragment>(CF))
588std::optional<MCFixupKind> X86AsmBackend::getFixupKind(
StringRef Name)
const {
593#define ELF_RELOC(X, Y) .Case(#X, Y)
594#include "llvm/BinaryFormat/ELFRelocs/x86_64.def"
596 .
Case(
"BFD_RELOC_NONE", ELF::R_X86_64_NONE)
597 .
Case(
"BFD_RELOC_8", ELF::R_X86_64_8)
598 .
Case(
"BFD_RELOC_16", ELF::R_X86_64_16)
599 .
Case(
"BFD_RELOC_32", ELF::R_X86_64_32)
600 .
Case(
"BFD_RELOC_64", ELF::R_X86_64_64)
604#define ELF_RELOC(X, Y) .Case(#X, Y)
605#include "llvm/BinaryFormat/ELFRelocs/i386.def"
607 .
Case(
"BFD_RELOC_NONE", ELF::R_386_NONE)
608 .
Case(
"BFD_RELOC_8", ELF::R_386_8)
609 .
Case(
"BFD_RELOC_16", ELF::R_386_16)
610 .
Case(
"BFD_RELOC_32", ELF::R_386_32)
626 {
"reloc_signed_4byte", 0, 32, 0},
627 {
"reloc_signed_4byte_relax", 0, 32, 0},
628 {
"reloc_global_offset_table", 0, 32, 0},
629 {
"reloc_global_offset_table8", 0, 64, 0},
647bool X86AsmBackend::shouldForceRelocation(
const MCAssembler &,
699 int64_t SignedValue =
static_cast<int64_t
>(
Value);
700 if ((
Target.isAbsolute() || IsResolved) &&
701 getFixupKindInfo(
Fixup.getKind()).Flags &
705 Asm.getContext().reportError(
706 Fixup.getLoc(),
"value of " +
Twine(SignedValue) +
707 " is too large for field of " +
Twine(
Size) +
708 ((
Size == 1) ?
" byte." :
" bytes."));
715 "Value does not fit in the Fixup field");
718 for (
unsigned i = 0; i !=
Size; ++i)
722bool X86AsmBackend::mayNeedRelaxation(
const MCInst &
MI,
724 unsigned Opcode =
MI.getOpcode();
727 MI.getOperand(
MI.getNumOperands() - 1).isExpr());
730bool X86AsmBackend::fixupNeedsRelaxation(
const MCFixup &
Fixup,
735 return !isInt<8>(
Value);
740void X86AsmBackend::relaxInstruction(
MCInst &Inst,
743 bool Is16BitMode = STI.
hasFeature(X86::Is16Bit);
759 unsigned &RemainingSize)
const {
773 const unsigned MaxPossiblePad = std::min(15 - OldSize, RemainingSize);
774 const unsigned RemainingPrefixSize = [&]() ->
unsigned {
777 assert(
Code.size() < 15 &&
"The number of prefixes must be less than 15.");
784 unsigned ExistingPrefixSize =
Code.size();
785 if (TargetPrefixMax <= ExistingPrefixSize)
787 return TargetPrefixMax - ExistingPrefixSize;
789 const unsigned PrefixBytesToAdd =
790 std::min(MaxPossiblePad, RemainingPrefixSize);
791 if (PrefixBytesToAdd == 0)
797 Code.append(PrefixBytesToAdd, Prefix);
803 F.setOffset(
F.getOffset() + PrefixBytesToAdd);
806 RemainingSize -= PrefixBytesToAdd;
812 unsigned &RemainingSize)
const {
825 const unsigned NewSize =
Code.size();
826 assert(NewSize >= OldSize &&
"size decrease during relaxation?");
827 unsigned Delta = NewSize - OldSize;
828 if (Delta > RemainingSize)
833 RemainingSize -= Delta;
839 unsigned &RemainingSize)
const {
840 bool Changed =
false;
841 if (RemainingSize != 0)
842 Changed |= padInstructionViaRelaxation(RF,
Emitter, RemainingSize);
843 if (RemainingSize != 0)
844 Changed |= padInstructionViaPrefix(RF,
Emitter, RemainingSize);
848void X86AsmBackend::finishLayout(
MCAssembler const &Asm,
856 if (!X86PadForAlign && !X86PadForBranchAlign)
864 LabeledFragments.
insert(S.getFragment(
false));
874 if (LabeledFragments.
count(&
F))
883 auto &RF = cast<MCRelaxableFragment>(*
I);
889 switch (
F.getKind()) {
893 return X86PadForAlign;
895 return X86PadForBranchAlign;
907 const uint64_t OrigSize =
Asm.computeFragmentSize(Layout,
F);
914 unsigned RemainingSize = OrigSize;
915 while (!Relaxable.
empty() && RemainingSize != 0) {
920 if (padInstructionEncoding(RF,
Asm.getEmitter(), RemainingSize))
921 FirstChangedFragment = &RF;
934 if (FirstChangedFragment) {
943 cast<MCBoundaryAlignFragment>(
F).setSize(RemainingSize);
947 const uint64_t FinalSize =
Asm.computeFragmentSize(Layout,
F);
948 assert(OrigOffset + OrigSize == FinalOffset + FinalSize &&
949 "can't move start of next fragment!");
950 assert(FinalSize == RemainingSize &&
"inconsistent size computation?");
956 if (
auto *BF = dyn_cast<MCBoundaryAlignFragment>(&
F)) {
957 const MCFragment *LastFragment = BF->getLastFragment();
960 while (&*
I != LastFragment)
967 for (
unsigned int i = 0, n = Layout.
getSectionOrder().size(); i != n; ++i) {
970 Asm.computeFragmentSize(Layout, *
Section.getFragmentList().rbegin());
974unsigned X86AsmBackend::getMaximumNopSize(
const MCSubtargetInfo &STI)
const {
996 static const char Nops32Bit[10][11] = {
1006 "\x0f\x1f\x44\x00\x00",
1008 "\x66\x0f\x1f\x44\x00\x00",
1010 "\x0f\x1f\x80\x00\x00\x00\x00",
1012 "\x0f\x1f\x84\x00\x00\x00\x00\x00",
1014 "\x66\x0f\x1f\x84\x00\x00\x00\x00\x00",
1016 "\x66\x2e\x0f\x1f\x84\x00\x00\x00\x00\x00",
1020 static const char Nops16Bit[4][11] = {
1031 const char(*Nops)[11] =
1032 STI->
hasFeature(X86::Is16Bit) ? Nops16Bit : Nops32Bit;
1039 const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength);
1040 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
1041 for (uint8_t i = 0; i < Prefixes; i++)
1043 const uint8_t Rest = ThisNopLength - Prefixes;
1045 OS.
write(Nops[Rest - 1], Rest);
1046 Count -= ThisNopLength;
1047 }
while (Count != 0);
1056class ELFX86AsmBackend :
public X86AsmBackend {
1060 : X86AsmBackend(
T, STI), OSABI(OSABI) {}
1063class ELFX86_32AsmBackend :
public ELFX86AsmBackend {
1065 ELFX86_32AsmBackend(
const Target &
T, uint8_t OSABI,
1067 : ELFX86AsmBackend(
T, OSABI, STI) {}
1069 std::unique_ptr<MCObjectTargetWriter>
1070 createObjectTargetWriter()
const override {
1075class ELFX86_X32AsmBackend :
public ELFX86AsmBackend {
1077 ELFX86_X32AsmBackend(
const Target &
T, uint8_t OSABI,
1079 : ELFX86AsmBackend(
T, OSABI, STI) {}
1081 std::unique_ptr<MCObjectTargetWriter>
1082 createObjectTargetWriter()
const override {
1088class ELFX86_IAMCUAsmBackend :
public ELFX86AsmBackend {
1090 ELFX86_IAMCUAsmBackend(
const Target &
T, uint8_t OSABI,
1092 : ELFX86AsmBackend(
T, OSABI, STI) {}
1094 std::unique_ptr<MCObjectTargetWriter>
1095 createObjectTargetWriter()
const override {
1101class ELFX86_64AsmBackend :
public ELFX86AsmBackend {
1103 ELFX86_64AsmBackend(
const Target &
T, uint8_t OSABI,
1105 : ELFX86AsmBackend(
T, OSABI, STI) {}
1107 std::unique_ptr<MCObjectTargetWriter>
1108 createObjectTargetWriter()
const override {
1113class WindowsX86AsmBackend :
public X86AsmBackend {
1119 : X86AsmBackend(
T, STI)
1123 std::optional<MCFixupKind> getFixupKind(
StringRef Name)
const override {
1131 std::unique_ptr<MCObjectTargetWriter>
1132 createObjectTargetWriter()
const override {
1143 UNWIND_MODE_BP_FRAME = 0x01000000,
1146 UNWIND_MODE_STACK_IMMD = 0x02000000,
1149 UNWIND_MODE_STACK_IND = 0x03000000,
1152 UNWIND_MODE_DWARF = 0x04000000,
1155 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
1158 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
1163class DarwinX86AsmBackend :
public X86AsmBackend {
1167 enum { CU_NUM_SAVED_REGS = 6 };
1169 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
1173 unsigned OffsetSize;
1174 unsigned MoveInstrSize;
1175 unsigned StackDivide;
1178 unsigned PushInstrSize(
unsigned Reg)
const {
1201 int getCompactUnwindRegNum(
unsigned Reg)
const {
1202 static const MCPhysReg CU32BitRegs[7] = {
1203 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
1205 static const MCPhysReg CU64BitRegs[] = {
1206 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
1208 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
1209 for (
int Idx = 1; *CURegs; ++CURegs, ++
Idx)
1218 uint32_t encodeCompactUnwindRegistersWithFrame()
const {
1223 for (
int i = 0,
Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
1224 unsigned Reg = SavedRegs[i];
1225 if (Reg == 0)
break;
1227 int CURegNum = getCompactUnwindRegNum(Reg);
1228 if (CURegNum == -1)
return ~0
U;
1232 RegEnc |= (CURegNum & 0x7) << (
Idx++ * 3);
1235 assert((RegEnc & 0x3FFFF) == RegEnc &&
1236 "Invalid compact register encoding!");
1243 uint32_t encodeCompactUnwindRegistersWithoutFrame(
unsigned RegCount)
const {
1257 for (
unsigned i = 0; i < RegCount; ++i) {
1258 int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
1259 if (CUReg == -1)
return ~0
U;
1260 SavedRegs[i] = CUReg;
1264 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
1266 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
1267 for (
unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
1268 unsigned Countless = 0;
1269 for (
unsigned j = CU_NUM_SAVED_REGS - RegCount;
j < i; ++
j)
1270 if (SavedRegs[j] < SavedRegs[i])
1273 RenumRegs[i] = SavedRegs[i] - Countless - 1;
1280 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
1281 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
1285 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
1286 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
1290 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
1291 + 3 * RenumRegs[4] + RenumRegs[5];
1294 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
1298 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
1301 permutationEncoding |= RenumRegs[5];
1305 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
1306 "Invalid compact register encoding!");
1307 return permutationEncoding;
1313 : X86AsmBackend(
T, STI),
MRI(
MRI),
TT(STI.getTargetTriple()),
1314 Is64Bit(
TT.isArch64Bit()) {
1315 memset(SavedRegs, 0,
sizeof(SavedRegs));
1316 OffsetSize = Is64Bit ? 8 : 4;
1317 MoveInstrSize = Is64Bit ? 3 : 2;
1318 StackDivide = Is64Bit ? 8 : 4;
1321 std::unique_ptr<MCObjectTargetWriter>
1322 createObjectTargetWriter()
const override {
1333 if (Instrs.
empty())
return 0;
1334 if (!isDarwinCanonicalPersonality(FI->
Personality) &&
1336 return CU::UNWIND_MODE_DWARF;
1339 unsigned SavedRegIdx = 0;
1340 memset(SavedRegs, 0,
sizeof(SavedRegs));
1345 uint32_t CompactUnwindEncoding = 0;
1347 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
1348 unsigned InstrOffset = 0;
1349 unsigned StackAdjust = 0;
1350 unsigned StackSize = 0;
1351 int MinAbsOffset = std::numeric_limits<int>::max();
1354 switch (Inst.getOperation()) {
1358 return CU::UNWIND_MODE_DWARF;
1370 if (*
MRI.getLLVMRegNum(Inst.getRegister(),
true) !=
1371 (Is64Bit ? X86::RBP : X86::EBP))
1372 return CU::UNWIND_MODE_DWARF;
1375 memset(SavedRegs, 0,
sizeof(SavedRegs));
1378 MinAbsOffset = std::numeric_limits<int>::max();
1379 InstrOffset += MoveInstrSize;
1397 StackSize = Inst.getOffset() / StackDivide;
1413 if (SavedRegIdx == CU_NUM_SAVED_REGS)
1416 return CU::UNWIND_MODE_DWARF;
1418 unsigned Reg = *
MRI.getLLVMRegNum(Inst.getRegister(),
true);
1419 SavedRegs[SavedRegIdx++] =
Reg;
1420 StackAdjust += OffsetSize;
1421 MinAbsOffset = std::min(MinAbsOffset,
abs(Inst.getOffset()));
1422 InstrOffset += PushInstrSize(Reg);
1428 StackAdjust /= StackDivide;
1431 if ((StackAdjust & 0xFF) != StackAdjust)
1433 return CU::UNWIND_MODE_DWARF;
1437 if (SavedRegIdx != 0 && MinAbsOffset != 3 * (
int)OffsetSize)
1438 return CU::UNWIND_MODE_DWARF;
1441 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
1442 if (RegEnc == ~0U)
return CU::UNWIND_MODE_DWARF;
1444 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
1445 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
1446 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
1448 SubtractInstrIdx += InstrOffset;
1451 if ((StackSize & 0xFF) == StackSize) {
1453 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
1456 CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
1458 if ((StackAdjust & 0x7) != StackAdjust)
1460 return CU::UNWIND_MODE_DWARF;
1463 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
1467 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
1470 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
1474 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
1475 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
1479 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
1480 if (RegEnc == ~0U)
return CU::UNWIND_MODE_DWARF;
1483 CompactUnwindEncoding |=
1484 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
1487 return CompactUnwindEncoding;
1499 return new DarwinX86AsmBackend(
T,
MRI, STI);
1502 return new WindowsX86AsmBackend(
T,
false, STI);
1507 return new ELFX86_IAMCUAsmBackend(
T, OSABI, STI);
1509 return new ELFX86_32AsmBackend(
T, OSABI, STI);
1518 return new DarwinX86AsmBackend(
T,
MRI, STI);
1521 return new WindowsX86AsmBackend(
T,
true, STI);
1523 if (TheTriple.
isUEFI()) {
1525 "Only COFF format is supported in UEFI environment.");
1526 return new WindowsX86AsmBackend(
T,
true, STI);
1531 if (TheTriple.
isX32())
1532 return new ELFX86_X32AsmBackend(
T, OSABI, STI);
1533 return new ELFX86_64AsmBackend(
T, OSABI, STI);
unsigned const MachineRegisterInfo * MRI
dxil DXContainer Global Emitter
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static MCInstrInfo * createMCInstrInfo()
static unsigned getRelaxedOpcodeBranch(unsigned Opcode, bool Is16BitMode=false)
static X86::SecondMacroFusionInstKind classifySecondInstInMacroFusion(const MCInst &MI, const MCInstrInfo &MCII)
static size_t getSizeForInstFragment(const MCFragment *F)
static bool isRIPRelative(const MCInst &MI, const MCInstrInfo &MCII)
Check if the instruction uses RIP relative addressing.
static bool isRightAfterData(MCFragment *CurrentFragment, const std::pair< MCFragment *, size_t > &PrevInstPosition)
Check if the instruction to be emitted is right after any data.
static bool isPrefix(const MCInst &MI, const MCInstrInfo &MCII)
Check if the instruction is a prefix.
static bool hasInterruptDelaySlot(const MCInst &Inst)
X86 has certain instructions which enable interrupts exactly one instruction after the instruction wh...
static bool isFirstMacroFusibleInst(const MCInst &Inst, const MCInstrInfo &MCII)
Check if the instruction is valid as the first instruction in macro fusion.
static X86::CondCode getCondFromBranch(const MCInst &MI, const MCInstrInfo &MCII)
static unsigned getRelaxedOpcode(const MCInst &MI, bool Is16BitMode)
static unsigned getFixupKindSize(unsigned Kind)
static bool isRelaxableBranch(unsigned Opcode)
static bool hasVariantSymbol(const MCInst &MI)
Check if the instruction has a variant symbol operand.
static bool is64Bit(const char *name)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool empty() const
empty - Check if the array is empty.
Implements a dense probed hash-table based set.
Generic interface to target specific assembler backends.
virtual bool allowEnhancedRelaxation() const
Return true if this target allows an unrelaxable instruction to be emitted into RelaxableFragment and...
virtual unsigned getMaximumNopSize(const MCSubtargetInfo &STI) const
Returns the maximum size of a nop in bytes on this target.
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
virtual bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const
Check whether the given instruction may need relaxation.
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const =0
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual void finishLayout(MCAssembler const &Asm, MCAsmLayout &Layout) const
Give backend an opportunity to finish layout after relaxation.
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target)
Hook to check if a relocation is needed for some target specific reason.
virtual void emitInstructionEnd(MCObjectStreamer &OS, const MCInst &Inst)
virtual void emitInstructionBegin(MCObjectStreamer &OS, const MCInst &Inst, const MCSubtargetInfo &STI)
Give the target a chance to manipulate state related to instruction alignment (e.g.
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual std::optional< MCFixupKind > getFixupKind(StringRef Name) const
Map a relocation name used in .reloc to a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
virtual bool allowAutoPadding() const
Return true if this target might automatically pad instructions and thus need to emit padding enable/...
Encapsulates the layout of an assembly file at a particular point in time.
void invalidateFragmentsFrom(MCFragment *F)
Invalidate the fragments starting with F because it has been resized.
llvm::SmallVectorImpl< MCSection * > & getSectionOrder()
uint64_t getFragmentOffset(const MCFragment *F) const
Get the offset of the given fragment inside its containing section.
Represents required padding such that a particular other set of fragments does not cross a particular...
void setLastFragment(const MCFragment *F)
MCCodeEmitter - Generic instruction encoding interface.
Context object for machine code objects.
bool emitCompactUnwindNonCanonical() const
Fragment for data and encoded instructions.
SmallVectorImpl< char > & getContents()
SmallVectorImpl< MCFixup > & getFixups()
const MCSubtargetInfo * getSubtargetInfo() const
Retrieve the MCSubTargetInfo in effect when the instruction was encoded.
Base class for the full range of assembler expressions which are needed for parsing.
@ SymbolRef
References to labels and assigned expressions.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Instances of this class represent a single low-level machine instruction.
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ", const MCRegisterInfo *RegInfo=nullptr) const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
unsigned getOpcode() const
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Streaming object file generation interface.
unsigned getReg() const
Returns the register number.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
bool getAllowAutoPadding() const
const MCInst & getInst() const
void setInst(const MCInst &Value)
Instances of this class represent a uniqued identifier for a section in the current translation unit.
void ensureMinAlignment(Align MinAlignment)
Makes sure that Alignment is at least MinAlignment.
SectionKind getKind() const
FragmentListType::iterator iterator
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
This represents an "assembler immediate".
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isX32() const
Tests whether the target is X32.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
OSType getOS() const
Get the parsed operating system type of this triple.
ArchType getArch() const
Get the parsed architecture type of this triple.
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
bool isUEFI() const
Tests whether the OS is UEFI.
bool isOSWindows() const
Tests whether the OS is Windows.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
std::pair< iterator, bool > insert(const ValueT &V)
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & write(unsigned char C)
A raw_ostream that writes to an SmallVector or SmallString.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CompactUnwindEncodings
Compact unwind encoding values.
Expected< uint32_t > getCPUSubType(const Triple &T)
Expected< uint32_t > getCPUType(const Triple &T)
Reg
All possible values of the reg field in the ModR/M byte.
bool isPrefix(uint64_t TSFlags)
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
@ RawFrmMemOffs
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
int getMemoryOperandNo(uint64_t TSFlags)
The function returns the MCInst operand # for the first field of the memory operand.
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion(unsigned Opcode)
AlignBranchBoundaryKind
Defines the possible values of the branch boundary alignment mask.
SecondMacroFusionInstKind
unsigned getOpcodeForLongImmediateForm(unsigned Opcode)
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(unsigned Reg)
Given a segment register, return the encoding of the segment override prefix for it.
bool isMacroFused(FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind)
@ reloc_global_offset_table8
@ reloc_signed_4byte_relax
@ reloc_branch_4byte_pcrel
@ reloc_riprel_4byte_relax
@ reloc_riprel_4byte_relax_rex
@ reloc_global_offset_table
@ reloc_riprel_4byte_movq_load
initializer< Ty > init(const Ty &Val)
LocationClass< Ty > location(Ty &L)
NodeAddr< CodeNode * > Code
This is an optimization pass for GlobalISel generic memory operations.
APFloat abs(APFloat X)
Returns the absolute value of the argument.
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createX86WinCOFFObjectWriter(bool Is64Bit)
Construct an X86 Win COFF object writer.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_PCRel_4
A four-byte pc relative fixup.
@ FK_PCRel_2
A two-byte pc relative fixup.
@ FK_SecRel_2
A two-byte section relative fixup.
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
@ FK_Data_8
A eight-byte fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_SecRel_8
A eight-byte section relative fixup.
@ FK_PCRel_8
A eight-byte pc relative fixup.
@ FK_SecRel_4
A four-byte section relative fixup.
@ FK_PCRel_1
A one-byte pc relative fixup.
@ FK_SecRel_1
A one-byte section relative fixup.
@ FK_Data_2
A two-byte fixup.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
std::unique_ptr< MCObjectTargetWriter > createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an X86 Mach-O object writer.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
std::unique_ptr< MCObjectTargetWriter > createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine)
Construct an X86 ELF object writer.
Align assumeAligned(uint64_t Value)
Treats the value 0 as a 1, so Align is always at least 1.
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Description of the encoding of one expression Op.
const MCSymbol * Personality
std::vector< MCCFIInstruction > Instructions
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...