42class X86AlignBranchKind {
44 uint8_t AlignBranchKind = 0;
47 void operator=(
const std::string &Val) {
52 for (
auto BranchType : BranchTypes) {
53 if (BranchType ==
"fused")
55 else if (BranchType ==
"jcc")
57 else if (BranchType ==
"jmp")
59 else if (BranchType ==
"call")
61 else if (BranchType ==
"ret")
63 else if (BranchType ==
"indirect")
67 <<
" to -x86-align-branch=; each element must be one of: fused, "
68 "jcc, jmp, call, ret, indirect.(plus separated)\n";
73 operator uint8_t()
const {
return AlignBranchKind; }
77X86AlignBranchKind X86AlignBranchKindLoc;
80 "x86-align-branch-boundary",
cl::init(0),
82 "Control how the assembler should align branches with NOP. If the "
83 "boundary's size is not 0, it should be a power of 2 and no less "
84 "than 32. Branches will be aligned to prevent from being across or "
85 "against the boundary of specified size. The default value 0 does not "
91 "Specify types of branches to align (plus separated list of types):"
92 "\njcc indicates conditional jumps"
93 "\nfused indicates fused conditional jumps"
94 "\njmp indicates direct unconditional jumps"
95 "\ncall indicates direct and indirect calls"
96 "\nret indicates rets"
97 "\nindirect indicates indirect unconditional jumps"),
101 "x86-branches-within-32B-boundaries",
cl::init(
false),
103 "Align selected instructions to mitigate negative performance impact "
104 "of Intel's micro code update for errata skx102. May break "
105 "assumptions about labels corresponding to particular instructions, "
106 "and should be used with caution."));
109 "x86-pad-max-prefix-size",
cl::init(0),
110 cl::desc(
"Maximum number of prefixes to use for padding"));
114 cl::desc(
"Pad previous instructions to implement align directives"));
118 cl::desc(
"Pad previous instructions to implement branch alignment"));
122 std::unique_ptr<const MCInstrInfo> MCII;
123 X86AlignBranchKind AlignBranchType;
125 unsigned TargetPrefixMax = 0;
128 unsigned PrevInstOpcode = 0;
130 std::pair<MCFragment *, size_t> PrevInstPosition;
131 bool IsRightAfterData =
false;
133 uint8_t determinePaddingPrefix(
const MCInst &Inst)
const;
135 bool needAlign(
const MCInst &Inst)
const;
143 if (X86AlignBranchWithin32BBoundaries) {
154 if (X86AlignBranchBoundary.getNumOccurrences())
156 if (X86AlignBranch.getNumOccurrences())
157 AlignBranchType = X86AlignBranchKindLoc;
158 if (X86PadMaxPrefixSize.getNumOccurrences())
159 TargetPrefixMax = X86PadMaxPrefixSize;
196 unsigned &RemainingSize)
const;
199 unsigned &RemainingSize)
const;
202 unsigned &RemainingSize)
const;
214 return Opcode == X86::JCC_1 || Opcode == X86::JMP_1;
218 bool Is16BitMode =
false) {
223 return (Is16BitMode) ? X86::JCC_2 : X86::JCC_4;
225 return (Is16BitMode) ? X86::JMP_2 : X86::JMP_4;
230 unsigned Opcode =
MI.getOpcode();
237 unsigned Opcode =
MI.getOpcode();
244 MI.getOperand(
Desc.getNumOperands() - 1).getImm());
252 return classifySecondCondCodeInMacroFusion(
CC);
257 unsigned Opcode =
MI.getOpcode();
262 if (MemoryOperand < 0)
265 unsigned BaseReg =
MI.getOperand(BaseRegNum).getReg();
266 return (BaseReg == X86::RIP);
282 return FIK != X86::FirstMacroFusionInstKind::Invalid;
294uint8_t X86AsmBackend::determinePaddingPrefix(
const MCInst &Inst)
const {
296 "Prefixes can be added only in 32-bit or 64-bit mode.");
302 if (MemoryOperand != -1)
305 unsigned SegmentReg = 0;
306 if (MemoryOperand >= 0) {
339 if (MemoryOperand >= 0) {
342 if (BaseReg == X86::ESP || BaseReg == X86::EBP)
349bool X86AsmBackend::isMacroFused(
const MCInst &Cmp,
const MCInst &Jcc)
const {
364 for (
auto &Operand :
MI) {
365 if (!Operand.isExpr())
367 const MCExpr &Expr = *Operand.getExpr();
375bool X86AsmBackend::allowAutoPadding()
const {
379bool X86AsmBackend::allowEnhancedRelaxation()
const {
380 return allowAutoPadding() && TargetPrefixMax != 0 && X86PadForBranchAlign;
387 switch (InstOpcode) {
407 const std::pair<MCFragment *, size_t> &PrevInstPosition) {
420 if (
auto *
DF = dyn_cast_or_null<MCDataFragment>(
F))
421 return DF->getContents().size() &&
422 (
DF != PrevInstPosition.first ||
423 DF->getContents().size() != PrevInstPosition.second);
430 if (!
F || !
F->hasInstructions())
433 switch (
F->getKind()) {
437 return cast<MCDataFragment>(*F).getContents().size();
439 return cast<MCRelaxableFragment>(*F).getContents().size();
456 if (
isPrefix(PrevInstOpcode, *MCII))
466 if (IsRightAfterData)
475 if (!
OS.getAllowAutoPadding())
477 assert(allowAutoPadding() &&
"incorrect initialization!");
480 if (!
OS.getCurrentSectionOnly()->isText())
484 if (
OS.getAssembler().isBundlingEnabled())
495bool X86AsmBackend::needAlign(
const MCInst &Inst)
const {
497 return (
Desc.isConditionalBranch() &&
499 (
Desc.isUnconditionalBranch() &&
503 (
Desc.isIndirectBranch() &&
515 if (!canPadBranches(
OS))
527 if (!canPadInst(Inst,
OS))
530 if (PendingBA && PendingBA->
getNext() ==
OS.getCurrentFragment()) {
558 OS.insert(PendingBA);
566 if (
auto *
F = dyn_cast_or_null<MCRelaxableFragment>(CF))
567 F->setAllowAutoPadding(canPadInst(Inst,
OS));
573 if (!canPadBranches(
OS))
579 if (!needAlign(Inst) || !PendingBA)
590 if (isa_and_nonnull<MCDataFragment>(CF))
598std::optional<MCFixupKind> X86AsmBackend::getFixupKind(
StringRef Name)
const {
603#define ELF_RELOC(X, Y) .Case(#X, Y)
604#include "llvm/BinaryFormat/ELFRelocs/x86_64.def"
606 .
Case(
"BFD_RELOC_NONE", ELF::R_X86_64_NONE)
607 .
Case(
"BFD_RELOC_8", ELF::R_X86_64_8)
608 .
Case(
"BFD_RELOC_16", ELF::R_X86_64_16)
609 .
Case(
"BFD_RELOC_32", ELF::R_X86_64_32)
610 .
Case(
"BFD_RELOC_64", ELF::R_X86_64_64)
614#define ELF_RELOC(X, Y) .Case(#X, Y)
615#include "llvm/BinaryFormat/ELFRelocs/i386.def"
617 .
Case(
"BFD_RELOC_NONE", ELF::R_386_NONE)
618 .
Case(
"BFD_RELOC_8", ELF::R_386_8)
619 .
Case(
"BFD_RELOC_16", ELF::R_386_16)
620 .
Case(
"BFD_RELOC_32", ELF::R_386_32)
636 {
"reloc_signed_4byte", 0, 32, 0},
637 {
"reloc_signed_4byte_relax", 0, 32, 0},
638 {
"reloc_global_offset_table", 0, 32, 0},
639 {
"reloc_global_offset_table8", 0, 64, 0},
657bool X86AsmBackend::shouldForceRelocation(
const MCAssembler &,
707 assert(
Fixup.getOffset() +
Size <= Data.size() &&
"Invalid fixup offset!");
709 int64_t SignedValue =
static_cast<int64_t
>(
Value);
710 if ((
Target.isAbsolute() || IsResolved) &&
711 getFixupKindInfo(
Fixup.getKind()).Flags &
715 Asm.getContext().reportError(
716 Fixup.getLoc(),
"value of " +
Twine(SignedValue) +
717 " is too large for field of " +
Twine(
Size) +
718 ((
Size == 1) ?
" byte." :
" bytes."));
725 "Value does not fit in the Fixup field");
728 for (
unsigned i = 0; i !=
Size; ++i)
729 Data[
Fixup.getOffset() + i] = uint8_t(
Value >> (i * 8));
732bool X86AsmBackend::mayNeedRelaxation(
const MCInst &
MI,
734 unsigned Opcode =
MI.getOpcode();
735 unsigned SkipOperands = X86::isCCMPCC(Opcode) ? 2 : 0;
738 MI.getOperand(
MI.getNumOperands() - 1 - SkipOperands).isExpr());
741bool X86AsmBackend::fixupNeedsRelaxation(
const MCFixup &
Fixup,
744 return !isInt<8>(
Value);
749void X86AsmBackend::relaxInstruction(
MCInst &Inst,
752 bool Is16BitMode = STI.
hasFeature(X86::Is16Bit);
768 unsigned &RemainingSize)
const {
782 const unsigned MaxPossiblePad = std::min(15 - OldSize, RemainingSize);
783 const unsigned RemainingPrefixSize = [&]() ->
unsigned {
786 assert(
Code.size() < 15 &&
"The number of prefixes must be less than 15.");
793 unsigned ExistingPrefixSize =
Code.size();
794 if (TargetPrefixMax <= ExistingPrefixSize)
796 return TargetPrefixMax - ExistingPrefixSize;
798 const unsigned PrefixBytesToAdd =
799 std::min(MaxPossiblePad, RemainingPrefixSize);
800 if (PrefixBytesToAdd == 0)
806 Code.append(PrefixBytesToAdd, Prefix);
812 F.setOffset(
F.getOffset() + PrefixBytesToAdd);
815 RemainingSize -= PrefixBytesToAdd;
821 unsigned &RemainingSize)
const {
834 const unsigned NewSize =
Code.size();
835 assert(NewSize >= OldSize &&
"size decrease during relaxation?");
836 unsigned Delta = NewSize - OldSize;
837 if (Delta > RemainingSize)
842 RemainingSize -= Delta;
848 unsigned &RemainingSize)
const {
849 bool Changed =
false;
850 if (RemainingSize != 0)
851 Changed |= padInstructionViaRelaxation(RF,
Emitter, RemainingSize);
852 if (RemainingSize != 0)
853 Changed |= padInstructionViaPrefix(RF,
Emitter, RemainingSize);
857void X86AsmBackend::finishLayout(
MCAssembler const &Asm)
const {
864 if (!X86PadForAlign && !X86PadForBranchAlign)
872 LabeledFragments.
insert(S.getFragment(
false));
882 if (LabeledFragments.
count(&
F))
889 auto &RF = cast<MCRelaxableFragment>(*
I);
895 switch (
F.getKind()) {
899 return X86PadForAlign;
901 return X86PadForBranchAlign;
919 unsigned RemainingSize = OrigSize;
920 while (!Relaxable.
empty() && RemainingSize != 0) {
925 if (padInstructionEncoding(RF,
Asm.getEmitter(), RemainingSize))
941 cast<MCBoundaryAlignFragment>(
F).setSize(RemainingSize);
946 assert(OrigOffset + OrigSize == FinalOffset + FinalSize &&
947 "can't move start of next fragment!");
948 assert(FinalSize == RemainingSize &&
"inconsistent size computation?");
954 if (
auto *BF = dyn_cast<MCBoundaryAlignFragment>(&
F)) {
955 const MCFragment *LastFragment = BF->getLastFragment();
958 while (&*
I != LastFragment)
966 Asm.getFragmentOffset(*
Section.curFragList()->Tail);
967 Asm.computeFragmentSize(*
Section.curFragList()->Tail);
971unsigned X86AsmBackend::getMaximumNopSize(
const MCSubtargetInfo &STI)
const {
993 static const char Nops32Bit[10][11] = {
1003 "\x0f\x1f\x44\x00\x00",
1005 "\x66\x0f\x1f\x44\x00\x00",
1007 "\x0f\x1f\x80\x00\x00\x00\x00",
1009 "\x0f\x1f\x84\x00\x00\x00\x00\x00",
1011 "\x66\x0f\x1f\x84\x00\x00\x00\x00\x00",
1013 "\x66\x2e\x0f\x1f\x84\x00\x00\x00\x00\x00",
1017 static const char Nops16Bit[4][11] = {
1028 const char(*Nops)[11] =
1029 STI->
hasFeature(X86::Is16Bit) ? Nops16Bit : Nops32Bit;
1036 const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength);
1037 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
1038 for (uint8_t i = 0; i < Prefixes; i++)
1040 const uint8_t Rest = ThisNopLength - Prefixes;
1042 OS.
write(Nops[Rest - 1], Rest);
1043 Count -= ThisNopLength;
1044 }
while (Count != 0);
1053class ELFX86AsmBackend :
public X86AsmBackend {
1057 : X86AsmBackend(
T, STI), OSABI(OSABI) {}
1060class ELFX86_32AsmBackend :
public ELFX86AsmBackend {
1062 ELFX86_32AsmBackend(
const Target &
T, uint8_t OSABI,
1064 : ELFX86AsmBackend(
T, OSABI, STI) {}
1066 std::unique_ptr<MCObjectTargetWriter>
1067 createObjectTargetWriter()
const override {
1072class ELFX86_X32AsmBackend :
public ELFX86AsmBackend {
1074 ELFX86_X32AsmBackend(
const Target &
T, uint8_t OSABI,
1076 : ELFX86AsmBackend(
T, OSABI, STI) {}
1078 std::unique_ptr<MCObjectTargetWriter>
1079 createObjectTargetWriter()
const override {
1085class ELFX86_IAMCUAsmBackend :
public ELFX86AsmBackend {
1087 ELFX86_IAMCUAsmBackend(
const Target &
T, uint8_t OSABI,
1089 : ELFX86AsmBackend(
T, OSABI, STI) {}
1091 std::unique_ptr<MCObjectTargetWriter>
1092 createObjectTargetWriter()
const override {
1098class ELFX86_64AsmBackend :
public ELFX86AsmBackend {
1100 ELFX86_64AsmBackend(
const Target &
T, uint8_t OSABI,
1102 : ELFX86AsmBackend(
T, OSABI, STI) {}
1104 std::unique_ptr<MCObjectTargetWriter>
1105 createObjectTargetWriter()
const override {
1110class WindowsX86AsmBackend :
public X86AsmBackend {
1116 : X86AsmBackend(
T, STI)
1120 std::optional<MCFixupKind> getFixupKind(
StringRef Name)
const override {
1128 std::unique_ptr<MCObjectTargetWriter>
1129 createObjectTargetWriter()
const override {
1140 UNWIND_MODE_BP_FRAME = 0x01000000,
1143 UNWIND_MODE_STACK_IMMD = 0x02000000,
1146 UNWIND_MODE_STACK_IND = 0x03000000,
1149 UNWIND_MODE_DWARF = 0x04000000,
1152 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
1155 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
1160class DarwinX86AsmBackend :
public X86AsmBackend {
1164 enum { CU_NUM_SAVED_REGS = 6 };
1166 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
1170 unsigned OffsetSize;
1171 unsigned MoveInstrSize;
1172 unsigned StackDivide;
1175 unsigned PushInstrSize(
unsigned Reg)
const {
1198 int getCompactUnwindRegNum(
unsigned Reg)
const {
1199 static const MCPhysReg CU32BitRegs[7] = {
1200 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
1202 static const MCPhysReg CU64BitRegs[] = {
1203 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
1205 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
1206 for (
int Idx = 1; *CURegs; ++CURegs, ++
Idx)
1215 uint32_t encodeCompactUnwindRegistersWithFrame()
const {
1220 for (
int i = 0,
Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
1221 unsigned Reg = SavedRegs[i];
1222 if (Reg == 0)
break;
1224 int CURegNum = getCompactUnwindRegNum(Reg);
1225 if (CURegNum == -1)
return ~0
U;
1229 RegEnc |= (CURegNum & 0x7) << (
Idx++ * 3);
1232 assert((RegEnc & 0x3FFFF) == RegEnc &&
1233 "Invalid compact register encoding!");
1240 uint32_t encodeCompactUnwindRegistersWithoutFrame(
unsigned RegCount)
const {
1254 for (
unsigned i = 0; i < RegCount; ++i) {
1255 int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
1256 if (CUReg == -1)
return ~0
U;
1257 SavedRegs[i] = CUReg;
1261 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
1263 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
1264 for (
unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
1265 unsigned Countless = 0;
1266 for (
unsigned j = CU_NUM_SAVED_REGS - RegCount;
j < i; ++
j)
1267 if (SavedRegs[j] < SavedRegs[i])
1270 RenumRegs[i] = SavedRegs[i] - Countless - 1;
1277 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
1278 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
1282 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
1283 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
1287 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
1288 + 3 * RenumRegs[4] + RenumRegs[5];
1291 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
1295 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
1298 permutationEncoding |= RenumRegs[5];
1302 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
1303 "Invalid compact register encoding!");
1304 return permutationEncoding;
1310 : X86AsmBackend(
T, STI),
MRI(
MRI),
TT(STI.getTargetTriple()),
1311 Is64Bit(
TT.isArch64Bit()) {
1312 memset(SavedRegs, 0,
sizeof(SavedRegs));
1313 OffsetSize = Is64Bit ? 8 : 4;
1314 MoveInstrSize = Is64Bit ? 3 : 2;
1315 StackDivide = Is64Bit ? 8 : 4;
1318 std::unique_ptr<MCObjectTargetWriter>
1319 createObjectTargetWriter()
const override {
1330 if (Instrs.
empty())
return 0;
1331 if (!isDarwinCanonicalPersonality(FI->
Personality) &&
1333 return CU::UNWIND_MODE_DWARF;
1336 unsigned SavedRegIdx = 0;
1337 memset(SavedRegs, 0,
sizeof(SavedRegs));
1342 uint64_t CompactUnwindEncoding = 0;
1344 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
1345 unsigned InstrOffset = 0;
1346 unsigned StackAdjust = 0;
1348 int64_t MinAbsOffset = std::numeric_limits<int64_t>::max();
1351 switch (Inst.getOperation()) {
1355 return CU::UNWIND_MODE_DWARF;
1367 if (*
MRI.getLLVMRegNum(Inst.getRegister(),
true) !=
1368 (Is64Bit ? X86::RBP : X86::EBP))
1369 return CU::UNWIND_MODE_DWARF;
1372 memset(SavedRegs, 0,
sizeof(SavedRegs));
1375 MinAbsOffset = std::numeric_limits<int64_t>::max();
1376 InstrOffset += MoveInstrSize;
1394 StackSize = Inst.getOffset() / StackDivide;
1410 if (SavedRegIdx == CU_NUM_SAVED_REGS)
1413 return CU::UNWIND_MODE_DWARF;
1415 unsigned Reg = *
MRI.getLLVMRegNum(Inst.getRegister(),
true);
1416 SavedRegs[SavedRegIdx++] =
Reg;
1417 StackAdjust += OffsetSize;
1418 MinAbsOffset = std::min(MinAbsOffset, std::abs(Inst.getOffset()));
1419 InstrOffset += PushInstrSize(Reg);
1425 StackAdjust /= StackDivide;
1428 if ((StackAdjust & 0xFF) != StackAdjust)
1430 return CU::UNWIND_MODE_DWARF;
1434 if (SavedRegIdx != 0 && MinAbsOffset != 3 * (
int)OffsetSize)
1435 return CU::UNWIND_MODE_DWARF;
1438 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
1439 if (RegEnc == ~0U)
return CU::UNWIND_MODE_DWARF;
1441 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
1442 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
1443 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
1445 SubtractInstrIdx += InstrOffset;
1448 if ((StackSize & 0xFF) == StackSize) {
1450 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
1453 CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
1455 if ((StackAdjust & 0x7) != StackAdjust)
1457 return CU::UNWIND_MODE_DWARF;
1460 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
1464 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
1467 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
1471 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
1472 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
1476 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
1477 if (RegEnc == ~0U)
return CU::UNWIND_MODE_DWARF;
1480 CompactUnwindEncoding |=
1481 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
1484 return CompactUnwindEncoding;
1496 return new DarwinX86AsmBackend(
T,
MRI, STI);
1499 return new WindowsX86AsmBackend(
T,
false, STI);
1504 return new ELFX86_IAMCUAsmBackend(
T, OSABI, STI);
1506 return new ELFX86_32AsmBackend(
T, OSABI, STI);
1515 return new DarwinX86AsmBackend(
T,
MRI, STI);
1518 return new WindowsX86AsmBackend(
T,
true, STI);
1520 if (TheTriple.
isUEFI()) {
1522 "Only COFF format is supported in UEFI environment.");
1523 return new WindowsX86AsmBackend(
T,
true, STI);
1528 if (TheTriple.
isX32())
1529 return new ELFX86_X32AsmBackend(
T, OSABI, STI);
1530 return new ELFX86_64AsmBackend(
T, OSABI, STI);
1536 X86ELFStreamer(
MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
1537 std::unique_ptr<MCObjectWriter> OW,
1538 std::unique_ptr<MCCodeEmitter>
Emitter)
1549 Backend.emitInstructionBegin(S, Inst, STI);
1550 S.MCObjectStreamer::emitInstruction(Inst, STI);
1551 Backend.emitInstructionEnd(S, Inst);
1554void X86ELFStreamer::emitInstruction(
const MCInst &Inst,
1560 std::unique_ptr<MCAsmBackend> &&MAB,
1561 std::unique_ptr<MCObjectWriter> &&MOW,
1562 std::unique_ptr<MCCodeEmitter> &&MCE) {
1563 return new X86ELFStreamer(Context, std::move(MAB), std::move(MOW),
unsigned const MachineRegisterInfo * MRI
dxil DXContainer Global Emitter
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static MCInstrInfo * createMCInstrInfo()
static unsigned getRelaxedOpcodeBranch(unsigned Opcode, bool Is16BitMode=false)
static X86::SecondMacroFusionInstKind classifySecondInstInMacroFusion(const MCInst &MI, const MCInstrInfo &MCII)
static size_t getSizeForInstFragment(const MCFragment *F)
static bool isRIPRelative(const MCInst &MI, const MCInstrInfo &MCII)
Check if the instruction uses RIP relative addressing.
static bool isRightAfterData(MCFragment *CurrentFragment, const std::pair< MCFragment *, size_t > &PrevInstPosition)
Check if the instruction to be emitted is right after any data.
static bool mayHaveInterruptDelaySlot(unsigned InstOpcode)
X86 has certain instructions which enable interrupts exactly one instruction after the instruction wh...
static bool isFirstMacroFusibleInst(const MCInst &Inst, const MCInstrInfo &MCII)
Check if the instruction is valid as the first instruction in macro fusion.
static X86::CondCode getCondFromBranch(const MCInst &MI, const MCInstrInfo &MCII)
static unsigned getRelaxedOpcode(const MCInst &MI, bool Is16BitMode)
static unsigned getFixupKindSize(unsigned Kind)
static bool isRelaxableBranch(unsigned Opcode)
static bool isPrefix(unsigned Opcode, const MCInstrInfo &MCII)
Check if the instruction is a prefix.
static bool hasVariantSymbol(const MCInst &MI)
Check if the instruction has a variant symbol operand.
static bool is64Bit(const char *name)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool empty() const
empty - Check if the array is empty.
Implements a dense probed hash-table based set.
Generic interface to target specific assembler backends.
virtual bool allowEnhancedRelaxation() const
Return true if this target allows an unrelaxable instruction to be emitted into RelaxableFragment and...
virtual unsigned getMaximumNopSize(const MCSubtargetInfo &STI) const
Returns the maximum size of a nop in bytes on this target.
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
virtual bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const
Check whether the given instruction may need relaxation.
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value) const
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual void finishLayout(MCAssembler const &Asm) const
Give backend an opportunity to finish layout after relaxation.
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI)
Hook to check if a relocation is needed for some target specific reason.
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual std::optional< MCFixupKind > getFixupKind(StringRef Name) const
Map a relocation name used in .reloc to a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
virtual bool allowAutoPadding() const
Return true if this target might automatically pad instructions and thus need to emit padding enable/...
MCAsmBackend & getBackend() const
Represents required padding such that a particular other set of fragments does not cross a particular...
void setLastFragment(const MCFragment *F)
MCCodeEmitter - Generic instruction encoding interface.
Context object for machine code objects.
bool emitCompactUnwindNonCanonical() const
Fragment for data and encoded instructions.
SmallVectorImpl< MCFixup > & getFixups()
SmallVectorImpl< char > & getContents()
const MCSubtargetInfo * getSubtargetInfo() const
Retrieve the MCSubTargetInfo in effect when the instruction was encoded.
Base class for the full range of assembler expressions which are needed for parsing.
@ SymbolRef
References to labels and assigned expressions.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
MCFragment * getNext() const
Instances of this class represent a single low-level machine instruction.
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ", const MCRegisterInfo *RegInfo=nullptr) const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
unsigned getOpcode() const
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Streaming object file generation interface.
MCAssembler & getAssembler()
void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override
Emit the given Instruction into the current section.
unsigned getReg() const
Returns the register number.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
bool getAllowAutoPadding() const
const MCInst & getInst() const
void setInst(const MCInst &Value)
Instances of this class represent a uniqued identifier for a section in the current translation unit.
void ensureMinAlignment(Align MinAlignment)
Makes sure that Alignment is at least MinAlignment.
void setHasLayout(bool Value)
Streaming machine code generation interface.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
This represents an "assembler immediate".
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isX32() const
Tests whether the target is X32.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
OSType getOS() const
Get the parsed operating system type of this triple.
ArchType getArch() const
Get the parsed architecture type of this triple.
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
bool isUEFI() const
Tests whether the OS is UEFI.
bool isOSWindows() const
Tests whether the OS is Windows.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
std::pair< iterator, bool > insert(const ValueT &V)
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & write(unsigned char C)
A raw_ostream that writes to an SmallVector or SmallString.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CompactUnwindEncodings
Compact unwind encoding values.
Expected< uint32_t > getCPUSubType(const Triple &T)
Expected< uint32_t > getCPUType(const Triple &T)
Reg
All possible values of the reg field in the ModR/M byte.
bool isPrefix(uint64_t TSFlags)
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
@ RawFrmMemOffs
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
int getMemoryOperandNo(uint64_t TSFlags)
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
void emitPrefix(MCCodeEmitter &MCE, const MCInst &MI, SmallVectorImpl< char > &CB, const MCSubtargetInfo &STI)
void emitInstruction(MCObjectStreamer &, const MCInst &Inst, const MCSubtargetInfo &STI)
FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion(unsigned Opcode)
AlignBranchBoundaryKind
Defines the possible values of the branch boundary alignment mask.
SecondMacroFusionInstKind
unsigned getOpcodeForLongImmediateForm(unsigned Opcode)
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(unsigned Reg)
Given a segment register, return the encoding of the segment override prefix for it.
bool isMacroFused(FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind)
@ reloc_global_offset_table8
@ reloc_signed_4byte_relax
@ reloc_branch_4byte_pcrel
@ reloc_riprel_4byte_relax
@ reloc_riprel_4byte_relax_rex
@ reloc_global_offset_table
@ reloc_riprel_4byte_movq_load
initializer< Ty > init(const Ty &Val)
LocationClass< Ty > location(Ty &L)
NodeAddr< CodeNode * > Code
This is an optimization pass for GlobalISel generic memory operations.
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createX86WinCOFFObjectWriter(bool Is64Bit)
Construct an X86 Win COFF object writer.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MCStreamer * createX86ELFStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&MOW, std::unique_ptr< MCCodeEmitter > &&MCE)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_PCRel_4
A four-byte pc relative fixup.
@ FK_PCRel_2
A two-byte pc relative fixup.
@ FK_SecRel_2
A two-byte section relative fixup.
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
@ FK_Data_8
A eight-byte fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_SecRel_8
A eight-byte section relative fixup.
@ FK_PCRel_8
A eight-byte pc relative fixup.
@ FK_SecRel_4
A four-byte section relative fixup.
@ FK_PCRel_1
A one-byte pc relative fixup.
@ FK_SecRel_1
A one-byte section relative fixup.
@ FK_Data_2
A two-byte fixup.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
std::unique_ptr< MCObjectTargetWriter > createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an X86 Mach-O object writer.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
std::unique_ptr< MCObjectTargetWriter > createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine)
Construct an X86 ELF object writer.
Align assumeAligned(uint64_t Value)
Treats the value 0 as a 1, so Align is always at least 1.
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Implement std::hash so that hash_code can be used in STL containers.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Description of the encoding of one expression Op.
const MCSymbol * Personality
std::vector< MCCFIInstruction > Instructions
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...