42class X86AlignBranchKind {
44 uint8_t AlignBranchKind = 0;
47 void operator=(
const std::string &Val) {
52 for (
auto BranchType : BranchTypes) {
53 if (BranchType ==
"fused")
55 else if (BranchType ==
"jcc")
57 else if (BranchType ==
"jmp")
59 else if (BranchType ==
"call")
61 else if (BranchType ==
"ret")
63 else if (BranchType ==
"indirect")
67 <<
" to -x86-align-branch=; each element must be one of: fused, "
68 "jcc, jmp, call, ret, indirect.(plus separated)\n";
73 operator uint8_t()
const {
return AlignBranchKind; }
77X86AlignBranchKind X86AlignBranchKindLoc;
80 "x86-align-branch-boundary",
cl::init(0),
82 "Control how the assembler should align branches with NOP. If the "
83 "boundary's size is not 0, it should be a power of 2 and no less "
84 "than 32. Branches will be aligned to prevent from being across or "
85 "against the boundary of specified size. The default value 0 does not "
91 "Specify types of branches to align (plus separated list of types):"
92 "\njcc indicates conditional jumps"
93 "\nfused indicates fused conditional jumps"
94 "\njmp indicates direct unconditional jumps"
95 "\ncall indicates direct and indirect calls"
96 "\nret indicates rets"
97 "\nindirect indicates indirect unconditional jumps"),
101 "x86-branches-within-32B-boundaries",
cl::init(
false),
103 "Align selected instructions to mitigate negative performance impact "
104 "of Intel's micro code update for errata skx102. May break "
105 "assumptions about labels corresponding to particular instructions, "
106 "and should be used with caution."));
109 "x86-pad-max-prefix-size",
cl::init(0),
110 cl::desc(
"Maximum number of prefixes to use for padding"));
114 cl::desc(
"Pad previous instructions to implement align directives"));
118 cl::desc(
"Pad previous instructions to implement branch alignment"));
122 std::unique_ptr<const MCInstrInfo> MCII;
123 X86AlignBranchKind AlignBranchType;
125 unsigned TargetPrefixMax = 0;
129 std::pair<MCFragment *, size_t> PrevInstPosition;
132 uint8_t determinePaddingPrefix(
const MCInst &Inst)
const;
134 bool needAlign(
const MCInst &Inst)
const;
142 if (X86AlignBranchWithin32BBoundaries) {
153 if (X86AlignBranchBoundary.getNumOccurrences())
155 if (X86AlignBranch.getNumOccurrences())
156 AlignBranchType = X86AlignBranchKindLoc;
157 if (X86PadMaxPrefixSize.getNumOccurrences())
158 TargetPrefixMax = X86PadMaxPrefixSize;
195 unsigned &RemainingSize)
const;
198 unsigned &RemainingSize)
const;
201 unsigned &RemainingSize)
const;
218 return (Is16BitMode) ? X86::JCC_2 : X86::JCC_4;
220 return (Is16BitMode) ? X86::JMP_2 : X86::JMP_4;
238 unsigned Opcode =
MI.getOpcode();
253 return classifySecondCondCodeInMacroFusion(
CC);
258 unsigned Opcode =
MI.getOpcode();
263 if (MemoryOperand < 0)
266 unsigned BaseReg =
MI.getOperand(BaseRegNum).getReg();
267 return (BaseReg == X86::RIP);
283 return FIK != X86::FirstMacroFusionInstKind::Invalid;
295uint8_t X86AsmBackend::determinePaddingPrefix(
const MCInst &Inst)
const {
297 "Prefixes can be added only in 32-bit or 64-bit mode.");
303 if (MemoryOperand != -1)
306 unsigned SegmentReg = 0;
307 if (MemoryOperand >= 0) {
340 if (MemoryOperand >= 0) {
343 if (BaseReg == X86::ESP || BaseReg == X86::EBP)
350bool X86AsmBackend::isMacroFused(
const MCInst &Cmp,
const MCInst &Jcc)
const {
365 for (
auto &Operand :
MI) {
366 if (!Operand.isExpr())
368 const MCExpr &Expr = *Operand.getExpr();
376bool X86AsmBackend::allowAutoPadding()
const {
380bool X86AsmBackend::allowEnhancedRelaxation()
const {
381 return allowAutoPadding() && TargetPrefixMax != 0 && X86PadForBranchAlign;
408 const std::pair<MCFragment *, size_t> &PrevInstPosition) {
413 for (; isa_and_nonnull<MCDataFragment>(
F);
F =
F->getPrevNode())
414 if (cast<MCDataFragment>(
F)->getContents().size() != 0)
427 if (
auto *
DF = dyn_cast_or_null<MCDataFragment>(
F))
428 return DF != PrevInstPosition.first ||
429 DF->getContents().size() != PrevInstPosition.second;
436 if (!
F || !
F->hasInstructions())
439 switch (
F->getKind()) {
443 return cast<MCDataFragment>(*F).getContents().size();
445 return cast<MCRelaxableFragment>(*F).getContents().size();
447 return cast<MCCompactEncodedInstFragment>(*F).getContents().size();
483 if (!
OS.getAllowAutoPadding())
485 assert(allowAutoPadding() &&
"incorrect initialization!");
488 if (!
OS.getCurrentSectionOnly()->getKind().isText())
492 if (
OS.getAssembler().isBundlingEnabled())
503bool X86AsmBackend::needAlign(
const MCInst &Inst)
const {
518 CanPadInst = canPadInst(Inst,
OS);
520 if (!canPadBranches(
OS))
530 if (PendingBA &&
OS.getCurrentFragment()->getPrevNode() == PendingBA) {
565 if (
auto *
F = dyn_cast_or_null<MCRelaxableFragment>(CF))
566 F->setAllowAutoPadding(CanPadInst);
568 if (!canPadBranches(
OS))
571 if (!needAlign(Inst) || !PendingBA)
582 if (isa_and_nonnull<MCDataFragment>(CF))
590std::optional<MCFixupKind> X86AsmBackend::getFixupKind(
StringRef Name)
const {
595#define ELF_RELOC(X, Y) .Case(#X, Y)
596#include "llvm/BinaryFormat/ELFRelocs/x86_64.def"
598 .
Case(
"BFD_RELOC_NONE", ELF::R_X86_64_NONE)
599 .
Case(
"BFD_RELOC_8", ELF::R_X86_64_8)
600 .
Case(
"BFD_RELOC_16", ELF::R_X86_64_16)
601 .
Case(
"BFD_RELOC_32", ELF::R_X86_64_32)
602 .
Case(
"BFD_RELOC_64", ELF::R_X86_64_64)
606#define ELF_RELOC(X, Y) .Case(#X, Y)
607#include "llvm/BinaryFormat/ELFRelocs/i386.def"
609 .
Case(
"BFD_RELOC_NONE", ELF::R_386_NONE)
610 .
Case(
"BFD_RELOC_8", ELF::R_386_8)
611 .
Case(
"BFD_RELOC_16", ELF::R_386_16)
612 .
Case(
"BFD_RELOC_32", ELF::R_386_32)
628 {
"reloc_signed_4byte", 0, 32, 0},
629 {
"reloc_signed_4byte_relax", 0, 32, 0},
630 {
"reloc_global_offset_table", 0, 32, 0},
631 {
"reloc_global_offset_table8", 0, 64, 0},
649bool X86AsmBackend::shouldForceRelocation(
const MCAssembler &,
701 int64_t SignedValue =
static_cast<int64_t
>(
Value);
702 if ((
Target.isAbsolute() || IsResolved) &&
703 getFixupKindInfo(
Fixup.getKind()).Flags &
707 Asm.getContext().reportError(
708 Fixup.getLoc(),
"value of " +
Twine(SignedValue) +
709 " is too large for field of " +
Twine(
Size) +
710 ((
Size == 1) ?
" byte." :
" bytes."));
717 "Value does not fit in the Fixup field");
720 for (
unsigned i = 0; i !=
Size; ++i)
724bool X86AsmBackend::mayNeedRelaxation(
const MCInst &Inst,
744bool X86AsmBackend::fixupNeedsRelaxation(
const MCFixup &
Fixup,
749 return !isInt<8>(
Value);
754void X86AsmBackend::relaxInstruction(
MCInst &Inst,
757 bool Is16BitMode = STI.
hasFeature(X86::Is16Bit);
776 bool Is16BitMode = STI.
hasFeature(X86::Is16Bit);
782 unsigned &RemainingSize)
const {
796 const unsigned MaxPossiblePad = std::min(15 - OldSize, RemainingSize);
797 const unsigned RemainingPrefixSize = [&]() ->
unsigned {
801 assert(
Code.size() < 15 &&
"The number of prefixes must be less than 15.");
808 unsigned ExistingPrefixSize =
Code.size();
809 if (TargetPrefixMax <= ExistingPrefixSize)
811 return TargetPrefixMax - ExistingPrefixSize;
813 const unsigned PrefixBytesToAdd =
814 std::min(MaxPossiblePad, RemainingPrefixSize);
815 if (PrefixBytesToAdd == 0)
821 Code.append(PrefixBytesToAdd, Prefix);
827 F.setOffset(
F.getOffset() + PrefixBytesToAdd);
830 RemainingSize -= PrefixBytesToAdd;
836 unsigned &RemainingSize)
const {
850 const unsigned NewSize =
Code.size();
851 assert(NewSize >= OldSize &&
"size decrease during relaxation?");
852 unsigned Delta = NewSize - OldSize;
853 if (Delta > RemainingSize)
858 RemainingSize -= Delta;
864 unsigned &RemainingSize)
const {
865 bool Changed =
false;
866 if (RemainingSize != 0)
867 Changed |= padInstructionViaRelaxation(RF,
Emitter, RemainingSize);
868 if (RemainingSize != 0)
869 Changed |= padInstructionViaPrefix(RF,
Emitter, RemainingSize);
873void X86AsmBackend::finishLayout(
MCAssembler const &Asm,
881 if (!X86PadForAlign && !X86PadForBranchAlign)
889 LabeledFragments.
insert(S.getFragment(
false));
899 if (LabeledFragments.
count(&
F))
908 auto &RF = cast<MCRelaxableFragment>(*
I);
914 switch (
F.getKind()) {
918 return X86PadForAlign;
920 return X86PadForBranchAlign;
932 const uint64_t OrigSize =
Asm.computeFragmentSize(Layout,
F);
939 unsigned RemainingSize = OrigSize;
940 while (!Relaxable.
empty() && RemainingSize != 0) {
945 if (padInstructionEncoding(RF,
Asm.getEmitter(), RemainingSize))
946 FirstChangedFragment = &RF;
959 if (FirstChangedFragment) {
968 cast<MCBoundaryAlignFragment>(
F).setSize(RemainingSize);
972 const uint64_t FinalSize =
Asm.computeFragmentSize(Layout,
F);
973 assert(OrigOffset + OrigSize == FinalOffset + FinalSize &&
974 "can't move start of next fragment!");
975 assert(FinalSize == RemainingSize &&
"inconsistent size computation?");
981 if (
auto *BF = dyn_cast<MCBoundaryAlignFragment>(&
F)) {
982 const MCFragment *LastFragment = BF->getLastFragment();
985 while (&*
I != LastFragment)
992 for (
unsigned int i = 0, n = Layout.
getSectionOrder().size(); i != n; ++i) {
995 Asm.computeFragmentSize(Layout, *
Section.getFragmentList().rbegin());
999unsigned X86AsmBackend::getMaximumNopSize(
const MCSubtargetInfo &STI)
const {
1006 if (STI.
hasFeature(X86::TuningFast15ByteNOP))
1008 if (STI.
hasFeature(X86::TuningFast11ByteNOP))
1021 static const char Nops32Bit[10][11] = {
1031 "\x0f\x1f\x44\x00\x00",
1033 "\x66\x0f\x1f\x44\x00\x00",
1035 "\x0f\x1f\x80\x00\x00\x00\x00",
1037 "\x0f\x1f\x84\x00\x00\x00\x00\x00",
1039 "\x66\x0f\x1f\x84\x00\x00\x00\x00\x00",
1041 "\x66\x2e\x0f\x1f\x84\x00\x00\x00\x00\x00",
1045 static const char Nops16Bit[4][11] = {
1056 const char(*Nops)[11] =
1057 STI->
hasFeature(X86::Is16Bit) ? Nops16Bit : Nops32Bit;
1064 const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength);
1065 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
1066 for (uint8_t i = 0; i < Prefixes; i++)
1068 const uint8_t Rest = ThisNopLength - Prefixes;
1070 OS.
write(Nops[Rest - 1], Rest);
1071 Count -= ThisNopLength;
1072 }
while (Count != 0);
1081class ELFX86AsmBackend :
public X86AsmBackend {
1085 : X86AsmBackend(
T, STI), OSABI(OSABI) {}
1088class ELFX86_32AsmBackend :
public ELFX86AsmBackend {
1090 ELFX86_32AsmBackend(
const Target &
T, uint8_t OSABI,
1092 : ELFX86AsmBackend(
T, OSABI, STI) {}
1094 std::unique_ptr<MCObjectTargetWriter>
1095 createObjectTargetWriter()
const override {
1100class ELFX86_X32AsmBackend :
public ELFX86AsmBackend {
1102 ELFX86_X32AsmBackend(
const Target &
T, uint8_t OSABI,
1104 : ELFX86AsmBackend(
T, OSABI, STI) {}
1106 std::unique_ptr<MCObjectTargetWriter>
1107 createObjectTargetWriter()
const override {
1113class ELFX86_IAMCUAsmBackend :
public ELFX86AsmBackend {
1115 ELFX86_IAMCUAsmBackend(
const Target &
T, uint8_t OSABI,
1117 : ELFX86AsmBackend(
T, OSABI, STI) {}
1119 std::unique_ptr<MCObjectTargetWriter>
1120 createObjectTargetWriter()
const override {
1126class ELFX86_64AsmBackend :
public ELFX86AsmBackend {
1128 ELFX86_64AsmBackend(
const Target &
T, uint8_t OSABI,
1130 : ELFX86AsmBackend(
T, OSABI, STI) {}
1132 std::unique_ptr<MCObjectTargetWriter>
1133 createObjectTargetWriter()
const override {
1138class WindowsX86AsmBackend :
public X86AsmBackend {
1144 : X86AsmBackend(
T, STI)
1148 std::optional<MCFixupKind> getFixupKind(
StringRef Name)
const override {
1156 std::unique_ptr<MCObjectTargetWriter>
1157 createObjectTargetWriter()
const override {
1168 UNWIND_MODE_BP_FRAME = 0x01000000,
1171 UNWIND_MODE_STACK_IMMD = 0x02000000,
1174 UNWIND_MODE_STACK_IND = 0x03000000,
1177 UNWIND_MODE_DWARF = 0x04000000,
1180 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
1183 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
1188class DarwinX86AsmBackend :
public X86AsmBackend {
1192 enum { CU_NUM_SAVED_REGS = 6 };
1194 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
1198 unsigned OffsetSize;
1199 unsigned MoveInstrSize;
1200 unsigned StackDivide;
1203 unsigned PushInstrSize(
unsigned Reg)
const {
1226 int getCompactUnwindRegNum(
unsigned Reg)
const {
1227 static const MCPhysReg CU32BitRegs[7] = {
1228 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
1230 static const MCPhysReg CU64BitRegs[] = {
1231 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
1233 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
1234 for (
int Idx = 1; *CURegs; ++CURegs, ++
Idx)
1243 uint32_t encodeCompactUnwindRegistersWithFrame()
const {
1248 for (
int i = 0,
Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
1249 unsigned Reg = SavedRegs[i];
1250 if (Reg == 0)
break;
1252 int CURegNum = getCompactUnwindRegNum(Reg);
1253 if (CURegNum == -1)
return ~0
U;
1257 RegEnc |= (CURegNum & 0x7) << (
Idx++ * 3);
1260 assert((RegEnc & 0x3FFFF) == RegEnc &&
1261 "Invalid compact register encoding!");
1268 uint32_t encodeCompactUnwindRegistersWithoutFrame(
unsigned RegCount)
const {
1282 for (
unsigned i = 0; i < RegCount; ++i) {
1283 int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
1284 if (CUReg == -1)
return ~0
U;
1285 SavedRegs[i] = CUReg;
1289 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
1291 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
1292 for (
unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
1293 unsigned Countless = 0;
1294 for (
unsigned j = CU_NUM_SAVED_REGS - RegCount;
j < i; ++
j)
1295 if (SavedRegs[j] < SavedRegs[i])
1298 RenumRegs[i] = SavedRegs[i] - Countless - 1;
1305 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
1306 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
1310 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
1311 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
1315 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
1316 + 3 * RenumRegs[4] + RenumRegs[5];
1319 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
1323 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
1326 permutationEncoding |= RenumRegs[5];
1330 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
1331 "Invalid compact register encoding!");
1332 return permutationEncoding;
1338 : X86AsmBackend(
T, STI),
MRI(
MRI),
TT(STI.getTargetTriple()),
1339 Is64Bit(
TT.isArch64Bit()) {
1340 memset(SavedRegs, 0,
sizeof(SavedRegs));
1341 OffsetSize = Is64Bit ? 8 : 4;
1342 MoveInstrSize = Is64Bit ? 3 : 2;
1343 StackDivide = Is64Bit ? 8 : 4;
1346 std::unique_ptr<MCObjectTargetWriter>
1347 createObjectTargetWriter()
const override {
1357 if (Instrs.
empty())
return 0;
1360 unsigned SavedRegIdx = 0;
1361 memset(SavedRegs, 0,
sizeof(SavedRegs));
1366 uint32_t CompactUnwindEncoding = 0;
1368 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
1369 unsigned InstrOffset = 0;
1370 unsigned StackAdjust = 0;
1371 unsigned StackSize = 0;
1372 int MinAbsOffset = std::numeric_limits<int>::max();
1375 switch (Inst.getOperation()) {
1379 return CU::UNWIND_MODE_DWARF;
1391 if (*
MRI.getLLVMRegNum(Inst.getRegister(),
true) !=
1392 (Is64Bit ? X86::RBP : X86::EBP))
1393 return CU::UNWIND_MODE_DWARF;
1396 memset(SavedRegs, 0,
sizeof(SavedRegs));
1399 MinAbsOffset = std::numeric_limits<int>::max();
1400 InstrOffset += MoveInstrSize;
1418 StackSize = Inst.getOffset() / StackDivide;
1434 if (SavedRegIdx == CU_NUM_SAVED_REGS)
1437 return CU::UNWIND_MODE_DWARF;
1439 unsigned Reg = *
MRI.getLLVMRegNum(Inst.getRegister(),
true);
1440 SavedRegs[SavedRegIdx++] =
Reg;
1441 StackAdjust += OffsetSize;
1442 MinAbsOffset = std::min(MinAbsOffset,
abs(Inst.getOffset()));
1443 InstrOffset += PushInstrSize(Reg);
1449 StackAdjust /= StackDivide;
1452 if ((StackAdjust & 0xFF) != StackAdjust)
1454 return CU::UNWIND_MODE_DWARF;
1458 if (SavedRegIdx != 0 && MinAbsOffset != 3 * (
int)OffsetSize)
1459 return CU::UNWIND_MODE_DWARF;
1462 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
1463 if (RegEnc == ~0U)
return CU::UNWIND_MODE_DWARF;
1465 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
1466 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
1467 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
1469 SubtractInstrIdx += InstrOffset;
1472 if ((StackSize & 0xFF) == StackSize) {
1474 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
1477 CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
1479 if ((StackAdjust & 0x7) != StackAdjust)
1481 return CU::UNWIND_MODE_DWARF;
1484 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
1488 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
1491 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
1495 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
1496 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
1500 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
1501 if (RegEnc == ~0U)
return CU::UNWIND_MODE_DWARF;
1504 CompactUnwindEncoding |=
1505 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
1508 return CompactUnwindEncoding;
1520 return new DarwinX86AsmBackend(
T,
MRI, STI);
1523 return new WindowsX86AsmBackend(
T,
false, STI);
1528 return new ELFX86_IAMCUAsmBackend(
T, OSABI, STI);
1530 return new ELFX86_32AsmBackend(
T, OSABI, STI);
1539 return new DarwinX86AsmBackend(
T,
MRI, STI);
1542 return new WindowsX86AsmBackend(
T,
true, STI);
1546 if (TheTriple.
isX32())
1547 return new ELFX86_X32AsmBackend(
T, OSABI, STI);
1548 return new ELFX86_64AsmBackend(
T, OSABI, STI);
unsigned const MachineRegisterInfo * MRI
dxil DXContainer Global Emitter
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static MCInstrInfo * createMCInstrInfo()
static X86::SecondMacroFusionInstKind classifySecondInstInMacroFusion(const MCInst &MI, const MCInstrInfo &MCII)
static size_t getSizeForInstFragment(const MCFragment *F)
static bool isRIPRelative(const MCInst &MI, const MCInstrInfo &MCII)
Check if the instruction uses RIP relative addressing.
static bool isRightAfterData(MCFragment *CurrentFragment, const std::pair< MCFragment *, size_t > &PrevInstPosition)
Check if the instruction to be emitted is right after any data.
static bool isPrefix(const MCInst &MI, const MCInstrInfo &MCII)
Check if the instruction is a prefix.
static unsigned getRelaxedOpcode(const MCInst &Inst, bool Is16BitMode)
static bool hasInterruptDelaySlot(const MCInst &Inst)
X86 has certain instructions which enable interrupts exactly one instruction after the instruction wh...
static bool isFirstMacroFusibleInst(const MCInst &Inst, const MCInstrInfo &MCII)
Check if the instruction is valid as the first instruction in macro fusion.
static X86::CondCode getCondFromBranch(const MCInst &MI, const MCInstrInfo &MCII)
static unsigned getRelaxedOpcodeArith(const MCInst &Inst)
static unsigned getRelaxedOpcodeBranch(const MCInst &Inst, bool Is16BitMode)
static unsigned getFixupKindSize(unsigned Kind)
static bool hasVariantSymbol(const MCInst &MI)
Check if the instruction has a variant symbol operand.
static bool isFullyRelaxed(const MCRelaxableFragment &RF)
Return true if this instruction has been fully relaxed into it's most general available form.
static bool is64Bit(const char *name)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool empty() const
empty - Check if the array is empty.
Implements a dense probed hash-table based set.
Generic interface to target specific assembler backends.
virtual bool allowEnhancedRelaxation() const
Return true if this target allows an unrelaxable instruction to be emitted into RelaxableFragment and...
virtual unsigned getMaximumNopSize(const MCSubtargetInfo &STI) const
Returns the maximum size of a nop in bytes on this target.
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
virtual bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const
Check whether the given instruction may need relaxation.
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const =0
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual void finishLayout(MCAssembler const &Asm, MCAsmLayout &Layout) const
Give backend an opportunity to finish layout after relaxation.
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target)
Hook to check if a relocation is needed for some target specific reason.
virtual void emitInstructionEnd(MCObjectStreamer &OS, const MCInst &Inst)
virtual void emitInstructionBegin(MCObjectStreamer &OS, const MCInst &Inst, const MCSubtargetInfo &STI)
Give the target a chance to manipulate state related to instruction alignment (e.g.
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual std::optional< MCFixupKind > getFixupKind(StringRef Name) const
Map a relocation name used in .reloc to a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
virtual bool allowAutoPadding() const
Return true if this target might automatically pad instructions and thus need to emit padding enable/...
Encapsulates the layout of an assembly file at a particular point in time.
void invalidateFragmentsFrom(MCFragment *F)
Invalidate the fragments starting with F because it has been resized.
llvm::SmallVectorImpl< MCSection * > & getSectionOrder()
uint64_t getFragmentOffset(const MCFragment *F) const
Get the offset of the given fragment inside its containing section.
Represents required padding such that a particular other set of fragments does not cross a particular...
void setLastFragment(const MCFragment *F)
MCCodeEmitter - Generic instruction encoding interface.
Fragment for data and encoded instructions.
SmallVectorImpl< char > & getContents()
SmallVectorImpl< MCFixup > & getFixups()
const MCSubtargetInfo * getSubtargetInfo() const
Retrieve the MCSubTargetInfo in effect when the instruction was encoded.
Base class for the full range of assembler expressions which are needed for parsing.
@ SymbolRef
References to labels and assigned expressions.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Instances of this class represent a single low-level machine instruction.
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ", const MCRegisterInfo *RegInfo=nullptr) const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
unsigned getNumOperands() const
unsigned getOpcode() const
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block.
bool isCall() const
Return true if the instruction is a call.
bool isReturn() const
Return true if the instruction is a return.
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Streaming object file generation interface.
unsigned getReg() const
Returns the register number.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
bool getAllowAutoPadding() const
const MCInst & getInst() const
void setInst(const MCInst &Value)
Instances of this class represent a uniqued identifier for a section in the current translation unit.
void ensureMinAlignment(Align MinAlignment)
Makes sure that Alignment is at least MinAlignment.
SectionKind getKind() const
FragmentListType::iterator iterator
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
This represents an "assembler immediate".
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isX32() const
Tests whether the target is X32.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
OSType getOS() const
Get the parsed operating system type of this triple.
ArchType getArch() const
Get the parsed architecture type of this triple.
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
bool isOSWindows() const
Tests whether the OS is Windows.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
std::pair< iterator, bool > insert(const ValueT &V)
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & write(unsigned char C)
A raw_ostream that writes to an SmallVector or SmallString.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CompactUnwindEncodings
Compact unwind encoding values.
Expected< uint32_t > getCPUSubType(const Triple &T)
Expected< uint32_t > getCPUType(const Triple &T)
Reg
All possible values of the reg field in the ModR/M byte.
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
@ RawFrmMemOffs
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
bool isPrefix(uint64_t TSFlags)
int getMemoryOperandNo(uint64_t TSFlags)
The function returns the MCInst operand # for the first field of the memory operand.
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion(unsigned Opcode)
AlignBranchBoundaryKind
Defines the possible values of the branch boundary alignment mask.
SecondMacroFusionInstKind
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
unsigned getRelaxedOpcodeArith(unsigned ShortOp)
Get the relaxed instruction opcode for a given short opcode.
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(unsigned Reg)
Given a segment register, return the encoding of the segment override prefix for it.
bool isMacroFused(FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind)
@ reloc_global_offset_table8
@ reloc_signed_4byte_relax
@ reloc_branch_4byte_pcrel
@ reloc_riprel_4byte_relax
@ reloc_riprel_4byte_relax_rex
@ reloc_global_offset_table
@ reloc_riprel_4byte_movq_load
initializer< Ty > init(const Ty &Val)
LocationClass< Ty > location(Ty &L)
This is an optimization pass for GlobalISel generic memory operations.
APFloat abs(APFloat X)
Returns the absolute value of the argument.
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createX86WinCOFFObjectWriter(bool Is64Bit)
Construct an X86 Win COFF object writer.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_PCRel_4
A four-byte pc relative fixup.
@ FK_PCRel_2
A two-byte pc relative fixup.
@ FK_SecRel_2
A two-byte section relative fixup.
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
@ FK_Data_8
A eight-byte fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_SecRel_8
A eight-byte section relative fixup.
@ FK_PCRel_8
A eight-byte pc relative fixup.
@ FK_SecRel_4
A four-byte section relative fixup.
@ FK_PCRel_1
A one-byte pc relative fixup.
@ FK_SecRel_1
A one-byte section relative fixup.
@ FK_Data_2
A two-byte fixup.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
std::unique_ptr< MCObjectTargetWriter > createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an X86 Mach-O object writer.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
std::unique_ptr< MCObjectTargetWriter > createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine)
Construct an X86 ELF object writer.
Align assumeAligned(uint64_t Value)
Treats the value 0 as a 1, so Align is always at least 1.
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...