LLVM 22.0.0git
X86AsmBackend.cpp File Reference

Go to the source code of this file.

Namespaces

namespace  CU

Macros

#define ELF_RELOC(X, Y)
#define ELF_RELOC(X, Y)

Functions

static bool isRelaxableBranch (unsigned Opcode)
static unsigned getRelaxedOpcodeBranch (unsigned Opcode, bool Is16BitMode=false)
static unsigned getRelaxedOpcode (const MCInst &MI, bool Is16BitMode)
static X86::CondCode getCondFromBranch (const MCInst &MI, const MCInstrInfo &MCII)
static X86::SecondMacroFusionInstKind classifySecondInstInMacroFusion (const MCInst &MI, const MCInstrInfo &MCII)
static bool isRIPRelative (const MCInst &MI, const MCInstrInfo &MCII)
 Check if the instruction uses RIP relative addressing.
static bool isPrefix (unsigned Opcode, const MCInstrInfo &MCII)
 Check if the instruction is a prefix.
static bool isFirstMacroFusibleInst (const MCInst &Inst, const MCInstrInfo &MCII)
 Check if the instruction is valid as the first instruction in macro fusion.
static bool hasVariantSymbol (const MCInst &MI)
 Check if the instruction has a variant symbol operand.
static bool mayHaveInterruptDelaySlot (unsigned InstOpcode)
 X86 has certain instructions which enable interrupts exactly one instruction after the instruction which stores to SS.
static unsigned getFixupKindSize (unsigned Kind)

Variables

constexpr char GotSymName [] = "_GLOBAL_OFFSET_TABLE_"

Macro Definition Documentation

◆ ELF_RELOC [1/2]

#define ELF_RELOC ( X,
Y )
Value:
.Case(#X, Y)
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

◆ ELF_RELOC [2/2]

#define ELF_RELOC ( X,
Y )
Value:
.Case(#X, Y)

Function Documentation

◆ classifySecondInstInMacroFusion()

X86::SecondMacroFusionInstKind classifySecondInstInMacroFusion ( const MCInst & MI,
const MCInstrInfo & MCII )
static

Definition at line 244 of file X86AsmBackend.cpp.

References getCondFromBranch(), and MI.

◆ getCondFromBranch()

X86::CondCode getCondFromBranch ( const MCInst & MI,
const MCInstrInfo & MCII )
static

Definition at line 229 of file X86AsmBackend.cpp.

References llvm::X86::COND_INVALID, llvm::MCInstrInfo::get(), and MI.

Referenced by classifySecondInstInMacroFusion().

◆ getFixupKindSize()

◆ getRelaxedOpcode()

unsigned getRelaxedOpcode ( const MCInst & MI,
bool Is16BitMode )
static

◆ getRelaxedOpcodeBranch()

unsigned getRelaxedOpcodeBranch ( unsigned Opcode,
bool Is16BitMode = false )
static

Definition at line 211 of file X86AsmBackend.cpp.

References llvm_unreachable.

Referenced by getRelaxedOpcode().

◆ hasVariantSymbol()

bool hasVariantSymbol ( const MCInst & MI)
static

Check if the instruction has a variant symbol operand.

Definition at line 357 of file X86AsmBackend.cpp.

References llvm::cast(), llvm::MCExpr::getKind(), MI, and llvm::MCExpr::SymbolRef.

◆ isFirstMacroFusibleInst()

bool isFirstMacroFusibleInst ( const MCInst & Inst,
const MCInstrInfo & MCII )
static

Check if the instruction is valid as the first instruction in macro fusion.

Definition at line 269 of file X86AsmBackend.cpp.

References llvm::X86::classifyFirstOpcodeInMacroFusion(), llvm::MCInst::getOpcode(), llvm::X86::Invalid, and isRIPRelative().

◆ isPrefix()

bool isPrefix ( unsigned Opcode,
const MCInstrInfo & MCII )
static

Check if the instruction is a prefix.

Definition at line 264 of file X86AsmBackend.cpp.

References llvm::MCInstrInfo::get(), llvm::X86II::isPrefix(), and llvm::MCInstrDesc::TSFlags.

Referenced by readPrefixes().

◆ isRelaxableBranch()

bool isRelaxableBranch ( unsigned Opcode)
static

Definition at line 207 of file X86AsmBackend.cpp.

Referenced by getRelaxedOpcode().

◆ isRIPRelative()

bool isRIPRelative ( const MCInst & MI,
const MCInstrInfo & MCII )
static

Check if the instruction uses RIP relative addressing.

Definition at line 250 of file X86AsmBackend.cpp.

References llvm::X86::AddrBaseReg, llvm::MCInstrInfo::get(), llvm::X86II::getMemoryOperandNo(), llvm::X86II::getOperandBias(), and MI.

Referenced by isFirstMacroFusibleInst().

◆ mayHaveInterruptDelaySlot()

bool mayHaveInterruptDelaySlot ( unsigned InstOpcode)
static

X86 has certain instructions which enable interrupts exactly one instruction after the instruction which stores to SS.

Return true if the given instruction may have such an interrupt delay slot.

Definition at line 372 of file X86AsmBackend.cpp.

Variable Documentation

◆ GotSymName

char GotSymName[] = "_GLOBAL_OFFSET_TABLE_"
constexpr

Definition at line 654 of file X86AsmBackend.cpp.