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46 unsigned getNumFixupKinds()
const override {
return 0; }
54 assert(
Fixup.getOffset() + Size <=
Data.size() &&
"Invalid fixup offset!");
61 "Value does not fit in the Fixup field");
64 for (
unsigned i = 0;
i !=
Size; ++
i)
68 bool mayNeedRelaxation(
const MCInst &Inst,
75 void relaxInstruction(
MCInst &Inst,
81 unsigned getMinimumNopSize()
const override {
return 2; }
149 bool M68kAsmBackend::mayNeedRelaxation(
const MCInst &Inst,
188 void M68kAsmBackend::relaxInstruction(
MCInst &Inst,
220 class M68kELFAsmBackend :
public M68kAsmBackend {
223 M68kELFAsmBackend(
const Target &
T, uint8_t OSABI)
224 : M68kAsmBackend(
T), OSABI(OSABI) {}
226 std::unique_ptr<MCObjectTargetWriter>
227 createObjectTargetWriter()
const override {
240 return new M68kELFAsmBackend(
T, OSABI);
This is an optimization pass for GlobalISel generic memory operations.
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Instances of this class represent a single low-level machine instruction.
Error applyFixup(LinkGraph &G, Block &B, const Edge &E)
Apply fixup expression for edge to block content.
unsigned getNumOperands() const
void setOpcode(unsigned Op)
MCAsmBackend * createM68kAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Generic interface to target specific assembler backends.
const Triple & getTargetTriple() const
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
This class implements an extremely fast bulk output stream that can only output to a stream.
static unsigned getFixupKindLog2Size(unsigned Kind)
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
constexpr bool isInt< 8 >(int64_t x)
static unsigned getRelaxedOpcodeBranch(const MCInst &Inst)
cc—Carry clear GE—Greater than or equal LS—Lower or same PL—Plus CS—Carry set GT—Greater than LT—Less...
OSType getOS() const
Get the parsed operating system type of this triple.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
PowerPC TLS Dynamic Call Fixup
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static unsigned getRelaxedOpcodeArith(const MCInst &Inst)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
constexpr bool isInt< 16 >(int64_t x)
Encapsulates the layout of an assembly file at a particular point in time.
std::unique_ptr< MCObjectTargetWriter > createM68kELFObjectWriter(uint8_t OSABI)
Construct an M68k ELF object writer.
unsigned getOpcode() const
const MCOperand & getOperand(unsigned i) const
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ", const MCRegisterInfo *RegInfo=nullptr) const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
A raw_ostream that writes to an SmallVector or SmallString.
static unsigned getRelaxedOpcode(const MCInst &Inst)
This represents an "assembler immediate".
Generic base class for all target subtargets.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
LLVM Value Representation.