LLVM  14.0.0git
SystemZInstrInfo.h
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1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SystemZ implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
14 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
15 
16 #include "SystemZ.h"
17 #include "SystemZRegisterInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
23 #include <cstdint>
24 
25 #define GET_INSTRINFO_HEADER
26 #include "SystemZGenInstrInfo.inc"
27 
28 namespace llvm {
29 
30 class SystemZSubtarget;
31 
32 namespace SystemZII {
33 
34 enum {
35  // See comments in SystemZInstrFormats.td.
36  SimpleBDXLoad = (1 << 0),
37  SimpleBDXStore = (1 << 1),
38  Has20BitOffset = (1 << 2),
39  HasIndex = (1 << 3),
40  Is128Bit = (1 << 4),
41  AccessSizeMask = (31 << 5),
43  CCValuesMask = (15 << 10),
45  CompareZeroCCMaskMask = (15 << 14),
47  CCMaskFirst = (1 << 18),
48  CCMaskLast = (1 << 19),
49  IsLogical = (1 << 20),
50  CCIfNoSignedWrap = (1 << 21),
51  MemMemOp = (1 << 22)
52 };
53 
54 static inline unsigned getAccessSize(unsigned int Flags) {
55  return (Flags & AccessSizeMask) >> AccessSizeShift;
56 }
57 
58 static inline unsigned getCCValues(unsigned int Flags) {
59  return (Flags & CCValuesMask) >> CCValuesShift;
60 }
61 
62 static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
64 }
65 
66 // SystemZ MachineOperand target flags.
67 enum {
68  // Masks out the bits for the access model.
69  MO_SYMBOL_MODIFIER = (3 << 0),
70 
71  // @GOT (aka @GOTENT)
72  MO_GOT = (1 << 0),
73 
74  // @INDNTPOFF
75  MO_INDNTPOFF = (2 << 0)
76 };
77 
78 // Classifies a branch.
79 enum BranchType {
80  // An instruction that branches on the current value of CC.
82 
83  // An instruction that peforms a 32-bit signed comparison and branches
84  // on the result.
86 
87  // An instruction that peforms a 32-bit unsigned comparison and branches
88  // on the result.
90 
91  // An instruction that peforms a 64-bit signed comparison and branches
92  // on the result.
94 
95  // An instruction that peforms a 64-bit unsigned comparison and branches
96  // on the result.
98 
99  // An instruction that decrements a 32-bit register and branches if
100  // the result is nonzero.
102 
103  // An instruction that decrements a 64-bit register and branches if
104  // the result is nonzero.
106 
107  // An instruction representing an asm goto statement.
109 };
110 
111 // Information about a branch instruction.
112 class Branch {
113  // The target of the branch. In case of INLINEASM_BR, this is nullptr.
114  const MachineOperand *Target;
115 
116 public:
117  // The type of the branch.
119 
120  // CCMASK_<N> is set if CC might be equal to N.
121  unsigned CCValid;
122 
123  // CCMASK_<N> is set if the branch should be taken when CC == N.
124  unsigned CCMask;
125 
126  Branch(BranchType type, unsigned ccValid, unsigned ccMask,
127  const MachineOperand *target)
128  : Target(target), Type(type), CCValid(ccValid), CCMask(ccMask) {}
129 
130  bool isIndirect() { return Target != nullptr && Target->isReg(); }
131  bool hasMBBTarget() { return Target != nullptr && Target->isMBB(); }
133  return hasMBBTarget() ? Target->getMBB() : nullptr;
134  }
135 };
136 
137 // Kinds of fused compares in compare-and-* instructions. Together with type
138 // of the converted compare, this identifies the compare-and-*
139 // instruction.
141  // Relative branch - CRJ etc.
143 
144  // Indirect branch, used for return - CRBReturn etc.
146 
147  // Indirect branch, used for sibcall - CRBCall etc.
149 
150  // Trap
152 };
153 
154 } // end namespace SystemZII
155 
156 namespace SystemZ {
157 int getTwoOperandOpcode(uint16_t Opcode);
158 int getTargetMemOpcode(uint16_t Opcode);
159 
160 // Return a version of comparison CC mask CCMask in which the LT and GT
161 // actions are swapped.
162 unsigned reverseCCMask(unsigned CCMask);
163 
164 // Create a new basic block after MBB.
165 MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB);
166 // Split MBB after MI and return the new block (the one that contains
167 // instructions after MI).
169  MachineBasicBlock *MBB);
170 // Split MBB before MI and return the new block (the one that contains MI).
172  MachineBasicBlock *MBB);
173 }
174 
176  const SystemZRegisterInfo RI;
177  SystemZSubtarget &STI;
178 
179  void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
180  void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
181  void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
182  bool ConvertHigh) const;
183  void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
184  unsigned LowOpcodeK, unsigned HighOpcode) const;
185  void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
186  unsigned HighOpcode) const;
187  void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
188  unsigned HighOpcode) const;
189  void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
190  unsigned Size) const;
191  void expandLoadStackGuard(MachineInstr *MI) const;
192 
195  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
196  unsigned LowLowOpcode, unsigned Size, bool KillSrc,
197  bool UndefSrc) const;
198 
199  virtual void anchor();
200 
201 protected:
202  /// Commutes the operands in the given instruction by changing the operands
203  /// order and/or changing the instruction's opcode and/or the immediate value
204  /// operand.
205  ///
206  /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
207  /// to be commuted.
208  ///
209  /// Do not call this method for a non-commutable instruction or
210  /// non-commutable operands.
211  /// Even though the instruction is commutable, the method may still
212  /// fail to commute the operands, null pointer is returned in such cases.
214  unsigned CommuteOpIdx1,
215  unsigned CommuteOpIdx2) const override;
216 
217 public:
218  explicit SystemZInstrInfo(SystemZSubtarget &STI);
219 
220  // Override TargetInstrInfo.
221  unsigned isLoadFromStackSlot(const MachineInstr &MI,
222  int &FrameIndex) const override;
223  unsigned isStoreToStackSlot(const MachineInstr &MI,
224  int &FrameIndex) const override;
225  bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
226  int &SrcFrameIndex) const override;
228  MachineBasicBlock *&FBB,
230  bool AllowModify) const override;
232  int *BytesRemoved = nullptr) const override;
235  const DebugLoc &DL,
236  int *BytesAdded = nullptr) const override;
237  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
238  Register &SrcReg2, int64_t &Mask,
239  int64_t &Value) const override;
241  Register, Register, Register, int &, int &,
242  int &) const override;
244  const DebugLoc &DL, Register DstReg,
246  Register FalseReg) const override;
248  MachineRegisterInfo *MRI) const override;
249  bool isPredicable(const MachineInstr &MI) const override;
250  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
251  unsigned ExtraPredCycles,
252  BranchProbability Probability) const override;
254  unsigned NumCyclesT, unsigned ExtraPredCyclesT,
255  MachineBasicBlock &FMBB,
256  unsigned NumCyclesF, unsigned ExtraPredCyclesF,
257  BranchProbability Probability) const override;
258  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
259  BranchProbability Probability) const override;
261  ArrayRef<MachineOperand> Pred) const override;
263  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
264  bool KillSrc) const override;
267  Register SrcReg, bool isKill, int FrameIndex,
268  const TargetRegisterClass *RC,
269  const TargetRegisterInfo *TRI) const override;
272  Register DestReg, int FrameIdx,
273  const TargetRegisterClass *RC,
274  const TargetRegisterInfo *TRI) const override;
276  LiveIntervals *LIS) const override;
277  MachineInstr *
279  ArrayRef<unsigned> Ops,
281  LiveIntervals *LIS = nullptr,
282  VirtRegMap *VRM = nullptr) const override;
285  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
286  LiveIntervals *LIS = nullptr) const override;
287  bool expandPostRAPseudo(MachineInstr &MBBI) const override;
289  override;
290 
291  // Return the SystemZRegisterInfo, which this class owns.
292  const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
293 
294  // Return the size in bytes of MI.
295  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
296 
297  // Return true if MI is a conditional or unconditional branch.
298  // When returning true, set Cond to the mask of condition-code
299  // values on which the instruction will branch, and set Target
300  // to the operand that contains the branch target. This target
301  // can be a register or a basic block.
303 
304  // Get the load and store opcodes for a given register class.
306  unsigned &LoadOpcode, unsigned &StoreOpcode) const;
307 
308  // Opcode is the opcode of an instruction that has an address operand,
309  // and the caller wants to perform that instruction's operation on an
310  // address that has displacement Offset. Return the opcode of a suitable
311  // instruction (which might be Opcode itself) or 0 if no such instruction
312  // exists.
313  unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
314 
315  // If Opcode is a load instruction that has a LOAD AND TEST form,
316  // return the opcode for the testing form, otherwise return 0.
317  unsigned getLoadAndTest(unsigned Opcode) const;
318 
319  // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
320  // Mask of the R2 operand, given that only the low BitSize bits of Mask are
321  // significant. Set Start and End to the I3 and I4 operands if so.
322  bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
323  unsigned &Start, unsigned &End) const;
324 
325  // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND *
326  // operation exists, return the opcode for the latter, otherwise return 0.
327  // MI, if nonnull, is the compare instruction.
328  unsigned getFusedCompare(unsigned Opcode,
330  const MachineInstr *MI = nullptr) const;
331 
332  // Try to find all CC users of the compare instruction (MBBI) and update
333  // all of them to maintain equivalent behavior after swapping the compare
334  // operands. Return false if not all users can be conclusively found and
335  // handled. The compare instruction is *not* changed.
337 
338  // If Opcode is a LOAD opcode for with an associated LOAD AND TRAP
339  // operation exists, returh the opcode for the latter, otherwise return 0.
340  unsigned getLoadAndTrap(unsigned Opcode) const;
341 
342  // Emit code before MBBI in MI to move immediate value Value into
343  // physical register Reg.
346  unsigned Reg, uint64_t Value) const;
347 
348  // Perform target specific instruction verification.
349  bool verifyInstruction(const MachineInstr &MI,
350  StringRef &ErrInfo) const override;
351 
352  // Sometimes, it is possible for the target to tell, even without
353  // aliasing information, that two MIs access different memory
354  // addresses. This function returns true if two MIs access different
355  // memory addresses and false otherwise.
356  bool
358  const MachineInstr &MIb) const override;
359 };
360 
361 } // end namespace llvm
362 
363 #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::SystemZInstrInfo::isRxSBGMask
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
Definition: SystemZInstrInfo.cpp:1696
llvm::SystemZInstrInfo::prepareCompareSwapOperands
bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const
Definition: SystemZInstrInfo.cpp:1841
llvm::SystemZInstrInfo::getFusedCompare
unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const
Definition: SystemZInstrInfo.cpp:1725
llvm::SystemZInstrInfo::isProfitableToDupForIfCvt
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: SystemZInstrInfo.cpp:714
llvm::SystemZInstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: SystemZInstrInfo.cpp:568
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::SystemZInstrInfo::getLoadStoreOpcodes
void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const
Definition: SystemZInstrInfo.cpp:1585
llvm::SystemZII::CompareZeroCCMaskMask
@ CompareZeroCCMaskMask
Definition: SystemZInstrInfo.h:45
llvm::SystemZII::CompareAndReturn
@ CompareAndReturn
Definition: SystemZInstrInfo.h:145
llvm::SystemZInstrInfo::convertToThreeAddress
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
Definition: SystemZInstrInfo.cpp:947
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::SystemZII::BranchType
BranchType
Definition: SystemZInstrInfo.h:79
llvm::SystemZII::BranchCTG
@ BranchCTG
Definition: SystemZInstrInfo.h:105
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::SystemZII::CCIfNoSignedWrap
@ CCIfNoSignedWrap
Definition: SystemZInstrInfo.h:50
llvm::SystemZ::splitBlockAfter
MachineBasicBlock * splitBlockAfter(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
Definition: SystemZInstrInfo.cpp:1897
llvm::SystemZ::emitBlockAfter
MachineBasicBlock * emitBlockAfter(MachineBasicBlock *MBB)
Definition: SystemZInstrInfo.cpp:1890
llvm::SystemZII::Branch::hasMBBTarget
bool hasMBBTarget()
Definition: SystemZInstrInfo.h:131
llvm::SystemZII::getCCValues
static unsigned getCCValues(unsigned int Flags)
Definition: SystemZInstrInfo.h:58
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::SystemZInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: SystemZInstrInfo.cpp:472
MachineBasicBlock.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
TargetInstrInfo.h
llvm::SystemZ::splitBlockBefore
MachineBasicBlock * splitBlockBefore(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
Definition: SystemZInstrInfo.cpp:1906
llvm::SystemZII::CompareAndBranch
@ CompareAndBranch
Definition: SystemZInstrInfo.h:142
llvm::SystemZInstrInfo::loadImmediate
void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const
Definition: SystemZInstrInfo.cpp:1933
SystemZGenInstrInfo
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::SystemZInstrInfo
Definition: SystemZInstrInfo.h:175
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::SystemZInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: SystemZInstrInfo.cpp:478
llvm::SystemZII::Branch::Branch
Branch(BranchType type, unsigned ccValid, unsigned ccMask, const MachineOperand *target)
Definition: SystemZInstrInfo.h:126
llvm::SystemZInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: SystemZInstrInfo.cpp:1987
llvm::SystemZInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
Definition: SystemZInstrInfo.cpp:610
llvm::SystemZInstrInfo::verifyInstruction
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Definition: SystemZInstrInfo.cpp:1964
llvm::SystemZII::Branch::CCValid
unsigned CCValid
Definition: SystemZInstrInfo.h:121
llvm::SystemZII::AccessSizeMask
@ AccessSizeMask
Definition: SystemZInstrInfo.h:41
llvm::SystemZII::CCValuesShift
@ CCValuesShift
Definition: SystemZInstrInfo.h:44
llvm::SystemZInstrInfo::isProfitableToIfCvt
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: SystemZInstrInfo.cpp:685
llvm::SystemZII::CCValuesMask
@ CCValuesMask
Definition: SystemZInstrInfo.h:43
llvm::SystemZII::CompareAndTrap
@ CompareAndTrap
Definition: SystemZInstrInfo.h:151
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SystemZII::getCompareZeroCCMask
static unsigned getCompareZeroCCMask(unsigned int Flags)
Definition: SystemZInstrInfo.h:62
llvm::SystemZInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MBBI) const override
Definition: SystemZInstrInfo.cpp:1337
llvm::SystemZInstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Definition: SystemZInstrInfo.cpp:998
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::SystemZII::MO_GOT
@ MO_GOT
Definition: SystemZInstrInfo.h:72
llvm::SystemZInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SystemZInstrInfo.cpp:878
llvm::SystemZInstrInfo::getLoadAndTrap
unsigned getLoadAndTrap(unsigned Opcode) const
Definition: SystemZInstrInfo.cpp:1914
llvm::SystemZInstrInfo::getBranchInfo
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
Definition: SystemZInstrInfo.cpp:1533
llvm::SystemZII::Branch::getMBBTarget
MachineBasicBlock * getMBBTarget()
Definition: SystemZInstrInfo.h:132
SystemZ.h
llvm::SystemZII::Branch
Definition: SystemZInstrInfo.h:112
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SystemZ::reverseCCMask
unsigned reverseCCMask(unsigned CCMask)
Definition: SystemZInstrInfo.cpp:1883
llvm::SystemZII::HasIndex
@ HasIndex
Definition: SystemZInstrInfo.h:39
llvm::SystemZII::BranchCG
@ BranchCG
Definition: SystemZInstrInfo.h:93
llvm::SystemZII::AccessSizeShift
@ AccessSizeShift
Definition: SystemZInstrInfo.h:42
type
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference and DH registers in an instruction requiring REX prefix divb and mulb both produce results in AH If isel emits a CopyFromReg which gets turned into a movb and that can be allocated a r8b r15b To get around isel emits a CopyFromReg from AX and then right shift it down by and truncate it It s not pretty but it works We need some register allocation magic to make the hack go which would often require a callee saved register Callees usually need to keep this value live for most of their body so it doesn t add a significant burden on them We currently implement this in however this is suboptimal because it means that it would be quite awkward to implement the optimization for callers A better implementation would be to relax the LLVM IR rules for sret arguments to allow a function with an sret argument to have a non void return type
Definition: README-X86-64.txt:70
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::SystemZII::BranchC
@ BranchC
Definition: SystemZInstrInfo.h:85
llvm::SystemZII::BranchNormal
@ BranchNormal
Definition: SystemZInstrInfo.h:81
llvm::SystemZII::FusedCompareType
FusedCompareType
Definition: SystemZInstrInfo.h:140
llvm::SystemZII::Is128Bit
@ Is128Bit
Definition: SystemZInstrInfo.h:40
llvm::SystemZII::BranchCT
@ BranchCT
Definition: SystemZInstrInfo.h:101
llvm::SystemZII::CompareZeroCCMaskShift
@ CompareZeroCCMaskShift
Definition: SystemZInstrInfo.h:46
llvm::SystemZII::MemMemOp
@ MemMemOp
Definition: SystemZInstrInfo.h:51
llvm::SystemZII::Branch::CCMask
unsigned CCMask
Definition: SystemZInstrInfo.h:124
llvm::SystemZInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: SystemZInstrInfo.cpp:446
ArrayRef.h
llvm::SystemZII::SimpleBDXLoad
@ SimpleBDXLoad
Definition: SystemZInstrInfo.h:36
llvm::SystemZInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SystemZInstrInfo.cpp:863
llvm::SystemZII::CCMaskLast
@ CCMaskLast
Definition: SystemZInstrInfo.h:48
llvm::SystemZSubtarget
Definition: SystemZSubtarget.h:33
llvm::SystemZInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: SystemZInstrInfo.cpp:354
llvm::SystemZII::Branch::Type
BranchType Type
Definition: SystemZInstrInfo.h:118
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::SystemZInstrInfo::SystemZInstrInfo
SystemZInstrInfo(SystemZSubtarget &STI)
Definition: SystemZInstrInfo.cpp:59
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:237
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::SystemZII::CCMaskFirst
@ CCMaskFirst
Definition: SystemZInstrInfo.h:47
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SystemZInstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
Definition: SystemZInstrInfo.cpp:534
llvm::SystemZ::getTargetMemOpcode
int getTargetMemOpcode(uint16_t Opcode)
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SystemZII::SimpleBDXStore
@ SimpleBDXStore
Definition: SystemZInstrInfo.h:37
llvm::SystemZII::getAccessSize
static unsigned getAccessSize(unsigned int Flags)
Definition: SystemZInstrInfo.h:54
llvm::SystemZII::CompareAndSibcall
@ CompareAndSibcall
Definition: SystemZInstrInfo.h:148
llvm::SystemZII::Branch::isIndirect
bool isIndirect()
Definition: SystemZInstrInfo.h:130
uint16_t
llvm::SystemZInstrInfo::getRegisterInfo
const SystemZRegisterInfo & getRegisterInfo() const
Definition: SystemZInstrInfo.h:292
llvm::SystemZInstrInfo::PredicateInstruction
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
Definition: SystemZInstrInfo.cpp:720
llvm::SystemZII::MO_INDNTPOFF
@ MO_INDNTPOFF
Definition: SystemZInstrInfo.h:75
llvm::SystemZII::BranchCL
@ BranchCL
Definition: SystemZInstrInfo.h:89
llvm::SystemZ::getTwoOperandOpcode
int getTwoOperandOpcode(uint16_t Opcode)
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::SystemZInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Definition: SystemZInstrInfo.cpp:1516
llvm::SystemZInstrInfo::isPredicable
bool isPredicable(const MachineInstr &MI) const override
Definition: SystemZInstrInfo.cpp:674
llvm::SystemZInstrInfo::getLoadAndTest
unsigned getLoadAndTest(unsigned Opcode) const
Definition: SystemZInstrInfo.cpp:1655
SystemZRegisterInfo.h
llvm::SystemZRegisterInfo
Definition: SystemZRegisterInfo.h:134
MachineInstrBuilder.h
llvm::SystemZII::AsmGoto
@ AsmGoto
Definition: SystemZInstrInfo.h:108
llvm::SystemZII::MO_SYMBOL_MODIFIER
@ MO_SYMBOL_MODIFIER
Definition: SystemZInstrInfo.h:69
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::SystemZII::Has20BitOffset
@ Has20BitOffset
Definition: SystemZInstrInfo.h:38
llvm::SystemZInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
Definition: SystemZInstrInfo.cpp:517
llvm::SystemZII::IsLogical
@ IsLogical
Definition: SystemZInstrInfo.h:49
llvm::SystemZInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SystemZInstrInfo.cpp:321
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::SystemZInstrInfo::getOpcodeForOffset
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const
Definition: SystemZInstrInfo.cpp:1628
llvm::SystemZII::BranchCLG
@ BranchCLG
Definition: SystemZInstrInfo.h:97
llvm::LiveVariables
Definition: LiveVariables.h:46
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SystemZInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SystemZInstrInfo.cpp:326
llvm::SystemZInstrInfo::isStackSlotCopy
bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override
Definition: SystemZInstrInfo.cpp:331
llvm::SystemZInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: SystemZInstrInfo.cpp:771
MachineFunction.h
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::SystemZInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
Definition: SystemZInstrInfo.cpp:273
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24