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SystemZInstrInfo.h
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1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SystemZ implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
14 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
15 
16 #include "SystemZ.h"
17 #include "SystemZRegisterInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
23 #include <cstdint>
24 
25 #define GET_INSTRINFO_HEADER
26 #include "SystemZGenInstrInfo.inc"
27 
28 namespace llvm {
29 
30 class SystemZSubtarget;
31 
32 namespace SystemZII {
33 
34 enum {
35  // See comments in SystemZInstrFormats.td.
36  SimpleBDXLoad = (1 << 0),
37  SimpleBDXStore = (1 << 1),
38  Has20BitOffset = (1 << 2),
39  HasIndex = (1 << 3),
40  Is128Bit = (1 << 4),
41  AccessSizeMask = (31 << 5),
43  CCValuesMask = (15 << 10),
45  CompareZeroCCMaskMask = (15 << 14),
47  CCMaskFirst = (1 << 18),
48  CCMaskLast = (1 << 19),
49  IsLogical = (1 << 20)
50 };
51 
52 static inline unsigned getAccessSize(unsigned int Flags) {
53  return (Flags & AccessSizeMask) >> AccessSizeShift;
54 }
55 
56 static inline unsigned getCCValues(unsigned int Flags) {
57  return (Flags & CCValuesMask) >> CCValuesShift;
58 }
59 
60 static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
62 }
63 
64 // SystemZ MachineOperand target flags.
65 enum {
66  // Masks out the bits for the access model.
67  MO_SYMBOL_MODIFIER = (3 << 0),
68 
69  // @GOT (aka @GOTENT)
70  MO_GOT = (1 << 0),
71 
72  // @INDNTPOFF
73  MO_INDNTPOFF = (2 << 0)
74 };
75 
76 // Classifies a branch.
77 enum BranchType {
78  // An instruction that branches on the current value of CC.
80 
81  // An instruction that peforms a 32-bit signed comparison and branches
82  // on the result.
84 
85  // An instruction that peforms a 32-bit unsigned comparison and branches
86  // on the result.
88 
89  // An instruction that peforms a 64-bit signed comparison and branches
90  // on the result.
92 
93  // An instruction that peforms a 64-bit unsigned comparison and branches
94  // on the result.
96 
97  // An instruction that decrements a 32-bit register and branches if
98  // the result is nonzero.
100 
101  // An instruction that decrements a 64-bit register and branches if
102  // the result is nonzero.
104 };
105 
106 // Information about a branch instruction.
107 struct Branch {
108  // The type of the branch.
110 
111  // CCMASK_<N> is set if CC might be equal to N.
112  unsigned CCValid;
113 
114  // CCMASK_<N> is set if the branch should be taken when CC == N.
115  unsigned CCMask;
116 
117  // The target of the branch.
119 
120  Branch(BranchType type, unsigned ccValid, unsigned ccMask,
121  const MachineOperand *target)
122  : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
123 };
124 
125 // Kinds of fused compares in compare-and-* instructions. Together with type
126 // of the converted compare, this identifies the compare-and-*
127 // instruction.
129  // Relative branch - CRJ etc.
131 
132  // Indirect branch, used for return - CRBReturn etc.
134 
135  // Indirect branch, used for sibcall - CRBCall etc.
137 
138  // Trap
140 };
141 
142 } // end namespace SystemZII
143 
144 namespace SystemZ {
145 int getTwoOperandOpcode(uint16_t Opcode);
146 int getTargetMemOpcode(uint16_t Opcode);
147 }
148 
150  const SystemZRegisterInfo RI;
151  SystemZSubtarget &STI;
152 
153  void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
154  void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
155  void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
156  bool ConvertHigh) const;
157  void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
158  unsigned LowOpcodeK, unsigned HighOpcode) const;
159  void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
160  unsigned HighOpcode) const;
161  void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
162  unsigned HighOpcode) const;
163  void expandLOCRPseudo(MachineInstr &MI, unsigned LowOpcode,
164  unsigned HighOpcode) const;
165  void expandSELRPseudo(MachineInstr &MI, unsigned LowOpcode,
166  unsigned HighOpcode, unsigned MixedOpcode) const;
167  void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
168  unsigned Size) const;
169  void expandLoadStackGuard(MachineInstr *MI) const;
170 
172  emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
173  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
174  unsigned LowLowOpcode, unsigned Size, bool KillSrc,
175  bool UndefSrc) const;
176 
177  virtual void anchor();
178 
179 protected:
180  /// Commutes the operands in the given instruction by changing the operands
181  /// order and/or changing the instruction's opcode and/or the immediate value
182  /// operand.
183  ///
184  /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
185  /// to be commuted.
186  ///
187  /// Do not call this method for a non-commutable instruction or
188  /// non-commutable operands.
189  /// Even though the instruction is commutable, the method may still
190  /// fail to commute the operands, null pointer is returned in such cases.
191  MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
192  unsigned CommuteOpIdx1,
193  unsigned CommuteOpIdx2) const override;
194 
195 public:
196  explicit SystemZInstrInfo(SystemZSubtarget &STI);
197 
198  // Override TargetInstrInfo.
199  unsigned isLoadFromStackSlot(const MachineInstr &MI,
200  int &FrameIndex) const override;
201  unsigned isStoreToStackSlot(const MachineInstr &MI,
202  int &FrameIndex) const override;
203  bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
204  int &SrcFrameIndex) const override;
205  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
206  MachineBasicBlock *&FBB,
208  bool AllowModify) const override;
209  unsigned removeBranch(MachineBasicBlock &MBB,
210  int *BytesRemoved = nullptr) const override;
211  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
213  const DebugLoc &DL,
214  int *BytesAdded = nullptr) const override;
215  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
216  unsigned &SrcReg2, int &Mask, int &Value) const override;
217  bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
218  unsigned, unsigned, int&, int&, int&) const override;
219  void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
220  const DebugLoc &DL, unsigned DstReg,
221  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
222  unsigned FalseReg) const override;
223  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
224  MachineRegisterInfo *MRI) const override;
225  bool isPredicable(const MachineInstr &MI) const override;
226  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
227  unsigned ExtraPredCycles,
228  BranchProbability Probability) const override;
229  bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
230  unsigned NumCyclesT, unsigned ExtraPredCyclesT,
231  MachineBasicBlock &FMBB,
232  unsigned NumCyclesF, unsigned ExtraPredCyclesF,
233  BranchProbability Probability) const override;
234  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
235  BranchProbability Probability) const override;
236  bool PredicateInstruction(MachineInstr &MI,
237  ArrayRef<MachineOperand> Pred) const override;
238  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
239  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
240  bool KillSrc) const override;
241  void storeRegToStackSlot(MachineBasicBlock &MBB,
243  unsigned SrcReg, bool isKill, int FrameIndex,
244  const TargetRegisterClass *RC,
245  const TargetRegisterInfo *TRI) const override;
246  void loadRegFromStackSlot(MachineBasicBlock &MBB,
248  unsigned DestReg, int FrameIdx,
249  const TargetRegisterClass *RC,
250  const TargetRegisterInfo *TRI) const override;
251  MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
252  MachineInstr &MI,
253  LiveVariables *LV) const override;
254  MachineInstr *
255  foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
256  ArrayRef<unsigned> Ops,
257  MachineBasicBlock::iterator InsertPt, int FrameIndex,
258  LiveIntervals *LIS = nullptr,
259  VirtRegMap *VRM = nullptr) const override;
260  MachineInstr *foldMemoryOperandImpl(
262  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
263  LiveIntervals *LIS = nullptr) const override;
264  bool expandPostRAPseudo(MachineInstr &MBBI) const override;
265  bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
266  override;
267 
268  // Return the SystemZRegisterInfo, which this class owns.
269  const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
270 
271  // Return the size in bytes of MI.
272  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
273 
274  // Return true if MI is a conditional or unconditional branch.
275  // When returning true, set Cond to the mask of condition-code
276  // values on which the instruction will branch, and set Target
277  // to the operand that contains the branch target. This target
278  // can be a register or a basic block.
279  SystemZII::Branch getBranchInfo(const MachineInstr &MI) const;
280 
281  // Get the load and store opcodes for a given register class.
282  void getLoadStoreOpcodes(const TargetRegisterClass *RC,
283  unsigned &LoadOpcode, unsigned &StoreOpcode) const;
284 
285  // Opcode is the opcode of an instruction that has an address operand,
286  // and the caller wants to perform that instruction's operation on an
287  // address that has displacement Offset. Return the opcode of a suitable
288  // instruction (which might be Opcode itself) or 0 if no such instruction
289  // exists.
290  unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
291 
292  // If Opcode is a load instruction that has a LOAD AND TEST form,
293  // return the opcode for the testing form, otherwise return 0.
294  unsigned getLoadAndTest(unsigned Opcode) const;
295 
296  // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
297  // Mask of the R2 operand, given that only the low BitSize bits of Mask are
298  // significant. Set Start and End to the I3 and I4 operands if so.
299  bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
300  unsigned &Start, unsigned &End) const;
301 
302  // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND *
303  // operation exists, return the opcode for the latter, otherwise return 0.
304  // MI, if nonnull, is the compare instruction.
305  unsigned getFusedCompare(unsigned Opcode,
307  const MachineInstr *MI = nullptr) const;
308 
309  // If Opcode is a LOAD opcode for with an associated LOAD AND TRAP
310  // operation exists, returh the opcode for the latter, otherwise return 0.
311  unsigned getLoadAndTrap(unsigned Opcode) const;
312 
313  // Emit code before MBBI in MI to move immediate value Value into
314  // physical register Reg.
315  void loadImmediate(MachineBasicBlock &MBB,
317  unsigned Reg, uint64_t Value) const;
318 
319  // Sometimes, it is possible for the target to tell, even without
320  // aliasing information, that two MIs access different memory
321  // addresses. This function returns true if two MIs access different
322  // memory addresses and false otherwise.
323  bool
324  areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
325  const MachineInstr &MIb,
326  AliasAnalysis *AA = nullptr) const override;
327 };
328 
329 } // end namespace llvm
330 
331 #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
const SystemZRegisterInfo & getRegisterInfo() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
int getTargetMemOpcode(uint16_t Opcode)
unsigned Reg
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Branch(BranchType type, unsigned ccValid, unsigned ccMask, const MachineOperand *target)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
const MachineOperand * Target
int getTwoOperandOpcode(uint16_t Opcode)
BasicBlockListType::iterator iterator
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
static unsigned getAccessSize(unsigned int Flags)
MachineInstrBuilder & UseMI
static void expandLoadStackGuard(MachineInstrBuilder &MIB, const TargetInstrInfo &TII)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static unsigned getCompareZeroCCMask(unsigned int Flags)
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
static unsigned getCCValues(unsigned int Flags)
uint32_t Size
Definition: Profile.cpp:46
LLVM Value Representation.
Definition: Value.h:72
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI