47#define GET_INSTRINFO_CTOR_DTOR
48#define GET_INSTRMAP_INFO
49#include "SystemZGenInstrInfo.inc"
51#define DEBUG_TYPE "systemz-II"
55 return Count == 0 ? 0 : (
uint64_t(1) << (Count - 1) << 1) - 1;
59void SystemZInstrInfo::anchor() {}
63 RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister()),
69 unsigned NewOpcode)
const {
84 HighRegOp.
setReg(RI.getSubReg(HighRegOp.
getReg(), SystemZ::subreg_h64));
85 LowRegOp.
setReg(RI.getSubReg(LowRegOp.
getReg(), SystemZ::subreg_l64));
112 assert(HighOpcode && LowOpcode &&
"Both offsets should be in range");
115 MI->setDesc(
get(LowOpcode));
131 assert(NewOpcode &&
"No support for huge argument lists yet");
132 MI->setDesc(
get(NewOpcode));
142void SystemZInstrInfo::expandRIPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
144 bool ConvertHigh)
const {
147 MI.setDesc(
get(IsHigh ? HighOpcode : LowOpcode));
148 if (IsHigh && ConvertHigh)
149 MI.getOperand(1).setImm(
uint32_t(
MI.getOperand(1).getImm()));
156void SystemZInstrInfo::expandRIEPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
158 unsigned HighOpcode)
const {
163 if (!DestIsHigh && !SrcIsHigh)
164 MI.setDesc(
get(LowOpcodeK));
166 if (DestReg != SrcReg) {
167 emitGRX32Move(*
MI.getParent(),
MI,
MI.getDebugLoc(), DestReg, SrcReg,
168 SystemZ::LR, 32,
MI.getOperand(1).isKill(),
169 MI.getOperand(1).isUndef());
170 MI.getOperand(1).setReg(DestReg);
172 MI.setDesc(
get(DestIsHigh ? HighOpcode : LowOpcode));
173 MI.tieOperands(0, 1);
180void SystemZInstrInfo::expandRXYPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
181 unsigned HighOpcode)
const {
185 MI.getOperand(2).getImm());
186 MI.setDesc(
get(Opcode));
192void SystemZInstrInfo::expandLOCPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
193 unsigned HighOpcode)
const {
196 MI.setDesc(
get(Opcode));
202void SystemZInstrInfo::expandZExtPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
203 unsigned Size)
const {
205 emitGRX32Move(*
MI.getParent(),
MI,
MI.getDebugLoc(),
206 MI.getOperand(0).getReg(),
MI.getOperand(1).getReg(), LowOpcode,
207 Size,
MI.getOperand(1).isKill(),
MI.getOperand(1).isUndef());
213 MI.eraseFromParent();
216void SystemZInstrInfo::expandLoadStackGuard(
MachineInstr *
MI)
const {
219 const Register Reg64 =
MI->getOperand(0).getReg();
220 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
241 MI->setDesc(
get(SystemZ::LG));
254 unsigned SrcReg,
unsigned LowLowOpcode,
255 unsigned Size,
bool KillSrc,
256 bool UndefSrc)
const {
260 if (DestIsHigh && SrcIsHigh)
261 Opcode = SystemZ::RISBHH;
262 else if (DestIsHigh && !SrcIsHigh)
263 Opcode = SystemZ::RISBHL;
264 else if (!DestIsHigh && SrcIsHigh)
265 Opcode = SystemZ::RISBLH;
270 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
280 unsigned OpIdx2)
const {
283 return *
MI.getParent()->getParent()->CloneMachineInstr(&
MI);
287 switch (
MI.getOpcode()) {
288 case SystemZ::SELRMux:
289 case SystemZ::SELFHR:
292 case SystemZ::LOCRMux:
293 case SystemZ::LOCFHR:
295 case SystemZ::LOCGR: {
296 auto &WorkingMI = cloneIfNew(
MI);
298 unsigned CCValid = WorkingMI.getOperand(3).getImm();
299 unsigned CCMask = WorkingMI.getOperand(4).getImm();
300 WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
317 if ((MCID.
TSFlags & Flag) &&
MI.getOperand(1).isFI() &&
318 MI.getOperand(2).getImm() == 0 &&
MI.getOperand(3).getReg() == 0) {
319 FrameIndex =
MI.getOperand(1).getIndex();
320 return MI.getOperand(0).getReg();
326 int &FrameIndex)
const {
331 int &FrameIndex)
const {
337 int &SrcFrameIndex)
const {
340 if (
MI.getOpcode() != SystemZ::MVC || !
MI.getOperand(0).isFI() ||
341 MI.getOperand(1).getImm() != 0 || !
MI.getOperand(3).isFI() ||
342 MI.getOperand(4).getImm() != 0)
346 int64_t
Length =
MI.getOperand(2).getImm();
347 unsigned FI1 =
MI.getOperand(0).getIndex();
348 unsigned FI2 =
MI.getOperand(3).getIndex();
353 DestFrameIndex = FI1;
362 bool AllowModify)
const {
370 if (
I->isDebugInstr())
375 if (!isUnpredicatedTerminator(*
I))
385 if (!Branch.hasMBBTarget())
395 TBB = Branch.getMBBTarget();
408 I->eraseFromParent();
414 TBB = Branch.getMBBTarget();
422 TBB = Branch.getMBBTarget();
429 assert(
Cond.size() == 2 &&
TBB &&
"Should have seen a conditional branch");
433 if (
TBB != Branch.getMBBTarget())
437 unsigned OldCCValid =
Cond[0].getImm();
438 unsigned OldCCMask =
Cond[1].getImm();
439 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
450 int *BytesRemoved)
const {
451 assert(!BytesRemoved &&
"code size not handled");
459 if (
I->isDebugInstr())
466 I->eraseFromParent();
476 assert(
Cond.size() == 2 &&
"Invalid condition");
486 int *BytesAdded)
const {
492 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
494 "SystemZ branch conditions have one component!");
495 assert(!BytesAdded &&
"code size not handled");
499 assert(!FBB &&
"Unconditional branch with multiple successors!");
506 unsigned CCValid =
Cond[0].getImm();
507 unsigned CCMask =
Cond[1].getImm();
522 int64_t &
Value)
const {
523 assert(
MI.isCompare() &&
"Caller should have checked for a comparison");
525 if (
MI.getNumExplicitOperands() == 2 &&
MI.getOperand(0).isReg() &&
526 MI.getOperand(1).isImm()) {
527 SrcReg =
MI.getOperand(0).getReg();
529 Value =
MI.getOperand(1).getImm();
542 int &FalseCycles)
const {
544 if (!STI.hasLoadStoreOnCond())
546 if (Pred.
size() != 2)
552 RI.getCommonSubClass(
MRI.getRegClass(TrueReg),
MRI.getRegClass(FalseReg));
557 if ((STI.hasLoadStoreOnCond2() &&
558 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
559 SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
560 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
580 assert(Pred.
size() == 2 &&
"Invalid condition");
581 unsigned CCValid = Pred[0].getImm();
582 unsigned CCMask = Pred[1].getImm();
585 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
586 if (STI.hasMiscellaneousExtensions3())
587 Opc = SystemZ::SELRMux;
588 else if (STI.hasLoadStoreOnCond2())
589 Opc = SystemZ::LOCRMux;
592 MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
593 Register TReg =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
594 Register FReg =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
600 }
else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
601 if (STI.hasMiscellaneousExtensions3())
602 Opc = SystemZ::SELGR;
604 Opc = SystemZ::LOCGR;
616 unsigned DefOpc =
DefMI.getOpcode();
617 if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
618 DefOpc != SystemZ::LGHI)
622 int32_t ImmVal = (int32_t)
DefMI.getOperand(1).getImm();
624 unsigned UseOpc =
UseMI.getOpcode();
630 case SystemZ::SELRMux:
633 case SystemZ::LOCRMux:
634 if (!STI.hasLoadStoreOnCond2())
636 NewUseOpc = SystemZ::LOCHIMux;
640 UseIdx = 2, CommuteIdx = 1;
648 if (!STI.hasLoadStoreOnCond2())
650 NewUseOpc = SystemZ::LOCGHI;
654 UseIdx = 2, CommuteIdx = 1;
662 if (CommuteIdx != -1)
663 if (!commuteInstruction(
UseMI,
false, CommuteIdx, UseIdx))
666 bool DeleteDef =
MRI->hasOneNonDBGUse(Reg);
669 UseMI.tieOperands(0, 1);
670 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
672 DefMI.eraseFromParent();
678 unsigned Opcode =
MI.getOpcode();
679 if (Opcode == SystemZ::Return ||
680 Opcode == SystemZ::Return_XPLINK ||
681 Opcode == SystemZ::Trap ||
682 Opcode == SystemZ::CallJG ||
683 Opcode == SystemZ::CallBR)
690 unsigned NumCycles,
unsigned ExtraPredCycles,
704 return NumCycles == 1;
709 unsigned NumCyclesT,
unsigned ExtraPredCyclesT,
711 unsigned NumCyclesF,
unsigned ExtraPredCyclesF,
721 return NumCycles == 1;
726 assert(Pred.
size() == 2 &&
"Invalid condition");
727 unsigned CCValid = Pred[0].getImm();
728 unsigned CCMask = Pred[1].getImm();
729 assert(CCMask > 0 && CCMask < 15 &&
"Invalid predicate");
730 unsigned Opcode =
MI.getOpcode();
731 if (Opcode == SystemZ::Trap) {
732 MI.setDesc(
get(SystemZ::CondTrap));
738 if (Opcode == SystemZ::Return || Opcode == SystemZ::Return_XPLINK) {
739 MI.setDesc(
get(Opcode == SystemZ::Return ? SystemZ::CondReturn
740 : SystemZ::CondReturn_XPLINK));
747 if (Opcode == SystemZ::CallJG) {
749 const uint32_t *RegMask =
MI.getOperand(1).getRegMask();
752 MI.setDesc(
get(SystemZ::CallBRCL));
761 if (Opcode == SystemZ::CallBR) {
763 const uint32_t *RegMask =
MI.getOperand(1).getRegMask();
766 MI.setDesc(
get(SystemZ::CallBCR));
784 if (SystemZ::GR128BitRegClass.
contains(DestReg, SrcReg)) {
786 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
790 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
796 if (SystemZ::GRX32BitRegClass.
contains(DestReg, SrcReg)) {
797 emitGRX32Move(
MBB,
MBBI,
DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
803 if (SystemZ::VR128BitRegClass.
contains(DestReg) &&
804 SystemZ::FP128BitRegClass.
contains(SrcReg)) {
806 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
807 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
809 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
810 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
817 if (SystemZ::FP128BitRegClass.
contains(DestReg) &&
818 SystemZ::VR128BitRegClass.
contains(SrcReg)) {
820 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
821 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
823 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
824 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
826 if (DestRegHi != SrcReg)
834 if (DestReg == SystemZ::CC) {
836 SystemZ::GR32BitRegClass.contains(SrcReg) ? SystemZ::TMLH : SystemZ::TMHH;
845 if (SystemZ::GR64BitRegClass.
contains(DestReg, SrcReg))
846 Opcode = SystemZ::LGR;
847 else if (SystemZ::FP32BitRegClass.
contains(DestReg, SrcReg))
849 Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
850 else if (SystemZ::FP64BitRegClass.
contains(DestReg, SrcReg))
851 Opcode = SystemZ::LDR;
852 else if (SystemZ::FP128BitRegClass.
contains(DestReg, SrcReg))
853 Opcode = SystemZ::LXR;
854 else if (SystemZ::VR32BitRegClass.
contains(DestReg, SrcReg))
855 Opcode = SystemZ::VLR32;
856 else if (SystemZ::VR64BitRegClass.
contains(DestReg, SrcReg))
857 Opcode = SystemZ::VLR64;
858 else if (SystemZ::VR128BitRegClass.
contains(DestReg, SrcReg))
859 Opcode = SystemZ::VLR;
860 else if (SystemZ::AR32BitRegClass.
contains(DestReg, SrcReg))
861 Opcode = SystemZ::CPYA;
877 unsigned LoadOpcode, StoreOpcode;
894 unsigned LoadOpcode, StoreOpcode;
904 return ((MCID.
TSFlags & Flag) &&
905 isUInt<12>(
MI->getOperand(2).getImm()) &&
906 MI->getOperand(3).getReg() == 0);
913 LogicOp(
unsigned regSize,
unsigned immLSB,
unsigned immSize)
914 :
RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
920 unsigned ImmSize = 0;
927 case SystemZ::NILMux:
return LogicOp(32, 0, 16);
928 case SystemZ::NIHMux:
return LogicOp(32, 16, 16);
929 case SystemZ::NILL64:
return LogicOp(64, 0, 16);
930 case SystemZ::NILH64:
return LogicOp(64, 16, 16);
931 case SystemZ::NIHL64:
return LogicOp(64, 32, 16);
932 case SystemZ::NIHH64:
return LogicOp(64, 48, 16);
933 case SystemZ::NIFMux:
return LogicOp(32, 0, 32);
934 case SystemZ::NILF64:
return LogicOp(64, 0, 32);
935 case SystemZ::NIHF64:
return LogicOp(64, 32, 32);
936 default:
return LogicOp();
943 if (CCDef !=
nullptr)
968 if (
And.RegSize == 64) {
969 NewOpcode = SystemZ::RISBG;
971 if (STI.hasMiscellaneousExtensions())
972 NewOpcode = SystemZ::RISBGN;
974 NewOpcode = SystemZ::RISBMux;
990 unsigned NumOps =
MI.getNumOperands();
991 for (
unsigned I = 1;
I < NumOps; ++
I) {
993 if (
Op.isReg() &&
Op.isKill())
1014 unsigned Opcode =
MI.getOpcode();
1019 bool CCLiveAtMI =
true;
1024 CCLiveRange = &LIS->
getRegUnit(*CCUnits.begin());
1025 CCLiveAtMI = CCLiveRange->
liveAt(MISlot);
1028 if (Ops.
size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1029 if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1030 isInt<8>(
MI.getOperand(2).getImm()) && !
MI.getOperand(3).getReg()) {
1033 MI.getDebugLoc(),
get(SystemZ::AGSI))
1036 .
addImm(
MI.getOperand(2).getImm());
1045 if (Ops.
size() != 1)
1048 unsigned OpNum = Ops[0];
1052 "Invalid size combination");
1054 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1055 isInt<8>(
MI.getOperand(2).getImm())) {
1057 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1059 BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
get(Opcode))
1062 .
addImm(
MI.getOperand(2).getImm());
1068 if ((Opcode == SystemZ::ALFI && OpNum == 0 &&
1069 isInt<8>((int32_t)
MI.getOperand(2).getImm())) ||
1070 (Opcode == SystemZ::ALGFI && OpNum == 0 &&
1071 isInt<8>((int64_t)
MI.getOperand(2).getImm()))) {
1073 Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);
1075 BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
get(Opcode))
1078 .
addImm((int8_t)
MI.getOperand(2).getImm());
1083 if ((Opcode == SystemZ::SLFI && OpNum == 0 &&
1084 isInt<8>((int32_t)-
MI.getOperand(2).getImm())) ||
1085 (Opcode == SystemZ::SLGFI && OpNum == 0 &&
1086 isInt<8>((int64_t)-
MI.getOperand(2).getImm()))) {
1088 Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);
1090 BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
get(Opcode))
1093 .
addImm((int8_t)-
MI.getOperand(2).getImm());
1098 unsigned MemImmOpc = 0;
1100 case SystemZ::LHIMux:
1101 case SystemZ::LHI: MemImmOpc = SystemZ::MVHI;
break;
1102 case SystemZ::LGHI: MemImmOpc = SystemZ::MVGHI;
break;
1103 case SystemZ::CHIMux:
1104 case SystemZ::CHI: MemImmOpc = SystemZ::CHSI;
break;
1105 case SystemZ::CGHI: MemImmOpc = SystemZ::CGHSI;
break;
1106 case SystemZ::CLFIMux:
1108 if (isUInt<16>(
MI.getOperand(1).getImm()))
1109 MemImmOpc = SystemZ::CLFHSI;
1111 case SystemZ::CLGFI:
1112 if (isUInt<16>(
MI.getOperand(1).getImm()))
1113 MemImmOpc = SystemZ::CLGHSI;
1118 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1122 .
addImm(
MI.getOperand(1).getImm());
1124 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1125 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1126 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1130 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1131 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1133 .
add(
MI.getOperand(1))
1141 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
1142 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1144 .
add(
MI.getOperand(0))
1164 if (OpNum == 0 &&
MI.hasOneMemOperand()) {
1169 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1174 .
add(
MI.getOperand(1))
1180 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1182 .
add(
MI.getOperand(1))
1195 unsigned NumOps =
MI.getNumExplicitOperands();
1196 int MemOpcode = SystemZ::getMemOpcode(Opcode);
1197 if (MemOpcode == -1 ||
1198 (CCLiveAtMI && !
MI.definesRegister(SystemZ::CC) &&
1199 get(MemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)))
1210 if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {
1216 !(SystemZ::FP32BitRegClass.
contains(PhysReg) ||
1217 SystemZ::FP64BitRegClass.
contains(PhysReg) ||
1218 SystemZ::VF128BitRegClass.
contains(PhysReg)))
1223 bool FusedFPOp = (Opcode == SystemZ::WFMADB || Opcode == SystemZ::WFMASB ||
1224 Opcode == SystemZ::WFMSDB || Opcode == SystemZ::WFMSSB);
1228 if (OpNum == 0 || OpNum == 3 || DstReg != AccReg)
1233 bool NeedsCommute =
false;
1234 if ((
MI.getOpcode() == SystemZ::CR ||
MI.getOpcode() == SystemZ::CGR ||
1235 MI.getOpcode() == SystemZ::CLR ||
MI.getOpcode() == SystemZ::CLGR ||
1236 MI.getOpcode() == SystemZ::WFCDB ||
MI.getOpcode() == SystemZ::WFCSB ||
1237 MI.getOpcode() == SystemZ::WFKDB ||
MI.getOpcode() == SystemZ::WFKSB) &&
1239 NeedsCommute =
true;
1241 bool CCOperands =
false;
1242 if (
MI.getOpcode() == SystemZ::LOCRMux ||
MI.getOpcode() == SystemZ::LOCGR ||
1243 MI.getOpcode() == SystemZ::SELRMux ||
MI.getOpcode() == SystemZ::SELGR) {
1244 assert(
MI.getNumOperands() == 6 && NumOps == 5 &&
1245 "LOCR/SELR instruction operands corrupt?");
1260 Register SrcReg = (OpNum == 2 ?
MI.getOperand(1).getReg()
1261 : ((OpNum == 1 &&
MI.isCommutable())
1262 ?
MI.getOperand(2).getReg()
1264 if (DstPhys && !SystemZ::GRH32BitRegClass.
contains(DstPhys) && SrcReg &&
1266 NeedsCommute = (OpNum == 1);
1272 if ((OpNum == NumOps - 1) || NeedsCommute || FusedFPOp) {
1275 assert(AccessBytes != 0 &&
"Size of access should be known");
1276 assert(AccessBytes <=
Size &&
"Access outside the frame index");
1279 MI.getDebugLoc(),
get(MemOpcode));
1280 if (
MI.isCompare()) {
1281 assert(NumOps == 2 &&
"Expected 2 register operands for a compare.");
1282 MIB.
add(
MI.getOperand(NeedsCommute ? 1 : 0));
1284 else if (FusedFPOp) {
1285 MIB.
add(
MI.getOperand(0));
1286 MIB.
add(
MI.getOperand(3));
1287 MIB.
add(
MI.getOperand(OpNum == 1 ? 2 : 1));
1290 MIB.
add(
MI.getOperand(0));
1292 MIB.
add(
MI.getOperand(2));
1294 for (
unsigned I = 1;
I < OpNum; ++
I)
1295 MIB.
add(
MI.getOperand(
I));
1301 unsigned CCValid =
MI.getOperand(NumOps).getImm();
1302 unsigned CCMask =
MI.getOperand(NumOps + 1).getImm();
1304 MIB.
addImm(NeedsCommute ? CCMask ^ CCValid : CCMask);
1307 (!
MI.definesRegister(SystemZ::CC) ||
1308 MI.registerDefIsDead(SystemZ::CC))) {
1316 if (MO.isReg() && MO.getReg().isVirtual()) {
1318 if (
MRI.getRegClass(Reg) == &SystemZ::VR32BitRegClass)
1319 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass);
1320 else if (
MRI.getRegClass(Reg) == &SystemZ::VR64BitRegClass)
1321 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass);
1322 else if (
MRI.getRegClass(Reg) == &SystemZ::VR128BitRegClass)
1323 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass);
1343 switch (
MI.getOpcode()) {
1345 splitMove(
MI, SystemZ::LG);
1348 case SystemZ::ST128:
1349 splitMove(
MI, SystemZ::STG);
1353 splitMove(
MI, SystemZ::LD);
1357 splitMove(
MI, SystemZ::STD);
1360 case SystemZ::LBMux:
1361 expandRXYPseudo(
MI, SystemZ::LB, SystemZ::LBH);
1364 case SystemZ::LHMux:
1365 expandRXYPseudo(
MI, SystemZ::LH, SystemZ::LHH);
1368 case SystemZ::LLCRMux:
1369 expandZExtPseudo(
MI, SystemZ::LLCR, 8);
1372 case SystemZ::LLHRMux:
1373 expandZExtPseudo(
MI, SystemZ::LLHR, 16);
1376 case SystemZ::LLCMux:
1377 expandRXYPseudo(
MI, SystemZ::LLC, SystemZ::LLCH);
1380 case SystemZ::LLHMux:
1381 expandRXYPseudo(
MI, SystemZ::LLH, SystemZ::LLHH);
1385 expandRXYPseudo(
MI, SystemZ::L, SystemZ::LFH);
1388 case SystemZ::LOCMux:
1389 expandLOCPseudo(
MI, SystemZ::LOC, SystemZ::LOCFH);
1392 case SystemZ::LOCHIMux:
1393 expandLOCPseudo(
MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1396 case SystemZ::STCMux:
1397 expandRXYPseudo(
MI, SystemZ::STC, SystemZ::STCH);
1400 case SystemZ::STHMux:
1401 expandRXYPseudo(
MI, SystemZ::STH, SystemZ::STHH);
1404 case SystemZ::STMux:
1405 expandRXYPseudo(
MI, SystemZ::ST, SystemZ::STFH);
1408 case SystemZ::STOCMux:
1409 expandLOCPseudo(
MI, SystemZ::STOC, SystemZ::STOCFH);
1412 case SystemZ::LHIMux:
1413 expandRIPseudo(
MI, SystemZ::LHI, SystemZ::IIHF,
true);
1416 case SystemZ::IIFMux:
1417 expandRIPseudo(
MI, SystemZ::IILF, SystemZ::IIHF,
false);
1420 case SystemZ::IILMux:
1421 expandRIPseudo(
MI, SystemZ::IILL, SystemZ::IIHL,
false);
1424 case SystemZ::IIHMux:
1425 expandRIPseudo(
MI, SystemZ::IILH, SystemZ::IIHH,
false);
1428 case SystemZ::NIFMux:
1429 expandRIPseudo(
MI, SystemZ::NILF, SystemZ::NIHF,
false);
1432 case SystemZ::NILMux:
1433 expandRIPseudo(
MI, SystemZ::NILL, SystemZ::NIHL,
false);
1436 case SystemZ::NIHMux:
1437 expandRIPseudo(
MI, SystemZ::NILH, SystemZ::NIHH,
false);
1440 case SystemZ::OIFMux:
1441 expandRIPseudo(
MI, SystemZ::OILF, SystemZ::OIHF,
false);
1444 case SystemZ::OILMux:
1445 expandRIPseudo(
MI, SystemZ::OILL, SystemZ::OIHL,
false);
1448 case SystemZ::OIHMux:
1449 expandRIPseudo(
MI, SystemZ::OILH, SystemZ::OIHH,
false);
1452 case SystemZ::XIFMux:
1453 expandRIPseudo(
MI, SystemZ::XILF, SystemZ::XIHF,
false);
1456 case SystemZ::TMLMux:
1457 expandRIPseudo(
MI, SystemZ::TMLL, SystemZ::TMHL,
false);
1460 case SystemZ::TMHMux:
1461 expandRIPseudo(
MI, SystemZ::TMLH, SystemZ::TMHH,
false);
1464 case SystemZ::AHIMux:
1465 expandRIPseudo(
MI, SystemZ::AHI, SystemZ::AIH,
false);
1468 case SystemZ::AHIMuxK:
1469 expandRIEPseudo(
MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1472 case SystemZ::AFIMux:
1473 expandRIPseudo(
MI, SystemZ::AFI, SystemZ::AIH,
false);
1476 case SystemZ::CHIMux:
1477 expandRIPseudo(
MI, SystemZ::CHI, SystemZ::CIH,
false);
1480 case SystemZ::CFIMux:
1481 expandRIPseudo(
MI, SystemZ::CFI, SystemZ::CIH,
false);
1484 case SystemZ::CLFIMux:
1485 expandRIPseudo(
MI, SystemZ::CLFI, SystemZ::CLIH,
false);
1489 expandRXYPseudo(
MI, SystemZ::C, SystemZ::CHF);
1492 case SystemZ::CLMux:
1493 expandRXYPseudo(
MI, SystemZ::CL, SystemZ::CLHF);
1496 case SystemZ::RISBMux: {
1499 if (SrcIsHigh == DestIsHigh)
1500 MI.setDesc(
get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1502 MI.setDesc(
get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1503 MI.getOperand(5).setImm(
MI.getOperand(5).getImm() ^ 32);
1508 case SystemZ::ADJDYNALLOC:
1509 splitAdjDynAlloc(
MI);
1512 case TargetOpcode::LOAD_STACK_GUARD:
1513 expandLoadStackGuard(&
MI);
1522 if (
MI.isInlineAsm()) {
1524 const char *AsmStr =
MI.getOperand(0).getSymbolName();
1527 else if (
MI.getOpcode() == SystemZ::PATCHPOINT)
1529 else if (
MI.getOpcode() == SystemZ::STACKMAP)
1530 return MI.getOperand(1).getImm();
1531 else if (
MI.getOpcode() == SystemZ::FENTRY_CALL)
1534 return MI.getDesc().getSize();
1539 switch (
MI.getOpcode()) {
1550 MI.getOperand(1).getImm(), &
MI.getOperand(2));
1553 case SystemZ::BRCTH:
1557 case SystemZ::BRCTG:
1564 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1569 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1574 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1576 case SystemZ::CLGIJ:
1577 case SystemZ::CLGRJ:
1579 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1581 case SystemZ::INLINEASM_BR:
1591 unsigned &LoadOpcode,
1592 unsigned &StoreOpcode)
const {
1593 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1594 LoadOpcode = SystemZ::L;
1595 StoreOpcode = SystemZ::ST;
1596 }
else if (RC == &SystemZ::GRH32BitRegClass) {
1597 LoadOpcode = SystemZ::LFH;
1598 StoreOpcode = SystemZ::STFH;
1599 }
else if (RC == &SystemZ::GRX32BitRegClass) {
1600 LoadOpcode = SystemZ::LMux;
1601 StoreOpcode = SystemZ::STMux;
1602 }
else if (RC == &SystemZ::GR64BitRegClass ||
1603 RC == &SystemZ::ADDR64BitRegClass) {
1604 LoadOpcode = SystemZ::LG;
1605 StoreOpcode = SystemZ::STG;
1606 }
else if (RC == &SystemZ::GR128BitRegClass ||
1607 RC == &SystemZ::ADDR128BitRegClass) {
1608 LoadOpcode = SystemZ::L128;
1609 StoreOpcode = SystemZ::ST128;
1610 }
else if (RC == &SystemZ::FP32BitRegClass) {
1611 LoadOpcode = SystemZ::LE;
1612 StoreOpcode = SystemZ::STE;
1613 }
else if (RC == &SystemZ::FP64BitRegClass) {
1614 LoadOpcode = SystemZ::LD;
1615 StoreOpcode = SystemZ::STD;
1616 }
else if (RC == &SystemZ::FP128BitRegClass) {
1617 LoadOpcode = SystemZ::LX;
1618 StoreOpcode = SystemZ::STX;
1619 }
else if (RC == &SystemZ::VR32BitRegClass) {
1620 LoadOpcode = SystemZ::VL32;
1621 StoreOpcode = SystemZ::VST32;
1622 }
else if (RC == &SystemZ::VR64BitRegClass) {
1623 LoadOpcode = SystemZ::VL64;
1624 StoreOpcode = SystemZ::VST64;
1625 }
else if (RC == &SystemZ::VF128BitRegClass ||
1626 RC == &SystemZ::VR128BitRegClass) {
1627 LoadOpcode = SystemZ::VL;
1628 StoreOpcode = SystemZ::VST;
1638 if (isUInt<12>(
Offset) && isUInt<12>(Offset2)) {
1640 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1641 if (Disp12Opcode >= 0)
1642 return Disp12Opcode;
1648 if (isInt<20>(
Offset) && isInt<20>(Offset2)) {
1650 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1651 if (Disp20Opcode >= 0)
1652 return Disp20Opcode;
1659 if (
MI &&
MI->getOperand(0).isReg()) {
1664 return SystemZ::LEY;
1665 case SystemZ::VST32:
1666 return SystemZ::STEY;
1668 return SystemZ::LDY;
1669 case SystemZ::VST64:
1670 return SystemZ::STDY;
1682 return SystemZ::getDisp12Opcode(Opcode) >= 0;
1683 return SystemZ::getDisp20Opcode(Opcode) >= 0;
1688 case SystemZ::L:
return SystemZ::LT;
1689 case SystemZ::LY:
return SystemZ::LT;
1690 case SystemZ::LG:
return SystemZ::LTG;
1691 case SystemZ::LGF:
return SystemZ::LTGF;
1692 case SystemZ::LR:
return SystemZ::LTR;
1693 case SystemZ::LGFR:
return SystemZ::LTGFR;
1694 case SystemZ::LGR:
return SystemZ::LTGR;
1695 case SystemZ::LER:
return SystemZ::LTEBR;
1696 case SystemZ::LDR:
return SystemZ::LTDBR;
1697 case SystemZ::LXR:
return SystemZ::LTXBR;
1698 case SystemZ::LCDFR:
return SystemZ::LCDBR;
1699 case SystemZ::LPDFR:
return SystemZ::LPDBR;
1700 case SystemZ::LNDFR:
return SystemZ::LNDBR;
1701 case SystemZ::LCDFR_32:
return SystemZ::LCEBR;
1702 case SystemZ::LPDFR_32:
return SystemZ::LPEBR;
1703 case SystemZ::LNDFR_32:
return SystemZ::LNEBR;
1708 case SystemZ::RISBGN:
return SystemZ::RISBG;
1714 unsigned &Start,
unsigned &
End)
const {
1724 Start = 63 - (LSB +
Length - 1);
1732 assert(LSB > 0 &&
"Bottom bit must be set");
1733 assert(LSB +
Length < BitSize &&
"Top bit must be set");
1734 Start = 63 - (LSB - 1);
1748 if (!(
MI && isInt<8>(
MI->getOperand(1).getImm())))
1752 case SystemZ::CLGFI:
1753 if (!(
MI && isUInt<8>(
MI->getOperand(1).getImm())))
1758 if (!STI.hasMiscellaneousExtensions())
1760 if (!(
MI &&
MI->getOperand(3).getReg() == 0))
1768 return SystemZ::CRJ;
1770 return SystemZ::CGRJ;
1772 return SystemZ::CIJ;
1774 return SystemZ::CGIJ;
1776 return SystemZ::CLRJ;
1778 return SystemZ::CLGRJ;
1780 return SystemZ::CLIJ;
1781 case SystemZ::CLGFI:
1782 return SystemZ::CLGIJ;
1789 return SystemZ::CRBReturn;
1791 return SystemZ::CGRBReturn;
1793 return SystemZ::CIBReturn;
1795 return SystemZ::CGIBReturn;
1797 return SystemZ::CLRBReturn;
1799 return SystemZ::CLGRBReturn;
1801 return SystemZ::CLIBReturn;
1802 case SystemZ::CLGFI:
1803 return SystemZ::CLGIBReturn;
1810 return SystemZ::CRBCall;
1812 return SystemZ::CGRBCall;
1814 return SystemZ::CIBCall;
1816 return SystemZ::CGIBCall;
1818 return SystemZ::CLRBCall;
1820 return SystemZ::CLGRBCall;
1822 return SystemZ::CLIBCall;
1823 case SystemZ::CLGFI:
1824 return SystemZ::CLGIBCall;
1831 return SystemZ::CRT;
1833 return SystemZ::CGRT;
1835 return SystemZ::CIT;
1837 return SystemZ::CGIT;
1839 return SystemZ::CLRT;
1841 return SystemZ::CLGRT;
1843 return SystemZ::CLFIT;
1844 case SystemZ::CLGFI:
1845 return SystemZ::CLGIT;
1847 return SystemZ::CLT;
1849 return SystemZ::CLGT;
1860 MBBI->getOperand(1).isReg() && !
MBBI->mayLoad() &&
1861 "Not a compare reg/reg.");
1867 if (
MI.readsRegister(SystemZ::CC)) {
1868 unsigned Flags =
MI.getDesc().TSFlags;
1874 if (
MI.definesRegister(SystemZ::CC)) {
1882 if (LiveRegs.
contains(SystemZ::CC))
1888 unsigned Flags = CCUsers[
Idx]->getDesc().TSFlags;
1890 0 : CCUsers[
Idx]->getNumExplicitOperands() - 2);
1893 CCMaskMO.
setImm(NewCCMask);
1931 if (!STI.hasLoadAndTrap())
1936 return SystemZ::LAT;
1938 return SystemZ::LGAT;
1940 return SystemZ::LFHAT;
1942 return SystemZ::LLGFAT;
1944 return SystemZ::LLGTAT;
1953 unsigned Opcode = 0;
1954 if (isInt<16>(
Value))
1955 Opcode = SystemZ::LGHI;
1957 Opcode = SystemZ::LLILL;
1959 Opcode = SystemZ::LLILH;
1962 else if (isInt<32>(
Value))
1963 Opcode = SystemZ::LGFI;
1970 assert (
MRI.isSSA() &&
"Huge values only handled before reg-alloc .");
1971 Register Reg0 =
MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
1972 Register Reg1 =
MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
1983 for (
unsigned I = 0,
E =
MI.getNumOperands();
I !=
E; ++
I) {
1994 ErrInfo =
"Addressing mode operands corrupt!";
2017 bool SameVal = (VALa && VALb && (VALa == VALb));
2021 if (PSVa && PSVb && (PSVa == PSVb))
2027 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
2028 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
2029 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2030 if (LowOffset + LowWidth <= HighOffset)
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag)
static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI)
static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI, MachineInstr::MIFlag Flag)
static int isSimpleMove(const MachineInstr &MI, int &FrameIndex, unsigned Flag)
static LogicOp interpretAndImmediate(unsigned Opcode)
static uint64_t allOnes(unsigned int Count)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
This class represents an Operation in the Expression.
SlotIndexes * getSlotIndexes() const
VNInfo::Allocator & getVNInfoAllocator()
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
A set of physical registers with utility functions to track liveness when walking backward/forward th...
bool contains(MCPhysReg Reg) const
Returns true if register Reg is contained in the set.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
This class represents the liveness of a register, stack slot, etc.
bool liveAt(SlotIndex index) const
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)
createDeadDef - Make sure the range has a value defined at Def.
void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
This holds information about one operand of a machine instruction, indicating the register class for ...
uint8_t OperandType
Information about the type of the operand.
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Wrapper class representing physical registers. Should be passed by value.
static MCRegister from(unsigned Val)
Check the provided unsigned value is a valid MCRegister.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
void insert(iterator MBBI, MachineBasicBlock *MBB)
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Representation of each machine instruction.
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
iterator_range< mop_iterator > operands()
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
void setFlag(MIFlag Flag)
Set a MI flag.
const MachineOperand & getOperand(unsigned i) const
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
A description of a memory reference used in the backend.
const PseudoSourceValue * getPseudoValue() const
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
uint64_t getSize() const
Return the size in bytes of the memory reference.
const Value * getValue() const
Return the base address of the memory access.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
MachineOperand class - Representation of each machine instruction operand.
void setImm(int64_t immVal)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setIsDead(bool Val=true)
void setReg(Register Reg)
Change the register this operand corresponds to.
void setIsKill(bool Val=true)
static MachineOperand CreateImm(int64_t Val)
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
MI-level patchpoint operands.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Special value supplied for machine level alias analysis.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
SlotIndex - An opaque wrapper around machine indexes.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
A SystemZ-specific class detailing special use registers particular for calling conventions.
virtual int getStackPointerBias()=0
virtual int getCallFrameSize()=0
unsigned getLoadAndTrap(unsigned Opcode) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
unsigned getLoadAndTest(unsigned Opcode) const
bool isPredicable(const MachineInstr &MI) const override
bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset, const MachineInstr *MI=nullptr) const
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
SystemZInstrInfo(SystemZSubtarget &STI)
bool hasDisplacementPairInsn(unsigned Opcode) const
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const
bool expandPostRAPseudo(MachineInstr &MBBI) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
SystemZCallingConventionRegisters * getSpecialRegisters() const
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Target - Wrapper for Target specific information.
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Undef
Value of the register doesn't matter.
static unsigned getAccessSize(unsigned int Flags)
unsigned getFirstReg(unsigned Reg)
MachineBasicBlock * splitBlockBefore(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
int getTargetMemOpcode(uint16_t Opcode)
const unsigned CCMASK_CMP_GT
const unsigned CCMASK_ANY
static bool isImmLL(uint64_t Val)
static bool isImmLH(uint64_t Val)
MachineBasicBlock * emitBlockAfter(MachineBasicBlock *MBB)
unsigned reverseCCMask(unsigned CCMask)
const unsigned CCMASK_CMP_EQ
const unsigned CCMASK_ICMP
MachineBasicBlock * splitBlockAfter(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
const unsigned CCMASK_CMP_LT
const unsigned CCMASK_CMP_NE
bool isHighReg(unsigned int Reg)
const unsigned CCMASK_CMP_UO
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
constexpr size_t range_size(R &&Range)
Returns the size of the Range, i.e., the number of elements.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
unsigned getUndefRegState(bool B)
@ And
Bitwise or logical AND of integers.
unsigned getKillRegState(bool B)