47#define GET_INSTRINFO_CTOR_DTOR
48#define GET_INSTRMAP_INFO
49#include "SystemZGenInstrInfo.inc"
51#define DEBUG_TYPE "systemz-II"
55 return Count == 0 ? 0 : (
uint64_t(1) << (Count - 1) << 1) - 1;
59void SystemZInstrInfo::anchor() {}
63 RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister()),
69 unsigned NewOpcode)
const {
85 HighRegOp.
setReg(RI.getSubReg(HighRegOp.
getReg(), SystemZ::subreg_h64));
86 LowRegOp.
setReg(RI.getSubReg(LowRegOp.
getReg(), SystemZ::subreg_l64));
97 assert(HighOpcode && LowOpcode &&
"Both offsets should be in range");
102 if (
MI->mayStore()) {
114 auto overlapsAddressReg = [&](
Register Reg) ->
bool {
115 return RI.regsOverlap(Reg,
MI->getOperand(1).getReg()) ||
116 RI.regsOverlap(Reg,
MI->getOperand(3).getReg());
118 if (overlapsAddressReg(HighRegOp.
getReg())) {
120 "Both loads clobber address!");
144 assert(NewOpcode &&
"No support for huge argument lists yet");
145 MI->setDesc(
get(NewOpcode));
155void SystemZInstrInfo::expandRIPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
157 bool ConvertHigh)
const {
160 MI.setDesc(
get(IsHigh ? HighOpcode : LowOpcode));
161 if (IsHigh && ConvertHigh)
162 MI.getOperand(1).setImm(
uint32_t(
MI.getOperand(1).getImm()));
169void SystemZInstrInfo::expandRIEPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
171 unsigned HighOpcode)
const {
176 if (!DestIsHigh && !SrcIsHigh)
177 MI.setDesc(
get(LowOpcodeK));
179 if (DestReg != SrcReg) {
180 emitGRX32Move(*
MI.getParent(),
MI,
MI.getDebugLoc(), DestReg, SrcReg,
181 SystemZ::LR, 32,
MI.getOperand(1).isKill(),
182 MI.getOperand(1).isUndef());
183 MI.getOperand(1).setReg(DestReg);
185 MI.setDesc(
get(DestIsHigh ? HighOpcode : LowOpcode));
186 MI.tieOperands(0, 1);
193void SystemZInstrInfo::expandRXYPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
194 unsigned HighOpcode)
const {
198 MI.getOperand(2).getImm());
199 MI.setDesc(
get(Opcode));
205void SystemZInstrInfo::expandLOCPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
206 unsigned HighOpcode)
const {
209 MI.setDesc(
get(Opcode));
215void SystemZInstrInfo::expandZExtPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
216 unsigned Size)
const {
218 emitGRX32Move(*
MI.getParent(),
MI,
MI.getDebugLoc(),
219 MI.getOperand(0).getReg(),
MI.getOperand(1).getReg(), LowOpcode,
220 Size,
MI.getOperand(1).isKill(),
MI.getOperand(1).isUndef());
226 MI.eraseFromParent();
229void SystemZInstrInfo::expandLoadStackGuard(
MachineInstr *
MI)
const {
232 const Register Reg64 =
MI->getOperand(0).getReg();
233 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
254 MI->setDesc(
get(SystemZ::LG));
267 unsigned SrcReg,
unsigned LowLowOpcode,
268 unsigned Size,
bool KillSrc,
269 bool UndefSrc)
const {
273 if (DestIsHigh && SrcIsHigh)
274 Opcode = SystemZ::RISBHH;
275 else if (DestIsHigh && !SrcIsHigh)
276 Opcode = SystemZ::RISBHL;
277 else if (!DestIsHigh && SrcIsHigh)
278 Opcode = SystemZ::RISBLH;
283 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
293 unsigned OpIdx2)
const {
296 return *
MI.getParent()->getParent()->CloneMachineInstr(&
MI);
300 switch (
MI.getOpcode()) {
301 case SystemZ::SELRMux:
302 case SystemZ::SELFHR:
305 case SystemZ::LOCRMux:
306 case SystemZ::LOCFHR:
308 case SystemZ::LOCGR: {
309 auto &WorkingMI = cloneIfNew(
MI);
311 unsigned CCValid = WorkingMI.getOperand(3).getImm();
312 unsigned CCMask = WorkingMI.getOperand(4).getImm();
313 WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
330 if ((MCID.
TSFlags & Flag) &&
MI.getOperand(1).isFI() &&
331 MI.getOperand(2).getImm() == 0 &&
MI.getOperand(3).getReg() == 0) {
332 FrameIndex =
MI.getOperand(1).getIndex();
333 return MI.getOperand(0).getReg();
339 int &FrameIndex)
const {
344 int &FrameIndex)
const {
350 int &SrcFrameIndex)
const {
353 if (
MI.getOpcode() != SystemZ::MVC || !
MI.getOperand(0).isFI() ||
354 MI.getOperand(1).getImm() != 0 || !
MI.getOperand(3).isFI() ||
355 MI.getOperand(4).getImm() != 0)
359 int64_t
Length =
MI.getOperand(2).getImm();
360 unsigned FI1 =
MI.getOperand(0).getIndex();
361 unsigned FI2 =
MI.getOperand(3).getIndex();
366 DestFrameIndex = FI1;
375 bool AllowModify)
const {
383 if (
I->isDebugInstr())
388 if (!isUnpredicatedTerminator(*
I))
398 if (!Branch.hasMBBTarget())
408 TBB = Branch.getMBBTarget();
421 I->eraseFromParent();
427 TBB = Branch.getMBBTarget();
435 TBB = Branch.getMBBTarget();
442 assert(
Cond.size() == 2 &&
TBB &&
"Should have seen a conditional branch");
446 if (
TBB != Branch.getMBBTarget())
450 unsigned OldCCValid =
Cond[0].getImm();
451 unsigned OldCCMask =
Cond[1].getImm();
452 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
463 int *BytesRemoved)
const {
464 assert(!BytesRemoved &&
"code size not handled");
472 if (
I->isDebugInstr())
479 I->eraseFromParent();
489 assert(
Cond.size() == 2 &&
"Invalid condition");
499 int *BytesAdded)
const {
505 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
507 "SystemZ branch conditions have one component!");
508 assert(!BytesAdded &&
"code size not handled");
512 assert(!FBB &&
"Unconditional branch with multiple successors!");
519 unsigned CCValid =
Cond[0].getImm();
520 unsigned CCMask =
Cond[1].getImm();
535 int64_t &
Value)
const {
536 assert(
MI.isCompare() &&
"Caller should have checked for a comparison");
538 if (
MI.getNumExplicitOperands() == 2 &&
MI.getOperand(0).isReg() &&
539 MI.getOperand(1).isImm()) {
540 SrcReg =
MI.getOperand(0).getReg();
542 Value =
MI.getOperand(1).getImm();
555 int &FalseCycles)
const {
557 if (!STI.hasLoadStoreOnCond())
559 if (Pred.
size() != 2)
565 RI.getCommonSubClass(
MRI.getRegClass(TrueReg),
MRI.getRegClass(FalseReg));
570 if ((STI.hasLoadStoreOnCond2() &&
571 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
572 SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
573 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
593 assert(Pred.
size() == 2 &&
"Invalid condition");
594 unsigned CCValid = Pred[0].getImm();
595 unsigned CCMask = Pred[1].getImm();
598 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
599 if (STI.hasMiscellaneousExtensions3())
600 Opc = SystemZ::SELRMux;
601 else if (STI.hasLoadStoreOnCond2())
602 Opc = SystemZ::LOCRMux;
605 MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
606 Register TReg =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
607 Register FReg =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
613 }
else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
614 if (STI.hasMiscellaneousExtensions3())
615 Opc = SystemZ::SELGR;
617 Opc = SystemZ::LOCGR;
631 DefMI =
MRI->getVRegDef(FoldAsLoadDefReg);
633 bool SawStore =
false;
638 MI.findRegisterUseOperandIdx(FoldAsLoadDefReg,
nullptr);
639 assert(UseOpIdx != -1 &&
"Expected FoldAsLoadDefReg to be used by MI.");
644 FoldAsLoadDefReg = 0;
654 unsigned DefOpc =
DefMI.getOpcode();
656 if (DefOpc == SystemZ::VGBM) {
657 int64_t ImmVal =
DefMI.getOperand(1).getImm();
672 MRI->getRegClass(CopyDstReg) == &SystemZ::GR128BitRegClass &&
673 MRI->hasOneNonDBGUse(Reg)) {
677 Register TmpReg =
MRI->createVirtualRegister(&SystemZ::GR64BitRegClass);
682 UseMI.setDesc(
get(SystemZ::REG_SEQUENCE));
683 UseMI.getOperand(1).setReg(TmpReg);
685 .
addImm(SystemZ::subreg_h64)
687 .
addImm(SystemZ::subreg_l64);
689 if (
MRI->use_nodbg_empty(Reg))
690 DefMI.eraseFromParent();
697 if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
698 DefOpc != SystemZ::LGHI)
702 int32_t ImmVal = (int32_t)
DefMI.getOperand(1).getImm();
704 unsigned UseOpc =
UseMI.getOpcode();
710 case SystemZ::SELRMux:
713 case SystemZ::LOCRMux:
714 if (!STI.hasLoadStoreOnCond2())
716 NewUseOpc = SystemZ::LOCHIMux;
720 UseIdx = 2, CommuteIdx = 1;
728 if (!STI.hasLoadStoreOnCond2())
730 NewUseOpc = SystemZ::LOCGHI;
734 UseIdx = 2, CommuteIdx = 1;
742 if (CommuteIdx != -1)
743 if (!commuteInstruction(
UseMI,
false, CommuteIdx, UseIdx))
746 bool DeleteDef =
MRI->hasOneNonDBGUse(Reg);
749 UseMI.tieOperands(0, 1);
750 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
752 DefMI.eraseFromParent();
758 unsigned Opcode =
MI.getOpcode();
759 if (Opcode == SystemZ::Return ||
760 Opcode == SystemZ::Return_XPLINK ||
761 Opcode == SystemZ::Trap ||
762 Opcode == SystemZ::CallJG ||
763 Opcode == SystemZ::CallBR)
770 unsigned NumCycles,
unsigned ExtraPredCycles,
784 return NumCycles == 1;
789 unsigned NumCyclesT,
unsigned ExtraPredCyclesT,
791 unsigned NumCyclesF,
unsigned ExtraPredCyclesF,
801 return NumCycles == 1;
806 assert(Pred.
size() == 2 &&
"Invalid condition");
807 unsigned CCValid = Pred[0].getImm();
808 unsigned CCMask = Pred[1].getImm();
809 assert(CCMask > 0 && CCMask < 15 &&
"Invalid predicate");
810 unsigned Opcode =
MI.getOpcode();
811 if (Opcode == SystemZ::Trap) {
812 MI.setDesc(
get(SystemZ::CondTrap));
818 if (Opcode == SystemZ::Return || Opcode == SystemZ::Return_XPLINK) {
819 MI.setDesc(
get(Opcode == SystemZ::Return ? SystemZ::CondReturn
820 : SystemZ::CondReturn_XPLINK));
827 if (Opcode == SystemZ::CallJG) {
829 const uint32_t *RegMask =
MI.getOperand(1).getRegMask();
832 MI.setDesc(
get(SystemZ::CallBRCL));
841 if (Opcode == SystemZ::CallBR) {
843 const uint32_t *RegMask =
MI.getOperand(1).getRegMask();
846 MI.setDesc(
get(SystemZ::CallBCR));
864 if (SystemZ::GR128BitRegClass.
contains(DestReg, SrcReg)) {
866 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
870 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
876 if (SystemZ::GRX32BitRegClass.
contains(DestReg, SrcReg)) {
877 emitGRX32Move(
MBB,
MBBI,
DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
883 if (SystemZ::VR128BitRegClass.
contains(DestReg) &&
884 SystemZ::FP128BitRegClass.
contains(SrcReg)) {
886 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
887 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
889 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
890 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
897 if (SystemZ::FP128BitRegClass.
contains(DestReg) &&
898 SystemZ::VR128BitRegClass.
contains(SrcReg)) {
900 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
901 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
903 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
904 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
906 if (DestRegHi != SrcReg)
913 if (SystemZ::FP128BitRegClass.
contains(DestReg) &&
914 SystemZ::GR128BitRegClass.
contains(SrcReg)) {
915 MCRegister DestRegHi = RI.getSubReg(DestReg, SystemZ::subreg_h64);
916 MCRegister DestRegLo = RI.getSubReg(DestReg, SystemZ::subreg_l64);
917 MCRegister SrcRegHi = RI.getSubReg(SrcReg, SystemZ::subreg_h64);
918 MCRegister SrcRegLo = RI.getSubReg(SrcReg, SystemZ::subreg_l64);
930 if (DestReg == SystemZ::CC) {
932 SystemZ::GR32BitRegClass.contains(SrcReg) ? SystemZ::TMLH : SystemZ::TMHH;
939 if (SystemZ::GR128BitRegClass.
contains(DestReg) &&
940 SystemZ::VR128BitRegClass.
contains(SrcReg)) {
941 MCRegister DestH64 = RI.getSubReg(DestReg, SystemZ::subreg_h64);
942 MCRegister DestL64 = RI.getSubReg(DestReg, SystemZ::subreg_l64);
946 .
addReg(SystemZ::NoRegister)
951 .
addReg(SystemZ::NoRegister)
956 if (SystemZ::VR128BitRegClass.
contains(DestReg) &&
957 SystemZ::GR128BitRegClass.
contains(SrcReg)) {
959 .
addReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64))
960 .
addReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64));
966 if (SystemZ::GR64BitRegClass.
contains(DestReg, SrcReg))
967 Opcode = SystemZ::LGR;
968 else if (SystemZ::FP32BitRegClass.
contains(DestReg, SrcReg))
970 Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
971 else if (SystemZ::FP64BitRegClass.
contains(DestReg, SrcReg))
972 Opcode = SystemZ::LDR;
973 else if (SystemZ::FP128BitRegClass.
contains(DestReg, SrcReg))
974 Opcode = SystemZ::LXR;
975 else if (SystemZ::VR32BitRegClass.
contains(DestReg, SrcReg))
976 Opcode = SystemZ::VLR32;
977 else if (SystemZ::VR64BitRegClass.
contains(DestReg, SrcReg))
978 Opcode = SystemZ::VLR64;
979 else if (SystemZ::VR128BitRegClass.
contains(DestReg, SrcReg))
980 Opcode = SystemZ::VLR;
981 else if (SystemZ::AR32BitRegClass.
contains(DestReg, SrcReg))
982 Opcode = SystemZ::CPYA;
998 unsigned LoadOpcode, StoreOpcode;
1015 unsigned LoadOpcode, StoreOpcode;
1025 return ((MCID.
TSFlags & Flag) &&
1026 isUInt<12>(
MI->getOperand(2).getImm()) &&
1027 MI->getOperand(3).getReg() == 0);
1033 LogicOp() =
default;
1034 LogicOp(
unsigned regSize,
unsigned immLSB,
unsigned immSize)
1035 :
RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
1037 explicit operator bool()
const {
return RegSize; }
1040 unsigned ImmLSB = 0;
1041 unsigned ImmSize = 0;
1048 case SystemZ::NILMux:
return LogicOp(32, 0, 16);
1049 case SystemZ::NIHMux:
return LogicOp(32, 16, 16);
1050 case SystemZ::NILL64:
return LogicOp(64, 0, 16);
1051 case SystemZ::NILH64:
return LogicOp(64, 16, 16);
1052 case SystemZ::NIHL64:
return LogicOp(64, 32, 16);
1053 case SystemZ::NIHH64:
return LogicOp(64, 48, 16);
1054 case SystemZ::NIFMux:
return LogicOp(32, 0, 32);
1055 case SystemZ::NILF64:
return LogicOp(64, 0, 32);
1056 case SystemZ::NIHF64:
return LogicOp(64, 32, 32);
1057 default:
return LogicOp();
1065 if (CCDef !=
nullptr)
1087 unsigned Start,
End;
1090 if (
And.RegSize == 64) {
1091 NewOpcode = SystemZ::RISBG;
1093 if (STI.hasMiscellaneousExtensions())
1094 NewOpcode = SystemZ::RISBGN;
1096 NewOpcode = SystemZ::RISBMux;
1112 unsigned NumOps =
MI.getNumOperands();
1113 for (
unsigned I = 1;
I < NumOps; ++
I) {
1115 if (
Op.isReg() &&
Op.isKill())
1129 bool Invert)
const {
1135 Opc = *InverseOpcode;
1142 case SystemZ::WFADB:
1143 case SystemZ::WFASB:
1144 case SystemZ::WFAXB:
1145 case SystemZ::VFADB:
1146 case SystemZ::VFASB:
1147 case SystemZ::WFMDB:
1148 case SystemZ::WFMSB:
1149 case SystemZ::WFMXB:
1150 case SystemZ::VFMDB:
1151 case SystemZ::VFMSB:
1159std::optional<unsigned>
1163 case SystemZ::WFADB:
1164 return SystemZ::WFSDB;
1165 case SystemZ::WFASB:
1166 return SystemZ::WFSSB;
1167 case SystemZ::WFAXB:
1168 return SystemZ::WFSXB;
1169 case SystemZ::VFADB:
1170 return SystemZ::VFSDB;
1171 case SystemZ::VFASB:
1172 return SystemZ::VFSSB;
1174 case SystemZ::WFSDB:
1175 return SystemZ::WFADB;
1176 case SystemZ::WFSSB:
1177 return SystemZ::WFASB;
1178 case SystemZ::WFSXB:
1179 return SystemZ::WFAXB;
1180 case SystemZ::VFSDB:
1181 return SystemZ::VFADB;
1182 case SystemZ::VFSSB:
1183 return SystemZ::VFASB;
1185 return std::nullopt;
1197 unsigned Opcode =
MI.getOpcode();
1202 bool CCLiveAtMI =
true;
1207 CCLiveRange = &LIS->
getRegUnit(*CCUnits.begin());
1208 CCLiveAtMI = CCLiveRange->
liveAt(MISlot);
1211 if (Ops.
size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1212 if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1213 isInt<8>(
MI.getOperand(2).getImm()) && !
MI.getOperand(3).getReg()) {
1216 MI.getDebugLoc(),
get(SystemZ::AGSI))
1219 .
addImm(
MI.getOperand(2).getImm());
1229 if (Ops.
size() != 1)
1232 unsigned OpNum = Ops[0];
1236 "Invalid size combination");
1238 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1239 isInt<8>(
MI.getOperand(2).getImm())) {
1241 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1243 BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
get(Opcode))
1246 .
addImm(
MI.getOperand(2).getImm());
1252 if ((Opcode == SystemZ::ALFI && OpNum == 0 &&
1253 isInt<8>((int32_t)
MI.getOperand(2).getImm())) ||
1254 (Opcode == SystemZ::ALGFI && OpNum == 0 &&
1255 isInt<8>((int64_t)
MI.getOperand(2).getImm()))) {
1257 Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);
1259 BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
get(Opcode))
1262 .
addImm((int8_t)
MI.getOperand(2).getImm());
1267 if ((Opcode == SystemZ::SLFI && OpNum == 0 &&
1268 isInt<8>((int32_t)-
MI.getOperand(2).getImm())) ||
1269 (Opcode == SystemZ::SLGFI && OpNum == 0 &&
1270 isInt<8>((int64_t)-
MI.getOperand(2).getImm()))) {
1272 Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);
1274 BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
get(Opcode))
1277 .
addImm((int8_t)-
MI.getOperand(2).getImm());
1282 unsigned MemImmOpc = 0;
1284 case SystemZ::LHIMux:
1285 case SystemZ::LHI: MemImmOpc = SystemZ::MVHI;
break;
1286 case SystemZ::LGHI: MemImmOpc = SystemZ::MVGHI;
break;
1287 case SystemZ::CHIMux:
1288 case SystemZ::CHI: MemImmOpc = SystemZ::CHSI;
break;
1289 case SystemZ::CGHI: MemImmOpc = SystemZ::CGHSI;
break;
1290 case SystemZ::CLFIMux:
1292 if (isUInt<16>(
MI.getOperand(1).getImm()))
1293 MemImmOpc = SystemZ::CLFHSI;
1295 case SystemZ::CLGFI:
1296 if (isUInt<16>(
MI.getOperand(1).getImm()))
1297 MemImmOpc = SystemZ::CLGHSI;
1302 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1306 .
addImm(
MI.getOperand(1).getImm());
1308 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1309 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1310 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1314 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1315 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1317 .
add(
MI.getOperand(1))
1325 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
1326 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1328 .
add(
MI.getOperand(0))
1348 if (OpNum == 0 &&
MI.hasOneMemOperand()) {
1353 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1358 .
add(
MI.getOperand(1))
1364 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1366 .
add(
MI.getOperand(1))
1379 unsigned NumOps =
MI.getNumExplicitOperands();
1380 int MemOpcode = SystemZ::getMemOpcode(Opcode);
1381 if (MemOpcode == -1 ||
1382 (CCLiveAtMI && !
MI.definesRegister(SystemZ::CC,
nullptr) &&
1383 get(MemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)))
1394 if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {
1400 !(SystemZ::FP32BitRegClass.
contains(PhysReg) ||
1401 SystemZ::FP64BitRegClass.
contains(PhysReg) ||
1402 SystemZ::VF128BitRegClass.
contains(PhysReg)))
1407 bool FusedFPOp = (Opcode == SystemZ::WFMADB || Opcode == SystemZ::WFMASB ||
1408 Opcode == SystemZ::WFMSDB || Opcode == SystemZ::WFMSSB);
1412 if (OpNum == 0 || OpNum == 3 || DstReg != AccReg)
1417 bool NeedsCommute =
false;
1418 if ((
MI.getOpcode() == SystemZ::CR ||
MI.getOpcode() == SystemZ::CGR ||
1419 MI.getOpcode() == SystemZ::CLR ||
MI.getOpcode() == SystemZ::CLGR ||
1420 MI.getOpcode() == SystemZ::WFCDB ||
MI.getOpcode() == SystemZ::WFCSB ||
1421 MI.getOpcode() == SystemZ::WFKDB ||
MI.getOpcode() == SystemZ::WFKSB) &&
1423 NeedsCommute =
true;
1425 bool CCOperands =
false;
1426 if (
MI.getOpcode() == SystemZ::LOCRMux ||
MI.getOpcode() == SystemZ::LOCGR ||
1427 MI.getOpcode() == SystemZ::SELRMux ||
MI.getOpcode() == SystemZ::SELGR) {
1428 assert(
MI.getNumOperands() == 6 && NumOps == 5 &&
1429 "LOCR/SELR instruction operands corrupt?");
1444 Register SrcReg = (OpNum == 2 ?
MI.getOperand(1).getReg()
1445 : ((OpNum == 1 &&
MI.isCommutable())
1446 ?
MI.getOperand(2).getReg()
1448 if (DstPhys && !SystemZ::GRH32BitRegClass.
contains(DstPhys) && SrcReg &&
1450 NeedsCommute = (OpNum == 1);
1456 if ((OpNum == NumOps - 1) || NeedsCommute || FusedFPOp) {
1459 assert(AccessBytes != 0 &&
"Size of access should be known");
1460 assert(AccessBytes <=
Size &&
"Access outside the frame index");
1463 MI.getDebugLoc(),
get(MemOpcode));
1464 if (
MI.isCompare()) {
1465 assert(NumOps == 2 &&
"Expected 2 register operands for a compare.");
1466 MIB.
add(
MI.getOperand(NeedsCommute ? 1 : 0));
1468 else if (FusedFPOp) {
1469 MIB.
add(
MI.getOperand(0));
1470 MIB.
add(
MI.getOperand(3));
1471 MIB.
add(
MI.getOperand(OpNum == 1 ? 2 : 1));
1474 MIB.
add(
MI.getOperand(0));
1476 MIB.
add(
MI.getOperand(2));
1478 for (
unsigned I = 1;
I < OpNum; ++
I)
1479 MIB.
add(
MI.getOperand(
I));
1485 unsigned CCValid =
MI.getOperand(NumOps).getImm();
1486 unsigned CCMask =
MI.getOperand(NumOps + 1).getImm();
1488 MIB.
addImm(NeedsCommute ? CCMask ^ CCValid : CCMask);
1491 (!
MI.definesRegister(SystemZ::CC,
nullptr) ||
1492 MI.registerDefIsDead(SystemZ::CC,
nullptr))) {
1500 if (MO.isReg() && MO.getReg().isVirtual()) {
1502 if (
MRI.getRegClass(Reg) == &SystemZ::VR32BitRegClass)
1503 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass);
1504 else if (
MRI.getRegClass(Reg) == &SystemZ::VR64BitRegClass)
1505 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass);
1506 else if (
MRI.getRegClass(Reg) == &SystemZ::VR128BitRegClass)
1507 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass);
1532 unsigned LoadOpc = 0;
1533 unsigned RegMemOpcode = 0;
1535 RegMemOpcode =
MI.getOpcode() == SystemZ::WFADB ? SystemZ::ADB
1536 :
MI.getOpcode() == SystemZ::WFSDB ? SystemZ::SDB
1537 :
MI.getOpcode() == SystemZ::WFMDB ? SystemZ::MDB
1540 LoadOpc = SystemZ::VL64;
1541 FPRC = &SystemZ::FP64BitRegClass;
1543 RegMemOpcode =
MI.getOpcode() == SystemZ::WFASB ? SystemZ::AEB
1544 :
MI.getOpcode() == SystemZ::WFSSB ? SystemZ::SEB
1545 :
MI.getOpcode() == SystemZ::WFMSB ? SystemZ::MEEB
1548 LoadOpc = SystemZ::VL32;
1549 FPRC = &SystemZ::FP32BitRegClass;
1552 if (!RegMemOpcode || LoadMI.
getOpcode() != LoadOpc)
1556 if (
get(RegMemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)) {
1558 assert(LoadMI != InsertPt &&
"Assuming InsertPt not to be first in MBB.");
1561 if (MII->definesRegister(SystemZ::CC,
nullptr)) {
1562 if (!MII->registerDefIsDead(SystemZ::CC,
nullptr))
1575 if (Ops.
size() != 1 || FoldAsLoadDefReg !=
MI.getOperand(Ops[0]).getReg())
1581 if ((RegMemOpcode == SystemZ::SDB || RegMemOpcode == SystemZ::SEB) &&
1582 FoldAsLoadDefReg !=
RHS.getReg())
1589 BuildMI(*
MI.getParent(), InsertPt,
MI.getDebugLoc(),
get(RegMemOpcode), DstReg)
1595 MRI->setRegClass(DstReg, FPRC);
1603 switch (
MI.getOpcode()) {
1605 splitMove(
MI, SystemZ::LG);
1608 case SystemZ::ST128:
1609 splitMove(
MI, SystemZ::STG);
1613 splitMove(
MI, SystemZ::LD);
1617 splitMove(
MI, SystemZ::STD);
1620 case SystemZ::LBMux:
1621 expandRXYPseudo(
MI, SystemZ::LB, SystemZ::LBH);
1624 case SystemZ::LHMux:
1625 expandRXYPseudo(
MI, SystemZ::LH, SystemZ::LHH);
1628 case SystemZ::LLCRMux:
1629 expandZExtPseudo(
MI, SystemZ::LLCR, 8);
1632 case SystemZ::LLHRMux:
1633 expandZExtPseudo(
MI, SystemZ::LLHR, 16);
1636 case SystemZ::LLCMux:
1637 expandRXYPseudo(
MI, SystemZ::LLC, SystemZ::LLCH);
1640 case SystemZ::LLHMux:
1641 expandRXYPseudo(
MI, SystemZ::LLH, SystemZ::LLHH);
1645 expandRXYPseudo(
MI, SystemZ::L, SystemZ::LFH);
1648 case SystemZ::LOCMux:
1649 expandLOCPseudo(
MI, SystemZ::LOC, SystemZ::LOCFH);
1652 case SystemZ::LOCHIMux:
1653 expandLOCPseudo(
MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1656 case SystemZ::STCMux:
1657 expandRXYPseudo(
MI, SystemZ::STC, SystemZ::STCH);
1660 case SystemZ::STHMux:
1661 expandRXYPseudo(
MI, SystemZ::STH, SystemZ::STHH);
1664 case SystemZ::STMux:
1665 expandRXYPseudo(
MI, SystemZ::ST, SystemZ::STFH);
1668 case SystemZ::STOCMux:
1669 expandLOCPseudo(
MI, SystemZ::STOC, SystemZ::STOCFH);
1672 case SystemZ::LHIMux:
1673 expandRIPseudo(
MI, SystemZ::LHI, SystemZ::IIHF,
true);
1676 case SystemZ::IIFMux:
1677 expandRIPseudo(
MI, SystemZ::IILF, SystemZ::IIHF,
false);
1680 case SystemZ::IILMux:
1681 expandRIPseudo(
MI, SystemZ::IILL, SystemZ::IIHL,
false);
1684 case SystemZ::IIHMux:
1685 expandRIPseudo(
MI, SystemZ::IILH, SystemZ::IIHH,
false);
1688 case SystemZ::NIFMux:
1689 expandRIPseudo(
MI, SystemZ::NILF, SystemZ::NIHF,
false);
1692 case SystemZ::NILMux:
1693 expandRIPseudo(
MI, SystemZ::NILL, SystemZ::NIHL,
false);
1696 case SystemZ::NIHMux:
1697 expandRIPseudo(
MI, SystemZ::NILH, SystemZ::NIHH,
false);
1700 case SystemZ::OIFMux:
1701 expandRIPseudo(
MI, SystemZ::OILF, SystemZ::OIHF,
false);
1704 case SystemZ::OILMux:
1705 expandRIPseudo(
MI, SystemZ::OILL, SystemZ::OIHL,
false);
1708 case SystemZ::OIHMux:
1709 expandRIPseudo(
MI, SystemZ::OILH, SystemZ::OIHH,
false);
1712 case SystemZ::XIFMux:
1713 expandRIPseudo(
MI, SystemZ::XILF, SystemZ::XIHF,
false);
1716 case SystemZ::TMLMux:
1717 expandRIPseudo(
MI, SystemZ::TMLL, SystemZ::TMHL,
false);
1720 case SystemZ::TMHMux:
1721 expandRIPseudo(
MI, SystemZ::TMLH, SystemZ::TMHH,
false);
1724 case SystemZ::AHIMux:
1725 expandRIPseudo(
MI, SystemZ::AHI, SystemZ::AIH,
false);
1728 case SystemZ::AHIMuxK:
1729 expandRIEPseudo(
MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1732 case SystemZ::AFIMux:
1733 expandRIPseudo(
MI, SystemZ::AFI, SystemZ::AIH,
false);
1736 case SystemZ::CHIMux:
1737 expandRIPseudo(
MI, SystemZ::CHI, SystemZ::CIH,
false);
1740 case SystemZ::CFIMux:
1741 expandRIPseudo(
MI, SystemZ::CFI, SystemZ::CIH,
false);
1744 case SystemZ::CLFIMux:
1745 expandRIPseudo(
MI, SystemZ::CLFI, SystemZ::CLIH,
false);
1749 expandRXYPseudo(
MI, SystemZ::C, SystemZ::CHF);
1752 case SystemZ::CLMux:
1753 expandRXYPseudo(
MI, SystemZ::CL, SystemZ::CLHF);
1756 case SystemZ::RISBMux: {
1759 if (SrcIsHigh == DestIsHigh)
1760 MI.setDesc(
get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1762 MI.setDesc(
get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1763 MI.getOperand(5).setImm(
MI.getOperand(5).getImm() ^ 32);
1768 case SystemZ::ADJDYNALLOC:
1769 splitAdjDynAlloc(
MI);
1772 case TargetOpcode::LOAD_STACK_GUARD:
1773 expandLoadStackGuard(&
MI);
1782 if (
MI.isInlineAsm()) {
1784 const char *AsmStr =
MI.getOperand(0).getSymbolName();
1787 else if (
MI.getOpcode() == SystemZ::PATCHPOINT)
1789 else if (
MI.getOpcode() == SystemZ::STACKMAP)
1790 return MI.getOperand(1).getImm();
1791 else if (
MI.getOpcode() == SystemZ::FENTRY_CALL)
1794 return MI.getDesc().getSize();
1799 switch (
MI.getOpcode()) {
1810 MI.getOperand(1).getImm(), &
MI.getOperand(2));
1813 case SystemZ::BRCTH:
1817 case SystemZ::BRCTG:
1824 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1829 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1834 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1836 case SystemZ::CLGIJ:
1837 case SystemZ::CLGRJ:
1839 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1841 case SystemZ::INLINEASM_BR:
1851 unsigned &LoadOpcode,
1852 unsigned &StoreOpcode)
const {
1853 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1854 LoadOpcode = SystemZ::L;
1855 StoreOpcode = SystemZ::ST;
1856 }
else if (RC == &SystemZ::GRH32BitRegClass) {
1857 LoadOpcode = SystemZ::LFH;
1858 StoreOpcode = SystemZ::STFH;
1859 }
else if (RC == &SystemZ::GRX32BitRegClass) {
1860 LoadOpcode = SystemZ::LMux;
1861 StoreOpcode = SystemZ::STMux;
1862 }
else if (RC == &SystemZ::GR64BitRegClass ||
1863 RC == &SystemZ::ADDR64BitRegClass) {
1864 LoadOpcode = SystemZ::LG;
1865 StoreOpcode = SystemZ::STG;
1866 }
else if (RC == &SystemZ::GR128BitRegClass ||
1867 RC == &SystemZ::ADDR128BitRegClass) {
1868 LoadOpcode = SystemZ::L128;
1869 StoreOpcode = SystemZ::ST128;
1870 }
else if (RC == &SystemZ::FP32BitRegClass) {
1871 LoadOpcode = SystemZ::LE;
1872 StoreOpcode = SystemZ::STE;
1873 }
else if (RC == &SystemZ::FP64BitRegClass) {
1874 LoadOpcode = SystemZ::LD;
1875 StoreOpcode = SystemZ::STD;
1876 }
else if (RC == &SystemZ::FP128BitRegClass) {
1877 LoadOpcode = SystemZ::LX;
1878 StoreOpcode = SystemZ::STX;
1879 }
else if (RC == &SystemZ::VR32BitRegClass) {
1880 LoadOpcode = SystemZ::VL32;
1881 StoreOpcode = SystemZ::VST32;
1882 }
else if (RC == &SystemZ::VR64BitRegClass) {
1883 LoadOpcode = SystemZ::VL64;
1884 StoreOpcode = SystemZ::VST64;
1885 }
else if (RC == &SystemZ::VF128BitRegClass ||
1886 RC == &SystemZ::VR128BitRegClass) {
1887 LoadOpcode = SystemZ::VL;
1888 StoreOpcode = SystemZ::VST;
1898 if (isUInt<12>(
Offset) && isUInt<12>(Offset2)) {
1900 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1901 if (Disp12Opcode >= 0)
1902 return Disp12Opcode;
1908 if (isInt<20>(
Offset) && isInt<20>(Offset2)) {
1910 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1911 if (Disp20Opcode >= 0)
1912 return Disp20Opcode;
1919 if (
MI &&
MI->getOperand(0).isReg()) {
1924 return SystemZ::LEY;
1925 case SystemZ::VST32:
1926 return SystemZ::STEY;
1928 return SystemZ::LDY;
1929 case SystemZ::VST64:
1930 return SystemZ::STDY;
1942 return SystemZ::getDisp12Opcode(Opcode) >= 0;
1943 return SystemZ::getDisp20Opcode(Opcode) >= 0;
1948 case SystemZ::L:
return SystemZ::LT;
1949 case SystemZ::LY:
return SystemZ::LT;
1950 case SystemZ::LG:
return SystemZ::LTG;
1951 case SystemZ::LGF:
return SystemZ::LTGF;
1952 case SystemZ::LR:
return SystemZ::LTR;
1953 case SystemZ::LGFR:
return SystemZ::LTGFR;
1954 case SystemZ::LGR:
return SystemZ::LTGR;
1955 case SystemZ::LCDFR:
return SystemZ::LCDBR;
1956 case SystemZ::LPDFR:
return SystemZ::LPDBR;
1957 case SystemZ::LNDFR:
return SystemZ::LNDBR;
1958 case SystemZ::LCDFR_32:
return SystemZ::LCEBR;
1959 case SystemZ::LPDFR_32:
return SystemZ::LPEBR;
1960 case SystemZ::LNDFR_32:
return SystemZ::LNEBR;
1965 case SystemZ::RISBGN:
return SystemZ::RISBG;
1971 unsigned &Start,
unsigned &
End)
const {
1981 Start = 63 - (LSB +
Length - 1);
1989 assert(LSB > 0 &&
"Bottom bit must be set");
1990 assert(LSB +
Length < BitSize &&
"Top bit must be set");
1991 Start = 63 - (LSB - 1);
2005 if (!(
MI && isInt<8>(
MI->getOperand(1).getImm())))
2009 case SystemZ::CLGFI:
2010 if (!(
MI && isUInt<8>(
MI->getOperand(1).getImm())))
2015 if (!STI.hasMiscellaneousExtensions())
2017 if (!(
MI &&
MI->getOperand(3).getReg() == 0))
2025 return SystemZ::CRJ;
2027 return SystemZ::CGRJ;
2029 return SystemZ::CIJ;
2031 return SystemZ::CGIJ;
2033 return SystemZ::CLRJ;
2035 return SystemZ::CLGRJ;
2037 return SystemZ::CLIJ;
2038 case SystemZ::CLGFI:
2039 return SystemZ::CLGIJ;
2046 return SystemZ::CRBReturn;
2048 return SystemZ::CGRBReturn;
2050 return SystemZ::CIBReturn;
2052 return SystemZ::CGIBReturn;
2054 return SystemZ::CLRBReturn;
2056 return SystemZ::CLGRBReturn;
2058 return SystemZ::CLIBReturn;
2059 case SystemZ::CLGFI:
2060 return SystemZ::CLGIBReturn;
2067 return SystemZ::CRBCall;
2069 return SystemZ::CGRBCall;
2071 return SystemZ::CIBCall;
2073 return SystemZ::CGIBCall;
2075 return SystemZ::CLRBCall;
2077 return SystemZ::CLGRBCall;
2079 return SystemZ::CLIBCall;
2080 case SystemZ::CLGFI:
2081 return SystemZ::CLGIBCall;
2088 return SystemZ::CRT;
2090 return SystemZ::CGRT;
2092 return SystemZ::CIT;
2094 return SystemZ::CGIT;
2096 return SystemZ::CLRT;
2098 return SystemZ::CLGRT;
2100 return SystemZ::CLFIT;
2101 case SystemZ::CLGFI:
2102 return SystemZ::CLGIT;
2104 return SystemZ::CLT;
2106 return SystemZ::CLGT;
2117 MBBI->getOperand(1).isReg() && !
MBBI->mayLoad() &&
2118 "Not a compare reg/reg.");
2124 if (
MI.readsRegister(SystemZ::CC,
nullptr)) {
2125 unsigned Flags =
MI.getDesc().TSFlags;
2131 if (
MI.definesRegister(SystemZ::CC,
nullptr)) {
2145 unsigned Flags = CCUsers[
Idx]->getDesc().TSFlags;
2147 0 : CCUsers[
Idx]->getNumExplicitOperands() - 2);
2150 CCMaskMO.
setImm(NewCCMask);
2188 if (!STI.hasLoadAndTrap())
2193 return SystemZ::LAT;
2195 return SystemZ::LGAT;
2197 return SystemZ::LFHAT;
2199 return SystemZ::LLGFAT;
2201 return SystemZ::LLGTAT;
2210 unsigned Opcode = 0;
2211 if (isInt<16>(
Value))
2212 Opcode = SystemZ::LGHI;
2214 Opcode = SystemZ::LLILL;
2216 Opcode = SystemZ::LLILH;
2219 else if (isInt<32>(
Value))
2220 Opcode = SystemZ::LGFI;
2227 assert (
MRI.isSSA() &&
"Huge values only handled before reg-alloc .");
2228 Register Reg0 =
MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
2229 Register Reg1 =
MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
2240 for (
unsigned I = 0, E =
MI.getNumOperands();
I != E; ++
I) {
2251 ErrInfo =
"Addressing mode operands corrupt!";
2274 bool SameVal = (VALa && VALb && (VALa == VALb));
2278 if (PSVa && PSVb && (PSVa == PSVb))
2284 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
2285 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
2286 LocationSize LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2288 LowOffset + (int)LowWidth.
getValue() <= HighOffset)
2297 int64_t &ImmVal)
const {
2299 if (
MI.getOpcode() == SystemZ::VGBM && Reg ==
MI.getOperand(0).getReg()) {
2300 ImmVal =
MI.getOperand(1).getImm();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag)
static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI)
static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI, MachineInstr::MIFlag Flag)
static int isSimpleMove(const MachineInstr &MI, int &FrameIndex, unsigned Flag)
static LogicOp interpretAndImmediate(unsigned Opcode)
static uint64_t allOnes(unsigned int Count)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
This class represents an Operation in the Expression.
SlotIndexes * getSlotIndexes() const
VNInfo::Allocator & getVNInfoAllocator()
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
This class represents the liveness of a register, stack slot, etc.
bool liveAt(SlotIndex index) const
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)
createDeadDef - Make sure the range has a value defined at Def.
A set of register units used to track register liveness.
bool available(MCPhysReg Reg) const
Returns true if no part of physical register Reg is live.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds registers living out of block MBB.
void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.
TypeSize getValue() const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
This holds information about one operand of a machine instruction, indicating the register class for ...
uint8_t OperandType
Information about the type of the operand.
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Wrapper class representing physical registers. Should be passed by value.
static MCRegister from(unsigned Val)
Check the provided unsigned value is a valid MCRegister.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
uint64_t getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
bool isSafeToMove(bool &SawStore) const
Return true if it is safe to move this instruction.
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI) const
Returns true if the register is dead in this machine instruction.
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr fully defines the specified register.
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
iterator_range< mop_iterator > operands()
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
void setFlag(MIFlag Flag)
Set a MI flag.
const MachineOperand & getOperand(unsigned i) const
MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
const PseudoSourceValue * getPseudoValue() const
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
const Value * getValue() const
Return the base address of the memory access.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
MachineOperand class - Representation of each machine instruction operand.
void setImm(int64_t immVal)
void setIsDead(bool Val=true)
void setReg(Register Reg)
Change the register this operand corresponds to.
void setIsKill(bool Val=true)
static MachineOperand CreateImm(int64_t Val)
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
MI-level patchpoint operands.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Special value supplied for machine level alias analysis.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
SlotIndex - An opaque wrapper around machine indexes.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
A SystemZ-specific class detailing special use registers particular for calling conventions.
virtual int getStackPointerBias()=0
virtual int getCallFrameSize()=0
unsigned getLoadAndTrap(unsigned Opcode) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
unsigned getLoadAndTest(unsigned Opcode) const
bool isPredicable(const MachineInstr &MI) const override
bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset, const MachineInstr *MI=nullptr) const
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
SystemZInstrInfo(SystemZSubtarget &STI)
bool hasDisplacementPairInsn(unsigned Opcode) const
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
std::optional< unsigned > getInverseOpcode(unsigned Opcode) const override
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const
bool expandPostRAPseudo(MachineInstr &MBBI) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
SystemZCallingConventionRegisters * getSpecialRegisters() const
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Target - Wrapper for Target specific information.
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Undef
Value of the register doesn't matter.
static unsigned getAccessSize(unsigned int Flags)
unsigned getFirstReg(unsigned Reg)
MachineBasicBlock * splitBlockBefore(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
int getTargetMemOpcode(uint16_t Opcode)
const unsigned CCMASK_CMP_GT
const unsigned CCMASK_ANY
static bool isImmLL(uint64_t Val)
static bool isImmLH(uint64_t Val)
MachineBasicBlock * emitBlockAfter(MachineBasicBlock *MBB)
unsigned reverseCCMask(unsigned CCMask)
const unsigned CCMASK_CMP_EQ
const unsigned CCMASK_ICMP
MachineBasicBlock * splitBlockAfter(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
const unsigned CCMASK_CMP_LT
const unsigned CCMASK_CMP_NE
bool isHighReg(unsigned int Reg)
const unsigned CCMASK_CMP_UO
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
constexpr size_t range_size(R &&Range)
Returns the size of the Range, i.e., the number of elements.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
unsigned getUndefRegState(bool B)
@ And
Bitwise or logical AND of integers.
unsigned getKillRegState(bool B)