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SystemZRegisterInfo.h
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1 //===-- SystemZRegisterInfo.h - SystemZ register information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZREGISTERINFO_H
10 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZREGISTERINFO_H
11 
12 #include "SystemZ.h"
14 
15 #define GET_REGINFO_HEADER
16 #include "SystemZGenRegisterInfo.inc"
17 
18 namespace llvm {
19 
20 class LiveIntervals;
21 
22 namespace SystemZ {
23 // Return the subreg to use for referring to the even and odd registers
24 // in a GR128 pair. Is32Bit says whether we want a GR32 or GR64.
25 inline unsigned even128(bool Is32bit) {
26  return Is32bit ? subreg_hl32 : subreg_h64;
27 }
28 inline unsigned odd128(bool Is32bit) {
29  return Is32bit ? subreg_l32 : subreg_l64;
30 }
31 
32 // Reg should be a 32-bit GPR. Return true if it is a high register rather
33 // than a low register.
34 inline bool isHighReg(unsigned int Reg) {
35  if (SystemZ::GRH32BitRegClass.contains(Reg))
36  return true;
37  assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
38  return false;
39 }
40 } // end namespace SystemZ
41 
43 public:
45 
46  /// getPointerRegClass - Return the register class to use to hold pointers.
47  /// This is currently only used by LOAD_STACK_GUARD, which requires a non-%r0
48  /// register, hence ADDR64.
49  const TargetRegisterClass *
51  unsigned Kind=0) const override {
52  return &SystemZ::ADDR64BitRegClass;
53  }
54 
55  /// getCrossCopyRegClass - Returns a legal register class to copy a register
56  /// in the specified class to or from. Returns NULL if it is possible to copy
57  /// between a two registers of the specified class.
58  const TargetRegisterClass *
59  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
60 
61  bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
63  const MachineFunction &MF, const VirtRegMap *VRM,
64  const LiveRegMatrix *Matrix) const override;
65 
66  // Override TargetRegisterInfo.h.
67  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
68  return true;
69  }
70  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
71  return true;
72  }
73  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
74  const uint32_t *getCallPreservedMask(const MachineFunction &MF,
75  CallingConv::ID CC) const override;
76  BitVector getReservedRegs(const MachineFunction &MF) const override;
77  void eliminateFrameIndex(MachineBasicBlock::iterator MI,
78  int SPAdj, unsigned FIOperandNum,
79  RegScavenger *RS) const override;
80 
81  /// SrcRC and DstRC will be morphed into NewRC if this returns true.
82  bool shouldCoalesce(MachineInstr *MI,
83  const TargetRegisterClass *SrcRC,
84  unsigned SubReg,
85  const TargetRegisterClass *DstRC,
86  unsigned DstSubReg,
87  const TargetRegisterClass *NewRC,
88  LiveIntervals &LIS) const override;
89 
90  Register getFrameRegister(const MachineFunction &MF) const override;
91 };
92 
93 } // end namespace llvm
94 
95 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned odd128(bool Is32bit)
unsigned Reg
return AArch64::GPR64RegClass contains(Reg)
Live Register Matrix
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
unsigned SubReg
bool isHighReg(unsigned int Reg)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Representation of each machine instruction.
Definition: MachineInstr.h:62
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned even128(bool Is32bit)
IRTranslator LLVM IR MI
Wrapper class representing virtual and physical registers.
Definition: Register.h:19