LLVM  10.0.0svn
SystemZRegisterInfo.cpp
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1 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SystemZRegisterInfo.h"
10 #include "SystemZInstrInfo.h"
11 #include "SystemZSubtarget.h"
13 #include "llvm/ADT/SmallSet.h"
18 
19 using namespace llvm;
20 
21 #define GET_REGINFO_TARGET_DESC
22 #include "SystemZGenRegisterInfo.inc"
23 
25  : SystemZGenRegisterInfo(SystemZ::R14D) {}
26 
27 // Given that MO is a GRX32 operand, return either GR32 or GRH32 if MO
28 // somehow belongs in it. Otherwise, return GRX32.
30  const VirtRegMap *VRM,
31  const MachineRegisterInfo *MRI) {
32  const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
33 
34  if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
35  MO.getSubReg() == SystemZ::subreg_l32 ||
36  MO.getSubReg() == SystemZ::subreg_hl32)
37  return &SystemZ::GR32BitRegClass;
38  if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
39  MO.getSubReg() == SystemZ::subreg_h32 ||
40  MO.getSubReg() == SystemZ::subreg_hh32)
41  return &SystemZ::GRH32BitRegClass;
42 
43  if (VRM && VRM->hasPhys(MO.getReg())) {
44  unsigned PhysReg = VRM->getPhys(MO.getReg());
45  if (SystemZ::GR32BitRegClass.contains(PhysReg))
46  return &SystemZ::GR32BitRegClass;
47  assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
48  "Phys reg not in GR32 or GRH32?");
49  return &SystemZ::GRH32BitRegClass;
50  }
51 
52  assert (RC == &SystemZ::GRX32BitRegClass);
53  return RC;
54 }
55 
56 // Pass the registers of RC as hints while making sure that if any of these
57 // registers are copy hints (and therefore already in Hints), hint them
58 // first.
59 static void addHints(ArrayRef<MCPhysReg> Order,
61  const TargetRegisterClass *RC,
62  const MachineRegisterInfo *MRI) {
63  SmallSet<unsigned, 4> CopyHints;
64  CopyHints.insert(Hints.begin(), Hints.end());
65  Hints.clear();
66  for (MCPhysReg Reg : Order)
67  if (CopyHints.count(Reg) &&
68  RC->contains(Reg) && !MRI->isReserved(Reg))
69  Hints.push_back(Reg);
70  for (MCPhysReg Reg : Order)
71  if (!CopyHints.count(Reg) &&
72  RC->contains(Reg) && !MRI->isReserved(Reg))
73  Hints.push_back(Reg);
74 }
75 
76 bool
78  ArrayRef<MCPhysReg> Order,
80  const MachineFunction &MF,
81  const VirtRegMap *VRM,
82  const LiveRegMatrix *Matrix) const {
83  const MachineRegisterInfo *MRI = &MF.getRegInfo();
84  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
85  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
86 
87  bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
88  VirtReg, Order, Hints, MF, VRM, Matrix);
89 
90  if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
91  SmallVector<unsigned, 8> Worklist;
92  SmallSet<unsigned, 4> DoneRegs;
93  Worklist.push_back(VirtReg);
94  while (Worklist.size()) {
95  unsigned Reg = Worklist.pop_back_val();
96  if (!DoneRegs.insert(Reg).second)
97  continue;
98 
99  for (auto &Use : MRI->reg_instructions(Reg)) {
100  // For LOCRMux, see if the other operand is already a high or low
101  // register, and in that case give the corresponding hints for
102  // VirtReg. LOCR instructions need both operands in either high or
103  // low parts. Same handling for SELRMux.
104  if (Use.getOpcode() == SystemZ::LOCRMux ||
105  Use.getOpcode() == SystemZ::SELRMux) {
106  MachineOperand &TrueMO = Use.getOperand(1);
107  MachineOperand &FalseMO = Use.getOperand(2);
108  const TargetRegisterClass *RC =
109  TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI),
110  getRC32(TrueMO, VRM, MRI));
111  if (Use.getOpcode() == SystemZ::SELRMux)
112  RC = TRI->getCommonSubClass(RC,
113  getRC32(Use.getOperand(0), VRM, MRI));
114  if (RC && RC != &SystemZ::GRX32BitRegClass) {
115  addHints(Order, Hints, RC, MRI);
116  // Return true to make these hints the only regs available to
117  // RA. This may mean extra spilling but since the alternative is
118  // a jump sequence expansion of the LOCRMux, it is preferred.
119  return true;
120  }
121 
122  // Add the other operand of the LOCRMux to the worklist.
123  unsigned OtherReg =
124  (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
125  if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
126  Worklist.push_back(OtherReg);
127  } // end LOCRMux
128  else if (Use.getOpcode() == SystemZ::CHIMux ||
129  Use.getOpcode() == SystemZ::CFIMux) {
130  if (Use.getOperand(1).getImm() == 0) {
131  bool OnlyLMuxes = true;
132  for (MachineInstr &DefMI : MRI->def_instructions(VirtReg))
133  if (DefMI.getOpcode() != SystemZ::LMux)
134  OnlyLMuxes = false;
135  if (OnlyLMuxes) {
136  addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI);
137  // Return false to make these hints preferred but not obligatory.
138  return false;
139  }
140  }
141  } // end CHIMux / CFIMux
142  }
143  }
144  }
145 
146  if (VRM == nullptr)
147  return BaseImplRetVal;
148 
149  // Add any two address hints after any copy hints.
150  SmallSet<unsigned, 4> TwoAddrHints;
151  for (auto &Use : MRI->reg_nodbg_instructions(VirtReg))
152  if (SystemZ::getTwoOperandOpcode(Use.getOpcode()) != -1) {
153  const MachineOperand *VRRegMO = nullptr;
154  const MachineOperand *OtherMO = nullptr;
155  const MachineOperand *CommuMO = nullptr;
156  if (VirtReg == Use.getOperand(0).getReg()) {
157  VRRegMO = &Use.getOperand(0);
158  OtherMO = &Use.getOperand(1);
159  if (Use.isCommutable())
160  CommuMO = &Use.getOperand(2);
161  } else if (VirtReg == Use.getOperand(1).getReg()) {
162  VRRegMO = &Use.getOperand(1);
163  OtherMO = &Use.getOperand(0);
164  } else if (VirtReg == Use.getOperand(2).getReg() && Use.isCommutable()) {
165  VRRegMO = &Use.getOperand(2);
166  OtherMO = &Use.getOperand(0);
167  } else
168  continue;
169 
170  auto tryAddHint = [&](const MachineOperand *MO) -> void {
171  Register Reg = MO->getReg();
172  Register PhysReg = isPhysicalRegister(Reg) ? Reg : VRM->getPhys(Reg);
173  if (PhysReg) {
174  if (MO->getSubReg())
175  PhysReg = getSubReg(PhysReg, MO->getSubReg());
176  if (VRRegMO->getSubReg())
177  PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),
178  MRI->getRegClass(VirtReg));
179  if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
180  TwoAddrHints.insert(PhysReg);
181  }
182  };
183  tryAddHint(OtherMO);
184  if (CommuMO)
185  tryAddHint(CommuMO);
186  }
187  for (MCPhysReg OrderReg : Order)
188  if (TwoAddrHints.count(OrderReg))
189  Hints.push_back(OrderReg);
190 
191  return BaseImplRetVal;
192 }
193 
194 const MCPhysReg *
196  const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
198  return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList
199  : CSR_SystemZ_AllRegs_SaveList;
202  Attribute::SwiftError))
203  return CSR_SystemZ_SwiftError_SaveList;
204  return CSR_SystemZ_SaveList;
205 }
206 
207 const uint32_t *
209  CallingConv::ID CC) const {
210  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
211  if (CC == CallingConv::AnyReg)
212  return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask
213  : CSR_SystemZ_AllRegs_RegMask;
216  Attribute::SwiftError))
217  return CSR_SystemZ_SwiftError_RegMask;
218  return CSR_SystemZ_RegMask;
219 }
220 
221 BitVector
223  BitVector Reserved(getNumRegs());
224  const SystemZFrameLowering *TFI = getFrameLowering(MF);
225 
226  if (TFI->hasFP(MF)) {
227  // R11D is the frame pointer. Reserve all aliases.
228  Reserved.set(SystemZ::R11D);
229  Reserved.set(SystemZ::R11L);
230  Reserved.set(SystemZ::R11H);
231  Reserved.set(SystemZ::R10Q);
232  }
233 
234  // R15D is the stack pointer. Reserve all aliases.
235  Reserved.set(SystemZ::R15D);
236  Reserved.set(SystemZ::R15L);
237  Reserved.set(SystemZ::R15H);
238  Reserved.set(SystemZ::R14Q);
239 
240  // A0 and A1 hold the thread pointer.
241  Reserved.set(SystemZ::A0);
242  Reserved.set(SystemZ::A1);
243 
244  // FPC is the floating-point control register.
245  Reserved.set(SystemZ::FPC);
246 
247  return Reserved;
248 }
249 
250 void
252  int SPAdj, unsigned FIOperandNum,
253  RegScavenger *RS) const {
254  assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
255 
256  MachineBasicBlock &MBB = *MI->getParent();
257  MachineFunction &MF = *MBB.getParent();
258  auto *TII =
259  static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
260  const SystemZFrameLowering *TFI = getFrameLowering(MF);
261  DebugLoc DL = MI->getDebugLoc();
262 
263  // Decompose the frame index into a base and offset.
264  int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
265  unsigned BasePtr;
266  int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) +
267  MI->getOperand(FIOperandNum + 1).getImm());
268 
269  // Special handling of dbg_value instructions.
270  if (MI->isDebugValue()) {
271  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
272  MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
273  return;
274  }
275 
276  // See if the offset is in range, or if an equivalent instruction that
277  // accepts the offset exists.
278  unsigned Opcode = MI->getOpcode();
279  unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
280  if (OpcodeForOffset) {
281  if (OpcodeForOffset == SystemZ::LE &&
283  // If LE is ok for offset, use LDE instead on z13.
284  OpcodeForOffset = SystemZ::LDE32;
285  }
286  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
287  }
288  else {
289  // Create an anchor point that is in range. Start at 0xffff so that
290  // can use LLILH to load the immediate.
291  int64_t OldOffset = Offset;
292  int64_t Mask = 0xffff;
293  do {
294  Offset = OldOffset & Mask;
295  OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
296  Mask >>= 1;
297  assert(Mask && "One offset must be OK");
298  } while (!OpcodeForOffset);
299 
300  unsigned ScratchReg =
301  MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
302  int64_t HighOffset = OldOffset - Offset;
303 
304  if (MI->getDesc().TSFlags & SystemZII::HasIndex
305  && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
306  // Load the offset into the scratch register and use it as an index.
307  // The scratch register then dies here.
308  TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
309  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
310  MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
311  false, false, true);
312  } else {
313  // Load the anchor address into a scratch register.
314  unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
315  if (LAOpcode)
316  BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
317  .addReg(BasePtr).addImm(HighOffset).addReg(0);
318  else {
319  // Load the high offset into the scratch register and use it as
320  // an index.
321  TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
322  BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
323  .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
324  }
325 
326  // Use the scratch register as the base. It then dies here.
327  MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
328  false, false, true);
329  }
330  }
331  MI->setDesc(TII->get(OpcodeForOffset));
332  MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
333 }
334 
336  const TargetRegisterClass *SrcRC,
337  unsigned SubReg,
338  const TargetRegisterClass *DstRC,
339  unsigned DstSubReg,
340  const TargetRegisterClass *NewRC,
341  LiveIntervals &LIS) const {
342  assert (MI->isCopy() && "Only expecting COPY instructions");
343 
344  // Coalesce anything which is not a COPY involving a subreg to/from GR128.
345  if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
346  (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
347  return true;
348 
349  // Allow coalescing of a GR128 subreg COPY only if the live ranges are small
350  // and local to one MBB with not too much interferring registers. Otherwise
351  // regalloc may run out of registers.
352 
353  unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
354  unsigned GR128Reg = MI->getOperand(WideOpNo).getReg();
355  unsigned GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
356  LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
357  LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
358 
359  // Check that the two virtual registers are local to MBB.
360  MachineBasicBlock *MBB = MI->getParent();
361  MachineInstr *FirstMI_GR128 =
362  LIS.getInstructionFromIndex(IntGR128.beginIndex());
363  MachineInstr *FirstMI_GRNar =
364  LIS.getInstructionFromIndex(IntGRNar.beginIndex());
365  MachineInstr *LastMI_GR128 = LIS.getInstructionFromIndex(IntGR128.endIndex());
366  MachineInstr *LastMI_GRNar = LIS.getInstructionFromIndex(IntGRNar.endIndex());
367  if ((!FirstMI_GR128 || FirstMI_GR128->getParent() != MBB) ||
368  (!FirstMI_GRNar || FirstMI_GRNar->getParent() != MBB) ||
369  (!LastMI_GR128 || LastMI_GR128->getParent() != MBB) ||
370  (!LastMI_GRNar || LastMI_GRNar->getParent() != MBB))
371  return false;
372 
373  MachineBasicBlock::iterator MII = nullptr, MEE = nullptr;
374  if (WideOpNo == 1) {
375  MII = FirstMI_GR128;
376  MEE = LastMI_GRNar;
377  } else {
378  MII = FirstMI_GRNar;
379  MEE = LastMI_GR128;
380  }
381 
382  // Check if coalescing seems safe by finding the set of clobbered physreg
383  // pairs in the region.
384  BitVector PhysClobbered(getNumRegs());
385  MEE++;
386  for (; MII != MEE; ++MII) {
387  for (const MachineOperand &MO : MII->operands())
388  if (MO.isReg() && isPhysicalRegister(MO.getReg())) {
389  for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
390  SI.isValid(); ++SI)
391  if (NewRC->contains(*SI)) {
392  PhysClobbered.set(*SI);
393  break;
394  }
395  }
396  }
397 
398  // Demand an arbitrary margin of free regs.
399  unsigned const DemandedFreeGR128 = 3;
400  if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
401  return false;
402 
403  return true;
404 }
405 
406 Register
408  const SystemZFrameLowering *TFI = getFrameLowering(MF);
409  return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
410 }
411 
412 const TargetRegisterClass *
414  if (RC == &SystemZ::CCRRegClass)
415  return &SystemZ::GR32BitRegClass;
416  return RC;
417 }
418 
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(unsigned Reg) const
BitVector & set()
Definition: BitVector.h:397
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned getNumRegs() const
Return the number of registers in this class.
BitVector getReservedRegs(const MachineFunction &MF) const override
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
virtual int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const
getFrameIndexReference - This method should return the base register and offset used to reference a f...
void push_back(const T &Elt)
Definition: SmallVector.h:211
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:675
unsigned Reg
unsigned getSubReg() const
virtual const TargetLowering * getTargetLowering() const
static void addHints(ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const TargetRegisterClass *RC, const MachineRegisterInfo *MRI)
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
return AArch64::GPR64RegClass contains(Reg)
Live Register Matrix
bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
MCSuperRegIterator enumerates all super-registers of Reg.
const HexagonInstrInfo * TII
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
unsigned SubReg
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
virtual const TargetInstrInfo * getInstrInfo() const
int getTwoOperandOpcode(uint16_t Opcode)
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
Definition: LiveInterval.h:379
unsigned const MachineRegisterInfo * MRI
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
bool isCopy() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
static const TargetRegisterClass * getRC32(MachineOperand &MO, const VirtRegMap *VRM, const MachineRegisterInfo *MRI)
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:172
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:374
LiveInterval & getInterval(unsigned Reg)
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Register getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:102
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:96
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
iterator_range< reg_instr_iterator > reg_instructions(unsigned Reg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SlotIndex beginIndex() const
beginIndex - Return the lowest numbered slot covered.
Definition: LiveInterval.h:372
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
const SystemZRegisterInfo * getRegisterInfo() const override
Wrapper class representing virtual and physical registers.
Definition: Register.h:18
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Register getFrameRegister(const MachineFunction &MF) const override
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1251