LLVM  14.0.0git
SystemZRegisterInfo.cpp
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1 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SystemZRegisterInfo.h"
10 #include "SystemZInstrInfo.h"
11 #include "SystemZSubtarget.h"
12 #include "llvm/ADT/SmallSet.h"
19 
20 using namespace llvm;
21 
22 #define GET_REGINFO_TARGET_DESC
23 #include "SystemZGenRegisterInfo.inc"
24 
25 // Given that MO is a GRX32 operand, return either GR32 or GRH32 if MO
26 // somehow belongs in it. Otherwise, return GRX32.
28  const VirtRegMap *VRM,
29  const MachineRegisterInfo *MRI) {
30  const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
31 
32  if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
33  MO.getSubReg() == SystemZ::subreg_l32 ||
34  MO.getSubReg() == SystemZ::subreg_hl32)
35  return &SystemZ::GR32BitRegClass;
36  if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
37  MO.getSubReg() == SystemZ::subreg_h32 ||
38  MO.getSubReg() == SystemZ::subreg_hh32)
39  return &SystemZ::GRH32BitRegClass;
40 
41  if (VRM && VRM->hasPhys(MO.getReg())) {
42  Register PhysReg = VRM->getPhys(MO.getReg());
43  if (SystemZ::GR32BitRegClass.contains(PhysReg))
44  return &SystemZ::GR32BitRegClass;
45  assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
46  "Phys reg not in GR32 or GRH32?");
47  return &SystemZ::GRH32BitRegClass;
48  }
49 
50  assert (RC == &SystemZ::GRX32BitRegClass);
51  return RC;
52 }
53 
54 // Pass the registers of RC as hints while making sure that if any of these
55 // registers are copy hints (and therefore already in Hints), hint them
56 // first.
57 static void addHints(ArrayRef<MCPhysReg> Order,
59  const TargetRegisterClass *RC,
60  const MachineRegisterInfo *MRI) {
61  SmallSet<unsigned, 4> CopyHints;
62  CopyHints.insert(Hints.begin(), Hints.end());
63  Hints.clear();
64  for (MCPhysReg Reg : Order)
65  if (CopyHints.count(Reg) &&
66  RC->contains(Reg) && !MRI->isReserved(Reg))
67  Hints.push_back(Reg);
68  for (MCPhysReg Reg : Order)
69  if (!CopyHints.count(Reg) &&
70  RC->contains(Reg) && !MRI->isReserved(Reg))
71  Hints.push_back(Reg);
72 }
73 
75  Register VirtReg, ArrayRef<MCPhysReg> Order,
77  const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
78  const MachineRegisterInfo *MRI = &MF.getRegInfo();
79  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
80  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
81 
82  bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
83  VirtReg, Order, Hints, MF, VRM, Matrix);
84 
85  if (VRM != nullptr) {
86  // Add any two address hints after any copy hints.
87  SmallSet<unsigned, 4> TwoAddrHints;
88  for (auto &Use : MRI->reg_nodbg_instructions(VirtReg))
89  if (SystemZ::getTwoOperandOpcode(Use.getOpcode()) != -1) {
90  const MachineOperand *VRRegMO = nullptr;
91  const MachineOperand *OtherMO = nullptr;
92  const MachineOperand *CommuMO = nullptr;
93  if (VirtReg == Use.getOperand(0).getReg()) {
94  VRRegMO = &Use.getOperand(0);
95  OtherMO = &Use.getOperand(1);
96  if (Use.isCommutable())
97  CommuMO = &Use.getOperand(2);
98  } else if (VirtReg == Use.getOperand(1).getReg()) {
99  VRRegMO = &Use.getOperand(1);
100  OtherMO = &Use.getOperand(0);
101  } else if (VirtReg == Use.getOperand(2).getReg() &&
102  Use.isCommutable()) {
103  VRRegMO = &Use.getOperand(2);
104  OtherMO = &Use.getOperand(0);
105  } else
106  continue;
107 
108  auto tryAddHint = [&](const MachineOperand *MO) -> void {
109  Register Reg = MO->getReg();
111  ? Reg
112  : Register(VRM->getPhys(Reg));
113  if (PhysReg) {
114  if (MO->getSubReg())
115  PhysReg = getSubReg(PhysReg, MO->getSubReg());
116  if (VRRegMO->getSubReg())
117  PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),
118  MRI->getRegClass(VirtReg));
119  if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
120  TwoAddrHints.insert(PhysReg);
121  }
122  };
123  tryAddHint(OtherMO);
124  if (CommuMO)
125  tryAddHint(CommuMO);
126  }
127  for (MCPhysReg OrderReg : Order)
128  if (TwoAddrHints.count(OrderReg))
129  Hints.push_back(OrderReg);
130  }
131 
132  if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
133  SmallVector<Register, 8> Worklist;
134  SmallSet<Register, 4> DoneRegs;
135  Worklist.push_back(VirtReg);
136  while (Worklist.size()) {
137  Register Reg = Worklist.pop_back_val();
138  if (!DoneRegs.insert(Reg).second)
139  continue;
140 
141  for (auto &Use : MRI->reg_instructions(Reg)) {
142  // For LOCRMux, see if the other operand is already a high or low
143  // register, and in that case give the corresponding hints for
144  // VirtReg. LOCR instructions need both operands in either high or
145  // low parts. Same handling for SELRMux.
146  if (Use.getOpcode() == SystemZ::LOCRMux ||
147  Use.getOpcode() == SystemZ::SELRMux) {
148  MachineOperand &TrueMO = Use.getOperand(1);
149  MachineOperand &FalseMO = Use.getOperand(2);
150  const TargetRegisterClass *RC =
151  TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI),
152  getRC32(TrueMO, VRM, MRI));
153  if (Use.getOpcode() == SystemZ::SELRMux)
154  RC = TRI->getCommonSubClass(RC,
155  getRC32(Use.getOperand(0), VRM, MRI));
156  if (RC && RC != &SystemZ::GRX32BitRegClass) {
157  addHints(Order, Hints, RC, MRI);
158  // Return true to make these hints the only regs available to
159  // RA. This may mean extra spilling but since the alternative is
160  // a jump sequence expansion of the LOCRMux, it is preferred.
161  return true;
162  }
163 
164  // Add the other operand of the LOCRMux to the worklist.
165  Register OtherReg =
166  (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
167  if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
168  Worklist.push_back(OtherReg);
169  } // end LOCRMux
170  else if (Use.getOpcode() == SystemZ::CHIMux ||
171  Use.getOpcode() == SystemZ::CFIMux) {
172  if (Use.getOperand(1).getImm() == 0) {
173  bool OnlyLMuxes = true;
174  for (MachineInstr &DefMI : MRI->def_instructions(VirtReg))
175  if (DefMI.getOpcode() != SystemZ::LMux)
176  OnlyLMuxes = false;
177  if (OnlyLMuxes) {
178  addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI);
179  // Return false to make these hints preferred but not obligatory.
180  return false;
181  }
182  }
183  } // end CHIMux / CFIMux
184  }
185  }
186  }
187 
188  return BaseImplRetVal;
189 }
190 
191 const MCPhysReg *
193  return CSR_SystemZ_XPLINK64_SaveList;
194 }
195 
196 const MCPhysReg *
198  const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
200  return CSR_SystemZ_NoRegs_SaveList;
202  return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList
203  : CSR_SystemZ_AllRegs_SaveList;
206  Attribute::SwiftError))
207  return CSR_SystemZ_SwiftError_SaveList;
208  return CSR_SystemZ_ELF_SaveList;
209 }
210 
211 const uint32_t *
213  CallingConv::ID CC) const {
214  return CSR_SystemZ_XPLINK64_RegMask;
215 }
216 
217 const uint32_t *
219  CallingConv::ID CC) const {
220  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
221  if (CC == CallingConv::GHC)
222  return CSR_SystemZ_NoRegs_RegMask;
223  if (CC == CallingConv::AnyReg)
224  return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask
225  : CSR_SystemZ_AllRegs_RegMask;
228  Attribute::SwiftError))
229  return CSR_SystemZ_SwiftError_RegMask;
230  return CSR_SystemZ_ELF_RegMask;
231 }
232 
235 
236 const MCPhysReg *
238 
239  const SystemZSubtarget *Subtarget = &MF->getSubtarget<SystemZSubtarget>();
241 
242  return Regs->getCalleeSavedRegs(MF);
243 }
244 
245 const uint32_t *
247  CallingConv::ID CC) const {
248 
249  const SystemZSubtarget *Subtarget = &MF.getSubtarget<SystemZSubtarget>();
251  return Regs->getCallPreservedMask(MF, CC);
252 }
253 
254 BitVector
256  BitVector Reserved(getNumRegs());
257  const SystemZFrameLowering *TFI = getFrameLowering(MF);
258  const SystemZSubtarget *Subtarget = &MF.getSubtarget<SystemZSubtarget>();
260  if (TFI->hasFP(MF))
261  // The frame pointer. Reserve all aliases.
262  for (MCRegAliasIterator AI(Regs->getFramePointerRegister(), this, true);
263  AI.isValid(); ++AI)
264  Reserved.set(*AI);
265 
266  // Reserve all aliases for the stack pointer.
267  for (MCRegAliasIterator AI(Regs->getStackPointerRegister(), this, true);
268  AI.isValid(); ++AI)
269  Reserved.set(*AI);
270 
271  // A0 and A1 hold the thread pointer.
272  Reserved.set(SystemZ::A0);
273  Reserved.set(SystemZ::A1);
274 
275  // FPC is the floating-point control register.
276  Reserved.set(SystemZ::FPC);
277 
278  return Reserved;
279 }
280 
281 void
283  int SPAdj, unsigned FIOperandNum,
284  RegScavenger *RS) const {
285  assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
286 
287  MachineBasicBlock &MBB = *MI->getParent();
288  MachineFunction &MF = *MBB.getParent();
289  auto *TII =
290  static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
291  const SystemZFrameLowering *TFI = getFrameLowering(MF);
292  DebugLoc DL = MI->getDebugLoc();
293 
294  // Decompose the frame index into a base and offset.
295  int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
296  Register BasePtr;
297  int64_t Offset =
298  (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed() +
299  MI->getOperand(FIOperandNum + 1).getImm());
300 
301  // Special handling of dbg_value instructions.
302  if (MI->isDebugValue()) {
303  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
304  if (MI->isNonListDebugValue()) {
305  MI->getDebugOffset().ChangeToImmediate(Offset);
306  } else {
307  unsigned OpIdx = MI->getDebugOperandIndex(&MI->getOperand(FIOperandNum));
310  Ops, TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed());
311  MI->getDebugExpressionOp().setMetadata(
312  DIExpression::appendOpsToArg(MI->getDebugExpression(), Ops, OpIdx));
313  }
314  return;
315  }
316 
317  // See if the offset is in range, or if an equivalent instruction that
318  // accepts the offset exists.
319  unsigned Opcode = MI->getOpcode();
320  unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
321  if (OpcodeForOffset) {
322  if (OpcodeForOffset == SystemZ::LE &&
324  // If LE is ok for offset, use LDE instead on z13.
325  OpcodeForOffset = SystemZ::LDE32;
326  }
327  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
328  }
329  else {
330  // Create an anchor point that is in range. Start at 0xffff so that
331  // can use LLILH to load the immediate.
332  int64_t OldOffset = Offset;
333  int64_t Mask = 0xffff;
334  do {
335  Offset = OldOffset & Mask;
336  OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
337  Mask >>= 1;
338  assert(Mask && "One offset must be OK");
339  } while (!OpcodeForOffset);
340 
341  Register ScratchReg =
342  MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
343  int64_t HighOffset = OldOffset - Offset;
344 
345  if (MI->getDesc().TSFlags & SystemZII::HasIndex
346  && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
347  // Load the offset into the scratch register and use it as an index.
348  // The scratch register then dies here.
349  TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
350  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
351  MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
352  false, false, true);
353  } else {
354  // Load the anchor address into a scratch register.
355  unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
356  if (LAOpcode)
357  BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
358  .addReg(BasePtr).addImm(HighOffset).addReg(0);
359  else {
360  // Load the high offset into the scratch register and use it as
361  // an index.
362  TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
363  BuildMI(MBB, MI, DL, TII->get(SystemZ::LA), ScratchReg)
364  .addReg(BasePtr, RegState::Kill).addImm(0).addReg(ScratchReg);
365  }
366 
367  // Use the scratch register as the base. It then dies here.
368  MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
369  false, false, true);
370  }
371  }
372  MI->setDesc(TII->get(OpcodeForOffset));
373  MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
374 }
375 
377  const TargetRegisterClass *SrcRC,
378  unsigned SubReg,
379  const TargetRegisterClass *DstRC,
380  unsigned DstSubReg,
381  const TargetRegisterClass *NewRC,
382  LiveIntervals &LIS) const {
383  assert (MI->isCopy() && "Only expecting COPY instructions");
384 
385  // Coalesce anything which is not a COPY involving a subreg to/from GR128.
386  if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
387  (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
388  return true;
389 
390  // Allow coalescing of a GR128 subreg COPY only if the live ranges are small
391  // and local to one MBB with not too much interferring registers. Otherwise
392  // regalloc may run out of registers.
393 
394  unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
395  Register GR128Reg = MI->getOperand(WideOpNo).getReg();
396  Register GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
397  LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
398  LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
399 
400  // Check that the two virtual registers are local to MBB.
401  MachineBasicBlock *MBB = MI->getParent();
402  MachineInstr *FirstMI_GR128 =
403  LIS.getInstructionFromIndex(IntGR128.beginIndex());
404  MachineInstr *FirstMI_GRNar =
405  LIS.getInstructionFromIndex(IntGRNar.beginIndex());
406  MachineInstr *LastMI_GR128 = LIS.getInstructionFromIndex(IntGR128.endIndex());
407  MachineInstr *LastMI_GRNar = LIS.getInstructionFromIndex(IntGRNar.endIndex());
408  if ((!FirstMI_GR128 || FirstMI_GR128->getParent() != MBB) ||
409  (!FirstMI_GRNar || FirstMI_GRNar->getParent() != MBB) ||
410  (!LastMI_GR128 || LastMI_GR128->getParent() != MBB) ||
411  (!LastMI_GRNar || LastMI_GRNar->getParent() != MBB))
412  return false;
413 
414  MachineBasicBlock::iterator MII = nullptr, MEE = nullptr;
415  if (WideOpNo == 1) {
416  MII = FirstMI_GR128;
417  MEE = LastMI_GRNar;
418  } else {
419  MII = FirstMI_GRNar;
420  MEE = LastMI_GR128;
421  }
422 
423  // Check if coalescing seems safe by finding the set of clobbered physreg
424  // pairs in the region.
425  BitVector PhysClobbered(getNumRegs());
426  MEE++;
427  for (; MII != MEE; ++MII) {
428  for (const MachineOperand &MO : MII->operands())
429  if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) {
430  for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
431  SI.isValid(); ++SI)
432  if (NewRC->contains(*SI)) {
433  PhysClobbered.set(*SI);
434  break;
435  }
436  }
437  }
438 
439  // Demand an arbitrary margin of free regs.
440  unsigned const DemandedFreeGR128 = 3;
441  if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
442  return false;
443 
444  return true;
445 }
446 
447 Register
449  const SystemZFrameLowering *TFI = getFrameLowering(MF);
450  const SystemZSubtarget *Subtarget = &MF.getSubtarget<SystemZSubtarget>();
452 
453  return TFI->hasFP(MF) ? Regs->getFramePointerRegister()
454  : Regs->getStackPointerRegister();
455 }
456 
457 const TargetRegisterClass *
459  if (RC == &SystemZ::CCRRegClass)
460  return &SystemZ::GR32BitRegClass;
461  return RC;
462 }
463 
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Definition: MachineInstrBuilder.h:131
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---------------------— PointerInfo ------------------------------------—
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Definition: SystemZRegisterInfo.cpp:212
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Definition: SmallVector.h:1168
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Definition: LiveIntervals.h:231
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Definition: SystemZSubtarget.h:108
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Definition: MachineRegisterInfo.h:915
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Return true if the specified register number is in the physical register namespace.
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Definition: TargetRegisterInfo.h:46
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Definition: MachineOperand.h:49
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Definition: MachineRegisterInfo.h:302
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Definition: AArch64BaseInfo.h:268
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Definition: BitVector.h:74
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Definition: LiveInterval.h:680
llvm::SystemZRegisterInfo::getRegAllocationHints
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
Definition: SystemZRegisterInfo.cpp:74
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::Function::getAttributes
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:326
llvm::VirtRegMap::hasPhys
bool hasPhys(Register virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:100
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::CallingConv::AnyReg
@ AnyReg
Definition: CallingConv.h:62
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::SystemZRegisterInfo::getCrossCopyRegClass
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
Definition: SystemZRegisterInfo.cpp:458
LiveIntervals.h
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:239
VirtRegMap.h
llvm::MachineRegisterInfo::def_instructions
iterator_range< def_instr_iterator > def_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:405
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:20
llvm::VirtRegMap::getPhys
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:106
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetRegisterInfo::getRegAllocationHints
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Definition: TargetRegisterInfo.cpp:421
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1616
llvm::SystemZRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
Definition: SystemZRegisterInfo.cpp:246
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:288
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:641
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::SystemZSubtarget
Definition: SystemZSubtarget.h:33
RA
SI optimize exec mask operations pre RA
Definition: SIOptimizeExecMaskingPreRA.cpp:71
llvm::SystemZCallingConventionRegisters::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const =0
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:114
llvm::MachineFunction
Definition: MachineFunction.h:230
SystemZSubtarget.h
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Matrix
Live Register Matrix
Definition: LiveRegMatrix.cpp:44
uint32_t
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SystemZRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Definition: SystemZRegisterInfo.cpp:237
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
llvm::StackOffset::getFixed
static StackOffset getFixed(ScalarTy Fixed)
Definition: TypeSize.h:143
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
llvm::LiveRange::endIndex
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
Definition: LiveInterval.h:384
llvm::SystemZCallingConventionRegisters
A SystemZ-specific class detailing special use registers particular for calling conventions.
Definition: SystemZRegisterInfo.h:46
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::DIExpression::appendOffset
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
Definition: DebugInfoMetadata.cpp:1228
llvm::TargetRegisterClass::getNumRegs
unsigned getNumRegs() const
Return the number of registers in this class.
Definition: TargetRegisterInfo.h:79
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
uint16_t
llvm::TargetFrameLowering::getFrameIndexReference
virtual StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const
getFrameIndexReference - This method should return the base register and offset used to reference a f...
Definition: TargetFrameLoweringImpl.cpp:45
llvm::SystemZ::getTwoOperandOpcode
int getTwoOperandOpcode(uint16_t Opcode)
SystemZGenRegisterInfo
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:585
llvm::SystemZFrameLowering
Definition: SystemZFrameLowering.h:21
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:805
SystemZRegisterInfo.h
llvm::TargetSubtargetInfo::getTargetLowering
virtual const TargetLowering * getTargetLowering() const
Definition: TargetSubtargetInfo.h:96
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::TargetLowering::supportSwiftError
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
Definition: TargetLowering.h:3650
llvm::SmallVectorImpl< MCPhysReg >
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SystemZII::HasIndex
@ HasIndex
Definition: SystemZInstrInfo.h:39
llvm::SystemZSubtarget::getSpecialRegisters
SystemZCallingConventionRegisters * getSpecialRegisters() const
Definition: SystemZSubtarget.h:94
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SystemZELFRegisters::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override final
Definition: SystemZRegisterInfo.cpp:197
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::CallingConv::GHC
@ GHC
Definition: CallingConv.h:51
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:580
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
SmallSet.h
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40