36 #define DEBUG_TYPE "mccodeemitter"
46 : MCII(mcii), Ctx(ctx) {}
47 X86MCCodeEmitter(
const X86MCCodeEmitter &) =
delete;
48 X86MCCodeEmitter &operator=(
const X86MCCodeEmitter &) =
delete;
49 ~X86MCCodeEmitter()
override =
default;
59 unsigned getX86RegNum(
const MCOperand &MO)
const;
61 unsigned getX86RegEncoding(
const MCInst &
MI,
unsigned OpNum)
const;
67 bool isREXExtendedReg(
const MCInst &
MI,
unsigned OpNum)
const;
69 void emitImmediate(
const MCOperand &Disp,
SMLoc Loc,
unsigned ImmSize,
73 void emitRegModRMByte(
const MCOperand &ModRMReg,
unsigned RegOpcodeFld,
76 void emitSIBByte(
unsigned SS,
unsigned Index,
unsigned Base,
79 void emitMemModRMByte(
const MCInst &
MI,
unsigned Op,
unsigned RegOpcodeField,
83 bool ForceSIB =
false)
const;
85 bool emitPrefixImpl(
unsigned &CurOp,
const MCInst &
MI,
88 void emitVEXOpcodePrefix(
int MemOperand,
const MCInst &
MI,
91 void emitSegmentOverridePrefix(
unsigned SegOperand,
const MCInst &
MI,
94 bool emitOpcodePrefix(
int MemOperand,
const MCInst &
MI,
97 bool emitREXPrefix(
int MemOperand,
const MCInst &
MI,
103 static uint8_t
modRMByte(
unsigned Mod,
unsigned RegOpcode,
unsigned RM) {
104 assert(
Mod < 4 && RegOpcode < 8 &&
RM < 8 &&
"ModRM Fields out of range!");
105 return RM | (RegOpcode << 3) | (
Mod << 6);
112 for (
unsigned i = 0;
i != Size; ++
i) {
126 if (!HasEVEX || CD8_Scale == 0)
130 if (
Value & (CD8_Scale - 1))
133 int CDisp8 =
Value / CD8_Scale;
138 ImmOffset = CDisp8 -
Value;
180 if (
S.getName() !=
"_GLOBAL_OFFSET_TABLE_")
196 unsigned Opcode =
MI.getOpcode();
198 if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4 &&
199 Opcode != X86::JCC_4) ||
212 unsigned X86MCCodeEmitter::getX86RegNum(
const MCOperand &MO)
const {
213 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg()) & 0x7;
216 unsigned X86MCCodeEmitter::getX86RegEncoding(
const MCInst &
MI,
217 unsigned OpNum)
const {
218 return Ctx.getRegisterInfo()->getEncodingValue(
MI.getOperand(OpNum).getReg());
225 bool X86MCCodeEmitter::isREXExtendedReg(
const MCInst &
MI,
226 unsigned OpNum)
const {
227 return (getX86RegEncoding(
MI, OpNum) >> 3) & 1;
230 void X86MCCodeEmitter::emitImmediate(
const MCOperand &DispOp,
SMLoc Loc,
234 int ImmOffset)
const {
235 const MCExpr *Expr =
nullptr;
236 if (DispOp.
isImm()) {
264 ImmOffset =
static_cast<int>(OS.
tell() - StartByte);
308 void X86MCCodeEmitter::emitRegModRMByte(
const MCOperand &ModRMReg,
309 unsigned RegOpcodeFld,
314 void X86MCCodeEmitter::emitSIBByte(
unsigned SS,
unsigned Index,
unsigned Base,
320 void X86MCCodeEmitter::emitMemModRMByte(
const MCInst &
MI,
unsigned Op,
321 unsigned RegOpcodeField,
326 bool ForceSIB)
const {
331 unsigned BaseReg =
Base.getReg();
334 if (BaseReg == X86::RIP ||
335 BaseReg == X86::EIP) {
337 "Rip-relative addressing requires 64-bit mode");
339 "Invalid rip-relative address");
342 unsigned Opcode =
MI.getOpcode();
346 if (!(Disp.
isExpr() && isa<MCSymbolRefExpr>(Disp.
getExpr())))
372 case X86::TAILJMPm64:
403 unsigned BaseRegNo = BaseReg ? getX86RegNum(
Base) : -1U;
420 static const unsigned R16Table[] = {0, 0, 0, 7, 0, 6, 4, 5};
421 unsigned RMfield = R16Table[BaseRegNo];
423 assert(RMfield &&
"invalid 16-bit base register");
426 unsigned IndexReg16 = R16Table[getX86RegNum(IndexReg)];
428 assert(IndexReg16 &&
"invalid 16-bit index register");
430 assert(((IndexReg16 ^ RMfield) & 2) &&
431 "invalid 16-bit base/index register combination");
433 "invalid scale for 16-bit memory reference");
437 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
439 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
443 if (Disp.
getImm() == 0 && RMfield != 6) {
456 assert(IndexReg.
getReg() == 0 &&
"Unexpected index register!");
471 bool AllowNoDisp = !UseDisp8 && !UseDisp32;
473 bool AllowDisp8 = !UseDisp32;
478 !ForceSIB && IndexReg.
getReg() == 0 &&
485 (!STI.
hasFeature(X86::Is64Bit) || BaseReg != 0)) {
498 if (Disp.
isImm() && Disp.
getImm() == 0 && AllowNoDisp) {
505 auto *Sym = dyn_cast<MCSymbolRefExpr>(Disp.
getExpr());
520 if (Disp.
isImm() && AllowDisp8) {
534 unsigned Opcode =
MI.getOpcode();
544 "Cannot use ESP as index reg!");
546 bool ForceDisp32 =
false;
547 bool ForceDisp8 =
false;
555 }
else if (Disp.
isImm() && Disp.
getImm() == 0 && AllowNoDisp &&
563 }
else if (Disp.
isImm() && AllowDisp8 &&
577 static const unsigned SSTable[] = {~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3};
578 unsigned SS = SSTable[Scale.
getImm()];
580 unsigned IndexRegNo = IndexReg.
getReg() ? getX86RegNum(IndexReg) : 4;
582 emitSIBByte(
SS, IndexRegNo, BaseRegNo, OS);
588 else if (ForceDisp32)
596 bool X86MCCodeEmitter::emitPrefixImpl(
unsigned &CurOp,
const MCInst &
MI,
599 uint64_t TSFlags = MCII.get(
MI.getOpcode()).TSFlags;
609 unsigned Flags =
MI.getFlags();
626 if (
MI.getOperand(2).getReg() !=
X86::DS)
627 emitSegmentOverridePrefix(2,
MI, OS);
633 if (
MI.getOperand(1).getReg() !=
X86::DS)
634 emitSegmentOverridePrefix(1,
MI, OS);
644 emitSegmentOverridePrefix(1,
MI, OS);
662 void X86MCCodeEmitter::emitVEXOpcodePrefix(
int MemOperand,
const MCInst &
MI,
681 uint8_t EVEX_R2 = 0x1;
747 uint8_t EVEX_V2 = 0x1;
784 uint8_t EVEX_z = (HasEVEX_K && (TSFlags &
X86II::EVEX_Z)) ? 1 : 0;
793 uint8_t EVEX_aaa = 0;
795 bool EncodeRC =
false;
816 VEX_B = ~(BaseRegEnc >> 3) & 1;
817 unsigned IndexRegEnc =
819 VEX_X = ~(IndexRegEnc >> 3) & 1;
821 EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
826 EVEX_aaa = getX86RegEncoding(
MI, CurOp++);
829 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
831 EVEX_V2 = ~(VRegEnc >> 4) & 1;
834 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
835 VEX_R = ~(RegEnc >> 3) & 1;
836 EVEX_R2 = ~(RegEnc >> 4) & 1;
849 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
850 VEX_R = ~(RegEnc >> 3) & 1;
851 EVEX_R2 = ~(RegEnc >> 4) & 1;
854 EVEX_aaa = getX86RegEncoding(
MI, CurOp++);
857 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
859 EVEX_V2 = ~(VRegEnc >> 4) & 1;
863 VEX_B = ~(BaseRegEnc >> 3) & 1;
864 unsigned IndexRegEnc =
866 VEX_X = ~(IndexRegEnc >> 3) & 1;
868 EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
875 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
876 VEX_R = ~(RegEnc >> 3) & 1;
879 VEX_B = ~(BaseRegEnc >> 3) & 1;
880 unsigned IndexRegEnc =
882 VEX_X = ~(IndexRegEnc >> 3) & 1;
889 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
890 VEX_R = ~(RegEnc >> 3) & 1;
892 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
896 VEX_B = ~(BaseRegEnc >> 3) & 1;
897 unsigned IndexRegEnc =
899 VEX_X = ~(IndexRegEnc >> 3) & 1;
914 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
916 EVEX_V2 = ~(VRegEnc >> 4) & 1;
920 EVEX_aaa = getX86RegEncoding(
MI, CurOp++);
923 VEX_B = ~(BaseRegEnc >> 3) & 1;
924 unsigned IndexRegEnc =
926 VEX_X = ~(IndexRegEnc >> 3) & 1;
928 EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
940 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
941 VEX_R = ~(RegEnc >> 3) & 1;
942 EVEX_R2 = ~(RegEnc >> 4) & 1;
945 EVEX_aaa = getX86RegEncoding(
MI, CurOp++);
948 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
950 EVEX_V2 = ~(VRegEnc >> 4) & 1;
953 RegEnc = getX86RegEncoding(
MI, CurOp++);
954 VEX_B = ~(RegEnc >> 3) & 1;
955 VEX_X = ~(RegEnc >> 4) & 1;
959 unsigned RcOperand = NumOps - 1;
960 assert(RcOperand >= CurOp);
961 EVEX_rc =
MI.getOperand(RcOperand).getImm();
962 assert(EVEX_rc <= 3 &&
"Invalid rounding control!");
971 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
972 VEX_R = ~(RegEnc >> 3) & 1;
974 RegEnc = getX86RegEncoding(
MI, CurOp++);
975 VEX_B = ~(RegEnc >> 3) & 1;
977 VEX_4V = ~getX86RegEncoding(
MI, CurOp++) & 0xf;
982 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
983 VEX_R = ~(RegEnc >> 3) & 1;
985 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
991 RegEnc = getX86RegEncoding(
MI, CurOp++);
992 VEX_B = ~(RegEnc >> 3) & 1;
993 VEX_X = ~(RegEnc >> 4) & 1;
1001 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
1002 VEX_B = ~(RegEnc >> 3) & 1;
1003 VEX_X = ~(RegEnc >> 4) & 1;
1006 EVEX_aaa = getX86RegEncoding(
MI, CurOp++);
1009 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
1011 EVEX_V2 = ~(VRegEnc >> 4) & 1;
1014 RegEnc = getX86RegEncoding(
MI, CurOp++);
1015 VEX_R = ~(RegEnc >> 3) & 1;
1016 EVEX_R2 = ~(RegEnc >> 4) & 1;
1025 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
1026 VEX_R = ~(RegEnc >> 3) & 1;
1027 EVEX_R2 = ~(RegEnc >> 4) & 1;
1041 unsigned VRegEnc = getX86RegEncoding(
MI, CurOp++);
1043 EVEX_V2 = ~(VRegEnc >> 4) & 1;
1046 EVEX_aaa = getX86RegEncoding(
MI, CurOp++);
1048 unsigned RegEnc = getX86RegEncoding(
MI, CurOp++);
1049 VEX_B = ~(RegEnc >> 3) & 1;
1050 VEX_X = ~(RegEnc >> 4) & 1;
1071 uint8_t LastByte = VEX_PP | (
VEX_L << 2) | (
VEX_4V << 3);
1075 VEX_B && VEX_X && !
VEX_W && (VEX_5M == 1)) {
1077 emitByte(LastByte | (VEX_R << 7), OS);
1083 emitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, OS);
1092 assert((VEX_5M & 0x7) == VEX_5M &&
1093 "More than 3 significant bits in VEX.m-mmmm fields for EVEX!");
1096 emitByte((VEX_R << 7) | (VEX_X << 6) | (VEX_B << 5) | (EVEX_R2 << 4) |
1101 emitByte((EVEX_z << 7) | (EVEX_rc << 5) | (EVEX_b << 4) | (EVEX_V2 << 3) |
1106 (EVEX_V2 << 3) | EVEX_aaa,
1117 bool X86MCCodeEmitter::emitREXPrefix(
int MemOperand,
const MCInst &
MI,
1120 uint8_t REX = [&, MemOperand]() {
1122 bool UsesHighByteReg =
false;
1130 if (
MI.getNumOperands() == 0)
1133 unsigned NumOps =
MI.getNumOperands();
1137 for (
unsigned i = CurOp;
i != NumOps; ++
i) {
1143 UsesHighByteReg =
true;
1154 const auto *
Ref = dyn_cast<MCSymbolRefExpr>(MO.
getExpr());
1164 REX |= isREXExtendedReg(
MI, CurOp++) << 0;
1168 REX |= isREXExtendedReg(
MI, CurOp++) << 2;
1169 REX |= isREXExtendedReg(
MI, CurOp++) << 0;
1173 REX |= isREXExtendedReg(
MI, CurOp++) << 2;
1179 REX |= isREXExtendedReg(
MI, CurOp++) << 0;
1180 REX |= isREXExtendedReg(
MI, CurOp++) << 2;
1186 REX |= isREXExtendedReg(
MI, CurOp++) << 2;
1211 REX |= isREXExtendedReg(
MI, CurOp++) << 0;
1214 REX |= isREXExtendedReg(
MI, CurOp++) << 2;
1219 if (REX && UsesHighByteReg)
1221 "Cannot encode high byte register in REX-prefixed instruction");
1233 void X86MCCodeEmitter::emitSegmentOverridePrefix(
unsigned SegOperand,
1237 if (
unsigned Reg =
MI.getOperand(SegOperand).getReg())
1247 bool X86MCCodeEmitter::emitOpcodePrefix(
int MemOperand,
const MCInst &
MI,
1280 "REX.W requires 64bit mode.");
1282 ? emitREXPrefix(MemOperand,
MI, STI, OS)
1309 unsigned Opcode =
MI.getOpcode();
1319 emitPrefixImpl(CurOp,
MI, STI, OS);
1325 unsigned Opcode =
MI.getOpcode();
1338 bool HasREX = emitPrefixImpl(CurOp,
MI, STI, OS);
1349 unsigned I8RegNum = 0;
1356 unsigned OpcodeOffset = 0;
1361 errs() <<
"FORM: " <<
Form <<
"\n";
1373 OpcodeOffset =
MI.getOperand(NumOps - 1).getImm();
1374 assert(OpcodeOffset < 16 &&
"Unexpected opcode offset!");
1378 emitByte(BaseOpcode + OpcodeOffset, OS);
1391 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(),
1398 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(),
1401 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(), 1,
FK_Data_1, StartByte,
1406 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(),
1409 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(), 2,
FK_Data_2, StartByte,
1414 emitByte(BaseOpcode + getX86RegNum(
MI.getOperand(CurOp++)), OS);
1419 unsigned SrcRegNum = CurOp + 1;
1427 emitRegModRMByte(
MI.getOperand(CurOp),
1428 getX86RegNum(
MI.getOperand(SrcRegNum)), OS);
1429 CurOp = SrcRegNum + 1;
1444 emitMemModRMByte(
MI, CurOp, getX86RegNum(
MI.getOperand(SrcRegNum)), TSFlags,
1445 HasREX, StartByte, OS,
Fixups, STI, ForceSIB);
1446 CurOp = SrcRegNum + 1;
1451 unsigned SrcRegNum = CurOp + 1;
1459 emitRegModRMByte(
MI.getOperand(SrcRegNum),
1460 getX86RegNum(
MI.getOperand(CurOp)), OS);
1461 CurOp = SrcRegNum + 1;
1463 I8RegNum = getX86RegEncoding(
MI, CurOp++);
1471 unsigned SrcRegNum = CurOp + 1;
1473 emitRegModRMByte(
MI.getOperand(SrcRegNum),
1474 getX86RegNum(
MI.getOperand(CurOp)), OS);
1475 CurOp = SrcRegNum + 1;
1481 unsigned SrcRegNum = CurOp + 1;
1487 assert(HasVEX_I8Reg &&
"MRMSrcRegOp4 should imply VEX_I8Reg");
1488 I8RegNum = getX86RegEncoding(
MI, SrcRegNum++);
1490 emitRegModRMByte(
MI.getOperand(SrcRegNum),
1491 getX86RegNum(
MI.getOperand(CurOp)), OS);
1492 CurOp = SrcRegNum + 1;
1496 unsigned FirstOp = CurOp++;
1497 unsigned SecondOp = CurOp++;
1499 unsigned CC =
MI.getOperand(CurOp++).getImm();
1502 emitRegModRMByte(
MI.getOperand(SecondOp),
1503 getX86RegNum(
MI.getOperand(FirstOp)), OS);
1508 unsigned FirstMemOp = CurOp + 1;
1519 emitMemModRMByte(
MI, FirstMemOp, getX86RegNum(
MI.getOperand(CurOp)),
1520 TSFlags, HasREX, StartByte, OS,
Fixups, STI, ForceSIB);
1523 I8RegNum = getX86RegEncoding(
MI, CurOp++);
1527 unsigned FirstMemOp = CurOp + 1;
1531 emitMemModRMByte(
MI, FirstMemOp, getX86RegNum(
MI.getOperand(CurOp)),
1532 TSFlags, HasREX, StartByte, OS,
Fixups, STI);
1538 unsigned FirstMemOp = CurOp + 1;
1543 assert(HasVEX_I8Reg &&
"MRMSrcRegOp4 should imply VEX_I8Reg");
1544 I8RegNum = getX86RegEncoding(
MI, FirstMemOp++);
1548 emitMemModRMByte(
MI, FirstMemOp, getX86RegNum(
MI.getOperand(CurOp)),
1549 TSFlags, HasREX, StartByte, OS,
Fixups, STI);
1554 unsigned RegOp = CurOp++;
1555 unsigned FirstMemOp = CurOp;
1558 unsigned CC =
MI.getOperand(CurOp++).getImm();
1561 emitMemModRMByte(
MI, FirstMemOp, getX86RegNum(
MI.getOperand(RegOp)),
1562 TSFlags, HasREX, StartByte, OS,
Fixups, STI);
1567 unsigned RegOp = CurOp++;
1569 unsigned CC =
MI.getOperand(CurOp++).getImm();
1571 emitRegModRMByte(
MI.getOperand(RegOp), 0, OS);
1589 emitRegModRMByte(
MI.getOperand(CurOp++),
1598 unsigned FirstMemOp = CurOp;
1601 unsigned CC =
MI.getOperand(CurOp++).getImm();
1604 emitMemModRMByte(
MI, FirstMemOp, 0, TSFlags, HasREX, StartByte, OS,
Fixups,
1623 emitMemModRMByte(
MI, CurOp,
1625 HasREX, StartByte, OS,
Fixups, STI);
1713 assert(I8RegNum < 16 &&
"Register encoding out of range");
1715 if (CurOp != NumOps) {
1716 unsigned Val =
MI.getOperand(CurOp++).getImm();
1717 assert(Val < 16 &&
"Immediate operand value out of range");
1726 while (CurOp != NumOps && NumOps - CurOp <= 2) {
1727 emitImmediate(
MI.getOperand(CurOp++),
MI.getLoc(),
1737 "The size of instruction must be no longer than 15.");
1740 if ( CurOp != NumOps) {
1741 errs() <<
"Cannot encode all operands of: ";
1751 return new X86MCCodeEmitter(MCII, Ctx);