13#ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
14#define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
20class formatted_raw_ostream;
27class MCObjectTargetWriter;
34class MCTargetStreamer;
41namespace DWARFFlavour {
70 const MCSubtargetInfo &STI);
98 const MCSubtargetInfo &STI,
99 const MCRegisterInfo &
MRI,
100 const MCTargetOptions &
Options);
102 const MCSubtargetInfo &STI,
103 const MCRegisterInfo &
MRI,
104 const MCTargetOptions &
Options);
108 formatted_raw_ostream &
OS,
109 MCInstPrinter *InstPrinter,
114 const MCSubtargetInfo &STI);
121 std::unique_ptr<MCAsmBackend> &&AB,
122 std::unique_ptr<MCObjectWriter> &&OW,
123 std::unique_ptr<MCCodeEmitter> &&CE,
125 bool IncrementalLinkerCompatible);
128std::unique_ptr<MCObjectTargetWriter>
132std::unique_ptr<MCObjectTargetWriter>
135std::unique_ptr<MCObjectTargetWriter>
151#define GET_REGINFO_ENUM
152#include "X86GenRegisterInfo.inc"
156#define GET_INSTRINFO_ENUM
157#define GET_INSTRINFO_MC_HELPER_DECLS
158#include "X86GenInstrInfo.inc"
160#define GET_SUBTARGETINFO_ENUM
161#include "X86GenSubtargetInfo.inc"
163#define GET_X86_MNEMONIC_TABLES_H
164#include "X86GenMnemonicTables.inc"
unsigned const MachineRegisterInfo * MRI
@ C
The default llvm calling convention, compatible with C.
bool is32BitMemOperand(const MCInst &MI, unsigned Op)
bool is16BitMemOperand(const MCInst &MI, unsigned Op, const MCSubtargetInfo &STI)
bool hasLockPrefix(const MCInst &MI)
Returns true if this instruction has a LOCK prefix.
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
bool needsAddressSizeOverride(const MCInst &MI, const MCSubtargetInfo &STI, int MemoryOperand, uint64_t TSFlags)
Returns true if this instruction needs an Address-Size override prefix.
std::string ParseX86Triple(const Triple &TT)
MCSubtargetInfo * createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a X86 MCSubtargetInfo instance.
bool is64BitMemOperand(const MCInst &MI, unsigned Op)
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
This is an optimization pass for GlobalISel generic memory operations.
MCTargetStreamer * createX86ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Implements X86-only directives for object files.
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createX86WinCOFFObjectWriter(bool Is64Bit)
Construct an X86 Win COFF object writer.
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCStreamer * createX86WinCOFFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > &&AB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool IncrementalLinkerCompatible)
Construct an X86 Windows COFF machine code streamer which will generate PE/COFF format object files.
std::unique_ptr< MCObjectTargetWriter > createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an X86 Mach-O object writer.
MCTargetStreamer * createX86AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrinter, bool IsVerboseAsm)
Implements X86-only directives for assembly emission.
std::unique_ptr< MCObjectTargetWriter > createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine)
Construct an X86 ELF object writer.
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)