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13 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
14 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
20 class formatted_raw_ostream;
27 class MCObjectTargetWriter;
32 class MCSubtargetInfo;
33 class MCTargetOptions;
34 class MCTargetStreamer;
41 namespace DWARFFlavour {
70 const MCSubtargetInfo &STI);
98 const MCSubtargetInfo &STI,
99 const MCRegisterInfo &
MRI,
100 const MCTargetOptions &
Options);
102 const MCSubtargetInfo &STI,
103 const MCRegisterInfo &
MRI,
104 const MCTargetOptions &
Options);
108 formatted_raw_ostream &OS,
109 MCInstPrinter *InstPrinter,
114 const MCSubtargetInfo &STI);
121 std::unique_ptr<MCAsmBackend> &&AB,
122 std::unique_ptr<MCObjectWriter> &&OW,
123 std::unique_ptr<MCCodeEmitter> &&CE,
125 bool IncrementalLinkerCompatible);
128 std::unique_ptr<MCObjectTargetWriter>
132 std::unique_ptr<MCObjectTargetWriter>
135 std::unique_ptr<MCObjectTargetWriter>
154 #define GET_REGINFO_ENUM
155 #include "X86GenRegisterInfo.inc"
159 #define GET_INSTRINFO_ENUM
160 #define GET_INSTRINFO_MC_HELPER_DECLS
161 #include "X86GenInstrInfo.inc"
163 #define GET_SUBTARGETINFO_ENUM
164 #include "X86GenSubtargetInfo.inc"
166 #define GET_X86_MNEMONIC_TABLES_H
167 #include "X86GenMnemonicTables.inc"
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
bool needsAddressSizeOverride(const MCInst &MI, const MCSubtargetInfo &STI, int MemoryOperand, uint64_t TSFlags)
Returns true if this instruction needs an Address-Size override prefix.
This is an optimization pass for GlobalISel generic memory operations.
bool hasLockPrefix(const MCInst &MI)
Returns true if this instruction has a LOCK prefix.
bool is64BitMemOperand(const MCInst &MI, unsigned Op)
MCStreamer * createX86WinCOFFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > &&AB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool IncrementalLinkerCompatible)
Construct an X86 Windows COFF machine code streamer which will generate PE/COFF format object files.
std::unique_ptr< MCObjectTargetWriter > createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine)
Construct an X86 ELF object writer.
std::unique_ptr< MCObjectTargetWriter > createX86WinCOFFObjectWriter(bool Is64Bit)
Construct an X86 Win COFF object writer.
MCRegister getX86SubSuperRegisterOrZero(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
bool is32BitMemOperand(const MCInst &MI, unsigned Op)
(vector float) vec_cmpeq(*A, *B) C
MCTargetStreamer * createX86ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Implements X86-only directives for object files.
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
MCSubtargetInfo * createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a X86 MCSubtargetInfo instance.
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
bool is16BitMemOperand(const MCInst &MI, unsigned Op, const MCSubtargetInfo &STI)
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
unsigned const MachineRegisterInfo * MRI
std::unique_ptr< MCObjectTargetWriter > createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an X86 Mach-O object writer.
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::string ParseX86Triple(const Triple &TT)
MCTargetStreamer * createX86AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrinter, bool IsVerboseAsm)
Implements X86-only directives for assembly emission.