LLVM 19.0.0git
Namespaces | Macros | Enumerations | Functions
X86MCTargetDesc.h File Reference
#include "llvm/ADT/SmallVector.h"
#include <memory>
#include <string>
#include "X86GenRegisterInfo.inc"
#include "X86GenInstrInfo.inc"
#include "X86GenSubtargetInfo.inc"
#include "X86GenMnemonicTables.inc"

Go to the source code of this file.


namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
namespace  llvm::DWARFFlavour
 Flavour of dwarf regnumbers.
namespace  llvm::N86
 Native X86 register numbers.
namespace  llvm::X86_MC




enum  { llvm::DWARFFlavour::X86_64 = 0 , llvm::DWARFFlavour::X86_32_DarwinEH = 1 , llvm::DWARFFlavour::X86_32_Generic = 2 }
enum  {
  llvm::N86::EAX = 0 , llvm::N86::ECX = 1 , llvm::N86::EDX = 2 , llvm::N86::EBX = 3 ,
  llvm::N86::ESP = 4 , llvm::N86::EBP = 5 , llvm::N86::ESI = 6 , llvm::N86::EDI = 7


std::string llvm::X86_MC::ParseX86Triple (const Triple &TT)
unsigned llvm::X86_MC::getDwarfRegFlavour (const Triple &TT, bool isEH)
void llvm::X86_MC::initLLVMToSEHAndCVRegMapping (MCRegisterInfo *MRI)
bool llvm::X86_MC::hasLockPrefix (const MCInst &MI)
 Returns true if this instruction has a LOCK prefix.
bool llvm::X86_MC::is16BitMemOperand (const MCInst &MI, unsigned Op, const MCSubtargetInfo &STI)
bool llvm::X86_MC::is32BitMemOperand (const MCInst &MI, unsigned Op)
bool llvm::X86_MC::is64BitMemOperand (const MCInst &MI, unsigned Op)
bool llvm::X86_MC::needsAddressSizeOverride (const MCInst &MI, const MCSubtargetInfo &STI, int MemoryOperand, uint64_t TSFlags)
 Returns true if this instruction needs an Address-Size override prefix.
MCSubtargetInfollvm::X86_MC::createX86MCSubtargetInfo (const Triple &TT, StringRef CPU, StringRef FS)
 Create a X86 MCSubtargetInfo instance.
void llvm::X86_MC::emitInstruction (MCObjectStreamer &, const MCInst &Inst, const MCSubtargetInfo &STI)
void llvm::X86_MC::emitPrefix (MCCodeEmitter &MCE, const MCInst &MI, SmallVectorImpl< char > &CB, const MCSubtargetInfo &STI)
MCCodeEmitterllvm::createX86MCCodeEmitter (const MCInstrInfo &MCII, MCContext &Ctx)
MCAsmBackendllvm::createX86_32AsmBackend (const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCAsmBackendllvm::createX86_64AsmBackend (const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCTargetStreamerllvm::createX86AsmTargetStreamer (MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrinter, bool IsVerboseAsm)
 Implements X86-only directives for assembly emission.
MCTargetStreamerllvm::createX86ObjectTargetStreamer (MCStreamer &S, const MCSubtargetInfo &STI)
 Implements X86-only directives for object files.
MCStreamerllvm::createX86WinCOFFStreamer (MCContext &C, std::unique_ptr< MCAsmBackend > &&AB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool IncrementalLinkerCompatible)
 Construct an X86 Windows COFF machine code streamer which will generate PE/COFF format object files.
MCStreamerllvm::createX86ELFStreamer (const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&MOW, std::unique_ptr< MCCodeEmitter > &&MCE)
std::unique_ptr< MCObjectTargetWriterllvm::createX86MachObjectWriter (bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
 Construct an X86 Mach-O object writer.
std::unique_ptr< MCObjectTargetWriterllvm::createX86ELFObjectWriter (bool IsELF64, uint8_t OSABI, uint16_t EMachine)
 Construct an X86 ELF object writer.
std::unique_ptr< MCObjectTargetWriterllvm::createX86WinCOFFObjectWriter (bool Is64Bit)
 Construct an X86 Win COFF object writer.
MCRegister llvm::getX86SubSuperRegister (MCRegister Reg, unsigned Size, bool High=false)

Macro Definition Documentation



Definition at line 168 of file X86MCTargetDesc.h.



Definition at line 169 of file X86MCTargetDesc.h.



Definition at line 163 of file X86MCTargetDesc.h.



Definition at line 172 of file X86MCTargetDesc.h.



Definition at line 175 of file X86MCTargetDesc.h.