LLVM  14.0.0git
X86MCTargetDesc.cpp
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1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides X86 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86MCTargetDesc.h"
15 #include "X86ATTInstPrinter.h"
16 #include "X86BaseInfo.h"
17 #include "X86IntelInstPrinter.h"
18 #include "X86MCAsmInfo.h"
19 #include "llvm/ADT/APInt.h"
20 #include "llvm/ADT/Triple.h"
22 #include "llvm/MC/MCDwarf.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/MC/TargetRegistry.h"
31 #include "llvm/Support/Host.h"
32 
33 using namespace llvm;
34 
35 #define GET_REGINFO_MC_DESC
36 #include "X86GenRegisterInfo.inc"
37 
38 #define GET_INSTRINFO_MC_DESC
39 #define GET_INSTRINFO_MC_HELPERS
40 #include "X86GenInstrInfo.inc"
41 
42 #define GET_SUBTARGETINFO_MC_DESC
43 #include "X86GenSubtargetInfo.inc"
44 
45 std::string X86_MC::ParseX86Triple(const Triple &TT) {
46  std::string FS;
47  // SSE2 should default to enabled in 64-bit mode, but can be turned off
48  // explicitly.
49  if (TT.isArch64Bit())
50  FS = "+64bit-mode,-32bit-mode,-16bit-mode,+sse2";
51  else if (TT.getEnvironment() != Triple::CODE16)
52  FS = "-64bit-mode,+32bit-mode,-16bit-mode";
53  else
54  FS = "-64bit-mode,-32bit-mode,+16bit-mode";
55 
56  return FS;
57 }
58 
59 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
60  if (TT.getArch() == Triple::x86_64)
61  return DWARFFlavour::X86_64;
62 
63  if (TT.isOSDarwin())
65  if (TT.isOSCygMing())
66  // Unsupported by now, just quick fallback
69 }
70 
72  return MI.getFlags() & X86::IP_HAS_LOCK;
73 }
74 
76  // FIXME: TableGen these.
77  for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
78  unsigned SEH = MRI->getEncodingValue(Reg);
79  MRI->mapLLVMRegToSEHReg(Reg, SEH);
80  }
81 
82  // Mapping from CodeView to MC register id.
83  static const struct {
85  MCPhysReg Reg;
86  } RegMap[] = {
88  {codeview::RegisterId::CL, X86::CL},
93  {codeview::RegisterId::DH, X86::DH},
95  {codeview::RegisterId::AX, X86::AX},
96  {codeview::RegisterId::CX, X86::CX},
97  {codeview::RegisterId::DX, X86::DX},
98  {codeview::RegisterId::BX, X86::BX},
99  {codeview::RegisterId::SP, X86::SP},
100  {codeview::RegisterId::BP, X86::BP},
102  {codeview::RegisterId::DI, X86::DI},
108  {codeview::RegisterId::EBP, X86::EBP},
111 
112  {codeview::RegisterId::EFLAGS, X86::EFLAGS},
113 
114  {codeview::RegisterId::ST0, X86::FP0},
115  {codeview::RegisterId::ST1, X86::FP1},
116  {codeview::RegisterId::ST2, X86::FP2},
117  {codeview::RegisterId::ST3, X86::FP3},
118  {codeview::RegisterId::ST4, X86::FP4},
119  {codeview::RegisterId::ST5, X86::FP5},
120  {codeview::RegisterId::ST6, X86::FP6},
121  {codeview::RegisterId::ST7, X86::FP7},
122 
123  {codeview::RegisterId::MM0, X86::MM0},
124  {codeview::RegisterId::MM1, X86::MM1},
125  {codeview::RegisterId::MM2, X86::MM2},
126  {codeview::RegisterId::MM3, X86::MM3},
127  {codeview::RegisterId::MM4, X86::MM4},
128  {codeview::RegisterId::MM5, X86::MM5},
129  {codeview::RegisterId::MM6, X86::MM6},
130  {codeview::RegisterId::MM7, X86::MM7},
131 
132  {codeview::RegisterId::XMM0, X86::XMM0},
133  {codeview::RegisterId::XMM1, X86::XMM1},
134  {codeview::RegisterId::XMM2, X86::XMM2},
135  {codeview::RegisterId::XMM3, X86::XMM3},
136  {codeview::RegisterId::XMM4, X86::XMM4},
137  {codeview::RegisterId::XMM5, X86::XMM5},
138  {codeview::RegisterId::XMM6, X86::XMM6},
139  {codeview::RegisterId::XMM7, X86::XMM7},
140 
141  {codeview::RegisterId::XMM8, X86::XMM8},
142  {codeview::RegisterId::XMM9, X86::XMM9},
143  {codeview::RegisterId::XMM10, X86::XMM10},
144  {codeview::RegisterId::XMM11, X86::XMM11},
145  {codeview::RegisterId::XMM12, X86::XMM12},
146  {codeview::RegisterId::XMM13, X86::XMM13},
147  {codeview::RegisterId::XMM14, X86::XMM14},
148  {codeview::RegisterId::XMM15, X86::XMM15},
149 
150  {codeview::RegisterId::SIL, X86::SIL},
151  {codeview::RegisterId::DIL, X86::DIL},
152  {codeview::RegisterId::BPL, X86::BPL},
153  {codeview::RegisterId::SPL, X86::SPL},
154  {codeview::RegisterId::RAX, X86::RAX},
155  {codeview::RegisterId::RBX, X86::RBX},
156  {codeview::RegisterId::RCX, X86::RCX},
157  {codeview::RegisterId::RDX, X86::RDX},
158  {codeview::RegisterId::RSI, X86::RSI},
159  {codeview::RegisterId::RDI, X86::RDI},
160  {codeview::RegisterId::RBP, X86::RBP},
161  {codeview::RegisterId::RSP, X86::RSP},
162  {codeview::RegisterId::R8, X86::R8},
163  {codeview::RegisterId::R9, X86::R9},
164  {codeview::RegisterId::R10, X86::R10},
165  {codeview::RegisterId::R11, X86::R11},
166  {codeview::RegisterId::R12, X86::R12},
167  {codeview::RegisterId::R13, X86::R13},
168  {codeview::RegisterId::R14, X86::R14},
169  {codeview::RegisterId::R15, X86::R15},
170  {codeview::RegisterId::R8B, X86::R8B},
171  {codeview::RegisterId::R9B, X86::R9B},
172  {codeview::RegisterId::R10B, X86::R10B},
173  {codeview::RegisterId::R11B, X86::R11B},
174  {codeview::RegisterId::R12B, X86::R12B},
175  {codeview::RegisterId::R13B, X86::R13B},
176  {codeview::RegisterId::R14B, X86::R14B},
177  {codeview::RegisterId::R15B, X86::R15B},
178  {codeview::RegisterId::R8W, X86::R8W},
179  {codeview::RegisterId::R9W, X86::R9W},
180  {codeview::RegisterId::R10W, X86::R10W},
181  {codeview::RegisterId::R11W, X86::R11W},
182  {codeview::RegisterId::R12W, X86::R12W},
183  {codeview::RegisterId::R13W, X86::R13W},
184  {codeview::RegisterId::R14W, X86::R14W},
185  {codeview::RegisterId::R15W, X86::R15W},
186  {codeview::RegisterId::R8D, X86::R8D},
187  {codeview::RegisterId::R9D, X86::R9D},
188  {codeview::RegisterId::R10D, X86::R10D},
189  {codeview::RegisterId::R11D, X86::R11D},
190  {codeview::RegisterId::R12D, X86::R12D},
191  {codeview::RegisterId::R13D, X86::R13D},
192  {codeview::RegisterId::R14D, X86::R14D},
193  {codeview::RegisterId::R15D, X86::R15D},
194  {codeview::RegisterId::AMD64_YMM0, X86::YMM0},
195  {codeview::RegisterId::AMD64_YMM1, X86::YMM1},
196  {codeview::RegisterId::AMD64_YMM2, X86::YMM2},
197  {codeview::RegisterId::AMD64_YMM3, X86::YMM3},
198  {codeview::RegisterId::AMD64_YMM4, X86::YMM4},
199  {codeview::RegisterId::AMD64_YMM5, X86::YMM5},
200  {codeview::RegisterId::AMD64_YMM6, X86::YMM6},
201  {codeview::RegisterId::AMD64_YMM7, X86::YMM7},
202  {codeview::RegisterId::AMD64_YMM8, X86::YMM8},
203  {codeview::RegisterId::AMD64_YMM9, X86::YMM9},
204  {codeview::RegisterId::AMD64_YMM10, X86::YMM10},
205  {codeview::RegisterId::AMD64_YMM11, X86::YMM11},
206  {codeview::RegisterId::AMD64_YMM12, X86::YMM12},
207  {codeview::RegisterId::AMD64_YMM13, X86::YMM13},
208  {codeview::RegisterId::AMD64_YMM14, X86::YMM14},
209  {codeview::RegisterId::AMD64_YMM15, X86::YMM15},
210  {codeview::RegisterId::AMD64_YMM16, X86::YMM16},
211  {codeview::RegisterId::AMD64_YMM17, X86::YMM17},
212  {codeview::RegisterId::AMD64_YMM18, X86::YMM18},
213  {codeview::RegisterId::AMD64_YMM19, X86::YMM19},
214  {codeview::RegisterId::AMD64_YMM20, X86::YMM20},
215  {codeview::RegisterId::AMD64_YMM21, X86::YMM21},
216  {codeview::RegisterId::AMD64_YMM22, X86::YMM22},
217  {codeview::RegisterId::AMD64_YMM23, X86::YMM23},
218  {codeview::RegisterId::AMD64_YMM24, X86::YMM24},
219  {codeview::RegisterId::AMD64_YMM25, X86::YMM25},
220  {codeview::RegisterId::AMD64_YMM26, X86::YMM26},
221  {codeview::RegisterId::AMD64_YMM27, X86::YMM27},
222  {codeview::RegisterId::AMD64_YMM28, X86::YMM28},
223  {codeview::RegisterId::AMD64_YMM29, X86::YMM29},
224  {codeview::RegisterId::AMD64_YMM30, X86::YMM30},
225  {codeview::RegisterId::AMD64_YMM31, X86::YMM31},
226  {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0},
227  {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1},
228  {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2},
229  {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3},
230  {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4},
231  {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5},
232  {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6},
233  {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7},
234  {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8},
235  {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9},
236  {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10},
237  {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11},
238  {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12},
239  {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13},
240  {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14},
241  {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15},
242  {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16},
243  {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17},
244  {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18},
245  {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19},
246  {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20},
247  {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21},
248  {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22},
249  {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23},
250  {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24},
251  {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25},
252  {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26},
253  {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27},
254  {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28},
255  {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29},
256  {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30},
257  {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31},
258  {codeview::RegisterId::AMD64_K0, X86::K0},
259  {codeview::RegisterId::AMD64_K1, X86::K1},
260  {codeview::RegisterId::AMD64_K2, X86::K2},
261  {codeview::RegisterId::AMD64_K3, X86::K3},
262  {codeview::RegisterId::AMD64_K4, X86::K4},
263  {codeview::RegisterId::AMD64_K5, X86::K5},
264  {codeview::RegisterId::AMD64_K6, X86::K6},
265  {codeview::RegisterId::AMD64_K7, X86::K7},
266  {codeview::RegisterId::AMD64_XMM16, X86::XMM16},
267  {codeview::RegisterId::AMD64_XMM17, X86::XMM17},
268  {codeview::RegisterId::AMD64_XMM18, X86::XMM18},
269  {codeview::RegisterId::AMD64_XMM19, X86::XMM19},
270  {codeview::RegisterId::AMD64_XMM20, X86::XMM20},
271  {codeview::RegisterId::AMD64_XMM21, X86::XMM21},
272  {codeview::RegisterId::AMD64_XMM22, X86::XMM22},
273  {codeview::RegisterId::AMD64_XMM23, X86::XMM23},
274  {codeview::RegisterId::AMD64_XMM24, X86::XMM24},
275  {codeview::RegisterId::AMD64_XMM25, X86::XMM25},
276  {codeview::RegisterId::AMD64_XMM26, X86::XMM26},
277  {codeview::RegisterId::AMD64_XMM27, X86::XMM27},
278  {codeview::RegisterId::AMD64_XMM28, X86::XMM28},
279  {codeview::RegisterId::AMD64_XMM29, X86::XMM29},
280  {codeview::RegisterId::AMD64_XMM30, X86::XMM30},
281  {codeview::RegisterId::AMD64_XMM31, X86::XMM31},
282 
283  };
284  for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
285  MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
286 }
287 
289  StringRef CPU, StringRef FS) {
290  std::string ArchFS = X86_MC::ParseX86Triple(TT);
291  assert(!ArchFS.empty() && "Failed to parse X86 triple");
292  if (!FS.empty())
293  ArchFS = (Twine(ArchFS) + "," + FS).str();
294 
295  if (CPU.empty())
296  CPU = "generic";
297 
298  return createX86MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
299 }
300 
302  MCInstrInfo *X = new MCInstrInfo();
303  InitX86MCInstrInfo(X);
304  return X;
305 }
306 
308  unsigned RA = (TT.getArch() == Triple::x86_64)
309  ? X86::RIP // Should have dwarf #16.
310  : X86::EIP; // Should have dwarf #8.
311 
313  InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
314  X86_MC::getDwarfRegFlavour(TT, true), RA);
316  return X;
317 }
318 
320  const Triple &TheTriple,
321  const MCTargetOptions &Options) {
322  bool is64Bit = TheTriple.getArch() == Triple::x86_64;
323 
324  MCAsmInfo *MAI;
325  if (TheTriple.isOSBinFormatMachO()) {
326  if (is64Bit)
327  MAI = new X86_64MCAsmInfoDarwin(TheTriple);
328  else
329  MAI = new X86MCAsmInfoDarwin(TheTriple);
330  } else if (TheTriple.isOSBinFormatELF()) {
331  // Force the use of an ELF container.
332  MAI = new X86ELFMCAsmInfo(TheTriple);
333  } else if (TheTriple.isWindowsMSVCEnvironment() ||
334  TheTriple.isWindowsCoreCLREnvironment()) {
335  if (Options.getAssemblyLanguage().equals_insensitive("masm"))
336  MAI = new X86MCAsmInfoMicrosoftMASM(TheTriple);
337  else
338  MAI = new X86MCAsmInfoMicrosoft(TheTriple);
339  } else if (TheTriple.isOSCygMing() ||
340  TheTriple.isWindowsItaniumEnvironment()) {
341  MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
342  } else {
343  // The default is ELF.
344  MAI = new X86ELFMCAsmInfo(TheTriple);
345  }
346 
347  // Initialize initial frame state.
348  // Calculate amount of bytes used for return address storing
349  int stackGrowth = is64Bit ? -8 : -4;
350 
351  // Initial state of the frame pointer is esp+stackGrowth.
352  unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
354  nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
355  MAI->addInitialFrameState(Inst);
356 
357  // Add return address to move list
358  unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
360  nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
361  MAI->addInitialFrameState(Inst2);
362 
363  return MAI;
364 }
365 
367  unsigned SyntaxVariant,
368  const MCAsmInfo &MAI,
369  const MCInstrInfo &MII,
370  const MCRegisterInfo &MRI) {
371  if (SyntaxVariant == 0)
372  return new X86ATTInstPrinter(MAI, MII, MRI);
373  if (SyntaxVariant == 1)
374  return new X86IntelInstPrinter(MAI, MII, MRI);
375  return nullptr;
376 }
377 
379  MCContext &Ctx) {
380  // Default to the stock relocation info.
381  return llvm::createMCRelocationInfo(TheTriple, Ctx);
382 }
383 
384 namespace llvm {
385 namespace X86_MC {
386 
388  X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete;
389  X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete;
390  virtual ~X86MCInstrAnalysis() = default;
391 
392 public:
394 
395 #define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
396 #include "X86GenSubtargetInfo.inc"
397 
398  bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
399  APInt &Mask) const override;
400  std::vector<std::pair<uint64_t, uint64_t>>
401  findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
402  uint64_t GotSectionVA,
403  const Triple &TargetTriple) const override;
404 
405  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
406  uint64_t &Target) const override;
408  const MCSubtargetInfo *STI,
409  uint64_t Addr,
410  uint64_t Size) const override;
411 };
412 
413 #define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
414 #include "X86GenSubtargetInfo.inc"
415 
417  const MCInst &Inst,
418  APInt &Mask) const {
419  const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
420  unsigned NumDefs = Desc.getNumDefs();
421  unsigned NumImplicitDefs = Desc.getNumImplicitDefs();
422  assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
423  "Unexpected number of bits in the mask!");
424 
425  bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX;
426  bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX;
427  bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP;
428 
429  const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID);
430  const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID);
431  const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID);
432 
433  auto ClearsSuperReg = [=](unsigned RegID) {
434  // On X86-64, a general purpose integer register is viewed as a 64-bit
435  // register internal to the processor.
436  // An update to the lower 32 bits of a 64 bit integer register is
437  // architecturally defined to zero extend the upper 32 bits.
438  if (GR32RC.contains(RegID))
439  return true;
440 
441  // Early exit if this instruction has no vex/evex/xop prefix.
442  if (!HasEVEX && !HasVEX && !HasXOP)
443  return false;
444 
445  // All VEX and EVEX encoded instructions are defined to zero the high bits
446  // of the destination register up to VLMAX (i.e. the maximum vector register
447  // width pertaining to the instruction).
448  // We assume the same behavior for XOP instructions too.
449  return VR128XRC.contains(RegID) || VR256XRC.contains(RegID);
450  };
451 
452  Mask.clearAllBits();
453  for (unsigned I = 0, E = NumDefs; I < E; ++I) {
454  const MCOperand &Op = Inst.getOperand(I);
455  if (ClearsSuperReg(Op.getReg()))
456  Mask.setBit(I);
457  }
458 
459  for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {
460  const MCPhysReg Reg = Desc.getImplicitDefs()[I];
461  if (ClearsSuperReg(Reg))
462  Mask.setBit(NumDefs + I);
463  }
464 
465  return Mask.getBoolValue();
466 }
467 
468 static std::vector<std::pair<uint64_t, uint64_t>>
469 findX86PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
470  uint64_t GotPltSectionVA) {
471  // Do a lightweight parsing of PLT entries.
472  std::vector<std::pair<uint64_t, uint64_t>> Result;
473  for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
474  // Recognize a jmp.
475  if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0xa3) {
476  // The jmp instruction at the beginning of each PLT entry jumps to the
477  // address of the base of the .got.plt section plus the immediate.
478  uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
479  Result.push_back(
480  std::make_pair(PltSectionVA + Byte, GotPltSectionVA + Imm));
481  Byte += 6;
482  } else if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
483  // The jmp instruction at the beginning of each PLT entry jumps to the
484  // immediate.
485  uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
486  Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
487  Byte += 6;
488  } else
489  Byte++;
490  }
491  return Result;
492 }
493 
494 static std::vector<std::pair<uint64_t, uint64_t>>
495 findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) {
496  // Do a lightweight parsing of PLT entries.
497  std::vector<std::pair<uint64_t, uint64_t>> Result;
498  for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
499  // Recognize a jmp.
500  if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
501  // The jmp instruction at the beginning of each PLT entry jumps to the
502  // address of the next instruction plus the immediate.
503  uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
504  Result.push_back(
505  std::make_pair(PltSectionVA + Byte, PltSectionVA + Byte + 6 + Imm));
506  Byte += 6;
507  } else
508  Byte++;
509  }
510  return Result;
511 }
512 
513 std::vector<std::pair<uint64_t, uint64_t>> X86MCInstrAnalysis::findPltEntries(
514  uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
515  uint64_t GotPltSectionVA, const Triple &TargetTriple) const {
516  switch (TargetTriple.getArch()) {
517  case Triple::x86:
518  return findX86PltEntries(PltSectionVA, PltContents, GotPltSectionVA);
519  case Triple::x86_64:
520  return findX86_64PltEntries(PltSectionVA, PltContents);
521  default:
522  return {};
523  }
524 }
525 
527  uint64_t Size, uint64_t &Target) const {
528  if (Inst.getNumOperands() == 0 ||
530  return false;
531  Target = Addr + Size + Inst.getOperand(0).getImm();
532  return true;
533 }
534 
536  const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
537  uint64_t Size) const {
538  const MCInstrDesc &MCID = Info->get(Inst.getOpcode());
539  int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags);
540  if (MemOpStart == -1)
541  return None;
542  MemOpStart += X86II::getOperandBias(MCID);
543 
544  const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg);
545  const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg);
546  const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg);
547  const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt);
548  const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp);
549  if (SegReg.getReg() != 0 || IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 ||
550  !Disp.isImm())
551  return None;
552 
553  // RIP-relative addressing.
554  if (BaseReg.getReg() == X86::RIP)
555  return Addr + Size + Disp.getImm();
556 
557  return None;
558 }
559 
560 } // end of namespace X86_MC
561 
562 } // end of namespace llvm
563 
565  return new X86_MC::X86MCInstrAnalysis(Info);
566 }
567 
568 // Force static initialization.
570  for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
571  // Register the MC asm info.
573 
574  // Register the MC instruction info.
575  TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
576 
577  // Register the MC register info.
578  TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo);
579 
580  // Register the MC subtarget info.
581  TargetRegistry::RegisterMCSubtargetInfo(*T,
583 
584  // Register the MC instruction analyzer.
585  TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis);
586 
587  // Register the code emitter.
588  TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter);
589 
590  // Register the obj target streamer.
591  TargetRegistry::RegisterObjectTargetStreamer(*T,
593 
594  // Register the asm target streamer.
595  TargetRegistry::RegisterAsmTargetStreamer(*T, createX86AsmTargetStreamer);
596 
597  TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer);
598 
599  // Register the MCInstPrinter.
600  TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter);
601 
602  // Register the MC relocation info.
603  TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);
604  }
605 
606  // Register the asm backend.
607  TargetRegistry::RegisterMCAsmBackend(getTheX86_32Target(),
609  TargetRegistry::RegisterMCAsmBackend(getTheX86_64Target(),
611 }
612 
614  bool High) {
615  switch (Size) {
616  default: return X86::NoRegister;
617  case 8:
618  if (High) {
619  switch (Reg.id()) {
620  default: return getX86SubSuperRegisterOrZero(Reg, 64);
621  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
622  return X86::SI;
623  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
624  return X86::DI;
625  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
626  return X86::BP;
627  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
628  return X86::SP;
629  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
630  return X86::AH;
631  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
632  return X86::DH;
633  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
634  return X86::CH;
635  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
636  return X86::BH;
637  }
638  } else {
639  switch (Reg.id()) {
640  default: return X86::NoRegister;
641  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
642  return X86::AL;
643  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
644  return X86::DL;
645  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
646  return X86::CL;
647  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
648  return X86::BL;
649  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
650  return X86::SIL;
651  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
652  return X86::DIL;
653  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
654  return X86::BPL;
655  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
656  return X86::SPL;
657  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
658  return X86::R8B;
659  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
660  return X86::R9B;
661  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
662  return X86::R10B;
663  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
664  return X86::R11B;
665  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
666  return X86::R12B;
667  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
668  return X86::R13B;
669  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
670  return X86::R14B;
671  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
672  return X86::R15B;
673  }
674  }
675  case 16:
676  switch (Reg.id()) {
677  default: return X86::NoRegister;
678  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
679  return X86::AX;
680  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
681  return X86::DX;
682  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
683  return X86::CX;
684  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
685  return X86::BX;
686  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
687  return X86::SI;
688  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
689  return X86::DI;
690  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
691  return X86::BP;
692  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
693  return X86::SP;
694  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
695  return X86::R8W;
696  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
697  return X86::R9W;
698  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
699  return X86::R10W;
700  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
701  return X86::R11W;
702  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
703  return X86::R12W;
704  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
705  return X86::R13W;
706  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
707  return X86::R14W;
708  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
709  return X86::R15W;
710  }
711  case 32:
712  switch (Reg.id()) {
713  default: return X86::NoRegister;
714  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
715  return X86::EAX;
716  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
717  return X86::EDX;
718  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
719  return X86::ECX;
720  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
721  return X86::EBX;
722  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
723  return X86::ESI;
724  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
725  return X86::EDI;
726  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
727  return X86::EBP;
728  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
729  return X86::ESP;
730  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
731  return X86::R8D;
732  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
733  return X86::R9D;
734  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
735  return X86::R10D;
736  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
737  return X86::R11D;
738  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
739  return X86::R12D;
740  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
741  return X86::R13D;
742  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
743  return X86::R14D;
744  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
745  return X86::R15D;
746  }
747  case 64:
748  switch (Reg.id()) {
749  default: return 0;
750  case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
751  return X86::RAX;
752  case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
753  return X86::RDX;
754  case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
755  return X86::RCX;
756  case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
757  return X86::RBX;
758  case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
759  return X86::RSI;
760  case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
761  return X86::RDI;
762  case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
763  return X86::RBP;
764  case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
765  return X86::RSP;
766  case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
767  return X86::R8;
768  case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
769  return X86::R9;
770  case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
771  return X86::R10;
772  case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
773  return X86::R11;
774  case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
775  return X86::R12;
776  case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
777  return X86::R13;
778  case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
779  return X86::R14;
780  case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
781  return X86::R15;
782  }
783  }
784 }
785 
788  assert(Res != X86::NoRegister && "Unexpected register or VT");
789  return Res;
790 }
791 
792 
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
LLVMInitializeX86TargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86TargetMC()
Definition: X86MCTargetDesc.cpp:569
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:243
llvm::X86_MC::getDwarfRegFlavour
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
Definition: X86MCTargetDesc.cpp:59
llvm::X86II::EncodingMask
@ EncodingMask
Definition: X86BaseInfo.h:900
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::X86II::getMemoryOperandNo
int getMemoryOperandNo(uint64_t TSFlags)
The function returns the MCInst operand # for the first field of the memory operand.
Definition: X86BaseInfo.h:1090
llvm::X86MCAsmInfoMicrosoft
Definition: X86MCAsmInfo.h:44
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::AArch64CC::AL
@ AL
Definition: AArch64BaseInfo.h:269
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::X86_MC::hasLockPrefix
bool hasLockPrefix(const MCInst &MI)
Returns true if this instruction has a LOCK prefix.
Definition: X86MCTargetDesc.cpp:71
llvm::X86::AddrIndexReg
@ AddrIndexReg
Definition: X86BaseInfo.h:34
llvm::createX86WinCOFFStreamer
MCStreamer * createX86WinCOFFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > &&AB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool IncrementalLinkerCompatible)
Construct an X86 Windows COFF machine code streamer which will generate PE/COFF format object files.
Definition: X86WinCOFFStreamer.cpp:68
T
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::getTheX86_64Target
Target & getTheX86_64Target()
Definition: X86TargetInfo.cpp:17
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1019
llvm::Triple::x86
@ x86
Definition: Triple.h:83
createX86MCInstrAnalysis
static MCInstrAnalysis * createX86MCInstrAnalysis(const MCInstrInfo *Info)
Definition: X86MCTargetDesc.cpp:564
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
High
uint64_t High
Definition: NVVMIntrRange.cpp:61
Host.h
llvm::MCRelocationInfo
Create MCExprs from relocations found in an object file.
Definition: MCRelocationInfo.h:24
ErrorHandling.h
CH
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference CH
Definition: README-X86-64.txt:44
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::X86II::XOP
@ XOP
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:906
llvm::X86MCAsmInfoMicrosoftMASM
Definition: X86MCAsmInfo.h:51
APInt.h
llvm::X86::IP_HAS_LOCK
@ IP_HAS_LOCK
Definition: X86BaseInfo.h:62
llvm::Triple::isWindowsItaniumEnvironment
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:567
llvm::Triple::x86_64
@ x86_64
Definition: Triple.h:84
llvm::Optional< uint64_t >
llvm::N86::EDX
@ EDX
Definition: X86MCTargetDesc.h:51
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition: MCRegisterInfo.h:68
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::X86II::VEX
@ VEX
Definition: X86BaseInfo.h:903
llvm::DWARFFlavour::X86_32_DarwinEH
@ X86_32_DarwinEH
Definition: X86MCTargetDesc.h:43
llvm::getX86SubSuperRegisterOrZero
MCRegister getX86SubSuperRegisterOrZero(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
Definition: X86MCTargetDesc.cpp:613
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:208
createX86MCRelocationInfo
static MCRelocationInfo * createX86MCRelocationInfo(const Triple &TheTriple, MCContext &Ctx)
Definition: X86MCTargetDesc.cpp:378
llvm::ARCISD::BL
@ BL
Definition: ARCISelLowering.h:34
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:162
llvm::DWARFFlavour::X86_32_Generic
@ X86_32_Generic
Definition: X86MCTargetDesc.h:43
X86ATTInstPrinter.h
llvm::Triple::isWindowsMSVCEnvironment
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:558
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
createX86MCInstrInfo
static MCInstrInfo * createX86MCInstrInfo()
Definition: X86MCTargetDesc.cpp:301
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:633
llvm::N86::ESP
@ ESP
Definition: X86MCTargetDesc.h:51
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::X86ELFMCAsmInfo
Definition: X86MCAsmInfo.h:37
llvm::Triple::CODE16
@ CODE16
Definition: Triple.h:217
llvm::X86_MC::findX86PltEntries
static std::vector< std::pair< uint64_t, uint64_t > > findX86PltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents, uint64_t GotPltSectionVA)
Definition: X86MCTargetDesc.cpp:469
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::MCInstrDesc::getImplicitDefs
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:581
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MCInstrAnalysis
Definition: MCInstrAnalysis.h:27
MCSubtargetInfo.h
llvm::createX86ObjectTargetStreamer
MCTargetStreamer * createX86ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Implements X86-only directives for object files.
Definition: X86WinCOFFTargetStreamer.cpp:455
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:646
llvm::createX86_32AsmBackend
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: X86AsmBackend.cpp:1605
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:584
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::X86::AddrScaleAmt
@ AddrScaleAmt
Definition: X86BaseInfo.h:33
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:61
CodeView.h
llvm::Triple::getArch
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:310
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1394
llvm::None
const NoneType None
Definition: None.h:23
llvm::RegisterMCAsmInfoFn
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
Definition: TargetRegistry.h:1097
llvm::MCCFIInstruction
Definition: MCDwarf.h:457
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::X86ATTInstPrinter
Definition: X86ATTInstPrinter.h:20
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::X86_MC::X86MCInstrAnalysis::X86MCInstrAnalysis
X86MCInstrAnalysis(const MCInstrInfo *MCII)
Definition: X86MCTargetDesc.cpp:393
llvm::getTheX86_32Target
Target & getTheX86_32Target()
Definition: X86TargetInfo.cpp:13
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::X86II::getOperandBias
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
Definition: X86BaseInfo.h:1050
X86MCTargetDesc.h
llvm::Triple::isOSCygMing
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:580
llvm::N86::EBP
@ EBP
Definition: X86MCTargetDesc.h:51
createX86MCRegisterInfo
static MCRegisterInfo * createX86MCRegisterInfo(const Triple &TT)
Definition: X86MCTargetDesc.cpp:307
uint64_t
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::getX86SubSuperRegister
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
Definition: X86MCTargetDesc.cpp:786
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
AH
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference AH
Definition: README-X86-64.txt:44
llvm::X86::AddrSegmentReg
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
llvm::MCInstrAnalysis::Info
const MCInstrInfo * Info
Definition: MCInstrAnalysis.h:31
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:95
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::X86_MC::findX86_64PltEntries
static std::vector< std::pair< uint64_t, uint64_t > > findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents)
Definition: X86MCTargetDesc.cpp:495
MCRegisterInfo.h
llvm::X86_MC::X86MCInstrAnalysis::evaluateBranch
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const override
Given a branch instruction try to get the address the branch targets.
Definition: X86MCTargetDesc.cpp:526
llvm::X86_MC::createX86MCSubtargetInfo
MCSubtargetInfo * createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a X86 MCSubtargetInfo instance.
Definition: X86MCTargetDesc.cpp:288
llvm::X86_MC::X86MCInstrAnalysis
Definition: X86MCTargetDesc.cpp:387
llvm::Triple::isWindowsCoreCLREnvironment
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:563
llvm::X86_MC::initLLVMToSEHAndCVRegMapping
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
Definition: X86MCTargetDesc.cpp:75
llvm::X86IntelInstPrinter
Definition: X86IntelInstPrinter.h:21
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI
StandardInstrumentations SI(Debug, VerifyEach)
createX86MCAsmInfo
static MCAsmInfo * createX86MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple, const MCTargetOptions &Options)
Definition: X86MCTargetDesc.cpp:319
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
llvm::codeview::RegisterId
RegisterId
Definition: CodeView.h:517
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:511
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:86
RA
SI optimize exec mask operations pre RA
Definition: SIOptimizeExecMaskingPreRA.cpp:71
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
Triple.h
llvm::createMCRelocationInfo
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
Definition: MCRelocationInfo.cpp:27
llvm::X86_MC::X86MCInstrAnalysis::evaluateMemoryOperandAddress
Optional< uint64_t > evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, uint64_t Size) const override
Given an instruction tries to get the address of a memory operand.
Definition: X86MCTargetDesc.cpp:535
llvm::ArrayRef< uint8_t >
MCInstrAnalysis.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
MachineLocation.h
uint32_t
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::createX86MCCodeEmitter
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: X86MCCodeEmitter.cpp:1844
llvm::X86_MC::X86MCInstrAnalysis::clearsSuperRegisters
bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, APInt &Mask) const override
Returns true if at least one of the register writes performed by.
Definition: X86MCTargetDesc.cpp:416
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
X86IntelInstPrinter.h
llvm::X86MCAsmInfoDarwin
Definition: X86MCAsmInfo.h:23
llvm::X86_MC::X86MCInstrAnalysis::findPltEntries
std::vector< std::pair< uint64_t, uint64_t > > findPltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents, uint64_t GotSectionVA, const Triple &TargetTriple) const override
Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
Definition: X86MCTargetDesc.cpp:513
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
X86MCAsmInfo.h
llvm::N86::EDI
@ EDI
Definition: X86MCTargetDesc.h:51
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::N86::EAX
@ EAX
Definition: X86MCTargetDesc.h:51
llvm::N86::ECX
@ ECX
Definition: X86MCTargetDesc.h:51
BH
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference BH
Definition: README-X86-64.txt:44
X86BaseInfo.h
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition: Endian.h:381
llvm::X86::AddrDisp
@ AddrDisp
Definition: X86BaseInfo.h:35
llvm::N86::ESI
@ ESI
Definition: X86MCTargetDesc.h:51
llvm::X86II::EVEX
@ EVEX
Definition: X86BaseInfo.h:912
MCStreamer.h
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::X86_64MCAsmInfoDarwin
Definition: X86MCAsmInfo.h:30
createX86MCInstPrinter
static MCInstPrinter * createX86MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: X86MCTargetDesc.cpp:366
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::MCCFIInstruction::createOffset
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:549
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::N86::EBX
@ EBX
Definition: X86MCTargetDesc.h:51
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
llvm::DWARFFlavour::X86_64
@ X86_64
Definition: X86MCTargetDesc.h:43
llvm::X86::AddrBaseReg
@ AddrBaseReg
Definition: X86BaseInfo.h:32
X86TargetInfo.h
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::createX86_64AsmBackend
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: X86AsmBackend.cpp:1624
llvm::X86_MC::ParseX86Triple
std::string ParseX86Triple(const Triple &TT)
Definition: X86MCTargetDesc.cpp:45
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
llvm::createX86AsmTargetStreamer
MCTargetStreamer * createX86AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrinter, bool IsVerboseAsm)
Implements X86-only directives for assembly emission.
Definition: X86WinCOFFTargetStreamer.cpp:445
llvm::X86MCAsmInfoGNUCOFF
Definition: X86MCAsmInfo.h:58