35 #define GET_REGINFO_MC_DESC
36 #include "X86GenRegisterInfo.inc"
38 #define GET_INSTRINFO_MC_DESC
39 #define GET_INSTRINFO_MC_HELPERS
40 #include "X86GenInstrInfo.inc"
42 #define GET_SUBTARGETINFO_MC_DESC
43 #include "X86GenSubtargetInfo.inc"
50 FS =
"+64bit-mode,-32bit-mode,-16bit-mode,+sse2";
52 FS =
"-64bit-mode,+32bit-mode,-16bit-mode";
54 FS =
"-64bit-mode,-32bit-mode,+16bit-mode";
81 (Index.isReg() && Index.getReg() != 0 && RC.
contains(Index.getReg()));
90 Index.isReg() && Index.getReg() == 0)
98 if (
Base.isReg() &&
Base.getReg() == X86::EIP) {
99 assert(Index.isReg() && Index.getReg() == 0 &&
"Invalid eip-based address");
102 if (Index.isReg() && Index.getReg() == X86::EIZ)
117 bool Is16BitMode = STI.
hasFeature(X86::Is16Bit);
118 bool Is32BitMode = STI.
hasFeature(X86::Is32Bit);
119 bool Is64BitMode = STI.
hasFeature(X86::Is64Bit);
129 unsigned siReg =
MI.getOperand(1).getReg();
132 (siReg == X86::RSI &&
MI.getOperand(0).getReg() == X86::RDI)) &&
133 "SI and DI register sizes do not match");
134 return (!Is32BitMode && siReg ==
X86::ESI) ||
135 (Is32BitMode && siReg ==
X86::SI);
138 unsigned siReg =
MI.getOperand(0).getReg();
139 return (!Is32BitMode && siReg ==
X86::ESI) ||
140 (Is32BitMode && siReg ==
X86::SI);
143 unsigned siReg =
MI.getOperand(0).getReg();
144 return (!Is32BitMode && siReg ==
X86::EDI) ||
145 (Is32BitMode && siReg == X86::DI);
168 for (
unsigned Reg = X86::NoRegister + 1;
Reg < X86::NUM_TARGET_REGS; ++
Reg) {
169 unsigned SEH =
MRI->getEncodingValue(
Reg);
170 MRI->mapLLVMRegToSEHReg(
Reg, SEH);
174 static const struct {
179 {codeview::RegisterId::CL, X86::CL},
184 {codeview::RegisterId::DH, X86::DH},
186 {codeview::RegisterId::AX, X86::AX},
187 {codeview::RegisterId::CX, X86::CX},
188 {codeview::RegisterId::DX, X86::DX},
189 {codeview::RegisterId::BX, X86::BX},
190 {codeview::RegisterId::SP, X86::SP},
191 {codeview::RegisterId::BP, X86::BP},
193 {codeview::RegisterId::DI, X86::DI},
203 {codeview::RegisterId::EFLAGS, X86::EFLAGS},
205 {codeview::RegisterId::ST0, X86::ST0},
206 {codeview::RegisterId::ST1, X86::ST1},
207 {codeview::RegisterId::ST2, X86::ST2},
208 {codeview::RegisterId::ST3, X86::ST3},
209 {codeview::RegisterId::ST4, X86::ST4},
210 {codeview::RegisterId::ST5, X86::ST5},
211 {codeview::RegisterId::ST6, X86::ST6},
212 {codeview::RegisterId::ST7, X86::ST7},
214 {codeview::RegisterId::ST0, X86::FP0},
215 {codeview::RegisterId::ST1, X86::FP1},
216 {codeview::RegisterId::ST2, X86::FP2},
217 {codeview::RegisterId::ST3, X86::FP3},
218 {codeview::RegisterId::ST4, X86::FP4},
219 {codeview::RegisterId::ST5, X86::FP5},
220 {codeview::RegisterId::ST6, X86::FP6},
221 {codeview::RegisterId::ST7, X86::FP7},
223 {codeview::RegisterId::MM0, X86::MM0},
224 {codeview::RegisterId::MM1, X86::MM1},
225 {codeview::RegisterId::MM2, X86::MM2},
226 {codeview::RegisterId::MM3, X86::MM3},
227 {codeview::RegisterId::MM4, X86::MM4},
228 {codeview::RegisterId::MM5, X86::MM5},
229 {codeview::RegisterId::MM6, X86::MM6},
230 {codeview::RegisterId::MM7, X86::MM7},
232 {codeview::RegisterId::XMM0, X86::XMM0},
233 {codeview::RegisterId::XMM1, X86::XMM1},
234 {codeview::RegisterId::XMM2, X86::XMM2},
235 {codeview::RegisterId::XMM3, X86::XMM3},
236 {codeview::RegisterId::XMM4, X86::XMM4},
237 {codeview::RegisterId::XMM5, X86::XMM5},
238 {codeview::RegisterId::XMM6, X86::XMM6},
239 {codeview::RegisterId::XMM7, X86::XMM7},
241 {codeview::RegisterId::XMM8, X86::XMM8},
242 {codeview::RegisterId::XMM9, X86::XMM9},
243 {codeview::RegisterId::XMM10, X86::XMM10},
244 {codeview::RegisterId::XMM11, X86::XMM11},
245 {codeview::RegisterId::XMM12, X86::XMM12},
246 {codeview::RegisterId::XMM13, X86::XMM13},
247 {codeview::RegisterId::XMM14, X86::XMM14},
248 {codeview::RegisterId::XMM15, X86::XMM15},
250 {codeview::RegisterId::SIL, X86::SIL},
251 {codeview::RegisterId::DIL, X86::DIL},
252 {codeview::RegisterId::BPL, X86::BPL},
253 {codeview::RegisterId::SPL, X86::SPL},
254 {codeview::RegisterId::RAX, X86::RAX},
255 {codeview::RegisterId::RBX, X86::RBX},
256 {codeview::RegisterId::RCX, X86::RCX},
257 {codeview::RegisterId::RDX, X86::RDX},
258 {codeview::RegisterId::RSI, X86::RSI},
259 {codeview::RegisterId::RDI, X86::RDI},
260 {codeview::RegisterId::RBP, X86::RBP},
261 {codeview::RegisterId::RSP, X86::RSP},
262 {codeview::RegisterId::R8, X86::R8},
263 {codeview::RegisterId::R9, X86::R9},
264 {codeview::RegisterId::R10, X86::R10},
265 {codeview::RegisterId::R11, X86::R11},
266 {codeview::RegisterId::R12, X86::R12},
267 {codeview::RegisterId::R13, X86::R13},
268 {codeview::RegisterId::R14, X86::R14},
269 {codeview::RegisterId::R15, X86::R15},
270 {codeview::RegisterId::R8B, X86::R8B},
271 {codeview::RegisterId::R9B, X86::R9B},
272 {codeview::RegisterId::R10B, X86::R10B},
273 {codeview::RegisterId::R11B, X86::R11B},
274 {codeview::RegisterId::R12B, X86::R12B},
275 {codeview::RegisterId::R13B, X86::R13B},
276 {codeview::RegisterId::R14B, X86::R14B},
277 {codeview::RegisterId::R15B, X86::R15B},
278 {codeview::RegisterId::R8W, X86::R8W},
279 {codeview::RegisterId::R9W, X86::R9W},
280 {codeview::RegisterId::R10W, X86::R10W},
281 {codeview::RegisterId::R11W, X86::R11W},
282 {codeview::RegisterId::R12W, X86::R12W},
283 {codeview::RegisterId::R13W, X86::R13W},
284 {codeview::RegisterId::R14W, X86::R14W},
285 {codeview::RegisterId::R15W, X86::R15W},
286 {codeview::RegisterId::R8D, X86::R8D},
287 {codeview::RegisterId::R9D, X86::R9D},
288 {codeview::RegisterId::R10D, X86::R10D},
289 {codeview::RegisterId::R11D, X86::R11D},
290 {codeview::RegisterId::R12D, X86::R12D},
291 {codeview::RegisterId::R13D, X86::R13D},
292 {codeview::RegisterId::R14D, X86::R14D},
293 {codeview::RegisterId::R15D, X86::R15D},
294 {codeview::RegisterId::AMD64_YMM0, X86::YMM0},
295 {codeview::RegisterId::AMD64_YMM1, X86::YMM1},
296 {codeview::RegisterId::AMD64_YMM2, X86::YMM2},
297 {codeview::RegisterId::AMD64_YMM3, X86::YMM3},
298 {codeview::RegisterId::AMD64_YMM4, X86::YMM4},
299 {codeview::RegisterId::AMD64_YMM5, X86::YMM5},
300 {codeview::RegisterId::AMD64_YMM6, X86::YMM6},
301 {codeview::RegisterId::AMD64_YMM7, X86::YMM7},
302 {codeview::RegisterId::AMD64_YMM8, X86::YMM8},
303 {codeview::RegisterId::AMD64_YMM9, X86::YMM9},
304 {codeview::RegisterId::AMD64_YMM10, X86::YMM10},
305 {codeview::RegisterId::AMD64_YMM11, X86::YMM11},
306 {codeview::RegisterId::AMD64_YMM12, X86::YMM12},
307 {codeview::RegisterId::AMD64_YMM13, X86::YMM13},
308 {codeview::RegisterId::AMD64_YMM14, X86::YMM14},
309 {codeview::RegisterId::AMD64_YMM15, X86::YMM15},
310 {codeview::RegisterId::AMD64_YMM16, X86::YMM16},
311 {codeview::RegisterId::AMD64_YMM17, X86::YMM17},
312 {codeview::RegisterId::AMD64_YMM18, X86::YMM18},
313 {codeview::RegisterId::AMD64_YMM19, X86::YMM19},
314 {codeview::RegisterId::AMD64_YMM20, X86::YMM20},
315 {codeview::RegisterId::AMD64_YMM21, X86::YMM21},
316 {codeview::RegisterId::AMD64_YMM22, X86::YMM22},
317 {codeview::RegisterId::AMD64_YMM23, X86::YMM23},
318 {codeview::RegisterId::AMD64_YMM24, X86::YMM24},
319 {codeview::RegisterId::AMD64_YMM25, X86::YMM25},
320 {codeview::RegisterId::AMD64_YMM26, X86::YMM26},
321 {codeview::RegisterId::AMD64_YMM27, X86::YMM27},
322 {codeview::RegisterId::AMD64_YMM28, X86::YMM28},
323 {codeview::RegisterId::AMD64_YMM29, X86::YMM29},
324 {codeview::RegisterId::AMD64_YMM30, X86::YMM30},
325 {codeview::RegisterId::AMD64_YMM31, X86::YMM31},
326 {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0},
327 {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1},
328 {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2},
329 {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3},
330 {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4},
331 {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5},
332 {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6},
333 {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7},
334 {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8},
335 {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9},
336 {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10},
337 {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11},
338 {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12},
339 {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13},
340 {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14},
341 {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15},
342 {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16},
343 {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17},
344 {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18},
345 {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19},
346 {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20},
347 {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21},
348 {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22},
349 {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23},
350 {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24},
351 {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25},
352 {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26},
353 {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27},
354 {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28},
355 {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29},
356 {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30},
357 {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31},
358 {codeview::RegisterId::AMD64_K0, X86::K0},
359 {codeview::RegisterId::AMD64_K1, X86::K1},
360 {codeview::RegisterId::AMD64_K2, X86::K2},
361 {codeview::RegisterId::AMD64_K3, X86::K3},
362 {codeview::RegisterId::AMD64_K4, X86::K4},
363 {codeview::RegisterId::AMD64_K5, X86::K5},
364 {codeview::RegisterId::AMD64_K6, X86::K6},
365 {codeview::RegisterId::AMD64_K7, X86::K7},
366 {codeview::RegisterId::AMD64_XMM16, X86::XMM16},
367 {codeview::RegisterId::AMD64_XMM17, X86::XMM17},
368 {codeview::RegisterId::AMD64_XMM18, X86::XMM18},
369 {codeview::RegisterId::AMD64_XMM19, X86::XMM19},
370 {codeview::RegisterId::AMD64_XMM20, X86::XMM20},
371 {codeview::RegisterId::AMD64_XMM21, X86::XMM21},
372 {codeview::RegisterId::AMD64_XMM22, X86::XMM22},
373 {codeview::RegisterId::AMD64_XMM23, X86::XMM23},
374 {codeview::RegisterId::AMD64_XMM24, X86::XMM24},
375 {codeview::RegisterId::AMD64_XMM25, X86::XMM25},
376 {codeview::RegisterId::AMD64_XMM26, X86::XMM26},
377 {codeview::RegisterId::AMD64_XMM27, X86::XMM27},
378 {codeview::RegisterId::AMD64_XMM28, X86::XMM28},
379 {codeview::RegisterId::AMD64_XMM29, X86::XMM29},
380 {codeview::RegisterId::AMD64_XMM30, X86::XMM30},
381 {codeview::RegisterId::AMD64_XMM31, X86::XMM31},
384 for (
const auto &
I : RegMap)
385 MRI->mapLLVMRegToCVReg(
I.Reg,
static_cast<int>(
I.CVReg));
391 assert(!ArchFS.empty() &&
"Failed to parse X86 triple");
393 ArchFS = (
Twine(ArchFS) +
"," +
FS).str();
398 return createX86MCSubtargetInfoImpl(TT, CPU, CPU, ArchFS);
403 InitX86MCInstrInfo(
X);
435 if (
Options.getAssemblyLanguage().equals_insensitive(
"masm"))
449 int stackGrowth =
is64Bit ? -8 : -4;
454 nullptr,
MRI.getDwarfRegNum(StackPtr,
true), -stackGrowth);
458 unsigned InstPtr =
is64Bit ? X86::RIP : X86::EIP;
460 nullptr,
MRI.getDwarfRegNum(InstPtr,
true), stackGrowth);
467 unsigned SyntaxVariant,
471 if (SyntaxVariant == 0)
473 if (SyntaxVariant == 1)
495 #define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
496 #include "X86GenSubtargetInfo.inc"
500 std::vector<std::pair<uint64_t, uint64_t>>
503 const Triple &TargetTriple)
const override;
516 #define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
517 #include "X86GenSubtargetInfo.inc"
525 assert(
Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
526 "Unexpected number of bits in the mask!");
536 auto ClearsSuperReg = [=](
unsigned RegID) {
545 if (!HasEVEX && !HasVEX && !HasXOP)
556 for (
unsigned I = 0,
E = NumDefs;
I <
E; ++
I) {
558 if (ClearsSuperReg(
Op.getReg()))
562 for (
unsigned I = 0,
E = NumImplicitDefs;
I <
E; ++
I) {
564 if (ClearsSuperReg(
Reg))
565 Mask.setBit(NumDefs +
I);
568 return Mask.getBoolValue();
571 static std::vector<std::pair<uint64_t, uint64_t>>
575 std::vector<std::pair<uint64_t, uint64_t>> Result;
576 for (
uint64_t Byte = 0, End = PltContents.
size(); Byte + 6 < End; ) {
578 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0xa3) {
583 std::make_pair(PltSectionVA + Byte, GotPltSectionVA + Imm));
585 }
else if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
589 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
597 static std::vector<std::pair<uint64_t, uint64_t>>
600 std::vector<std::pair<uint64_t, uint64_t>> Result;
601 for (
uint64_t Byte = 0, End = PltContents.
size(); Byte + 6 < End; ) {
603 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
608 std::make_pair(PltSectionVA + Byte, PltSectionVA + Byte + 6 + Imm));
619 switch (TargetTriple.
getArch()) {
643 if (MemOpStart == -1)
657 if (BaseReg.
getReg() == X86::RIP)
670 if (MemOpStart == -1)
679 if (BaseReg.
getReg() != X86::RIP || SegReg.
getReg() != 0 ||
683 assert(Size > 4 &&
"invalid instruction size for rip-relative lea");
708 TargetRegistry::RegisterMCSubtargetInfo(*
T,
718 TargetRegistry::RegisterObjectTargetStreamer(*
T,
743 default:
return X86::NoRegister;
750 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
752 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
754 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
758 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
760 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
767 default:
return X86::NoRegister;
770 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
772 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
778 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
780 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
782 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
784 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
786 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
788 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
790 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
792 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
794 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
796 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
798 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
804 default:
return X86::NoRegister;
807 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
809 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
815 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
817 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
819 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
821 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
823 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
825 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
827 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
829 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
831 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
833 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
835 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
840 default:
return X86::NoRegister;
843 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
845 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
851 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
853 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
855 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
857 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
859 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
861 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
863 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
865 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
867 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
869 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
871 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
879 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
881 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
887 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
889 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
891 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
893 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
895 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
897 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
899 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
901 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
903 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
905 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
907 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
915 assert(Res != X86::NoRegister &&
"Unexpected register or VT");