LLVM 17.0.0git
X86MCTargetDesc.cpp
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1//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides X86 specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86MCTargetDesc.h"
14#include "TargetInfo/X86TargetInfo.h"
15#include "X86ATTInstPrinter.h"
16#include "X86BaseInfo.h"
17#include "X86IntelInstPrinter.h"
18#include "X86MCAsmInfo.h"
19#include "X86TargetStreamer.h"
20#include "llvm/ADT/APInt.h"
21#include "llvm/DebugInfo/CodeView/CodeView.h"
22#include "llvm/MC/MCDwarf.h"
23#include "llvm/MC/MCInstrAnalysis.h"
24#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/MC/MCRegisterInfo.h"
26#include "llvm/MC/MCStreamer.h"
27#include "llvm/MC/MCSubtargetInfo.h"
28#include "llvm/MC/MachineLocation.h"
29#include "llvm/MC/TargetRegistry.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/TargetParser/Host.h"
32#include "llvm/TargetParser/Triple.h"
33
34using namespace llvm;
35
36#define GET_REGINFO_MC_DESC
37#include "X86GenRegisterInfo.inc"
38
39#define GET_INSTRINFO_MC_DESC
40#define GET_INSTRINFO_MC_HELPERS
41#define ENABLE_INSTR_PREDICATE_VERIFIER
42#include "X86GenInstrInfo.inc"
43
44#define GET_SUBTARGETINFO_MC_DESC
45#include "X86GenSubtargetInfo.inc"
46
47std::string X86_MC::ParseX86Triple(const Triple &TT) {
48 std::string FS;
49 // SSE2 should default to enabled in 64-bit mode, but can be turned off
50 // explicitly.
51 if (TT.isArch64Bit())
52 FS = "+64bit-mode,-32bit-mode,-16bit-mode,+sse2";
53 else if (TT.getEnvironment() != Triple::CODE16)
54 FS = "-64bit-mode,+32bit-mode,-16bit-mode";
55 else
56 FS = "-64bit-mode,-32bit-mode,+16bit-mode";
57
58 return FS;
59}
60
61unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
62 if (TT.getArch() == Triple::x86_64)
63 return DWARFFlavour::X86_64;
64
65 if (TT.isOSDarwin())
66 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
67 if (TT.isOSCygMing())
68 // Unsupported by now, just quick fallback
69 return DWARFFlavour::X86_32_Generic;
70 return DWARFFlavour::X86_32_Generic;
71}
72
73bool X86_MC::hasLockPrefix(const MCInst &MI) {
74 return MI.getFlags() & X86::IP_HAS_LOCK;
75}
76
77static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID) {
78 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);
79 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg);
80 const MCRegisterClass &RC = X86MCRegisterClasses[RegClassID];
81
82 return (Base.isReg() && Base.getReg() != 0 && RC.contains(Base.getReg())) ||
83 (Index.isReg() && Index.getReg() != 0 && RC.contains(Index.getReg()));
84}
85
86bool X86_MC::is16BitMemOperand(const MCInst &MI, unsigned Op,
87 const MCSubtargetInfo &STI) {
88 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);
89 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg);
90
91 if (STI.hasFeature(X86::Is16Bit) && Base.isReg() && Base.getReg() == 0 &&
92 Index.isReg() && Index.getReg() == 0)
93 return true;
94 return isMemOperand(MI, Op, X86::GR16RegClassID);
95}
96
97bool X86_MC::is32BitMemOperand(const MCInst &MI, unsigned Op) {
98 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);
99 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg);
100 if (Base.isReg() && Base.getReg() == X86::EIP) {
101 assert(Index.isReg() && Index.getReg() == 0 && "Invalid eip-based address");
102 return true;
103 }
104 if (Index.isReg() && Index.getReg() == X86::EIZ)
105 return true;
106 return isMemOperand(MI, Op, X86::GR32RegClassID);
107}
108
109#ifndef NDEBUG
110bool X86_MC::is64BitMemOperand(const MCInst &MI, unsigned Op) {
111 return isMemOperand(MI, Op, X86::GR64RegClassID);
112}
113#endif
114
115bool X86_MC::needsAddressSizeOverride(const MCInst &MI,
116 const MCSubtargetInfo &STI,
117 int MemoryOperand, uint64_t TSFlags) {
118 uint64_t AdSize = TSFlags & X86II::AdSizeMask;
119 bool Is16BitMode = STI.hasFeature(X86::Is16Bit);
120 bool Is32BitMode = STI.hasFeature(X86::Is32Bit);
121 bool Is64BitMode = STI.hasFeature(X86::Is64Bit);
122 if ((Is16BitMode && AdSize == X86II::AdSize32) ||
123 (Is32BitMode && AdSize == X86II::AdSize16) ||
124 (Is64BitMode && AdSize == X86II::AdSize32))
125 return true;
126 uint64_t Form = TSFlags & X86II::FormMask;
127 switch (Form) {
128 default:
129 break;
130 case X86II::RawFrmDstSrc: {
131 unsigned siReg = MI.getOperand(1).getReg();
132 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) ||
133 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) ||
134 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&
135 "SI and DI register sizes do not match");
136 return (!Is32BitMode && siReg == X86::ESI) ||
137 (Is32BitMode && siReg == X86::SI);
138 }
139 case X86II::RawFrmSrc: {
140 unsigned siReg = MI.getOperand(0).getReg();
141 return (!Is32BitMode && siReg == X86::ESI) ||
142 (Is32BitMode && siReg == X86::SI);
143 }
144 case X86II::RawFrmDst: {
145 unsigned siReg = MI.getOperand(0).getReg();
146 return (!Is32BitMode && siReg == X86::EDI) ||
147 (Is32BitMode && siReg == X86::DI);
148 }
149 }
150
151 // Determine where the memory operand starts, if present.
152 if (MemoryOperand < 0)
153 return false;
154
155 if (STI.hasFeature(X86::Is64Bit)) {
156 assert(!is16BitMemOperand(MI, MemoryOperand, STI));
157 return is32BitMemOperand(MI, MemoryOperand);
158 }
159 if (STI.hasFeature(X86::Is32Bit)) {
160 assert(!is64BitMemOperand(MI, MemoryOperand));
161 return is16BitMemOperand(MI, MemoryOperand, STI);
162 }
163 assert(STI.hasFeature(X86::Is16Bit));
164 assert(!is64BitMemOperand(MI, MemoryOperand));
165 return !is16BitMemOperand(MI, MemoryOperand, STI);
166}
167
168void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {
169 // FIXME: TableGen these.
170 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
171 unsigned SEH = MRI->getEncodingValue(Reg);
172 MRI->mapLLVMRegToSEHReg(Reg, SEH);
173 }
174
175 // Mapping from CodeView to MC register id.
176 static const struct {
177 codeview::RegisterId CVReg;
178 MCPhysReg Reg;
179 } RegMap[] = {
180 {codeview::RegisterId::AL, X86::AL},
181 {codeview::RegisterId::CL, X86::CL},
182 {codeview::RegisterId::DL, X86::DL},
183 {codeview::RegisterId::BL, X86::BL},
184 {codeview::RegisterId::AH, X86::AH},
185 {codeview::RegisterId::CH, X86::CH},
186 {codeview::RegisterId::DH, X86::DH},
187 {codeview::RegisterId::BH, X86::BH},
188 {codeview::RegisterId::AX, X86::AX},
189 {codeview::RegisterId::CX, X86::CX},
190 {codeview::RegisterId::DX, X86::DX},
191 {codeview::RegisterId::BX, X86::BX},
192 {codeview::RegisterId::SP, X86::SP},
193 {codeview::RegisterId::BP, X86::BP},
194 {codeview::RegisterId::SI, X86::SI},
195 {codeview::RegisterId::DI, X86::DI},
196 {codeview::RegisterId::EAX, X86::EAX},
197 {codeview::RegisterId::ECX, X86::ECX},
198 {codeview::RegisterId::EDX, X86::EDX},
199 {codeview::RegisterId::EBX, X86::EBX},
200 {codeview::RegisterId::ESP, X86::ESP},
201 {codeview::RegisterId::EBP, X86::EBP},
202 {codeview::RegisterId::ESI, X86::ESI},
203 {codeview::RegisterId::EDI, X86::EDI},
204
205 {codeview::RegisterId::EFLAGS, X86::EFLAGS},
206
207 {codeview::RegisterId::ST0, X86::ST0},
208 {codeview::RegisterId::ST1, X86::ST1},
209 {codeview::RegisterId::ST2, X86::ST2},
210 {codeview::RegisterId::ST3, X86::ST3},
211 {codeview::RegisterId::ST4, X86::ST4},
212 {codeview::RegisterId::ST5, X86::ST5},
213 {codeview::RegisterId::ST6, X86::ST6},
214 {codeview::RegisterId::ST7, X86::ST7},
215
216 {codeview::RegisterId::ST0, X86::FP0},
217 {codeview::RegisterId::ST1, X86::FP1},
218 {codeview::RegisterId::ST2, X86::FP2},
219 {codeview::RegisterId::ST3, X86::FP3},
220 {codeview::RegisterId::ST4, X86::FP4},
221 {codeview::RegisterId::ST5, X86::FP5},
222 {codeview::RegisterId::ST6, X86::FP6},
223 {codeview::RegisterId::ST7, X86::FP7},
224
225 {codeview::RegisterId::MM0, X86::MM0},
226 {codeview::RegisterId::MM1, X86::MM1},
227 {codeview::RegisterId::MM2, X86::MM2},
228 {codeview::RegisterId::MM3, X86::MM3},
229 {codeview::RegisterId::MM4, X86::MM4},
230 {codeview::RegisterId::MM5, X86::MM5},
231 {codeview::RegisterId::MM6, X86::MM6},
232 {codeview::RegisterId::MM7, X86::MM7},
233
234 {codeview::RegisterId::XMM0, X86::XMM0},
235 {codeview::RegisterId::XMM1, X86::XMM1},
236 {codeview::RegisterId::XMM2, X86::XMM2},
237 {codeview::RegisterId::XMM3, X86::XMM3},
238 {codeview::RegisterId::XMM4, X86::XMM4},
239 {codeview::RegisterId::XMM5, X86::XMM5},
240 {codeview::RegisterId::XMM6, X86::XMM6},
241 {codeview::RegisterId::XMM7, X86::XMM7},
242
243 {codeview::RegisterId::XMM8, X86::XMM8},
244 {codeview::RegisterId::XMM9, X86::XMM9},
245 {codeview::RegisterId::XMM10, X86::XMM10},
246 {codeview::RegisterId::XMM11, X86::XMM11},
247 {codeview::RegisterId::XMM12, X86::XMM12},
248 {codeview::RegisterId::XMM13, X86::XMM13},
249 {codeview::RegisterId::XMM14, X86::XMM14},
250 {codeview::RegisterId::XMM15, X86::XMM15},
251
252 {codeview::RegisterId::SIL, X86::SIL},
253 {codeview::RegisterId::DIL, X86::DIL},
254 {codeview::RegisterId::BPL, X86::BPL},
255 {codeview::RegisterId::SPL, X86::SPL},
256 {codeview::RegisterId::RAX, X86::RAX},
257 {codeview::RegisterId::RBX, X86::RBX},
258 {codeview::RegisterId::RCX, X86::RCX},
259 {codeview::RegisterId::RDX, X86::RDX},
260 {codeview::RegisterId::RSI, X86::RSI},
261 {codeview::RegisterId::RDI, X86::RDI},
262 {codeview::RegisterId::RBP, X86::RBP},
263 {codeview::RegisterId::RSP, X86::RSP},
264 {codeview::RegisterId::R8, X86::R8},
265 {codeview::RegisterId::R9, X86::R9},
266 {codeview::RegisterId::R10, X86::R10},
267 {codeview::RegisterId::R11, X86::R11},
268 {codeview::RegisterId::R12, X86::R12},
269 {codeview::RegisterId::R13, X86::R13},
270 {codeview::RegisterId::R14, X86::R14},
271 {codeview::RegisterId::R15, X86::R15},
272 {codeview::RegisterId::R8B, X86::R8B},
273 {codeview::RegisterId::R9B, X86::R9B},
274 {codeview::RegisterId::R10B, X86::R10B},
275 {codeview::RegisterId::R11B, X86::R11B},
276 {codeview::RegisterId::R12B, X86::R12B},
277 {codeview::RegisterId::R13B, X86::R13B},
278 {codeview::RegisterId::R14B, X86::R14B},
279 {codeview::RegisterId::R15B, X86::R15B},
280 {codeview::RegisterId::R8W, X86::R8W},
281 {codeview::RegisterId::R9W, X86::R9W},
282 {codeview::RegisterId::R10W, X86::R10W},
283 {codeview::RegisterId::R11W, X86::R11W},
284 {codeview::RegisterId::R12W, X86::R12W},
285 {codeview::RegisterId::R13W, X86::R13W},
286 {codeview::RegisterId::R14W, X86::R14W},
287 {codeview::RegisterId::R15W, X86::R15W},
288 {codeview::RegisterId::R8D, X86::R8D},
289 {codeview::RegisterId::R9D, X86::R9D},
290 {codeview::RegisterId::R10D, X86::R10D},
291 {codeview::RegisterId::R11D, X86::R11D},
292 {codeview::RegisterId::R12D, X86::R12D},
293 {codeview::RegisterId::R13D, X86::R13D},
294 {codeview::RegisterId::R14D, X86::R14D},
295 {codeview::RegisterId::R15D, X86::R15D},
296 {codeview::RegisterId::AMD64_YMM0, X86::YMM0},
297 {codeview::RegisterId::AMD64_YMM1, X86::YMM1},
298 {codeview::RegisterId::AMD64_YMM2, X86::YMM2},
299 {codeview::RegisterId::AMD64_YMM3, X86::YMM3},
300 {codeview::RegisterId::AMD64_YMM4, X86::YMM4},
301 {codeview::RegisterId::AMD64_YMM5, X86::YMM5},
302 {codeview::RegisterId::AMD64_YMM6, X86::YMM6},
303 {codeview::RegisterId::AMD64_YMM7, X86::YMM7},
304 {codeview::RegisterId::AMD64_YMM8, X86::YMM8},
305 {codeview::RegisterId::AMD64_YMM9, X86::YMM9},
306 {codeview::RegisterId::AMD64_YMM10, X86::YMM10},
307 {codeview::RegisterId::AMD64_YMM11, X86::YMM11},
308 {codeview::RegisterId::AMD64_YMM12, X86::YMM12},
309 {codeview::RegisterId::AMD64_YMM13, X86::YMM13},
310 {codeview::RegisterId::AMD64_YMM14, X86::YMM14},
311 {codeview::RegisterId::AMD64_YMM15, X86::YMM15},
312 {codeview::RegisterId::AMD64_YMM16, X86::YMM16},
313 {codeview::RegisterId::AMD64_YMM17, X86::YMM17},
314 {codeview::RegisterId::AMD64_YMM18, X86::YMM18},
315 {codeview::RegisterId::AMD64_YMM19, X86::YMM19},
316 {codeview::RegisterId::AMD64_YMM20, X86::YMM20},
317 {codeview::RegisterId::AMD64_YMM21, X86::YMM21},
318 {codeview::RegisterId::AMD64_YMM22, X86::YMM22},
319 {codeview::RegisterId::AMD64_YMM23, X86::YMM23},
320 {codeview::RegisterId::AMD64_YMM24, X86::YMM24},
321 {codeview::RegisterId::AMD64_YMM25, X86::YMM25},
322 {codeview::RegisterId::AMD64_YMM26, X86::YMM26},
323 {codeview::RegisterId::AMD64_YMM27, X86::YMM27},
324 {codeview::RegisterId::AMD64_YMM28, X86::YMM28},
325 {codeview::RegisterId::AMD64_YMM29, X86::YMM29},
326 {codeview::RegisterId::AMD64_YMM30, X86::YMM30},
327 {codeview::RegisterId::AMD64_YMM31, X86::YMM31},
328 {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0},
329 {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1},
330 {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2},
331 {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3},
332 {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4},
333 {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5},
334 {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6},
335 {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7},
336 {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8},
337 {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9},
338 {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10},
339 {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11},
340 {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12},
341 {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13},
342 {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14},
343 {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15},
344 {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16},
345 {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17},
346 {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18},
347 {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19},
348 {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20},
349 {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21},
350 {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22},
351 {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23},
352 {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24},
353 {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25},
354 {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26},
355 {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27},
356 {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28},
357 {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29},
358 {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30},
359 {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31},
360 {codeview::RegisterId::AMD64_K0, X86::K0},
361 {codeview::RegisterId::AMD64_K1, X86::K1},
362 {codeview::RegisterId::AMD64_K2, X86::K2},
363 {codeview::RegisterId::AMD64_K3, X86::K3},
364 {codeview::RegisterId::AMD64_K4, X86::K4},
365 {codeview::RegisterId::AMD64_K5, X86::K5},
366 {codeview::RegisterId::AMD64_K6, X86::K6},
367 {codeview::RegisterId::AMD64_K7, X86::K7},
368 {codeview::RegisterId::AMD64_XMM16, X86::XMM16},
369 {codeview::RegisterId::AMD64_XMM17, X86::XMM17},
370 {codeview::RegisterId::AMD64_XMM18, X86::XMM18},
371 {codeview::RegisterId::AMD64_XMM19, X86::XMM19},
372 {codeview::RegisterId::AMD64_XMM20, X86::XMM20},
373 {codeview::RegisterId::AMD64_XMM21, X86::XMM21},
374 {codeview::RegisterId::AMD64_XMM22, X86::XMM22},
375 {codeview::RegisterId::AMD64_XMM23, X86::XMM23},
376 {codeview::RegisterId::AMD64_XMM24, X86::XMM24},
377 {codeview::RegisterId::AMD64_XMM25, X86::XMM25},
378 {codeview::RegisterId::AMD64_XMM26, X86::XMM26},
379 {codeview::RegisterId::AMD64_XMM27, X86::XMM27},
380 {codeview::RegisterId::AMD64_XMM28, X86::XMM28},
381 {codeview::RegisterId::AMD64_XMM29, X86::XMM29},
382 {codeview::RegisterId::AMD64_XMM30, X86::XMM30},
383 {codeview::RegisterId::AMD64_XMM31, X86::XMM31},
384
385 };
386 for (const auto &I : RegMap)
387 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
388}
389
390MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
391 StringRef CPU, StringRef FS) {
392 std::string ArchFS = X86_MC::ParseX86Triple(TT);
393 assert(!ArchFS.empty() && "Failed to parse X86 triple");
394 if (!FS.empty())
395 ArchFS = (Twine(ArchFS) + "," + FS).str();
396
397 if (CPU.empty())
398 CPU = "generic";
399
400 return createX86MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
401}
402
403static MCInstrInfo *createX86MCInstrInfo() {
404 MCInstrInfo *X = new MCInstrInfo();
405 InitX86MCInstrInfo(X);
406 return X;
407}
408
409static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
410 unsigned RA = (TT.getArch() == Triple::x86_64)
411 ? X86::RIP // Should have dwarf #16.
412 : X86::EIP; // Should have dwarf #8.
413
414 MCRegisterInfo *X = new MCRegisterInfo();
415 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
416 X86_MC::getDwarfRegFlavour(TT, true), RA);
417 X86_MC::initLLVMToSEHAndCVRegMapping(X);
418 return X;
419}
420
421static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
422 const Triple &TheTriple,
423 const MCTargetOptions &Options) {
424 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
425
426 MCAsmInfo *MAI;
427 if (TheTriple.isOSBinFormatMachO()) {
428 if (is64Bit)
429 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
430 else
431 MAI = new X86MCAsmInfoDarwin(TheTriple);
432 } else if (TheTriple.isOSBinFormatELF()) {
433 // Force the use of an ELF container.
434 MAI = new X86ELFMCAsmInfo(TheTriple);
435 } else if (TheTriple.isWindowsMSVCEnvironment() ||
436 TheTriple.isWindowsCoreCLREnvironment()) {
437 if (Options.getAssemblyLanguage().equals_insensitive("masm"))
438 MAI = new X86MCAsmInfoMicrosoftMASM(TheTriple);
439 else
440 MAI = new X86MCAsmInfoMicrosoft(TheTriple);
441 } else if (TheTriple.isOSCygMing() ||
442 TheTriple.isWindowsItaniumEnvironment()) {
443 MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
444 } else {
445 // The default is ELF.
446 MAI = new X86ELFMCAsmInfo(TheTriple);
447 }
448
449 // Initialize initial frame state.
450 // Calculate amount of bytes used for return address storing
451 int stackGrowth = is64Bit ? -8 : -4;
452
453 // Initial state of the frame pointer is esp+stackGrowth.
454 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
455 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
456 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
457 MAI->addInitialFrameState(Inst);
458
459 // Add return address to move list
460 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
461 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
462 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
463 MAI->addInitialFrameState(Inst2);
464
465 return MAI;
466}
467
468static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
469 unsigned SyntaxVariant,
470 const MCAsmInfo &MAI,
471 const MCInstrInfo &MII,
472 const MCRegisterInfo &MRI) {
473 if (SyntaxVariant == 0)
474 return new X86ATTInstPrinter(MAI, MII, MRI);
475 if (SyntaxVariant == 1)
476 return new X86IntelInstPrinter(MAI, MII, MRI);
477 return nullptr;
478}
479
480static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
481 MCContext &Ctx) {
482 // Default to the stock relocation info.
483 return llvm::createMCRelocationInfo(TheTriple, Ctx);
484}
485
486namespace llvm {
487namespace X86_MC {
488
489class X86MCInstrAnalysis : public MCInstrAnalysis {
490 X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete;
491 X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete;
492 virtual ~X86MCInstrAnalysis() = default;
493
494public:
495 X86MCInstrAnalysis(const MCInstrInfo *MCII) : MCInstrAnalysis(MCII) {}
496
497#define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
498#include "X86GenSubtargetInfo.inc"
499
500 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
501 APInt &Mask) const override;
502 std::vector<std::pair<uint64_t, uint64_t>>
503 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
504 uint64_t GotSectionVA,
505 const Triple &TargetTriple) const override;
506
507 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
508 uint64_t &Target) const override;
509 std::optional<uint64_t>
510 evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI,
511 uint64_t Addr, uint64_t Size) const override;
512 std::optional<uint64_t>
513 getMemoryOperandRelocationOffset(const MCInst &Inst,
514 uint64_t Size) const override;
515};
516
517#define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
518#include "X86GenSubtargetInfo.inc"
519
520bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI,
521 const MCInst &Inst,
522 APInt &Mask) const {
523 const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
524 unsigned NumDefs = Desc.getNumDefs();
525 unsigned NumImplicitDefs = Desc.implicit_defs().size();
526 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
527 "Unexpected number of bits in the mask!");
528
529 bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX;
530 bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX;
531 bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP;
532
533 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID);
534 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID);
535 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID);
536
537 auto ClearsSuperReg = [=](unsigned RegID) {
538 // On X86-64, a general purpose integer register is viewed as a 64-bit
539 // register internal to the processor.
540 // An update to the lower 32 bits of a 64 bit integer register is
541 // architecturally defined to zero extend the upper 32 bits.
542 if (GR32RC.contains(RegID))
543 return true;
544
545 // Early exit if this instruction has no vex/evex/xop prefix.
546 if (!HasEVEX && !HasVEX && !HasXOP)
547 return false;
548
549 // All VEX and EVEX encoded instructions are defined to zero the high bits
550 // of the destination register up to VLMAX (i.e. the maximum vector register
551 // width pertaining to the instruction).
552 // We assume the same behavior for XOP instructions too.
553 return VR128XRC.contains(RegID) || VR256XRC.contains(RegID);
554 };
555
556 Mask.clearAllBits();
557 for (unsigned I = 0, E = NumDefs; I < E; ++I) {
558 const MCOperand &Op = Inst.getOperand(I);
559 if (ClearsSuperReg(Op.getReg()))
560 Mask.setBit(I);
561 }
562
563 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {
564 const MCPhysReg Reg = Desc.implicit_defs()[I];
565 if (ClearsSuperReg(Reg))
566 Mask.setBit(NumDefs + I);
567 }
568
569 return Mask.getBoolValue();
570}
571
572static std::vector<std::pair<uint64_t, uint64_t>>
573findX86PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
574 uint64_t GotPltSectionVA) {
575 // Do a lightweight parsing of PLT entries.
576 std::vector<std::pair<uint64_t, uint64_t>> Result;
577 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
578 // Recognize a jmp.
579 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0xa3) {
580 // The jmp instruction at the beginning of each PLT entry jumps to the
581 // address of the base of the .got.plt section plus the immediate.
582 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
583 Result.push_back(
584 std::make_pair(PltSectionVA + Byte, GotPltSectionVA + Imm));
585 Byte += 6;
586 } else if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
587 // The jmp instruction at the beginning of each PLT entry jumps to the
588 // immediate.
589 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
590 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
591 Byte += 6;
592 } else
593 Byte++;
594 }
595 return Result;
596}
597
598static std::vector<std::pair<uint64_t, uint64_t>>
599findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) {
600 // Do a lightweight parsing of PLT entries.
601 std::vector<std::pair<uint64_t, uint64_t>> Result;
602 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
603 // Recognize a jmp.
604 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
605 // The jmp instruction at the beginning of each PLT entry jumps to the
606 // address of the next instruction plus the immediate.
607 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
608 Result.push_back(
609 std::make_pair(PltSectionVA + Byte, PltSectionVA + Byte + 6 + Imm));
610 Byte += 6;
611 } else
612 Byte++;
613 }
614 return Result;
615}
616
617std::vector<std::pair<uint64_t, uint64_t>> X86MCInstrAnalysis::findPltEntries(
618 uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
619 uint64_t GotPltSectionVA, const Triple &TargetTriple) const {
620 switch (TargetTriple.getArch()) {
621 case Triple::x86:
622 return findX86PltEntries(PltSectionVA, PltContents, GotPltSectionVA);
623 case Triple::x86_64:
624 return findX86_64PltEntries(PltSectionVA, PltContents);
625 default:
626 return {};
627 }
628}
629
630bool X86MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
631 uint64_t Size, uint64_t &Target) const {
632 if (Inst.getNumOperands() == 0 ||
633 Info->get(Inst.getOpcode()).operands()[0].OperandType !=
634 MCOI::OPERAND_PCREL)
635 return false;
636 Target = Addr + Size + Inst.getOperand(0).getImm();
637 return true;
638}
639
640std::optional<uint64_t> X86MCInstrAnalysis::evaluateMemoryOperandAddress(
641 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
642 uint64_t Size) const {
643 const MCInstrDesc &MCID = Info->get(Inst.getOpcode());
644 int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags);
645 if (MemOpStart == -1)
646 return std::nullopt;
647 MemOpStart += X86II::getOperandBias(MCID);
648
649 const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg);
650 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg);
651 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg);
652 const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt);
653 const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp);
654 if (SegReg.getReg() != 0 || IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 ||
655 !Disp.isImm())
656 return std::nullopt;
657
658 // RIP-relative addressing.
659 if (BaseReg.getReg() == X86::RIP)
660 return Addr + Size + Disp.getImm();
661
662 return std::nullopt;
663}
664
665std::optional<uint64_t>
666X86MCInstrAnalysis::getMemoryOperandRelocationOffset(const MCInst &Inst,
667 uint64_t Size) const {
668 if (Inst.getOpcode() != X86::LEA64r)
669 return std::nullopt;
670 const MCInstrDesc &MCID = Info->get(Inst.getOpcode());
671 int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags);
672 if (MemOpStart == -1)
673 return std::nullopt;
674 MemOpStart += X86II::getOperandBias(MCID);
675 const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg);
676 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg);
677 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg);
678 const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt);
679 const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp);
680 // Must be a simple rip-relative address.
681 if (BaseReg.getReg() != X86::RIP || SegReg.getReg() != 0 ||
682 IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || !Disp.isImm())
683 return std::nullopt;
684 // rip-relative ModR/M immediate is 32 bits.
685 assert(Size > 4 && "invalid instruction size for rip-relative lea");
686 return Size - 4;
687}
688
689} // end of namespace X86_MC
690
691} // end of namespace llvm
692
693static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
694 return new X86_MC::X86MCInstrAnalysis(Info);
695}
696
697// Force static initialization.
698extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86TargetMC() {
699 for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
700 // Register the MC asm info.
701 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
702
703 // Register the MC instruction info.
704 TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
705
706 // Register the MC register info.
707 TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo);
708
709 // Register the MC subtarget info.
710 TargetRegistry::RegisterMCSubtargetInfo(*T,
711 X86_MC::createX86MCSubtargetInfo);
712
713 // Register the MC instruction analyzer.
714 TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis);
715
716 // Register the code emitter.
717 TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter);
718
719 // Register the obj target streamer.
720 TargetRegistry::RegisterObjectTargetStreamer(*T,
721 createX86ObjectTargetStreamer);
722
723 // Register the asm target streamer.
724 TargetRegistry::RegisterAsmTargetStreamer(*T, createX86AsmTargetStreamer);
725
726 // Register the null streamer.
727 TargetRegistry::RegisterNullTargetStreamer(*T, createX86NullTargetStreamer);
728
729 TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer);
730
731 // Register the MCInstPrinter.
732 TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter);
733
734 // Register the MC relocation info.
735 TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);
736 }
737
738 // Register the asm backend.
739 TargetRegistry::RegisterMCAsmBackend(getTheX86_32Target(),
740 createX86_32AsmBackend);
741 TargetRegistry::RegisterMCAsmBackend(getTheX86_64Target(),
742 createX86_64AsmBackend);
743}
744
745MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size,
746 bool High) {
747 switch (Size) {
748 default: llvm_unreachable("illegal register size");
749 case 8:
750 if (High) {
751 switch (Reg.id()) {
752 default: return X86::NoRegister;
753 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
754 return X86::AH;
755 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
756 return X86::DH;
757 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
758 return X86::CH;
759 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
760 return X86::BH;
761 }
762 } else {
763 switch (Reg.id()) {
764 default: return X86::NoRegister;
765 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
766 return X86::AL;
767 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
768 return X86::DL;
769 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
770 return X86::CL;
771 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
772 return X86::BL;
773 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
774 return X86::SIL;
775 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
776 return X86::DIL;
777 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
778 return X86::BPL;
779 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
780 return X86::SPL;
781 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
782 return X86::R8B;
783 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
784 return X86::R9B;
785 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
786 return X86::R10B;
787 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
788 return X86::R11B;
789 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
790 return X86::R12B;
791 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
792 return X86::R13B;
793 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
794 return X86::R14B;
795 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
796 return X86::R15B;
797 }
798 }
799 case 16:
800 switch (Reg.id()) {
801 default: return X86::NoRegister;
802 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
803 return X86::AX;
804 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
805 return X86::DX;
806 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
807 return X86::CX;
808 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
809 return X86::BX;
810 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
811 return X86::SI;
812 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
813 return X86::DI;
814 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
815 return X86::BP;
816 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
817 return X86::SP;
818 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
819 return X86::R8W;
820 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
821 return X86::R9W;
822 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
823 return X86::R10W;
824 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
825 return X86::R11W;
826 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
827 return X86::R12W;
828 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
829 return X86::R13W;
830 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
831 return X86::R14W;
832 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
833 return X86::R15W;
834 }
835 case 32:
836 switch (Reg.id()) {
837 default: return X86::NoRegister;
838 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
839 return X86::EAX;
840 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
841 return X86::EDX;
842 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
843 return X86::ECX;
844 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
845 return X86::EBX;
846 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
847 return X86::ESI;
848 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
849 return X86::EDI;
850 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
851 return X86::EBP;
852 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
853 return X86::ESP;
854 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
855 return X86::R8D;
856 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
857 return X86::R9D;
858 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
859 return X86::R10D;
860 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
861 return X86::R11D;
862 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
863 return X86::R12D;
864 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
865 return X86::R13D;
866 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
867 return X86::R14D;
868 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
869 return X86::R15D;
870 }
871 case 64:
872 switch (Reg.id()) {
873 default: return X86::NoRegister;
874 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
875 return X86::RAX;
876 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
877 return X86::RDX;
878 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
879 return X86::RCX;
880 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
881 return X86::RBX;
882 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
883 return X86::RSI;
884 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
885 return X86::RDI;
886 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
887 return X86::RBP;
888 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
889 return X86::RSP;
890 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
891 return X86::R8;
892 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
893 return X86::R9;
894 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
895 return X86::R10;
896 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
897 return X86::R11;
898 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
899 return X86::R12;
900 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
901 return X86::R13;
902 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
903 return X86::R14;
904 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
905 return X86::R15;
906 }
907 }
908}
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
APInt.h
This file implements a class to represent arbitrary precision integral constant values and operations...
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
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uint64_t Addr
Definition: ELFObjHandler.cpp:79
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
Options
static LVOptions Options
Definition: LVOptions.cpp:25
I
#define I(x, y, z)
Definition: MD5.cpp:58
High
uint64_t High
Definition: NVVMIntrRange.cpp:61
TSFlags
uint64_t TSFlags
Definition: RISCVInsertVSETVLI.cpp:635
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RA
SI optimize exec mask operations pre RA
Definition: SIOptimizeExecMaskingPreRA.cpp:71
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1015
LLVMInitializeX86TargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86TargetMC()
Definition: X86MCTargetDesc.cpp:698
createX86MCRelocationInfo
static MCRelocationInfo * createX86MCRelocationInfo(const Triple &TheTriple, MCContext &Ctx)
Definition: X86MCTargetDesc.cpp:480
createX86MCInstrInfo
static MCInstrInfo * createX86MCInstrInfo()
Definition: X86MCTargetDesc.cpp:403
createX86MCRegisterInfo
static MCRegisterInfo * createX86MCRegisterInfo(const Triple &TT)
Definition: X86MCTargetDesc.cpp:409
createX86MCInstPrinter
static MCInstPrinter * createX86MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: X86MCTargetDesc.cpp:468
createX86MCInstrAnalysis
static MCInstrAnalysis * createX86MCInstrAnalysis(const MCInstrInfo *Info)
Definition: X86MCTargetDesc.cpp:693
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static MCAsmInfo * createX86MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple, const MCTargetOptions &Options)
Definition: X86MCTargetDesc.cpp:421
isMemOperand
static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID)
Definition: X86MCTargetDesc.cpp:77
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:160
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:86
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static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:533
llvm::MCCFIInstruction::createOffset
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:571
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:44
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:208
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::MCInstrAnalysis::Info
const MCInstrInfo * Info
Definition: MCInstrAnalysis.h:33
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCInstrDesc::operands
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:248
llvm::MCInstrDesc::implicit_defs
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:580
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition: MCRegisterInfo.h:68
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MCRelocationInfo
Create MCExprs from relocations found in an object file.
Definition: MCRelocationInfo.h:24
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:119
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::Triple::isOSCygMing
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:622
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:688
llvm::Triple::isWindowsCoreCLREnvironment
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:605
llvm::Triple::getArch
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:356
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:675
llvm::Triple::isWindowsMSVCEnvironment
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:594
llvm::Triple::isWindowsItaniumEnvironment
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:609
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::X86_MC::X86MCInstrAnalysis
Definition: X86MCTargetDesc.cpp:489
llvm::X86_MC::X86MCInstrAnalysis::evaluateBranch
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const override
Given a branch instruction try to get the address the branch targets.
Definition: X86MCTargetDesc.cpp:630
llvm::X86_MC::X86MCInstrAnalysis::X86MCInstrAnalysis
X86MCInstrAnalysis(const MCInstrInfo *MCII)
Definition: X86MCTargetDesc.cpp:495
llvm::X86_MC::X86MCInstrAnalysis::findPltEntries
std::vector< std::pair< uint64_t, uint64_t > > findPltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents, uint64_t GotSectionVA, const Triple &TargetTriple) const override
Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
Definition: X86MCTargetDesc.cpp:617
llvm::X86_MC::X86MCInstrAnalysis::evaluateMemoryOperandAddress
std::optional< uint64_t > evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, uint64_t Size) const override
Given an instruction tries to get the address of a memory operand.
Definition: X86MCTargetDesc.cpp:640
llvm::X86_MC::X86MCInstrAnalysis::getMemoryOperandRelocationOffset
std::optional< uint64_t > getMemoryOperandRelocationOffset(const MCInst &Inst, uint64_t Size) const override
Given an instruction with a memory operand that could require relocation, returns the offset within t...
Definition: X86MCTargetDesc.cpp:666
llvm::X86_MC::X86MCInstrAnalysis::clearsSuperRegisters
bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, APInt &Mask) const override
Returns true if at least one of the register writes performed by.
Definition: X86MCTargetDesc.cpp:520
uint16_t
uint32_t
uint64_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::X86II::RawFrmDstSrc
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
Definition: X86BaseInfo.h:612
llvm::X86II::RawFrmDst
@ RawFrmDst
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/RDI.
Definition: X86BaseInfo.h:607
llvm::X86II::XOP
@ XOP
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:916
llvm::X86II::RawFrmSrc
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
Definition: X86BaseInfo.h:603
llvm::X86II::getMemoryOperandNo
int getMemoryOperandNo(uint64_t TSFlags)
The function returns the MCInst operand # for the first field of the memory operand.
Definition: X86BaseInfo.h:1100
llvm::X86II::getOperandBias
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
Definition: X86BaseInfo.h:1060
llvm::X86_MC::is32BitMemOperand
bool is32BitMemOperand(const MCInst &MI, unsigned Op)
Definition: X86MCTargetDesc.cpp:97
llvm::X86_MC::is16BitMemOperand
bool is16BitMemOperand(const MCInst &MI, unsigned Op, const MCSubtargetInfo &STI)
Definition: X86MCTargetDesc.cpp:86
llvm::X86_MC::hasLockPrefix
bool hasLockPrefix(const MCInst &MI)
Returns true if this instruction has a LOCK prefix.
Definition: X86MCTargetDesc.cpp:73
llvm::X86_MC::initLLVMToSEHAndCVRegMapping
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
Definition: X86MCTargetDesc.cpp:168
llvm::X86_MC::findX86PltEntries
static std::vector< std::pair< uint64_t, uint64_t > > findX86PltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents, uint64_t GotPltSectionVA)
Definition: X86MCTargetDesc.cpp:573
llvm::X86_MC::findX86_64PltEntries
static std::vector< std::pair< uint64_t, uint64_t > > findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents)
Definition: X86MCTargetDesc.cpp:599
llvm::X86_MC::needsAddressSizeOverride
bool needsAddressSizeOverride(const MCInst &MI, const MCSubtargetInfo &STI, int MemoryOperand, uint64_t TSFlags)
Returns true if this instruction needs an Address-Size override prefix.
Definition: X86MCTargetDesc.cpp:115
llvm::X86_MC::ParseX86Triple
std::string ParseX86Triple(const Triple &TT)
Definition: X86MCTargetDesc.cpp:47
llvm::X86_MC::createX86MCSubtargetInfo
MCSubtargetInfo * createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a X86 MCSubtargetInfo instance.
Definition: X86MCTargetDesc.cpp:390
llvm::X86_MC::is64BitMemOperand
bool is64BitMemOperand(const MCInst &MI, unsigned Op)
Definition: X86MCTargetDesc.cpp:110
llvm::X86_MC::getDwarfRegFlavour
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
Definition: X86MCTargetDesc.cpp:61
llvm::X86::AddrScaleAmt
@ AddrScaleAmt
Definition: X86BaseInfo.h:33
llvm::X86::AddrSegmentReg
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
llvm::X86::AddrIndexReg
@ AddrIndexReg
Definition: X86BaseInfo.h:34
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition: Endian.h:381
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::createX86ObjectTargetStreamer
MCTargetStreamer * createX86ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Implements X86-only directives for object files.
Definition: X86WinCOFFTargetStreamer.cpp:456
llvm::getX86SubSuperRegister
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
Definition: X86MCTargetDesc.cpp:745
llvm::createX86_64AsmBackend
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: X86AsmBackend.cpp:1533
llvm::createX86MCCodeEmitter
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: X86MCCodeEmitter.cpp:1790
llvm::getTheX86_32Target
Target & getTheX86_32Target()
Definition: X86TargetInfo.cpp:13
llvm::createMCRelocationInfo
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
Definition: MCRelocationInfo.cpp:27
llvm::createX86WinCOFFStreamer
MCStreamer * createX86WinCOFFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > &&AB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool IncrementalLinkerCompatible)
Construct an X86 Windows COFF machine code streamer which will generate PE/COFF format object files.
Definition: X86WinCOFFStreamer.cpp:69
llvm::createX86AsmTargetStreamer
MCTargetStreamer * createX86AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrinter, bool IsVerboseAsm)
Implements X86-only directives for assembly emission.
Definition: X86WinCOFFTargetStreamer.cpp:446
llvm::createX86_32AsmBackend
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: X86AsmBackend.cpp:1514
llvm::getTheX86_64Target
Target & getTheX86_64Target()
Definition: X86TargetInfo.cpp:17
llvm::createX86NullTargetStreamer
MCTargetStreamer * createX86NullTargetStreamer(MCStreamer &S)
Implements X86-only null emission.
Definition: X86TargetStreamer.h:39
llvm::RegisterMCAsmInfoFn
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
Definition: TargetRegistry.h:1176
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:893
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:933
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:999
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:906
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1042
llvm::TargetRegistry::RegisterMCInstrAnalysis
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition: TargetRegistry.h:879
llvm::TargetRegistry::RegisterNullTargetStreamer
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1031
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:986
llvm::TargetRegistry::RegisterCOFFStreamer
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
Definition: TargetRegistry.h:1003
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:873
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1036
llvm::TargetRegistry::RegisterMCRelocationInfo
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target.
Definition: TargetRegistry.h:1056
llvm::X86_64MCAsmInfoDarwin
Definition: X86MCAsmInfo.h:30
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