LLVM  16.0.0git
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llvm::X86_MC::X86MCInstrAnalysis Class Reference
Inheritance diagram for llvm::X86_MC::X86MCInstrAnalysis:
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Public Member Functions

 X86MCInstrAnalysis (const MCInstrInfo *MCII)
bool clearsSuperRegisters (const MCRegisterInfo &MRI, const MCInst &Inst, APInt &Mask) const override
 Returns true if at least one of the register writes performed by. More...
std::vector< std::pair< uint64_t, uint64_t > > findPltEntries (uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents, uint64_t GotSectionVA, const Triple &TargetTriple) const override
 Returns (PLT virtual address, GOT virtual address) pairs for PLT entries. More...
bool evaluateBranch (const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const override
 Given a branch instruction try to get the address the branch targets. More...
Optional< uint64_tevaluateMemoryOperandAddress (const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, uint64_t Size) const override
 Given an instruction tries to get the address of a memory operand. More...
Optional< uint64_tgetMemoryOperandRelocationOffset (const MCInst &Inst, uint64_t Size) const override
 Given an instruction with a memory operand that could require relocation, returns the offset within the instruction of that relocation. More...
- Public Member Functions inherited from llvm::MCInstrAnalysis
 MCInstrAnalysis (const MCInstrInfo *Info)
virtual ~MCInstrAnalysis ()=default
virtual bool isBranch (const MCInst &Inst) const
virtual bool isConditionalBranch (const MCInst &Inst) const
virtual bool isUnconditionalBranch (const MCInst &Inst) const
virtual bool isIndirectBranch (const MCInst &Inst) const
virtual bool isCall (const MCInst &Inst) const
virtual bool isReturn (const MCInst &Inst) const
virtual bool isTerminator (const MCInst &Inst) const
virtual bool isZeroIdiom (const MCInst &MI, APInt &Mask, unsigned CPUID) const
 Returns true if MI is a dependency breaking zero-idiom for the given subtarget. More...
virtual bool isDependencyBreaking (const MCInst &MI, APInt &Mask, unsigned CPUID) const
 Returns true if MI is a dependency breaking instruction for the subtarget associated with CPUID . More...
virtual bool isOptimizableRegisterMove (const MCInst &MI, unsigned CPUID) const
 Returns true if MI is a candidate for move elimination. More...

Additional Inherited Members

- Protected Attributes inherited from llvm::MCInstrAnalysis
const MCInstrInfoInfo

Detailed Description

Definition at line 489 of file X86MCTargetDesc.cpp.

Constructor & Destructor Documentation

◆ X86MCInstrAnalysis()

llvm::X86_MC::X86MCInstrAnalysis::X86MCInstrAnalysis ( const MCInstrInfo MCII)

Definition at line 495 of file X86MCTargetDesc.cpp.

Member Function Documentation

◆ clearsSuperRegisters()

bool llvm::X86_MC::X86MCInstrAnalysis::clearsSuperRegisters ( const MCRegisterInfo MRI,
const MCInst Inst,
APInt Writes 
) const

Returns true if at least one of the register writes performed by.

Instimplicitly clears the upper portion of all super-registers.

Example: on X86-64, a write to EAX implicitly clears the upper half of RAX. Also (still on x86) an XMM write perfomed by an AVX 128-bit instruction implicitly clears the upper portion of the correspondent YMM register.

This method also updates an APInt which is used as mask of register writes. There is one bit for every explicit/implicit write performed by the instruction. If a write implicitly clears its super-registers, then the corresponding bit is set (vic. the corresponding bit is cleared).

The first bits in the APint are related to explicit writes. The remaining bits are related to implicit writes. The sequence of writes follows the machine operand sequence. For implicit writes, the sequence is defined by the MCInstrDesc.

The assumption is that the bit-width of the APInt is correctly set by the caller. The default implementation conservatively assumes that none of the writes clears the upper portion of a super-register.

Reimplemented from llvm::MCInstrAnalysis.

Definition at line 521 of file X86MCTargetDesc.cpp.

References assert(), llvm::MCRegisterClass::contains(), E, llvm::X86II::EncodingMask, llvm::X86II::EVEX, llvm::MCInstrInfo::get(), llvm::MCInstrDesc::getImplicitDefs(), llvm::MCInstrDesc::getNumDefs(), llvm::MCInstrDesc::getNumImplicitDefs(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MachineRegisterInfo::getRegClass(), I, llvm::MCInstrAnalysis::Info, llvm::BitmaskEnumDetail::Mask(), MRI, llvm::MCInstrDesc::TSFlags, llvm::X86II::VEX, and llvm::X86II::XOP.

◆ evaluateBranch()

bool llvm::X86_MC::X86MCInstrAnalysis::evaluateBranch ( const MCInst Inst,
uint64_t  Addr,
uint64_t  Size,
uint64_t Target 
) const

Given a branch instruction try to get the address the branch targets.

Return true on success, and the address in Target.

Reimplemented from llvm::MCInstrAnalysis.

Definition at line 631 of file X86MCTargetDesc.cpp.

References Addr, llvm::MCInstrInfo::get(), llvm::MCOperand::getImm(), llvm::MCInst::getNumOperands(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCInstrAnalysis::Info, llvm::MCOI::OPERAND_PCREL, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

◆ evaluateMemoryOperandAddress()

Optional< uint64_t > llvm::X86_MC::X86MCInstrAnalysis::evaluateMemoryOperandAddress ( const MCInst Inst,
const MCSubtargetInfo STI,
uint64_t  Addr,
uint64_t  Size 
) const

◆ findPltEntries()

std::vector< std::pair< uint64_t, uint64_t > > llvm::X86_MC::X86MCInstrAnalysis::findPltEntries ( uint64_t  PltSectionVA,
ArrayRef< uint8_t >  PltContents,
uint64_t  GotPltSectionVA,
const Triple TargetTriple 
) const

Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.

Reimplemented from llvm::MCInstrAnalysis.

Definition at line 618 of file X86MCTargetDesc.cpp.

References llvm::X86_MC::findX86_64PltEntries(), llvm::X86_MC::findX86PltEntries(), llvm::Triple::getArch(), llvm::Triple::x86, and llvm::Triple::x86_64.

◆ getMemoryOperandRelocationOffset()

Optional< uint64_t > llvm::X86_MC::X86MCInstrAnalysis::getMemoryOperandRelocationOffset ( const MCInst Inst,
uint64_t  Size 
) const

The documentation for this class was generated from the following file: