42#define DEBUG_TYPE "M68k-isel"
108 for (
auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
116 for (
auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
126 for (
auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
134 for (
auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
185 {MVT::i8, MVT::i16, MVT::i32},
LibCall);
229#include "M68kGenCallingConv.inc"
269 Chain,
DL, Dst, Src, SizeNode,
Flags.getNonZeroByValAlign(),
301 unsigned Bytes =
Arg.getValueType().getSizeInBits() / 8;
305 unsigned Op =
Arg.getOpcode();
311 const SDValue &TruncInput =
Arg.getOperand(0);
313 cast<VTSDNode>(TruncInput.
getOperand(1))->getVT() ==
314 Arg.getValueType()) {
324 Register VR = cast<RegisterSDNode>(
Arg.getOperand(1))->getReg();
330 if (!
Flags.isByVal()) {
334 unsigned Opcode = Def->getOpcode();
335 if ((Opcode == M68k::LEA32p || Opcode == M68k::LEA32f) &&
336 Def->getOperand(1).isFI()) {
337 FI = Def->getOperand(1).getIndex();
338 Bytes =
Flags.getByValSize();
342 }
else if (
auto *Ld = dyn_cast<LoadSDNode>(
Arg)) {
358 Bytes =
Flags.getByValSize();
382M68kTargetLowering::getReturnAddressFrameIndex(
SelectionDAG &DAG)
const {
387 if (ReturnAddrIndex == 0) {
391 SlotSize, -(int64_t)SlotSize,
false);
392 FuncInfo->setRAIndex(ReturnAddrIndex);
401 bool IsTailCall,
int FPDiff,
404 OutRetAddr = getReturnAddressFrameIndex(DAG);
411SDValue M68kTargetLowering::EmitTailCallStoreRetAddr(
413 EVT PtrVT,
unsigned SlotSize,
int FPDiff,
const SDLoc &
DL)
const {
419 SlotSize, (int64_t)FPDiff - SlotSize,
false);
424 Chain,
DL, RetFI, NewFI,
435 unsigned ArgIdx)
const {
452 }
else if (VA.
getValVT() == MVT::i16) {
466 bool IsImmutable = !AlwaysUseMutable && !
Flags.isByVal();
468 if (
Flags.isByVal()) {
469 unsigned Bytes =
Flags.getByValSize();
492 ValVT,
DL, Chain, FIN,
512 Chain,
DL,
Arg, PtrOff,
535 bool IsSibcall =
false;
543 if (Attr.getValueAsBool())
554 }
else if (IsTailCall) {
556 IsTailCall = IsEligibleForTailCallOptimization(
571 "Var args not supported with calling convention fastcc");
578 M68kCCState CCInfo(ArgTypes, CallConv, IsVarArg, MF, ArgLocs,
580 CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
583 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
590 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
594 if (IsTailCall && !IsSibcall && !IsMustTail) {
598 FPDiff = NumBytesCallerPushed - NumBytes;
602 if (FPDiff < MFI->getTCReturnAddrDelta())
606 unsigned NumBytesToPush = NumBytes;
607 unsigned NumBytesToPop = NumBytes;
612 if (!Outs.
empty() && Outs.
back().Flags.isInAlloca()) {
614 if (!ArgLocs.
back().isMemLoc())
617 if (ArgLocs.
back().getLocMemOffset() != 0)
619 "the only memory argument");
624 NumBytes - NumBytesToPush,
DL);
628 if (IsTailCall && FPDiff)
629 Chain = EmitTailCallLoadRetAddr(DAG, RetFI, Chain, IsTailCall, FPDiff,
DL);
638 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
642 if (
Flags.isInAlloca())
648 bool IsByVal =
Flags.isByVal();
671 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
673 Chain,
DL,
Arg, SpillSlot,
682 }
else if (!IsSibcall && (!IsTailCall || IsByVal)) {
689 LowerMemOpCallTo(Chain, StackPtr,
Arg,
DL, DAG, VA, Flags));
693 if (!MemOpChains.
empty())
700 if (IsVarArg && IsMustTail) {
702 for (
const auto &
F : Forwards) {
704 RegsToPass.
push_back(std::make_pair(
unsigned(
F.PReg), Val));
711 if (!IsSibcall && IsTailCall) {
723 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
731 if (
Flags.isInAlloca())
739 if (
Flags.isByVal()) {
754 ArgChain,
DL,
Arg, FIN,
759 if (!MemOpChains2.
empty())
763 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetFI,
771 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
773 RegsToPass[i].second, InGlue);
806 unsigned char OpFlags =
817 if (!IsSibcall && IsTailCall) {
830 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i)
832 RegsToPass[i].second.getValueType()));
836 assert(Mask &&
"Missing call preserved mask for calling convention");
852 unsigned NumBytesForCalleeToPop;
855 NumBytesForCalleeToPop = NumBytes;
859 NumBytesForCalleeToPop = 4;
861 NumBytesForCalleeToPop = 0;
867 NumBytesForCalleeToPop = NumBytes;
872 Chain = DAG.
getCALLSEQ_END(Chain, NumBytesToPop, NumBytesForCalleeToPop,
879 return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins,
DL, DAG,
883SDValue M68kTargetLowering::LowerCallResult(
892 CCInfo.AnalyzeCallResult(Ins, RetCC_M68k);
895 for (
unsigned i = 0, e = RVLocs.
size(); i != e; ++i) {
918SDValue M68kTargetLowering::LowerFormalArguments(
935 CCInfo.AnalyzeFormalArguments(Ins, CC_M68k);
937 unsigned LastVal = ~0
U;
939 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
941 assert(VA.
getValNo() != LastVal &&
"Same value in different locations");
948 if (RegVT == MVT::i32)
949 RC = &M68k::XR32RegClass;
974 ArgValue = LowerMemArgument(Chain, CCID, Ins,
DL, DAG, VA, MFI, i);
986 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
995 if (Ins[i].
Flags.isSRet()) {
1008 unsigned StackSize = CCInfo.getStackSize();
1011 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1016 if (MFI.hasVAStart()) {
1020 if (IsVarArg && MFI.hasMustTailInVarArgFunc()) {
1023 MVT IntVT = MVT::i32;
1030 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_M68k);
1061bool M68kTargetLowering::CanLowerReturn(
1065 CCState CCInfo(CCID, IsVarArg, MF, RVLocs, Context);
1066 return CCInfo.CheckReturn(Outs, RetCC_M68k);
1080 CCInfo.AnalyzeReturn(Outs, RetCC_M68k);
1091 for (
unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1094 SDValue ValToCopy = OutVals[i];
1152 unsigned RetValReg = M68k::D0;
1202M68kTargetLowering::GetAlignedArgumentStackSize(
unsigned StackSize,
1206 uint64_t AlignMask = StackAlignment - 1;
1207 int64_t
Offset = StackSize;
1209 if ((
Offset & AlignMask) <= (StackAlignment - SlotSize)) {
1211 Offset += ((StackAlignment - SlotSize) - (
Offset & AlignMask));
1215 ((~AlignMask) &
Offset) + StackAlignment + (StackAlignment - SlotSize);
1222bool M68kTargetLowering::IsEligibleForTailCallOptimization(
1224 bool IsCalleeStructRet,
bool IsCallerStructRet,
Type *
RetTy,
1236 bool CCMatch = CallerCC == CalleeCC;
1250 if (
RegInfo->hasStackRealignment(MF))
1255 if (IsCalleeStructRet || IsCallerStructRet)
1261 if (IsVarArg && !Outs.
empty()) {
1264 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs,
C);
1266 CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
1267 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i)
1268 if (!ArgLocs[i].isRegLoc())
1279 const uint32_t *CallerPreserved =
TRI->getCallPreservedMask(MF, CallerCC);
1281 const uint32_t *CalleePreserved =
TRI->getCallPreservedMask(MF, CalleeCC);
1282 if (!
TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
1286 unsigned StackArgsSize = 0;
1290 if (!Outs.
empty()) {
1294 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs,
C);
1296 CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
1297 StackArgsSize = CCInfo.getStackSize();
1299 if (StackArgsSize) {
1305 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
1325 if ((!isa<GlobalAddressSDNode>(
Callee) &&
1326 !isa<ExternalSymbolSDNode>(
Callee)) ||
1327 PositionIndependent) {
1328 unsigned NumInRegs = 0;
1331 unsigned MaxInRegs = PositionIndependent ? 1 : 2;
1333 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
1343 if (++NumInRegs == MaxInRegs)
1358 if (
unsigned BytesToPop =
1361 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
1362 if (!CalleePopMatches)
1364 }
else if (CalleeWillPop && StackArgsSize > 0) {
1378 switch (Op.getOpcode()) {
1387 return LowerXALUO(Op, DAG);
1389 return LowerSETCC(Op, DAG);
1391 return LowerSETCCCARRY(Op, DAG);
1393 return LowerSELECT(Op, DAG);
1395 return LowerBRCOND(Op, DAG);
1400 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1402 return LowerConstantPool(Op, DAG);
1404 return LowerGlobalAddress(Op, DAG);
1406 return LowerExternalSymbol(Op, DAG);
1408 return LowerBlockAddress(Op, DAG);
1410 return LowerJumpTable(Op, DAG);
1412 return LowerVASTART(Op, DAG);
1414 return LowerDYNAMIC_STACKALLOC(Op, DAG);
1416 return LowerShiftLeftParts(Op, DAG);
1418 return LowerShiftRightParts(Op, DAG,
true);
1420 return LowerShiftRightParts(Op, DAG,
false);
1422 return LowerATOMICFENCE(Op, DAG);
1426bool M68kTargetLowering::decomposeMulByConstant(
LLVMContext &Context,
EVT VT,
1444 unsigned BaseOp = 0;
1447 switch (Op.getOpcode()) {
1485 if (Src.getValueType() == MVT::i8 || Src.getValueType() == MVT::i16)
1519 unsigned AndBitWidth =
And.getValueSizeInBits();
1522 if (Known.countMinLeadingZeros() <
BitWidth - AndBitWidth)
1528 }
else if (
auto *AndRHS = dyn_cast<ConstantSDNode>(Op1)) {
1529 uint64_t AndRHSVal = AndRHS->getZExtValue();
1551 switch (SetCCOpcode) {
1585 if (SetCCOpcode ==
ISD::SETGT && RHSC->isAllOnes()) {
1590 if (SetCCOpcode ==
ISD::SETLT && RHSC->isZero()) {
1594 if (SetCCOpcode ==
ISD::SETLT && RHSC->getZExtValue() == 1) {
1608 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
1612 switch (SetCCOpcode) {
1629 switch (SetCCOpcode) {
1665 "Expected TRUNCATE to i1 node");
1667 if (Op.getOperand(0).getOpcode() !=
ISD::SRL)
1670 SDValue ShiftRight = Op.getOperand(0);
1680 unsigned UOpNo = UI.getOperandNo();
1699 bool NeedCF =
false;
1700 bool NeedOF =
false;
1719 switch (
Op->getOpcode()) {
1724 if (
Op.getNode()->getFlags().hasNoSignedWrap())
1738 if (
Op.getResNo() != 0 || NeedOF || NeedCF) {
1743 unsigned Opcode = 0;
1744 unsigned NumOperands = 0;
1749 bool NeedTruncation =
false;
1763 NeedTruncation =
true;
1783 Op->hasOneUse() && isa<ConstantSDNode>(
Op->getOperand(1)) &&
1785 EVT VT =
Op.getValueType();
1787 unsigned ShAmt =
Op->getConstantOperandVal(1);
1793 if (!
Mask.isSignedIntN(32))
1808 bool IsLegalAndnType = VT == MVT::i32 || VT == MVT::i64;
1812 if ( !IsAndn || !IsLegalAndnType)
1821 for (
const auto *U :
Op.getNode()->uses())
1858 if (NeedTruncation) {
1859 EVT VT =
Op.getValueType();
1862 unsigned ConvertedOp = 0;
1932 return EmitTest(Op0, M68kCC,
DL, DAG);
1935 "Unexpected comparison operation for MVT::i1 operands");
1942 (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1))) &&
1946 Op0 = DAG.
getNode(ExtendOp,
DL, MVT::i32, Op0);
1947 Op1 = DAG.
getNode(ExtendOp,
DL, MVT::i32, Op1);
1970 MVT VT =
Op.getSimpleValueType();
1971 assert(VT == MVT::i8 &&
"SetCC type must be 8-bit integer");
1985 if (
SDValue NewSetCC = LowerToBTST(Op0,
CC,
DL, DAG)) {
2030 SDValue CCR = EmitCmp(Op0, Op1, M68kCC,
DL, DAG);
2043 assert(
LHS.getSimpleValueType().isInteger() &&
"SETCCCARRY is integer only.");
2061 unsigned Opc = Op.getNode()->getOpcode();
2064 if (Op.getResNo() == 1 &&
2080 SDValue VOp0 = V.getOperand(0);
2082 unsigned Bits = V.getValueSizeInBits();
2088 bool addTest =
true;
2110 cast<ConstantSDNode>(
Cond.getOperand(0))->getZExtValue();
2159 unsigned CondOpcode =
Cond.getOpcode();
2164 unsigned Opc =
Cmp.getOpcode();
2166 bool IllegalFPCMov =
false;
2180 switch (CondOpcode) {
2209 VTs = DAG.
getVTList(
LHS.getValueType(),
LHS.getValueType(), MVT::i32);
2233 CC = NewSetCC.getOperand(0);
2234 Cond = NewSetCC.getOperand(1);
2250 unsigned CondCode = cast<ConstantSDNode>(
CC)->getZExtValue();
2270 if (
T1.getValueType() == T2.getValueType() &&
2290 Opc = Op.getOpcode();
2294 Op.getOperand(0).hasOneUse() &&
2296 Op.getOperand(1).hasOneUse());
2306 Op.getOperand(0).hasOneUse();
2311 bool AddTest =
true;
2317 bool Inverted =
false;
2321 if (cast<CondCodeSDNode>(
Cond.getOperand(2))->get() ==
ISD::SETEQ &&
2323 Cond.getOperand(0).getResNo() == 1 &&
2344 unsigned CondOpcode =
Cond.getOpcode();
2349 unsigned Opc =
Cmp.getOpcode();
2355 switch (cast<ConstantSDNode>(
CC)->getZExtValue()) {
2362 Cond =
Cond.getNode()->getOperand(1);
2368 CondOpcode =
Cond.getOpcode();
2379 switch (CondOpcode) {
2434 CC =
Cond.getOperand(0).getOperand(0);
2437 CC =
Cond.getOperand(1).getOperand(0);
2448 Op.getNode()->hasOneUse()) {
2484 Cond =
Cond.getOperand(0).getOperand(1);
2495 if (
Cond.hasOneUse()) {
2497 CC = NewSetCC.getOperand(0);
2498 Cond = NewSetCC.getOperand(1);
2515 MVT VT =
Op.getNode()->getSimpleValueType(0);
2524 bool ExtraOp =
false;
2525 switch (
Op.getOpcode()) {
2545 return DAG.
getNode(Opc,
SDLoc(Op), VTs,
Op.getOperand(0),
Op.getOperand(1));
2546 return DAG.
getNode(Opc,
SDLoc(Op), VTs,
Op.getOperand(0),
Op.getOperand(1),
2571 CP->getConstVal(), PtrVT,
CP->getAlign(),
CP->getOffset(), OpFlag);
2588 const char *
Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
2626 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2627 int64_t
Offset = cast<BlockAddressSDNode>(Op)->getOffset();
2697 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2698 int64_t
Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
2699 return LowerGlobalAddress(GV,
SDLoc(Op),
Offset, DAG);
2763 if (Constraint.
size() > 0) {
2764 switch (Constraint[0]) {
2778 if (Constraint.
size() == 2)
2779 switch (Constraint[1]) {
2800 std::string &Constraint,
2801 std::vector<SDValue> &Ops,
2805 if (Constraint.size() == 1) {
2807 switch (Constraint[0]) {
2816 auto *
C = dyn_cast<ConstantSDNode>(Op);
2820 int64_t Val =
C->getSExtValue();
2821 switch (Constraint[0]) {
2823 if (Val > 0 && Val <= 8)
2831 if (Val < -0x80 || Val >= 0x80)
2835 if (Val < 0 && Val >= -8)
2839 if (Val < -0x100 || Val >= 0x100)
2843 if (Val >= 24 && Val <= 31)
2851 if (Val >= 8 && Val <= 15)
2866 if (Constraint.size() == 2) {
2867 switch (Constraint[0]) {
2870 switch (Constraint[1]) {
2874 auto *
C = dyn_cast<ConstantSDNode>(Op);
2878 int64_t Val =
C->getSExtValue();
2879 switch (Constraint[1]) {
2887 if (!isInt<16>(
C->getSExtValue()))
2906 if (Result.getNode()) {
2907 Ops.push_back(Result);
2914std::pair<unsigned, const TargetRegisterClass *>
2918 if (Constraint.
size() == 1) {
2919 switch (Constraint[0]) {
2924 return std::make_pair(0U, &M68k::DR8RegClass);
2926 return std::make_pair(0U, &M68k::DR16RegClass);
2928 return std::make_pair(0U, &M68k::DR32RegClass);
2936 return std::make_pair(0U, &M68k::AR16RegClass);
2938 return std::make_pair(0U, &M68k::AR32RegClass);
2954 bool GuaranteeTCO) {
2962 switch (
MI.getOpcode()) {
2993 if (miI == BB->
end())
2995 if (SBB->isLiveIn(M68k::CCR))
3000 SelectItr->addRegisterKilled(M68k::CCR,
TRI);
3076 (NextMIIt->getOperand(3).getImm() ==
CC ||
3077 NextMIIt->getOperand(3).getImm() == OppCC)) {
3078 LastCMOV = &*NextMIIt;
3085 if (LastCMOV == &
MI && NextMIIt !=
MBB->
end() &&
3086 NextMIIt->getOpcode() ==
MI.getOpcode() &&
3087 NextMIIt->getOperand(2).getReg() ==
MI.getOperand(2).getReg() &&
3088 NextMIIt->getOperand(1).getReg() ==
MI.getOperand(0).getReg() &&
3089 NextMIIt->getOperand(1).isKill()) {
3090 CascadedCMOV = &*NextMIIt;
3098 Jcc1MBB =
F->CreateMachineBasicBlock(BB);
3099 F->insert(It, Jcc1MBB);
3105 F->insert(It, Copy0MBB);
3106 F->insert(It, SinkMBB);
3112 MachineInstr *LastCCRSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
3173 Register DestReg = MIIt->getOperand(0).getReg();
3174 Register Op1Reg = MIIt->getOperand(1).getReg();
3175 Register Op2Reg = MIIt->getOperand(2).getReg();
3180 if (MIIt->getOperand(3).getImm() == OppCC)
3183 if (RegRewriteTable.
find(Op1Reg) != RegRewriteTable.
end())
3184 Op1Reg = RegRewriteTable[Op1Reg].first;
3186 if (RegRewriteTable.
find(Op2Reg) != RegRewriteTable.
end())
3187 Op2Reg = RegRewriteTable[Op2Reg].second;
3190 BuildMI(*SinkMBB, SinkInsertionPoint,
DL,
TII->get(M68k::PHI), DestReg)
3197 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
3206 DL,
TII->get(TargetOpcode::COPY),
3208 .
addReg(
MI.getOperand(0).getReg());
3214 (MIIt++)->eraseFromParent();
3222 llvm_unreachable(
"Cannot lower Segmented Stack Alloca with stack-split on");
3228 switch (
MI.getOpcode()) {
3234 return EmitLoweredSelect(
MI, BB);
3236 return EmitLoweredSegAlloca(
MI, BB);
3245 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3251 return DAG.
getStore(Op.getOperand(0),
DL, FR, Op.getOperand(1),
3263 const SDValue AsmOperands[4] = {
3274 DAG.
getVTList(MVT::Other, MVT::Glue), AsmOperands);
3293 unsigned Align = cast<ConstantSDNode>(
Op.getOperand(2))->getZExtValue();
3294 EVT VT =
Node->getValueType(0);
3305 Register Vreg =
MRI.createVirtualRegister(ARClass);
3312 assert(SPReg &&
"Target cannot require DYNAMIC_STACKALLOC expansion and"
3313 " not tell us which reg is the stack pointer!");
3320 if (
Align > StackAlign)
3338 EVT VT =
Lo.getValueType();
3351 SDValue ShamtMinusRegisterSize =
3353 SDValue RegisterSizeMinus1Shamt =
3379 EVT VT =
Lo.getValueType();
3403 SDValue ShamtMinusRegisterSize =
3405 SDValue RegisterSizeMinus1Shamt =
3415 DAG.
getNode(ShiftRightOp,
DL, VT,
Hi, ShamtMinusRegisterSize);
3508 MVT VT =
N->getSimpleValueType(0);
3511 N->getOperand(1),
Flags);
3521 MVT VT =
N->getSimpleValueType(0);
3524 N->getOperand(1),
Flags);
3531 DAGCombinerInfo &DCI)
const {
3533 switch (
N->getOpcode()) {
3553 return "M68kISD::CALL";
3555 return "M68kISD::TAIL_CALL";
3557 return "M68kISD::RET";
3559 return "M68kISD::TC_RETURN";
3561 return "M68kISD::ADD";
3563 return "M68kISD::SUB";
3565 return "M68kISD::ADDX";
3567 return "M68kISD::SUBX";
3569 return "M68kISD::SMUL";
3571 return "M68kISD::UMUL";
3573 return "M68kISD::OR";
3575 return "M68kISD::XOR";
3577 return "M68kISD::AND";
3579 return "M68kISD::CMP";
3581 return "M68kISD::BTST";
3583 return "M68kISD::SELECT";
3585 return "M68kISD::CMOV";
3587 return "M68kISD::BRCOND";
3589 return "M68kISD::SETCC";
3591 return "M68kISD::SETCC_CARRY";
3593 return "M68kISD::GLOBAL_BASE_REG";
3595 return "M68kISD::Wrapper";
3597 return "M68kISD::WrapperPC";
3599 return "M68kISD::SEG_ALLOCA";
3606 bool IsVarArg)
const {
3608 return RetCC_M68k_C;
unsigned const MachineRegisterInfo * MRI
static SDValue getSETCC(AArch64CC::CondCode CC, SDValue NZCV, const SDLoc &DL, SelectionDAG &DAG)
Helper function to create 'CSET', which is equivalent to 'CSINC <Wd>, WZR, WZR, invert(<cond>)'.
static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls)
Return true if the calling convention is one that we can guarantee TCO for.
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Callee
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII)
MatchingStackOffset - Return true if the given stack call argument is already available in the same p...
SmallVector< MachineOperand, 4 > Cond
const HexagonInstrInfo * TII
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst...
This file contains the custom routines for the M68k Calling Convention that aren't done by tablegen.
static SDValue LowerTruncateToBTST(SDValue Op, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
static SDValue combineADDX(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc)
Return true if node is an ISD::AND or ISD::OR of two M68k::SETcc nodes each of which has no other use...
static bool hasNonFlagsUse(SDValue Op)
return true if Op has a use that doesn't just read flags.
static bool isM68kCCUnsigned(unsigned M68kCC)
Return true if the condition is an unsigned comparison operation.
static StructReturnType callIsStructReturn(const SmallVectorImpl< ISD::OutputArg > &Outs)
static bool isXor1OfSetCC(SDValue Op)
Return true if node is an ISD::XOR of a M68kISD::SETCC and 1 and that the SETCC node has a single use...
static SDValue LowerAndToBTST(SDValue And, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
Result of 'and' is compared against zero. Change to a BTST node if possible.
static SDValue combineM68kBrCond(SDNode *N, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
static M68k::CondCode TranslateIntegerM68kCC(ISD::CondCode SetCCOpcode)
static StructReturnType argsAreStructReturn(const SmallVectorImpl< ISD::InputArg > &Ins)
Determines whether a function uses struct return semantics.
static bool isCMOVPseudo(MachineInstr &MI)
static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt)
Return true if the function is being made into a tailcall target by changing its ABI.
static bool isM68kLogicalCmp(SDValue Op)
Return true if opcode is a M68k logical comparison.
static SDValue combineM68kSetCC(SDNode *N, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
static SDValue combineSetCCCCR(SDValue CCR, M68k::CondCode &CC, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
Optimize a CCR definition used according to the condition code CC into a simpler CCR value,...
static SDValue combineCarryThroughADD(SDValue CCR)
static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
Create a BTST (Bit Test) node - Test bit BitNo in Src and set condition according to equal/not-equal ...
static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG)
static bool checkAndUpdateCCRKill(MachineBasicBlock::iterator SelectItr, MachineBasicBlock *BB, const TargetRegisterInfo *TRI)
static SDValue combineSUBX(SDNode *N, SelectionDAG &DAG)
static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL, bool IsFP, SDValue &LHS, SDValue &RHS, SelectionDAG &DAG)
Do a one-to-one translation of a ISD::CondCode to the M68k-specific condition code,...
This file defines the interfaces that M68k uses to lower LLVM code into a selection DAG.
This file declares the M68k specific subclass of MachineFunctionInfo.
This file declares the M68k specific subclass of TargetSubtargetInfo.
This file declares the M68k specific subclass of TargetMachine.
This file contains declarations for M68k ELF object file lowering.
unsigned const TargetRegisterInfo * TRI
typename CallsiteContextGraph< DerivedCCG, FuncTy, CallTy >::FuncInfo FuncInfo
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Class for arbitrary precision integers.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
This class represents an incoming formal argument to a Function.
an instruction that atomically reads a memory location, combines it with another value,...
LLVM Basic Block Representation.
The address of a basic block.
CCState - This class holds information needed while lowering arguments and return values.
static bool resultsCompatible(CallingConv::ID CalleeCC, CallingConv::ID CallerCC, MachineFunction &MF, LLVMContext &C, const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn CalleeFn, CCAssignFn CallerFn)
Returns true if the results of the two calling conventions are compatible.
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
int64_t getLocMemOffset() const
unsigned getValNo() const
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
This is an important base class in LLVM.
A parsed version of the target data layout string in and methods for querying it.
iterator find(const_arg_type_t< KeyT > Val)
iterator_range< arg_iterator > args()
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
bool hasDLLImportStorageClass() const
Module * getParent()
Get the module that this global value is contained inside of...
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
This is an important class for using LLVM in a threaded context.
void setVarArgsFrameIndex(int Index)
void setSRetReturnReg(unsigned Reg)
SmallVectorImpl< ForwardedRegister > & getForwardedMustTailRegParms()
void setBytesToPopOnReturn(unsigned bytes)
unsigned getBytesToPopOnReturn() const
unsigned getSRetReturnReg() const
void setArgumentStackSize(unsigned size)
void setTCReturnAddrDelta(int delta)
unsigned char classifyExternalReference(const Module &M) const
Classify a external variable reference for the current subtarget according to how we should reference...
unsigned char classifyBlockAddressReference() const
Classify a blockaddress reference for the current subtarget according to how we should reference it i...
unsigned getSlotSize() const
getSlotSize - Stack slot size in bytes.
const M68kInstrInfo * getInstrInfo() const override
unsigned char classifyGlobalReference(const GlobalValue *GV, const Module &M) const
Classify a global variable reference for the current subtarget according to how we should reference i...
unsigned getJumpTableEncoding() const
unsigned char classifyLocalReference(const GlobalValue *GV) const
Classify a global variable reference for the current subtarget according to how we should reference i...
const M68kRegisterInfo * getRegisterInfo() const override
bool atLeastM68020() const
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const Module &M) const
Classify a global function reference for the current subtarget.
const M68kFrameLowering * getFrameLowering() const override
ConstraintType getConstraintType(StringRef ConstraintStr) const override
Given a constraint, return the type of constraint it is for this target.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
CCAssignFn * getCCAssignFn(CallingConv::ID CC, bool Return, bool IsVarArg) const
M68kTargetLowering(const M68kTargetMachine &TM, const M68kSubtarget &STI)
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
static MVT getIntegerVT(unsigned BitWidth)
MVT getScalarType() const
If this is a vector, return the element type, otherwise return this.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< succ_iterator > successors()
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineInstrBundleIterator< MachineInstr > iterator
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
void setObjectZExt(int ObjectIdx, bool IsZExt)
void setObjectSExt(int ObjectIdx, bool IsSExt)
void setHasTailCall(bool V=true)
bool isObjectZExt(int ObjectIdx) const
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isObjectSExt(int ObjectIdx) const
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MCSymbol * getJTISymbol(unsigned JTI, MCContext &Ctx, bool isLinkerPrivate=false) const
getJTISymbol - Return the MCSymbol for the specified non-empty jump table.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool shouldSplitStack() const
Should we be emitting segmented stack stuff for the function.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Representation of each machine instruction.
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
@ EK_Custom32
EK_Custom32 - Each entry is a 32-bit value that is custom lowered by the TargetLowering::LowerCustomJ...
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
A Module instance is used to store all the information related to an LLVM module.
Wrapper class representing virtual and physical registers.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
This class provides iterator support for SDUse operands that use a specific SDNode.
Represents one node in the SelectionDAG.
bool hasOneUse() const
Return true if there is exactly one use of this node.
const SDValue & getOperand(unsigned Num) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
uint64_t getConstantOperandVal(unsigned i) const
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getStackArgumentTokenFactor(SDValue Chain)
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
const TargetLowering & getTargetLoweringInfo() const
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getMDNode(const MDNode *MD)
Return an MDNodeSDNode which holds an MDNode.
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
const TargetMachine & getTarget() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
LLVMContext * getContext() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
constexpr size_t size() const
size - Get the string size.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Information about stack frame layout on the target.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
const TargetMachine & getTargetMachine() const
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
MVT getProgramPointerTy(const DataLayout &DL) const
Return the type for code pointers, which is determined by the program address space specified through...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
bool isPositionIndependent() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Value * getOperand(unsigned i) const
LLVM Value Representation.
bool hasOneUse() const
Return true if there is exactly one use of this value.
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ M68k_INTR
Used for M68k interrupt routines.
@ Swift
Calling convention for Swift.
@ C
The default llvm calling convention, compatible with C.
CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.