LLVM 18.0.0git
M68kISelLowering.cpp
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1//===-- M68kISelLowering.cpp - M68k DAG Lowering Impl -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file defines the interfaces that M68k uses to lower LLVM code into a
11/// selection DAG.
12///
13//===----------------------------------------------------------------------===//
14
15#include "M68kISelLowering.h"
16#include "M68kCallingConv.h"
17#include "M68kMachineFunction.h"
18#include "M68kSubtarget.h"
19#include "M68kTargetMachine.h"
21
22#include "llvm/ADT/Statistic.h"
31#include "llvm/IR/CallingConv.h"
35#include "llvm/Support/Debug.h"
39
40using namespace llvm;
41
42#define DEBUG_TYPE "M68k-isel"
43
44STATISTIC(NumTailCalls, "Number of tail calls");
45
47 const M68kSubtarget &STI)
48 : TargetLowering(TM), Subtarget(STI), TM(TM) {
49
50 MVT PtrVT = MVT::i32;
51
53
54 auto *RegInfo = Subtarget.getRegisterInfo();
55 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
56
57 // Set up the register classes.
58 addRegisterClass(MVT::i8, &M68k::DR8RegClass);
59 addRegisterClass(MVT::i16, &M68k::XR16RegClass);
60 addRegisterClass(MVT::i32, &M68k::XR32RegClass);
61
62 for (auto VT : MVT::integer_valuetypes()) {
66 }
67
68 // We don't accept any truncstore of integer registers.
69 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
70 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
71 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
72 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
73 setTruncStoreAction(MVT::i32, MVT::i8, Expand);
74 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
75
78 if (Subtarget.atLeastM68020())
80 else
83
84 for (auto OP :
87 setOperationAction(OP, MVT::i8, Promote);
88 setOperationAction(OP, MVT::i16, Legal);
89 setOperationAction(OP, MVT::i32, LibCall);
90 }
91
92 for (auto OP : {ISD::UMUL_LOHI, ISD::SMUL_LOHI}) {
93 setOperationAction(OP, MVT::i8, Expand);
94 setOperationAction(OP, MVT::i16, Expand);
95 }
96
97 // FIXME It would be better to use a custom lowering
98 for (auto OP : {ISD::SMULO, ISD::UMULO}) {
99 setOperationAction(OP, MVT::i8, Expand);
100 setOperationAction(OP, MVT::i16, Expand);
101 setOperationAction(OP, MVT::i32, Expand);
102 }
103
105 setOperationAction(OP, MVT::i32, Custom);
106
107 // Add/Sub overflow ops with MVT::Glues are lowered to CCR dependences.
108 for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
113 }
114
115 // SADDO and friends are legal with this setup, i hope
116 for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
121 }
122
125
126 for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
132 }
133
134 for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
139 }
140
147
152
155
157
159
160 // We lower the `atomic-compare-and-swap` to `__sync_val_compare_and_swap`
161 // for subtarget < M68020
163 setOperationAction(ISD::ATOMIC_CMP_SWAP, {MVT::i8, MVT::i16, MVT::i32},
164 Subtarget.atLeastM68020() ? Legal : LibCall);
165
167
168 // M68k does not have native read-modify-write support, so expand all of them
169 // to `__sync_fetch_*` for target < M68020, otherwise expand to CmpxChg.
170 // See `shouldExpandAtomicRMWInIR` below.
172 {
184 },
185 {MVT::i8, MVT::i16, MVT::i32}, LibCall);
186
188}
189
192 return Subtarget.atLeastM68020()
195}
196
199 return M68k::D0;
200}
201
204 return M68k::D1;
205}
206
209 return StringSwitch<InlineAsm::ConstraintCode>(ConstraintCode)
211 // We borrow ConstraintCode::Um for 'U'.
214}
215
217 LLVMContext &Context, EVT VT) const {
218 // M68k SETcc producess either 0x00 or 0xFF
219 return MVT::i8;
220}
221
223 EVT Ty) const {
224 if (Ty.isSimple()) {
225 return Ty.getSimpleVT();
226 }
227 return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
228}
229
230#include "M68kGenCallingConv.inc"
231
233
234static StructReturnType
236 if (Outs.empty())
237 return NotStructReturn;
238
239 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
240 if (!Flags.isSRet())
241 return NotStructReturn;
242 if (Flags.isInReg())
243 return RegStructReturn;
244 return StackStructReturn;
245}
246
247/// Determines whether a function uses struct return semantics.
248static StructReturnType
250 if (Ins.empty())
251 return NotStructReturn;
252
253 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
254 if (!Flags.isSRet())
255 return NotStructReturn;
256 if (Flags.isInReg())
257 return RegStructReturn;
258 return StackStructReturn;
259}
260
261/// Make a copy of an aggregate at address specified by "Src" to address
262/// "Dst" with size and alignment information specified by the specific
263/// parameter attribute. The copy will be passed as a byval function parameter.
265 SDValue Chain, ISD::ArgFlagsTy Flags,
266 SelectionDAG &DAG, const SDLoc &DL) {
267 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), DL, MVT::i32);
268
269 return DAG.getMemcpy(
270 Chain, DL, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
271 /*isVolatile=*/false, /*AlwaysInline=*/true,
272 /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo());
273}
274
275/// Return true if the calling convention is one that we can guarantee TCO for.
276static bool canGuaranteeTCO(CallingConv::ID CC) { return false; }
277
278/// Return true if we might ever do TCO for calls with this calling convention.
280 switch (CC) {
281 // C calling conventions:
282 case CallingConv::C:
283 return true;
284 default:
285 return canGuaranteeTCO(CC);
286 }
287}
288
289/// Return true if the function is being made into a tailcall target by
290/// changing its ABI.
291static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
292 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
293}
294
295/// Return true if the given stack call argument is already available in the
296/// same position (relatively) of the caller's incoming argument stack.
297static bool MatchingStackOffset(SDValue Arg, unsigned Offset,
300 const M68kInstrInfo *TII,
301 const CCValAssign &VA) {
302 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
303
304 for (;;) {
305 // Look through nodes that don't alter the bits of the incoming value.
306 unsigned Op = Arg.getOpcode();
308 Arg = Arg.getOperand(0);
309 continue;
310 }
311 if (Op == ISD::TRUNCATE) {
312 const SDValue &TruncInput = Arg.getOperand(0);
313 if (TruncInput.getOpcode() == ISD::AssertZext &&
314 cast<VTSDNode>(TruncInput.getOperand(1))->getVT() ==
315 Arg.getValueType()) {
316 Arg = TruncInput.getOperand(0);
317 continue;
318 }
319 }
320 break;
321 }
322
323 int FI = INT_MAX;
324 if (Arg.getOpcode() == ISD::CopyFromReg) {
325 Register VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
327 return false;
328 MachineInstr *Def = MRI->getVRegDef(VR);
329 if (!Def)
330 return false;
331 if (!Flags.isByVal()) {
332 if (!TII->isLoadFromStackSlot(*Def, FI))
333 return false;
334 } else {
335 unsigned Opcode = Def->getOpcode();
336 if ((Opcode == M68k::LEA32p || Opcode == M68k::LEA32f) &&
337 Def->getOperand(1).isFI()) {
338 FI = Def->getOperand(1).getIndex();
339 Bytes = Flags.getByValSize();
340 } else
341 return false;
342 }
343 } else if (auto *Ld = dyn_cast<LoadSDNode>(Arg)) {
344 if (Flags.isByVal())
345 // ByVal argument is passed in as a pointer but it's now being
346 // dereferenced. e.g.
347 // define @foo(%struct.X* %A) {
348 // tail call @bar(%struct.X* byval %A)
349 // }
350 return false;
351 SDValue Ptr = Ld->getBasePtr();
352 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
353 if (!FINode)
354 return false;
355 FI = FINode->getIndex();
356 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
357 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
358 FI = FINode->getIndex();
359 Bytes = Flags.getByValSize();
360 } else
361 return false;
362
363 assert(FI != INT_MAX);
364 if (!MFI.isFixedObjectIndex(FI))
365 return false;
366
367 if (Offset != MFI.getObjectOffset(FI))
368 return false;
369
370 if (VA.getLocVT().getSizeInBits() > Arg.getValueType().getSizeInBits()) {
371 // If the argument location is wider than the argument type, check that any
372 // extension flags match.
373 if (Flags.isZExt() != MFI.isObjectZExt(FI) ||
374 Flags.isSExt() != MFI.isObjectSExt(FI)) {
375 return false;
376 }
377 }
378
379 return Bytes == MFI.getObjectSize(FI);
380}
381
383M68kTargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
386 int ReturnAddrIndex = FuncInfo->getRAIndex();
387
388 if (ReturnAddrIndex == 0) {
389 // Set up a frame object for the return address.
390 unsigned SlotSize = Subtarget.getSlotSize();
391 ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(
392 SlotSize, -(int64_t)SlotSize, false);
393 FuncInfo->setRAIndex(ReturnAddrIndex);
394 }
395
396 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
397}
398
399SDValue M68kTargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
400 SDValue &OutRetAddr,
401 SDValue Chain,
402 bool IsTailCall, int FPDiff,
403 const SDLoc &DL) const {
404 EVT VT = getPointerTy(DAG.getDataLayout());
405 OutRetAddr = getReturnAddressFrameIndex(DAG);
406
407 // Load the "old" Return address.
408 OutRetAddr = DAG.getLoad(VT, DL, Chain, OutRetAddr, MachinePointerInfo());
409 return SDValue(OutRetAddr.getNode(), 1);
410}
411
412SDValue M68kTargetLowering::EmitTailCallStoreRetAddr(
413 SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue RetFI,
414 EVT PtrVT, unsigned SlotSize, int FPDiff, const SDLoc &DL) const {
415 if (!FPDiff)
416 return Chain;
417
418 // Calculate the new stack slot for the return address.
419 int NewFO = MF.getFrameInfo().CreateFixedObject(
420 SlotSize, (int64_t)FPDiff - SlotSize, false);
421
422 SDValue NewFI = DAG.getFrameIndex(NewFO, PtrVT);
423 // Store the return address to the appropriate stack slot.
424 Chain = DAG.getStore(
425 Chain, DL, RetFI, NewFI,
427 return Chain;
428}
429
431M68kTargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
433 const SDLoc &DL, SelectionDAG &DAG,
434 const CCValAssign &VA,
435 MachineFrameInfo &MFI,
436 unsigned ArgIdx) const {
437 // Create the nodes corresponding to a load from this parameter slot.
438 ISD::ArgFlagsTy Flags = Ins[ArgIdx].Flags;
439 EVT ValVT;
440
441 // If value is passed by pointer we have address passed instead of the value
442 // itself.
444 ValVT = VA.getLocVT();
445 else
446 ValVT = VA.getValVT();
447
448 // Because we are dealing with BE architecture we need to offset loading of
449 // partial types
450 int Offset = VA.getLocMemOffset();
451 if (VA.getValVT() == MVT::i8) {
452 Offset += 3;
453 } else if (VA.getValVT() == MVT::i16) {
454 Offset += 2;
455 }
456
457 // TODO Interrupt handlers
458 // Calculate SP offset of interrupt parameter, re-arrange the slot normally
459 // taken by a return address.
460
461 // FIXME For now, all byval parameter objects are marked mutable. This can
462 // be changed with more analysis. In case of tail call optimization mark all
463 // arguments mutable. Since they could be overwritten by lowering of arguments
464 // in case of a tail call.
465 bool AlwaysUseMutable = shouldGuaranteeTCO(
466 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
467 bool IsImmutable = !AlwaysUseMutable && !Flags.isByVal();
468
469 if (Flags.isByVal()) {
470 unsigned Bytes = Flags.getByValSize();
471 if (Bytes == 0)
472 Bytes = 1; // Don't create zero-sized stack objects.
473 int FI = MFI.CreateFixedObject(Bytes, Offset, IsImmutable);
474 // TODO Interrupt handlers
475 // Adjust SP offset of interrupt parameter.
476 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
477 } else {
478 int FI =
479 MFI.CreateFixedObject(ValVT.getSizeInBits() / 8, Offset, IsImmutable);
480
481 // Set SExt or ZExt flag.
482 if (VA.getLocInfo() == CCValAssign::ZExt) {
483 MFI.setObjectZExt(FI, true);
484 } else if (VA.getLocInfo() == CCValAssign::SExt) {
485 MFI.setObjectSExt(FI, true);
486 }
487
488 // TODO Interrupt handlers
489 // Adjust SP offset of interrupt parameter.
490
491 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
492 SDValue Val = DAG.getLoad(
493 ValVT, DL, Chain, FIN,
495 return VA.isExtInLoc() ? DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val)
496 : Val;
497 }
498}
499
500SDValue M68kTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
501 SDValue Arg, const SDLoc &DL,
502 SelectionDAG &DAG,
503 const CCValAssign &VA,
504 ISD::ArgFlagsTy Flags) const {
505 unsigned LocMemOffset = VA.getLocMemOffset();
506 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, DL);
507 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
508 StackPtr, PtrOff);
509 if (Flags.isByVal())
510 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, DL);
511
512 return DAG.getStore(
513 Chain, DL, Arg, PtrOff,
515}
516
517//===----------------------------------------------------------------------===//
518// Call
519//===----------------------------------------------------------------------===//
520
521SDValue M68kTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
522 SmallVectorImpl<SDValue> &InVals) const {
523 SelectionDAG &DAG = CLI.DAG;
524 SDLoc &DL = CLI.DL;
526 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
528 SDValue Chain = CLI.Chain;
529 SDValue Callee = CLI.Callee;
530 CallingConv::ID CallConv = CLI.CallConv;
531 bool &IsTailCall = CLI.IsTailCall;
532 bool IsVarArg = CLI.IsVarArg;
533
536 bool IsSibcall = false;
538 // const M68kRegisterInfo *TRI = Subtarget.getRegisterInfo();
539
540 if (CallConv == CallingConv::M68k_INTR)
541 report_fatal_error("M68k interrupts may not be called directly");
542
543 auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
544 if (Attr.getValueAsBool())
545 IsTailCall = false;
546
547 // FIXME Add tailcalls support
548
549 bool IsMustTail = CLI.CB && CLI.CB->isMustTailCall();
550 if (IsMustTail) {
551 // Force this to be a tail call. The verifier rules are enough to ensure
552 // that we can lower this successfully without moving the return address
553 // around.
554 IsTailCall = true;
555 } else if (IsTailCall) {
556 // Check if it's really possible to do a tail call.
557 IsTailCall = IsEligibleForTailCallOptimization(
558 Callee, CallConv, IsVarArg, SR != NotStructReturn,
559 MF.getFunction().hasStructRetAttr(), CLI.RetTy, Outs, OutVals, Ins,
560 DAG);
561
562 // Sibcalls are automatically detected tailcalls which do not require
563 // ABI changes.
564 if (!MF.getTarget().Options.GuaranteedTailCallOpt && IsTailCall)
565 IsSibcall = true;
566
567 if (IsTailCall)
568 ++NumTailCalls;
569 }
570
571 assert(!(IsVarArg && canGuaranteeTCO(CallConv)) &&
572 "Var args not supported with calling convention fastcc");
573
574 // Analyze operands of the call, assigning locations to each operand.
576 SmallVector<Type *, 4> ArgTypes;
577 for (const auto &Arg : CLI.getArgs())
578 ArgTypes.emplace_back(Arg.Ty);
579 M68kCCState CCInfo(ArgTypes, CallConv, IsVarArg, MF, ArgLocs,
580 *DAG.getContext());
581 CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
582
583 // Get a count of how many bytes are to be pushed on the stack.
584 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
585 if (IsSibcall) {
586 // This is a sibcall. The memory operands are available in caller's
587 // own caller's stack.
588 NumBytes = 0;
589 } else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
590 canGuaranteeTCO(CallConv)) {
591 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
592 }
593
594 int FPDiff = 0;
595 if (IsTailCall && !IsSibcall && !IsMustTail) {
596 // Lower arguments at fp - stackoffset + fpdiff.
597 unsigned NumBytesCallerPushed = MFI->getBytesToPopOnReturn();
598
599 FPDiff = NumBytesCallerPushed - NumBytes;
600
601 // Set the delta of movement of the returnaddr stackslot.
602 // But only set if delta is greater than previous delta.
603 if (FPDiff < MFI->getTCReturnAddrDelta())
604 MFI->setTCReturnAddrDelta(FPDiff);
605 }
606
607 unsigned NumBytesToPush = NumBytes;
608 unsigned NumBytesToPop = NumBytes;
609
610 // If we have an inalloca argument, all stack space has already been allocated
611 // for us and be right at the top of the stack. We don't support multiple
612 // arguments passed in memory when using inalloca.
613 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
614 NumBytesToPush = 0;
615 if (!ArgLocs.back().isMemLoc())
616 report_fatal_error("cannot use inalloca attribute on a register "
617 "parameter");
618 if (ArgLocs.back().getLocMemOffset() != 0)
619 report_fatal_error("any parameter with the inalloca attribute must be "
620 "the only memory argument");
621 }
622
623 if (!IsSibcall)
624 Chain = DAG.getCALLSEQ_START(Chain, NumBytesToPush,
625 NumBytes - NumBytesToPush, DL);
626
627 SDValue RetFI;
628 // Load return address for tail calls.
629 if (IsTailCall && FPDiff)
630 Chain = EmitTailCallLoadRetAddr(DAG, RetFI, Chain, IsTailCall, FPDiff, DL);
631
633 SmallVector<SDValue, 8> MemOpChains;
635
636 // Walk the register/memloc assignments, inserting copies/loads. In the case
637 // of tail call optimization arguments are handle later.
638 const M68kRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
639 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
640 ISD::ArgFlagsTy Flags = Outs[i].Flags;
641
642 // Skip inalloca arguments, they have already been written.
643 if (Flags.isInAlloca())
644 continue;
645
646 CCValAssign &VA = ArgLocs[i];
647 EVT RegVT = VA.getLocVT();
648 SDValue Arg = OutVals[i];
649 bool IsByVal = Flags.isByVal();
650
651 // Promote the value if needed.
652 switch (VA.getLocInfo()) {
653 default:
654 llvm_unreachable("Unknown loc info!");
656 break;
658 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
659 break;
661 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
662 break;
664 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
665 break;
667 Arg = DAG.getBitcast(RegVT, Arg);
668 break;
670 // Store the argument.
671 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
672 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
673 Chain = DAG.getStore(
674 Chain, DL, Arg, SpillSlot,
676 Arg = SpillSlot;
677 break;
678 }
679 }
680
681 if (VA.isRegLoc()) {
682 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
683 } else if (!IsSibcall && (!IsTailCall || IsByVal)) {
684 assert(VA.isMemLoc());
685 if (!StackPtr.getNode()) {
686 StackPtr = DAG.getCopyFromReg(Chain, DL, RegInfo->getStackRegister(),
688 }
689 MemOpChains.push_back(
690 LowerMemOpCallTo(Chain, StackPtr, Arg, DL, DAG, VA, Flags));
691 }
692 }
693
694 if (!MemOpChains.empty())
695 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
696
697 // FIXME Make sure PIC style GOT works as expected
698 // The only time GOT is really needed is for Medium-PIC static data
699 // otherwise we are happy with pc-rel or static references
700
701 if (IsVarArg && IsMustTail) {
702 const auto &Forwards = MFI->getForwardedMustTailRegParms();
703 for (const auto &F : Forwards) {
704 SDValue Val = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT);
705 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
706 }
707 }
708
709 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
710 // don't need this because the eligibility check rejects calls that require
711 // shuffling arguments passed in memory.
712 if (!IsSibcall && IsTailCall) {
713 // Force all the incoming stack arguments to be loaded from the stack
714 // before any new outgoing arguments are stored to the stack, because the
715 // outgoing stack slots may alias the incoming argument stack slots, and
716 // the alias isn't otherwise explicit. This is slightly more conservative
717 // than necessary, because it means that each store effectively depends
718 // on every argument instead of just those arguments it would clobber.
719 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
720
721 SmallVector<SDValue, 8> MemOpChains2;
722 SDValue FIN;
723 int FI = 0;
724 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
725 CCValAssign &VA = ArgLocs[i];
726 if (VA.isRegLoc())
727 continue;
728 assert(VA.isMemLoc());
729 SDValue Arg = OutVals[i];
730 ISD::ArgFlagsTy Flags = Outs[i].Flags;
731 // Skip inalloca arguments. They don't require any work.
732 if (Flags.isInAlloca())
733 continue;
734 // Create frame index.
735 int32_t Offset = VA.getLocMemOffset() + FPDiff;
736 uint32_t OpSize = (VA.getLocVT().getSizeInBits() + 7) / 8;
737 FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
738 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
739
740 if (Flags.isByVal()) {
741 // Copy relative to framepointer.
743 if (!StackPtr.getNode()) {
744 StackPtr = DAG.getCopyFromReg(Chain, DL, RegInfo->getStackRegister(),
746 }
749
750 MemOpChains2.push_back(
751 CreateCopyOfByValArgument(Source, FIN, ArgChain, Flags, DAG, DL));
752 } else {
753 // Store relative to framepointer.
754 MemOpChains2.push_back(DAG.getStore(
755 ArgChain, DL, Arg, FIN,
757 }
758 }
759
760 if (!MemOpChains2.empty())
761 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains2);
762
763 // Store the return address to the appropriate stack slot.
764 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetFI,
766 Subtarget.getSlotSize(), FPDiff, DL);
767 }
768
769 // Build a sequence of copy-to-reg nodes chained together with token chain
770 // and flag operands which copy the outgoing args into registers.
771 SDValue InGlue;
772 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
773 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
774 RegsToPass[i].second, InGlue);
775 InGlue = Chain.getValue(1);
776 }
777
778 if (Callee->getOpcode() == ISD::GlobalAddress) {
779 // If the callee is a GlobalAddress node (quite common, every direct call
780 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
781 // it.
782 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
783
784 // We should use extra load for direct calls to dllimported functions in
785 // non-JIT mode.
786 const GlobalValue *GV = G->getGlobal();
787 if (!GV->hasDLLImportStorageClass()) {
788 unsigned char OpFlags = Subtarget.classifyGlobalFunctionReference(GV);
789
791 GV, DL, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
792
793 if (OpFlags == M68kII::MO_GOTPCREL) {
794
795 // Add a wrapper.
797 getPointerTy(DAG.getDataLayout()), Callee);
798
799 // Add extra indirection
800 Callee = DAG.getLoad(
801 getPointerTy(DAG.getDataLayout()), DL, DAG.getEntryNode(), Callee,
803 }
804 }
805 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
807 unsigned char OpFlags =
808 Subtarget.classifyGlobalFunctionReference(nullptr, *Mod);
809
811 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
812 }
813
814 // Returns a chain & a flag for retval copy to use.
815 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
817
818 if (!IsSibcall && IsTailCall) {
819 Chain = DAG.getCALLSEQ_END(Chain, NumBytesToPop, 0, InGlue, DL);
820 InGlue = Chain.getValue(1);
821 }
822
823 Ops.push_back(Chain);
824 Ops.push_back(Callee);
825
826 if (IsTailCall)
827 Ops.push_back(DAG.getConstant(FPDiff, DL, MVT::i32));
828
829 // Add argument registers to the end of the list so that they are known live
830 // into the call.
831 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
832 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
833 RegsToPass[i].second.getValueType()));
834
835 // Add a register mask operand representing the call-preserved registers.
836 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
837 assert(Mask && "Missing call preserved mask for calling convention");
838
839 Ops.push_back(DAG.getRegisterMask(Mask));
840
841 if (InGlue.getNode())
842 Ops.push_back(InGlue);
843
844 if (IsTailCall) {
846 return DAG.getNode(M68kISD::TC_RETURN, DL, NodeTys, Ops);
847 }
848
849 Chain = DAG.getNode(M68kISD::CALL, DL, NodeTys, Ops);
850 InGlue = Chain.getValue(1);
851
852 // Create the CALLSEQ_END node.
853 unsigned NumBytesForCalleeToPop;
854 if (M68k::isCalleePop(CallConv, IsVarArg,
856 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
857 } else if (!canGuaranteeTCO(CallConv) && SR == StackStructReturn) {
858 // If this is a call to a struct-return function, the callee
859 // pops the hidden struct pointer, so we have to push it back.
860 NumBytesForCalleeToPop = 4;
861 } else {
862 NumBytesForCalleeToPop = 0; // Callee pops nothing.
863 }
864
865 if (CLI.DoesNotReturn && !getTargetMachine().Options.TrapUnreachable) {
866 // No need to reset the stack after the call if the call doesn't return. To
867 // make the MI verify, we'll pretend the callee does it for us.
868 NumBytesForCalleeToPop = NumBytes;
869 }
870
871 // Returns a flag for retval copy to use.
872 if (!IsSibcall) {
873 Chain = DAG.getCALLSEQ_END(Chain, NumBytesToPop, NumBytesForCalleeToPop,
874 InGlue, DL);
875 InGlue = Chain.getValue(1);
876 }
877
878 // Handle result values, copying them out of physregs into vregs that we
879 // return.
880 return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins, DL, DAG,
881 InVals);
882}
883
884SDValue M68kTargetLowering::LowerCallResult(
885 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool IsVarArg,
886 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
887 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
888
889 // Assign locations to each value returned by this call.
891 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
892 *DAG.getContext());
893 CCInfo.AnalyzeCallResult(Ins, RetCC_M68k);
894
895 // Copy all of the result registers out of their specified physreg.
896 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
897 CCValAssign &VA = RVLocs[i];
898 EVT CopyVT = VA.getLocVT();
899
900 /// ??? is this correct?
901 Chain = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), CopyVT, InGlue)
902 .getValue(1);
903 SDValue Val = Chain.getValue(0);
904
905 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
906 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
907
908 InGlue = Chain.getValue(2);
909 InVals.push_back(Val);
910 }
911
912 return Chain;
913}
914
915//===----------------------------------------------------------------------===//
916// Formal Arguments Calling Convention Implementation
917//===----------------------------------------------------------------------===//
918
919SDValue M68kTargetLowering::LowerFormalArguments(
920 SDValue Chain, CallingConv::ID CCID, bool IsVarArg,
921 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
922 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
925 // const TargetFrameLowering &TFL = *Subtarget.getFrameLowering();
926
927 MachineFrameInfo &MFI = MF.getFrameInfo();
928
929 // Assign locations to all of the incoming arguments.
931 SmallVector<Type *, 4> ArgTypes;
932 for (const Argument &Arg : MF.getFunction().args())
933 ArgTypes.emplace_back(Arg.getType());
934 M68kCCState CCInfo(ArgTypes, CCID, IsVarArg, MF, ArgLocs, *DAG.getContext());
935
936 CCInfo.AnalyzeFormalArguments(Ins, CC_M68k);
937
938 unsigned LastVal = ~0U;
939 SDValue ArgValue;
940 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
941 CCValAssign &VA = ArgLocs[i];
942 assert(VA.getValNo() != LastVal && "Same value in different locations");
943
944 LastVal = VA.getValNo();
945
946 if (VA.isRegLoc()) {
947 EVT RegVT = VA.getLocVT();
948 const TargetRegisterClass *RC;
949 if (RegVT == MVT::i32)
950 RC = &M68k::XR32RegClass;
951 else
952 llvm_unreachable("Unknown argument type!");
953
954 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
955 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
956
957 // If this is an 8 or 16-bit value, it is really passed promoted to 32
958 // bits. Insert an assert[sz]ext to capture this, then truncate to the
959 // right size.
960 if (VA.getLocInfo() == CCValAssign::SExt) {
961 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
962 DAG.getValueType(VA.getValVT()));
963 } else if (VA.getLocInfo() == CCValAssign::ZExt) {
964 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
965 DAG.getValueType(VA.getValVT()));
966 } else if (VA.getLocInfo() == CCValAssign::BCvt) {
967 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
968 }
969
970 if (VA.isExtInLoc()) {
971 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
972 }
973 } else {
974 assert(VA.isMemLoc());
975 ArgValue = LowerMemArgument(Chain, CCID, Ins, DL, DAG, VA, MFI, i);
976 }
977
978 // If value is passed via pointer - do a load.
979 // TODO Make sure this handling on indirect arguments is correct
981 ArgValue =
982 DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue, MachinePointerInfo());
983
984 InVals.push_back(ArgValue);
985 }
986
987 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
988 // Swift calling convention does not require we copy the sret argument
989 // into %D0 for the return. We don't set SRetReturnReg for Swift.
990 if (CCID == CallingConv::Swift)
991 continue;
992
993 // ABI require that for returning structs by value we copy the sret argument
994 // into %D0 for the return. Save the argument into a virtual register so
995 // that we can access it from the return points.
996 if (Ins[i].Flags.isSRet()) {
997 unsigned Reg = MMFI->getSRetReturnReg();
998 if (!Reg) {
999 MVT PtrTy = getPointerTy(DAG.getDataLayout());
1001 MMFI->setSRetReturnReg(Reg);
1002 }
1003 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
1004 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
1005 break;
1006 }
1007 }
1008
1009 unsigned StackSize = CCInfo.getStackSize();
1010 // Align stack specially for tail calls.
1012 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1013
1014 // If the function takes variable number of arguments, make a frame index for
1015 // the start of the first vararg value... for expansion of llvm.va_start. We
1016 // can skip this if there are no va_start calls.
1017 if (MFI.hasVAStart()) {
1018 MMFI->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
1019 }
1020
1021 if (IsVarArg && MFI.hasMustTailInVarArgFunc()) {
1022 // We forward some GPRs and some vector types.
1023 SmallVector<MVT, 2> RegParmTypes;
1024 MVT IntVT = MVT::i32;
1025 RegParmTypes.push_back(IntVT);
1026
1027 // Compute the set of forwarded registers. The rest are scratch.
1028 // ??? what is this for?
1031 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_M68k);
1032
1033 // Copy all forwards from physical to virtual registers.
1034 for (ForwardedRegister &F : Forwards) {
1035 // FIXME Can we use a less constrained schedule?
1036 SDValue RegVal = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT);
1038 Chain = DAG.getCopyToReg(Chain, DL, F.VReg, RegVal);
1039 }
1040 }
1041
1042 // Some CCs need callee pop.
1043 if (M68k::isCalleePop(CCID, IsVarArg,
1045 MMFI->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1046 } else {
1047 MMFI->setBytesToPopOnReturn(0); // Callee pops nothing.
1048 // If this is an sret function, the return should pop the hidden pointer.
1050 MMFI->setBytesToPopOnReturn(4);
1051 }
1052
1053 MMFI->setArgumentStackSize(StackSize);
1054
1055 return Chain;
1056}
1057
1058//===----------------------------------------------------------------------===//
1059// Return Value Calling Convention Implementation
1060//===----------------------------------------------------------------------===//
1061
1062bool M68kTargetLowering::CanLowerReturn(
1063 CallingConv::ID CCID, MachineFunction &MF, bool IsVarArg,
1064 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1066 CCState CCInfo(CCID, IsVarArg, MF, RVLocs, Context);
1067 return CCInfo.CheckReturn(Outs, RetCC_M68k);
1068}
1069
1070SDValue
1071M68kTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CCID,
1072 bool IsVarArg,
1074 const SmallVectorImpl<SDValue> &OutVals,
1075 const SDLoc &DL, SelectionDAG &DAG) const {
1078
1080 CCState CCInfo(CCID, IsVarArg, MF, RVLocs, *DAG.getContext());
1081 CCInfo.AnalyzeReturn(Outs, RetCC_M68k);
1082
1083 SDValue Glue;
1085 // Operand #0 = Chain (updated below)
1086 RetOps.push_back(Chain);
1087 // Operand #1 = Bytes To Pop
1088 RetOps.push_back(
1089 DAG.getTargetConstant(MFI->getBytesToPopOnReturn(), DL, MVT::i32));
1090
1091 // Copy the result values into the output registers.
1092 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1093 CCValAssign &VA = RVLocs[i];
1094 assert(VA.isRegLoc() && "Can only return in registers!");
1095 SDValue ValToCopy = OutVals[i];
1096 EVT ValVT = ValToCopy.getValueType();
1097
1098 // Promote values to the appropriate types.
1099 if (VA.getLocInfo() == CCValAssign::SExt)
1100 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy);
1101 else if (VA.getLocInfo() == CCValAssign::ZExt)
1102 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), ValToCopy);
1103 else if (VA.getLocInfo() == CCValAssign::AExt) {
1104 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
1105 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy);
1106 else
1107 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), ValToCopy);
1108 } else if (VA.getLocInfo() == CCValAssign::BCvt)
1109 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
1110
1111 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), ValToCopy, Glue);
1112 Glue = Chain.getValue(1);
1113 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1114 }
1115
1116 // Swift calling convention does not require we copy the sret argument
1117 // into %d0 for the return, and SRetReturnReg is not set for Swift.
1118
1119 // ABI require that for returning structs by value we copy the sret argument
1120 // into %D0 for the return. Save the argument into a virtual register so that
1121 // we can access it from the return points.
1122 //
1123 // Checking Function.hasStructRetAttr() here is insufficient because the IR
1124 // may not have an explicit sret argument. If MFI.CanLowerReturn is
1125 // false, then an sret argument may be implicitly inserted in the SelDAG. In
1126 // either case MFI->setSRetReturnReg() will have been called.
1127 if (unsigned SRetReg = MFI->getSRetReturnReg()) {
1128 // ??? Can i just move this to the top and escape this explanation?
1129 // When we have both sret and another return value, we should use the
1130 // original Chain stored in RetOps[0], instead of the current Chain updated
1131 // in the above loop. If we only have sret, RetOps[0] equals to Chain.
1132
1133 // For the case of sret and another return value, we have
1134 // Chain_0 at the function entry
1135 // Chain_1 = getCopyToReg(Chain_0) in the above loop
1136 // If we use Chain_1 in getCopyFromReg, we will have
1137 // Val = getCopyFromReg(Chain_1)
1138 // Chain_2 = getCopyToReg(Chain_1, Val) from below
1139
1140 // getCopyToReg(Chain_0) will be glued together with
1141 // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
1142 // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
1143 // Data dependency from Unit B to Unit A due to usage of Val in
1144 // getCopyToReg(Chain_1, Val)
1145 // Chain dependency from Unit A to Unit B
1146
1147 // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
1148 SDValue Val = DAG.getCopyFromReg(RetOps[0], DL, SRetReg,
1150
1151 // ??? How will this work if CC does not use registers for args passing?
1152 // ??? What if I return multiple structs?
1153 unsigned RetValReg = M68k::D0;
1154 Chain = DAG.getCopyToReg(Chain, DL, RetValReg, Val, Glue);
1155 Glue = Chain.getValue(1);
1156
1157 RetOps.push_back(
1158 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
1159 }
1160
1161 RetOps[0] = Chain; // Update chain.
1162
1163 // Add the glue if we have it.
1164 if (Glue.getNode())
1165 RetOps.push_back(Glue);
1166
1167 return DAG.getNode(M68kISD::RET, DL, MVT::Other, RetOps);
1168}
1169
1170//===----------------------------------------------------------------------===//
1171// Fast Calling Convention (tail call) implementation
1172//===----------------------------------------------------------------------===//
1173
1174// Like std call, callee cleans arguments, convention except that ECX is
1175// reserved for storing the tail called function address. Only 2 registers are
1176// free for argument passing (inreg). Tail call optimization is performed
1177// provided:
1178// * tailcallopt is enabled
1179// * caller/callee are fastcc
1180// On M68k_64 architecture with GOT-style position independent code only
1181// local (within module) calls are supported at the moment. To keep the stack
1182// aligned according to platform abi the function GetAlignedArgumentStackSize
1183// ensures that argument delta is always multiples of stack alignment. (Dynamic
1184// linkers need this - darwin's dyld for example) If a tail called function
1185// callee has more arguments than the caller the caller needs to make sure that
1186// there is room to move the RETADDR to. This is achieved by reserving an area
1187// the size of the argument delta right after the original RETADDR, but before
1188// the saved framepointer or the spilled registers e.g. caller(arg1, arg2)
1189// calls callee(arg1, arg2,arg3,arg4) stack layout:
1190// arg1
1191// arg2
1192// RETADDR
1193// [ new RETADDR
1194// move area ]
1195// (possible EBP)
1196// ESI
1197// EDI
1198// local1 ..
1199
1200/// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
1201/// requirement.
1202unsigned
1203M68kTargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1204 SelectionDAG &DAG) const {
1205 const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
1206 unsigned StackAlignment = TFI.getStackAlignment();
1207 uint64_t AlignMask = StackAlignment - 1;
1208 int64_t Offset = StackSize;
1209 unsigned SlotSize = Subtarget.getSlotSize();
1210 if ((Offset & AlignMask) <= (StackAlignment - SlotSize)) {
1211 // Number smaller than 12 so just add the difference.
1212 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1213 } else {
1214 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1215 Offset =
1216 ((~AlignMask) & Offset) + StackAlignment + (StackAlignment - SlotSize);
1217 }
1218 return Offset;
1219}
1220
1221/// Check whether the call is eligible for tail call optimization. Targets
1222/// that want to do tail call optimization should implement this function.
1223bool M68kTargetLowering::IsEligibleForTailCallOptimization(
1224 SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
1225 bool IsCalleeStructRet, bool IsCallerStructRet, Type *RetTy,
1227 const SmallVectorImpl<SDValue> &OutVals,
1228 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
1229 if (!mayTailCallThisCC(CalleeCC))
1230 return false;
1231
1232 // If -tailcallopt is specified, make fastcc functions tail-callable.
1234 const auto &CallerF = MF.getFunction();
1235
1236 CallingConv::ID CallerCC = CallerF.getCallingConv();
1237 bool CCMatch = CallerCC == CalleeCC;
1238
1240 if (canGuaranteeTCO(CalleeCC) && CCMatch)
1241 return true;
1242 return false;
1243 }
1244
1245 // Look for obvious safe cases to perform tail call optimization that do not
1246 // require ABI changes. This is what gcc calls sibcall.
1247
1248 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
1249 // emit a special epilogue.
1250 const M68kRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1251 if (RegInfo->hasStackRealignment(MF))
1252 return false;
1253
1254 // Also avoid sibcall optimization if either caller or callee uses struct
1255 // return semantics.
1256 if (IsCalleeStructRet || IsCallerStructRet)
1257 return false;
1258
1259 // Do not sibcall optimize vararg calls unless all arguments are passed via
1260 // registers.
1261 LLVMContext &C = *DAG.getContext();
1262 if (IsVarArg && !Outs.empty()) {
1263
1265 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, C);
1266
1267 CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
1268 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
1269 if (!ArgLocs[i].isRegLoc())
1270 return false;
1271 }
1272
1273 // Check that the call results are passed in the same way.
1274 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins, RetCC_M68k,
1275 RetCC_M68k))
1276 return false;
1277
1278 // The callee has to preserve all registers the caller needs to preserve.
1279 const M68kRegisterInfo *TRI = Subtarget.getRegisterInfo();
1280 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
1281 if (!CCMatch) {
1282 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
1283 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
1284 return false;
1285 }
1286
1287 unsigned StackArgsSize = 0;
1288
1289 // If the callee takes no arguments then go on to check the results of the
1290 // call.
1291 if (!Outs.empty()) {
1292 // Check if stack adjustment is needed. For now, do not do this if any
1293 // argument is passed on the stack.
1295 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, C);
1296
1297 CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
1298 StackArgsSize = CCInfo.getStackSize();
1299
1300 if (StackArgsSize) {
1301 // Check if the arguments are already laid out in the right way as
1302 // the caller's fixed stack objects.
1303 MachineFrameInfo &MFI = MF.getFrameInfo();
1304 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1305 const M68kInstrInfo *TII = Subtarget.getInstrInfo();
1306 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1307 CCValAssign &VA = ArgLocs[i];
1308 SDValue Arg = OutVals[i];
1309 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1311 return false;
1312 if (!VA.isRegLoc()) {
1313 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, MFI, MRI,
1314 TII, VA))
1315 return false;
1316 }
1317 }
1318 }
1319
1320 bool PositionIndependent = isPositionIndependent();
1321 // If the tailcall address may be in a register, then make sure it's
1322 // possible to register allocate for it. The call address can
1323 // only target %A0 or %A1 since the tail call must be scheduled after
1324 // callee-saved registers are restored. These happen to be the same
1325 // registers used to pass 'inreg' arguments so watch out for those.
1326 if ((!isa<GlobalAddressSDNode>(Callee) &&
1327 !isa<ExternalSymbolSDNode>(Callee)) ||
1328 PositionIndependent) {
1329 unsigned NumInRegs = 0;
1330 // In PIC we need an extra register to formulate the address computation
1331 // for the callee.
1332 unsigned MaxInRegs = PositionIndependent ? 1 : 2;
1333
1334 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1335 CCValAssign &VA = ArgLocs[i];
1336 if (!VA.isRegLoc())
1337 continue;
1338 Register Reg = VA.getLocReg();
1339 switch (Reg) {
1340 default:
1341 break;
1342 case M68k::A0:
1343 case M68k::A1:
1344 if (++NumInRegs == MaxInRegs)
1345 return false;
1346 break;
1347 }
1348 }
1349 }
1350
1351 const MachineRegisterInfo &MRI = MF.getRegInfo();
1352 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
1353 return false;
1354 }
1355
1356 bool CalleeWillPop = M68k::isCalleePop(
1357 CalleeCC, IsVarArg, MF.getTarget().Options.GuaranteedTailCallOpt);
1358
1359 if (unsigned BytesToPop =
1361 // If we have bytes to pop, the callee must pop them.
1362 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
1363 if (!CalleePopMatches)
1364 return false;
1365 } else if (CalleeWillPop && StackArgsSize > 0) {
1366 // If we don't have bytes to pop, make sure the callee doesn't pop any.
1367 return false;
1368 }
1369
1370 return true;
1371}
1372
1373//===----------------------------------------------------------------------===//
1374// Custom Lower
1375//===----------------------------------------------------------------------===//
1376
1378 SelectionDAG &DAG) const {
1379 switch (Op.getOpcode()) {
1380 default:
1381 llvm_unreachable("Should not custom lower this!");
1382 case ISD::SADDO:
1383 case ISD::UADDO:
1384 case ISD::SSUBO:
1385 case ISD::USUBO:
1386 case ISD::SMULO:
1387 case ISD::UMULO:
1388 return LowerXALUO(Op, DAG);
1389 case ISD::SETCC:
1390 return LowerSETCC(Op, DAG);
1391 case ISD::SETCCCARRY:
1392 return LowerSETCCCARRY(Op, DAG);
1393 case ISD::SELECT:
1394 return LowerSELECT(Op, DAG);
1395 case ISD::BRCOND:
1396 return LowerBRCOND(Op, DAG);
1397 case ISD::ADDC:
1398 case ISD::ADDE:
1399 case ISD::SUBC:
1400 case ISD::SUBE:
1401 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1402 case ISD::ConstantPool:
1403 return LowerConstantPool(Op, DAG);
1404 case ISD::GlobalAddress:
1405 return LowerGlobalAddress(Op, DAG);
1407 return LowerExternalSymbol(Op, DAG);
1408 case ISD::BlockAddress:
1409 return LowerBlockAddress(Op, DAG);
1410 case ISD::JumpTable:
1411 return LowerJumpTable(Op, DAG);
1412 case ISD::VASTART:
1413 return LowerVASTART(Op, DAG);
1415 return LowerDYNAMIC_STACKALLOC(Op, DAG);
1416 case ISD::SHL_PARTS:
1417 return LowerShiftLeftParts(Op, DAG);
1418 case ISD::SRA_PARTS:
1419 return LowerShiftRightParts(Op, DAG, true);
1420 case ISD::SRL_PARTS:
1421 return LowerShiftRightParts(Op, DAG, false);
1422 case ISD::ATOMIC_FENCE:
1423 return LowerATOMICFENCE(Op, DAG);
1425 return LowerGlobalTLSAddress(Op, DAG);
1426 }
1427}
1428
1429SDValue M68kTargetLowering::LowerExternalSymbolCall(SelectionDAG &DAG,
1430 SDLoc Loc,
1431 llvm::StringRef SymbolName,
1432 ArgListTy &&ArgList) const {
1433 PointerType *PtrTy = PointerType::get(*DAG.getContext(), 0);
1434 CallLoweringInfo CLI(DAG);
1435 CLI.setDebugLoc(Loc)
1436 .setChain(DAG.getEntryNode())
1438 DAG.getExternalSymbol(SymbolName.data(),
1440 std::move(ArgList));
1441 return LowerCallTo(CLI).first;
1442}
1443
1444SDValue M68kTargetLowering::getTLSGetAddr(GlobalAddressSDNode *GA,
1445 SelectionDAG &DAG,
1446 unsigned TargetFlags) const {
1447 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1449 GA->getGlobal(), GA, GA->getValueType(0), GA->getOffset(), TargetFlags);
1450 SDValue Arg = DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, GOT, TGA);
1451
1452 PointerType *PtrTy = PointerType::get(*DAG.getContext(), 0);
1453
1454 ArgListTy Args;
1455 ArgListEntry Entry;
1456 Entry.Node = Arg;
1457 Entry.Ty = PtrTy;
1458 Args.push_back(Entry);
1459 return LowerExternalSymbolCall(DAG, SDLoc(GA), "__tls_get_addr",
1460 std::move(Args));
1461}
1462
1463SDValue M68kTargetLowering::getM68kReadTp(SDLoc Loc, SelectionDAG &DAG) const {
1464 return LowerExternalSymbolCall(DAG, Loc, "__m68k_read_tp", ArgListTy());
1465}
1466
1467SDValue M68kTargetLowering::LowerTLSGeneralDynamic(GlobalAddressSDNode *GA,
1468 SelectionDAG &DAG) const {
1469 return getTLSGetAddr(GA, DAG, M68kII::MO_TLSGD);
1470}
1471
1472SDValue M68kTargetLowering::LowerTLSLocalDynamic(GlobalAddressSDNode *GA,
1473 SelectionDAG &DAG) const {
1474 SDValue Addr = getTLSGetAddr(GA, DAG, M68kII::MO_TLSLDM);
1475 SDValue TGA =
1476 DAG.getTargetGlobalAddress(GA->getGlobal(), GA, GA->getValueType(0),
1478 return DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, TGA, Addr);
1479}
1480
1481SDValue M68kTargetLowering::LowerTLSInitialExec(GlobalAddressSDNode *GA,
1482 SelectionDAG &DAG) const {
1483 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1484 SDValue Tp = getM68kReadTp(SDLoc(GA), DAG);
1485 SDValue TGA =
1486 DAG.getTargetGlobalAddress(GA->getGlobal(), GA, GA->getValueType(0),
1488 SDValue Addr = DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, TGA, GOT);
1489 SDValue Offset =
1490 DAG.getLoad(MVT::i32, SDLoc(GA), DAG.getEntryNode(), Addr,
1492
1493 return DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, Offset, Tp);
1494}
1495
1496SDValue M68kTargetLowering::LowerTLSLocalExec(GlobalAddressSDNode *GA,
1497 SelectionDAG &DAG) const {
1498 SDValue Tp = getM68kReadTp(SDLoc(GA), DAG);
1499 SDValue TGA =
1500 DAG.getTargetGlobalAddress(GA->getGlobal(), GA, GA->getValueType(0),
1502 return DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, TGA, Tp);
1503}
1504
1505SDValue M68kTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1506 SelectionDAG &DAG) const {
1507 assert(Subtarget.isTargetELF());
1508
1509 auto *GA = cast<GlobalAddressSDNode>(Op);
1510 TLSModel::Model AccessModel = DAG.getTarget().getTLSModel(GA->getGlobal());
1511
1512 switch (AccessModel) {
1514 return LowerTLSGeneralDynamic(GA, DAG);
1516 return LowerTLSLocalDynamic(GA, DAG);
1518 return LowerTLSInitialExec(GA, DAG);
1520 return LowerTLSLocalExec(GA, DAG);
1521 }
1522
1523 llvm_unreachable("Unexpected TLS access model type");
1524}
1525
1526bool M68kTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
1527 SDValue C) const {
1528 // Shifts and add instructions in M68000 and M68010 support
1529 // up to 32 bits, but mul only has 16-bit variant. So it's almost
1530 // certainly beneficial to lower 8/16/32-bit mul to their
1531 // add / shifts counterparts. But for 64-bits mul, it might be
1532 // safer to just leave it to compiler runtime implementations.
1533 return VT.bitsLE(MVT::i32) || Subtarget.atLeastM68020();
1534}
1535
1536SDValue M68kTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
1537 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
1538 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
1539 // looks for this combo and may remove the "setcc" instruction if the "setcc"
1540 // has only one use.
1541 SDNode *N = Op.getNode();
1542 SDValue LHS = N->getOperand(0);
1543 SDValue RHS = N->getOperand(1);
1544 unsigned BaseOp = 0;
1545 unsigned Cond = 0;
1546 SDLoc DL(Op);
1547 switch (Op.getOpcode()) {
1548 default:
1549 llvm_unreachable("Unknown ovf instruction!");
1550 case ISD::SADDO:
1551 BaseOp = M68kISD::ADD;
1553 break;
1554 case ISD::UADDO:
1555 BaseOp = M68kISD::ADD;
1557 break;
1558 case ISD::SSUBO:
1559 BaseOp = M68kISD::SUB;
1561 break;
1562 case ISD::USUBO:
1563 BaseOp = M68kISD::SUB;
1565 break;
1566 }
1567
1568 // Also sets CCR.
1569 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i8);
1570 SDValue Arith = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
1571 SDValue SetCC = DAG.getNode(M68kISD::SETCC, DL, N->getValueType(1),
1572 DAG.getConstant(Cond, DL, MVT::i8),
1573 SDValue(Arith.getNode(), 1));
1574
1575 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Arith, SetCC);
1576}
1577
1578/// Create a BTST (Bit Test) node - Test bit \p BitNo in \p Src and set
1579/// condition according to equal/not-equal condition code \p CC.
1581 const SDLoc &DL, SelectionDAG &DAG) {
1582 // If Src is i8, promote it to i32 with any_extend. There is no i8 BTST
1583 // instruction. Since the shift amount is in-range-or-undefined, we know
1584 // that doing a bittest on the i32 value is ok.
1585 if (Src.getValueType() == MVT::i8 || Src.getValueType() == MVT::i16)
1586 Src = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Src);
1587
1588 // If the operand types disagree, extend the shift amount to match. Since
1589 // BTST ignores high bits (like shifts) we can use anyextend.
1590 if (Src.getValueType() != BitNo.getValueType())
1591 BitNo = DAG.getNode(ISD::ANY_EXTEND, DL, Src.getValueType(), BitNo);
1592
1593 SDValue BTST = DAG.getNode(M68kISD::BTST, DL, MVT::i32, Src, BitNo);
1594
1595 // NOTE BTST sets CCR.Z flag
1597 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
1598 DAG.getConstant(Cond, DL, MVT::i8), BTST);
1599}
1600
1601/// Result of 'and' is compared against zero. Change to a BTST node if possible.
1603 SelectionDAG &DAG) {
1604 SDValue Op0 = And.getOperand(0);
1605 SDValue Op1 = And.getOperand(1);
1606 if (Op0.getOpcode() == ISD::TRUNCATE)
1607 Op0 = Op0.getOperand(0);
1608 if (Op1.getOpcode() == ISD::TRUNCATE)
1609 Op1 = Op1.getOperand(0);
1610
1611 SDValue LHS, RHS;
1612 if (Op1.getOpcode() == ISD::SHL)
1613 std::swap(Op0, Op1);
1614 if (Op0.getOpcode() == ISD::SHL) {
1615 if (isOneConstant(Op0.getOperand(0))) {
1616 // If we looked past a truncate, check that it's only truncating away
1617 // known zeros.
1618 unsigned BitWidth = Op0.getValueSizeInBits();
1619 unsigned AndBitWidth = And.getValueSizeInBits();
1620 if (BitWidth > AndBitWidth) {
1621 auto Known = DAG.computeKnownBits(Op0);
1622 if (Known.countMinLeadingZeros() < BitWidth - AndBitWidth)
1623 return SDValue();
1624 }
1625 LHS = Op1;
1626 RHS = Op0.getOperand(1);
1627 }
1628 } else if (auto *AndRHS = dyn_cast<ConstantSDNode>(Op1)) {
1629 uint64_t AndRHSVal = AndRHS->getZExtValue();
1630 SDValue AndLHS = Op0;
1631
1632 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
1633 LHS = AndLHS.getOperand(0);
1634 RHS = AndLHS.getOperand(1);
1635 }
1636
1637 // Use BTST if the immediate can't be encoded in a TEST instruction.
1638 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
1639 LHS = AndLHS;
1640 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), DL, LHS.getValueType());
1641 }
1642 }
1643
1644 if (LHS.getNode())
1645 return getBitTestCondition(LHS, RHS, CC, DL, DAG);
1646
1647 return SDValue();
1648}
1649
1651 switch (SetCCOpcode) {
1652 default:
1653 llvm_unreachable("Invalid integer condition!");
1654 case ISD::SETEQ:
1655 return M68k::COND_EQ;
1656 case ISD::SETGT:
1657 return M68k::COND_GT;
1658 case ISD::SETGE:
1659 return M68k::COND_GE;
1660 case ISD::SETLT:
1661 return M68k::COND_LT;
1662 case ISD::SETLE:
1663 return M68k::COND_LE;
1664 case ISD::SETNE:
1665 return M68k::COND_NE;
1666 case ISD::SETULT:
1667 return M68k::COND_CS;
1668 case ISD::SETUGE:
1669 return M68k::COND_CC;
1670 case ISD::SETUGT:
1671 return M68k::COND_HI;
1672 case ISD::SETULE:
1673 return M68k::COND_LS;
1674 }
1675}
1676
1677/// Do a one-to-one translation of a ISD::CondCode to the M68k-specific
1678/// condition code, returning the condition code and the LHS/RHS of the
1679/// comparison to make.
1680static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL,
1681 bool IsFP, SDValue &LHS, SDValue &RHS,
1682 SelectionDAG &DAG) {
1683 if (!IsFP) {
1684 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1685 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnes()) {
1686 // X > -1 -> X == 0, jump !sign.
1687 RHS = DAG.getConstant(0, DL, RHS.getValueType());
1688 return M68k::COND_PL;
1689 }
1690 if (SetCCOpcode == ISD::SETLT && RHSC->isZero()) {
1691 // X < 0 -> X == 0, jump on sign.
1692 return M68k::COND_MI;
1693 }
1694 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
1695 // X < 1 -> X <= 0
1696 RHS = DAG.getConstant(0, DL, RHS.getValueType());
1697 return M68k::COND_LE;
1698 }
1699 }
1700
1701 return TranslateIntegerM68kCC(SetCCOpcode);
1702 }
1703
1704 // First determine if it is required or is profitable to flip the operands.
1705
1706 // If LHS is a foldable load, but RHS is not, flip the condition.
1707 if (ISD::isNON_EXTLoad(LHS.getNode()) && !ISD::isNON_EXTLoad(RHS.getNode())) {
1708 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
1709 std::swap(LHS, RHS);
1710 }
1711
1712 switch (SetCCOpcode) {
1713 default:
1714 break;
1715 case ISD::SETOLT:
1716 case ISD::SETOLE:
1717 case ISD::SETUGT:
1718 case ISD::SETUGE:
1719 std::swap(LHS, RHS);
1720 break;
1721 }
1722
1723 // On a floating point condition, the flags are set as follows:
1724 // ZF PF CF op
1725 // 0 | 0 | 0 | X > Y
1726 // 0 | 0 | 1 | X < Y
1727 // 1 | 0 | 0 | X == Y
1728 // 1 | 1 | 1 | unordered
1729 switch (SetCCOpcode) {
1730 default:
1731 llvm_unreachable("Condcode should be pre-legalized away");
1732 case ISD::SETUEQ:
1733 case ISD::SETEQ:
1734 return M68k::COND_EQ;
1735 case ISD::SETOLT: // flipped
1736 case ISD::SETOGT:
1737 case ISD::SETGT:
1738 return M68k::COND_HI;
1739 case ISD::SETOLE: // flipped
1740 case ISD::SETOGE:
1741 case ISD::SETGE:
1742 return M68k::COND_CC;
1743 case ISD::SETUGT: // flipped
1744 case ISD::SETULT:
1745 case ISD::SETLT:
1746 return M68k::COND_CS;
1747 case ISD::SETUGE: // flipped
1748 case ISD::SETULE:
1749 case ISD::SETLE:
1750 return M68k::COND_LS;
1751 case ISD::SETONE:
1752 case ISD::SETNE:
1753 return M68k::COND_NE;
1754 case ISD::SETOEQ:
1755 case ISD::SETUNE:
1756 return M68k::COND_INVALID;
1757 }
1758}
1759
1760// Convert (truncate (srl X, N) to i1) to (bt X, N)
1762 const SDLoc &DL, SelectionDAG &DAG) {
1763
1764 assert(Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1 &&
1765 "Expected TRUNCATE to i1 node");
1766
1767 if (Op.getOperand(0).getOpcode() != ISD::SRL)
1768 return SDValue();
1769
1770 SDValue ShiftRight = Op.getOperand(0);
1771 return getBitTestCondition(ShiftRight.getOperand(0), ShiftRight.getOperand(1),
1772 CC, DL, DAG);
1773}
1774
1775/// \brief return true if \c Op has a use that doesn't just read flags.
1777 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
1778 ++UI) {
1779 SDNode *User = *UI;
1780 unsigned UOpNo = UI.getOperandNo();
1781 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
1782 // Look pass truncate.
1783 UOpNo = User->use_begin().getOperandNo();
1784 User = *User->use_begin();
1785 }
1786
1787 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
1788 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
1789 return true;
1790 }
1791 return false;
1792}
1793
1794SDValue M68kTargetLowering::EmitTest(SDValue Op, unsigned M68kCC,
1795 const SDLoc &DL, SelectionDAG &DAG) const {
1796
1797 // CF and OF aren't always set the way we want. Determine which
1798 // of these we need.
1799 bool NeedCF = false;
1800 bool NeedOF = false;
1801 switch (M68kCC) {
1802 default:
1803 break;
1804 case M68k::COND_HI:
1805 case M68k::COND_CC:
1806 case M68k::COND_CS:
1807 case M68k::COND_LS:
1808 NeedCF = true;
1809 break;
1810 case M68k::COND_GT:
1811 case M68k::COND_GE:
1812 case M68k::COND_LT:
1813 case M68k::COND_LE:
1814 case M68k::COND_VS:
1815 case M68k::COND_VC: {
1816 // Check if we really need to set the
1817 // Overflow flag. If NoSignedWrap is present
1818 // that is not actually needed.
1819 switch (Op->getOpcode()) {
1820 case ISD::ADD:
1821 case ISD::SUB:
1822 case ISD::MUL:
1823 case ISD::SHL: {
1824 if (Op.getNode()->getFlags().hasNoSignedWrap())
1825 break;
1826 [[fallthrough]];
1827 }
1828 default:
1829 NeedOF = true;
1830 break;
1831 }
1832 break;
1833 }
1834 }
1835 // See if we can use the CCR value from the operand instead of
1836 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
1837 // we prove that the arithmetic won't overflow, we can't use OF or CF.
1838 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
1839 // Emit a CMP with 0, which is the TEST pattern.
1840 return DAG.getNode(M68kISD::CMP, DL, MVT::i8,
1841 DAG.getConstant(0, DL, Op.getValueType()), Op);
1842 }
1843 unsigned Opcode = 0;
1844 unsigned NumOperands = 0;
1845
1846 // Truncate operations may prevent the merge of the SETCC instruction
1847 // and the arithmetic instruction before it. Attempt to truncate the operands
1848 // of the arithmetic instruction and use a reduced bit-width instruction.
1849 bool NeedTruncation = false;
1850 SDValue ArithOp = Op;
1851 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
1852 SDValue Arith = Op->getOperand(0);
1853 // Both the trunc and the arithmetic op need to have one user each.
1854 if (Arith->hasOneUse())
1855 switch (Arith.getOpcode()) {
1856 default:
1857 break;
1858 case ISD::ADD:
1859 case ISD::SUB:
1860 case ISD::AND:
1861 case ISD::OR:
1862 case ISD::XOR: {
1863 NeedTruncation = true;
1864 ArithOp = Arith;
1865 }
1866 }
1867 }
1868
1869 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
1870 // which may be the result of a CAST. We use the variable 'Op', which is the
1871 // non-casted variable when we check for possible users.
1872 switch (ArithOp.getOpcode()) {
1873 case ISD::ADD:
1874 Opcode = M68kISD::ADD;
1875 NumOperands = 2;
1876 break;
1877 case ISD::SHL:
1878 case ISD::SRL:
1879 // If we have a constant logical shift that's only used in a comparison
1880 // against zero turn it into an equivalent AND. This allows turning it into
1881 // a TEST instruction later.
1882 if ((M68kCC == M68k::COND_EQ || M68kCC == M68k::COND_NE) &&
1883 Op->hasOneUse() && isa<ConstantSDNode>(Op->getOperand(1)) &&
1884 !hasNonFlagsUse(Op)) {
1885 EVT VT = Op.getValueType();
1886 unsigned BitWidth = VT.getSizeInBits();
1887 unsigned ShAmt = Op->getConstantOperandVal(1);
1888 if (ShAmt >= BitWidth) // Avoid undefined shifts.
1889 break;
1890 APInt Mask = ArithOp.getOpcode() == ISD::SRL
1892 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
1893 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
1894 break;
1895 Op = DAG.getNode(ISD::AND, DL, VT, Op->getOperand(0),
1896 DAG.getConstant(Mask, DL, VT));
1897 }
1898 break;
1899
1900 case ISD::AND:
1901 // If the primary 'and' result isn't used, don't bother using
1902 // M68kISD::AND, because a TEST instruction will be better.
1903 if (!hasNonFlagsUse(Op)) {
1904 SDValue Op0 = ArithOp->getOperand(0);
1905 SDValue Op1 = ArithOp->getOperand(1);
1906 EVT VT = ArithOp.getValueType();
1907 bool IsAndn = isBitwiseNot(Op0) || isBitwiseNot(Op1);
1908 bool IsLegalAndnType = VT == MVT::i32 || VT == MVT::i64;
1909
1910 // But if we can combine this into an ANDN operation, then create an AND
1911 // now and allow it to be pattern matched into an ANDN.
1912 if (/*!Subtarget.hasBMI() ||*/ !IsAndn || !IsLegalAndnType)
1913 break;
1914 }
1915 [[fallthrough]];
1916 case ISD::SUB:
1917 case ISD::OR:
1918 case ISD::XOR:
1919 // Due to the ISEL shortcoming noted above, be conservative if this op is
1920 // likely to be selected as part of a load-modify-store instruction.
1921 for (const auto *U : Op.getNode()->uses())
1922 if (U->getOpcode() == ISD::STORE)
1923 goto default_case;
1924
1925 // Otherwise use a regular CCR-setting instruction.
1926 switch (ArithOp.getOpcode()) {
1927 default:
1928 llvm_unreachable("unexpected operator!");
1929 case ISD::SUB:
1930 Opcode = M68kISD::SUB;
1931 break;
1932 case ISD::XOR:
1933 Opcode = M68kISD::XOR;
1934 break;
1935 case ISD::AND:
1936 Opcode = M68kISD::AND;
1937 break;
1938 case ISD::OR:
1939 Opcode = M68kISD::OR;
1940 break;
1941 }
1942
1943 NumOperands = 2;
1944 break;
1945 case M68kISD::ADD:
1946 case M68kISD::SUB:
1947 case M68kISD::OR:
1948 case M68kISD::XOR:
1949 case M68kISD::AND:
1950 return SDValue(Op.getNode(), 1);
1951 default:
1952 default_case:
1953 break;
1954 }
1955
1956 // If we found that truncation is beneficial, perform the truncation and
1957 // update 'Op'.
1958 if (NeedTruncation) {
1959 EVT VT = Op.getValueType();
1960 SDValue WideVal = Op->getOperand(0);
1961 EVT WideVT = WideVal.getValueType();
1962 unsigned ConvertedOp = 0;
1963 // Use a target machine opcode to prevent further DAGCombine
1964 // optimizations that may separate the arithmetic operations
1965 // from the setcc node.
1966 switch (WideVal.getOpcode()) {
1967 default:
1968 break;
1969 case ISD::ADD:
1970 ConvertedOp = M68kISD::ADD;
1971 break;
1972 case ISD::SUB:
1973 ConvertedOp = M68kISD::SUB;
1974 break;
1975 case ISD::AND:
1976 ConvertedOp = M68kISD::AND;
1977 break;
1978 case ISD::OR:
1979 ConvertedOp = M68kISD::OR;
1980 break;
1981 case ISD::XOR:
1982 ConvertedOp = M68kISD::XOR;
1983 break;
1984 }
1985
1986 if (ConvertedOp) {
1987 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1988 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
1989 SDValue V0 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(0));
1990 SDValue V1 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(1));
1991 Op = DAG.getNode(ConvertedOp, DL, VT, V0, V1);
1992 }
1993 }
1994 }
1995
1996 if (Opcode == 0) {
1997 // Emit a CMP with 0, which is the TEST pattern.
1998 return DAG.getNode(M68kISD::CMP, DL, MVT::i8,
1999 DAG.getConstant(0, DL, Op.getValueType()), Op);
2000 }
2001 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i8);
2002 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
2003
2004 SDValue New = DAG.getNode(Opcode, DL, VTs, Ops);
2005 DAG.ReplaceAllUsesWith(Op, New);
2006 return SDValue(New.getNode(), 1);
2007}
2008
2009/// \brief Return true if the condition is an unsigned comparison operation.
2010static bool isM68kCCUnsigned(unsigned M68kCC) {
2011 switch (M68kCC) {
2012 default:
2013 llvm_unreachable("Invalid integer condition!");
2014 case M68k::COND_EQ:
2015 case M68k::COND_NE:
2016 case M68k::COND_CS:
2017 case M68k::COND_HI:
2018 case M68k::COND_LS:
2019 case M68k::COND_CC:
2020 return true;
2021 case M68k::COND_GT:
2022 case M68k::COND_GE:
2023 case M68k::COND_LT:
2024 case M68k::COND_LE:
2025 return false;
2026 }
2027}
2028
2029SDValue M68kTargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned M68kCC,
2030 const SDLoc &DL, SelectionDAG &DAG) const {
2031 if (isNullConstant(Op1))
2032 return EmitTest(Op0, M68kCC, DL, DAG);
2033
2034 assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
2035 "Unexpected comparison operation for MVT::i1 operands");
2036
2037 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
2038 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
2039 // Only promote the compare up to I32 if it is a 16 bit operation
2040 // with an immediate. 16 bit immediates are to be avoided.
2041 if ((Op0.getValueType() == MVT::i16 &&
2042 (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1))) &&
2044 unsigned ExtendOp =
2046 Op0 = DAG.getNode(ExtendOp, DL, MVT::i32, Op0);
2047 Op1 = DAG.getNode(ExtendOp, DL, MVT::i32, Op1);
2048 }
2049 // Use SUB instead of CMP to enable CSE between SUB and CMP.
2050 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i8);
2051 SDValue Sub = DAG.getNode(M68kISD::SUB, DL, VTs, Op0, Op1);
2052 return SDValue(Sub.getNode(), 1);
2053 }
2054 return DAG.getNode(M68kISD::CMP, DL, MVT::i8, Op0, Op1);
2055}
2056
2057/// Result of 'and' or 'trunc to i1' is compared against zero.
2058/// Change to a BTST node if possible.
2059SDValue M68kTargetLowering::LowerToBTST(SDValue Op, ISD::CondCode CC,
2060 const SDLoc &DL,
2061 SelectionDAG &DAG) const {
2062 if (Op.getOpcode() == ISD::AND)
2063 return LowerAndToBTST(Op, CC, DL, DAG);
2064 if (Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1)
2065 return LowerTruncateToBTST(Op, CC, DL, DAG);
2066 return SDValue();
2067}
2068
2069SDValue M68kTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2070 MVT VT = Op.getSimpleValueType();
2071 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
2072
2073 SDValue Op0 = Op.getOperand(0);
2074 SDValue Op1 = Op.getOperand(1);
2075 SDLoc DL(Op);
2076 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2077
2078 // Optimize to BTST if possible.
2079 // Lower (X & (1 << N)) == 0 to BTST(X, N).
2080 // Lower ((X >>u N) & 1) != 0 to BTST(X, N).
2081 // Lower ((X >>s N) & 1) != 0 to BTST(X, N).
2082 // Lower (trunc (X >> N) to i1) to BTST(X, N).
2083 if (Op0.hasOneUse() && isNullConstant(Op1) &&
2084 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2085 if (SDValue NewSetCC = LowerToBTST(Op0, CC, DL, DAG)) {
2086 if (VT == MVT::i1)
2087 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, NewSetCC);
2088 return NewSetCC;
2089 }
2090 }
2091
2092 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
2093 // these.
2094 if ((isOneConstant(Op1) || isNullConstant(Op1)) &&
2095 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2096
2097 // If the input is a setcc, then reuse the input setcc or use a new one with
2098 // the inverted condition.
2099 if (Op0.getOpcode() == M68kISD::SETCC) {
2101 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
2102 if (!Invert)
2103 return Op0;
2104
2105 CCode = M68k::GetOppositeBranchCondition(CCode);
2106 SDValue SetCC =
2107 DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
2108 DAG.getConstant(CCode, DL, MVT::i8), Op0.getOperand(1));
2109 if (VT == MVT::i1)
2110 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
2111 return SetCC;
2112 }
2113 }
2114 if (Op0.getValueType() == MVT::i1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2115 if (isOneConstant(Op1)) {
2117 return DAG.getSetCC(DL, VT, Op0, DAG.getConstant(0, DL, MVT::i1), NewCC);
2118 }
2119 if (!isNullConstant(Op1)) {
2120 SDValue Xor = DAG.getNode(ISD::XOR, DL, MVT::i1, Op0, Op1);
2121 return DAG.getSetCC(DL, VT, Xor, DAG.getConstant(0, DL, MVT::i1), CC);
2122 }
2123 }
2124
2125 bool IsFP = Op1.getSimpleValueType().isFloatingPoint();
2126 unsigned M68kCC = TranslateM68kCC(CC, DL, IsFP, Op0, Op1, DAG);
2127 if (M68kCC == M68k::COND_INVALID)
2128 return SDValue();
2129
2130 SDValue CCR = EmitCmp(Op0, Op1, M68kCC, DL, DAG);
2131 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
2132 DAG.getConstant(M68kCC, DL, MVT::i8), CCR);
2133}
2134
2135SDValue M68kTargetLowering::LowerSETCCCARRY(SDValue Op,
2136 SelectionDAG &DAG) const {
2137 SDValue LHS = Op.getOperand(0);
2138 SDValue RHS = Op.getOperand(1);
2139 SDValue Carry = Op.getOperand(2);
2140 SDValue Cond = Op.getOperand(3);
2141 SDLoc DL(Op);
2142
2143 assert(LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only.");
2144 M68k::CondCode CC = TranslateIntegerM68kCC(cast<CondCodeSDNode>(Cond)->get());
2145
2146 EVT CarryVT = Carry.getValueType();
2147 APInt NegOne = APInt::getAllOnes(CarryVT.getScalarSizeInBits());
2148 Carry = DAG.getNode(M68kISD::ADD, DL, DAG.getVTList(CarryVT, MVT::i32), Carry,
2149 DAG.getConstant(NegOne, DL, CarryVT));
2150
2151 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
2152 SDValue Cmp =
2153 DAG.getNode(M68kISD::SUBX, DL, VTs, LHS, RHS, Carry.getValue(1));
2154
2155 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
2156 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
2157}
2158
2159/// Return true if opcode is a M68k logical comparison.
2161 unsigned Opc = Op.getNode()->getOpcode();
2162 if (Opc == M68kISD::CMP)
2163 return true;
2164 if (Op.getResNo() == 1 &&
2165 (Opc == M68kISD::ADD || Opc == M68kISD::SUB || Opc == M68kISD::ADDX ||
2166 Opc == M68kISD::SUBX || Opc == M68kISD::SMUL || Opc == M68kISD::UMUL ||
2167 Opc == M68kISD::OR || Opc == M68kISD::XOR || Opc == M68kISD::AND))
2168 return true;
2169
2170 if (Op.getResNo() == 2 && Opc == M68kISD::UMUL)
2171 return true;
2172
2173 return false;
2174}
2175
2177 if (V.getOpcode() != ISD::TRUNCATE)
2178 return false;
2179
2180 SDValue VOp0 = V.getOperand(0);
2181 unsigned InBits = VOp0.getValueSizeInBits();
2182 unsigned Bits = V.getValueSizeInBits();
2183 return DAG.MaskedValueIsZero(VOp0,
2184 APInt::getHighBitsSet(InBits, InBits - Bits));
2185}
2186
2187SDValue M68kTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2188 bool addTest = true;
2189 SDValue Cond = Op.getOperand(0);
2190 SDValue Op1 = Op.getOperand(1);
2191 SDValue Op2 = Op.getOperand(2);
2192 SDLoc DL(Op);
2193 SDValue CC;
2194
2195 if (Cond.getOpcode() == ISD::SETCC) {
2196 if (SDValue NewCond = LowerSETCC(Cond, DAG))
2197 Cond = NewCond;
2198 }
2199
2200 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
2201 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
2202 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
2203 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
2204 if (Cond.getOpcode() == M68kISD::SETCC &&
2205 Cond.getOperand(1).getOpcode() == M68kISD::CMP &&
2206 isNullConstant(Cond.getOperand(1).getOperand(0))) {
2207 SDValue Cmp = Cond.getOperand(1);
2208
2209 unsigned CondCode =
2210 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
2211
2212 if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
2213 (CondCode == M68k::COND_EQ || CondCode == M68k::COND_NE)) {
2214 SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
2215
2216 SDValue CmpOp0 = Cmp.getOperand(1);
2217 // Apply further optimizations for special cases
2218 // (select (x != 0), -1, 0) -> neg & sbb
2219 // (select (x == 0), 0, -1) -> neg & sbb
2220 if (isNullConstant(Y) &&
2221 (isAllOnesConstant(Op1) == (CondCode == M68k::COND_NE))) {
2222
2223 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
2224
2225 SDValue Neg =
2226 DAG.getNode(M68kISD::SUB, DL, VTs,
2227 DAG.getConstant(0, DL, CmpOp0.getValueType()), CmpOp0);
2228
2229 SDValue Res = DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(),
2230 DAG.getConstant(M68k::COND_CS, DL, MVT::i8),
2231 SDValue(Neg.getNode(), 1));
2232 return Res;
2233 }
2234
2235 Cmp = DAG.getNode(M68kISD::CMP, DL, MVT::i8,
2236 DAG.getConstant(1, DL, CmpOp0.getValueType()), CmpOp0);
2237
2238 SDValue Res = // Res = 0 or -1.
2239 DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(),
2240 DAG.getConstant(M68k::COND_CS, DL, MVT::i8), Cmp);
2241
2242 if (isAllOnesConstant(Op1) != (CondCode == M68k::COND_EQ))
2243 Res = DAG.getNOT(DL, Res, Res.getValueType());
2244
2245 if (!isNullConstant(Op2))
2246 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
2247 return Res;
2248 }
2249 }
2250
2251 // Look past (and (setcc_carry (cmp ...)), 1).
2252 if (Cond.getOpcode() == ISD::AND &&
2253 Cond.getOperand(0).getOpcode() == M68kISD::SETCC_CARRY &&
2254 isOneConstant(Cond.getOperand(1)))
2255 Cond = Cond.getOperand(0);
2256
2257 // If condition flag is set by a M68kISD::CMP, then use it as the condition
2258 // setting operand in place of the M68kISD::SETCC.
2259 unsigned CondOpcode = Cond.getOpcode();
2260 if (CondOpcode == M68kISD::SETCC || CondOpcode == M68kISD::SETCC_CARRY) {
2261 CC = Cond.getOperand(0);
2262
2263 SDValue Cmp = Cond.getOperand(1);
2264 unsigned Opc = Cmp.getOpcode();
2265
2266 bool IllegalFPCMov = false;
2267
2268 if ((isM68kLogicalCmp(Cmp) && !IllegalFPCMov) || Opc == M68kISD::BTST) {
2269 Cond = Cmp;
2270 addTest = false;
2271 }
2272 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
2273 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
2274 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) {
2275 SDValue LHS = Cond.getOperand(0);
2276 SDValue RHS = Cond.getOperand(1);
2277 unsigned MxOpcode;
2278 unsigned MxCond;
2279 SDVTList VTs;
2280 switch (CondOpcode) {
2281 case ISD::UADDO:
2282 MxOpcode = M68kISD::ADD;
2283 MxCond = M68k::COND_CS;
2284 break;
2285 case ISD::SADDO:
2286 MxOpcode = M68kISD::ADD;
2287 MxCond = M68k::COND_VS;
2288 break;
2289 case ISD::USUBO:
2290 MxOpcode = M68kISD::SUB;
2291 MxCond = M68k::COND_CS;
2292 break;
2293 case ISD::SSUBO:
2294 MxOpcode = M68kISD::SUB;
2295 MxCond = M68k::COND_VS;
2296 break;
2297 case ISD::UMULO:
2298 MxOpcode = M68kISD::UMUL;
2299 MxCond = M68k::COND_VS;
2300 break;
2301 case ISD::SMULO:
2302 MxOpcode = M68kISD::SMUL;
2303 MxCond = M68k::COND_VS;
2304 break;
2305 default:
2306 llvm_unreachable("unexpected overflowing operator");
2307 }
2308 if (CondOpcode == ISD::UMULO)
2309 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), MVT::i32);
2310 else
2311 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
2312
2313 SDValue MxOp = DAG.getNode(MxOpcode, DL, VTs, LHS, RHS);
2314
2315 if (CondOpcode == ISD::UMULO)
2316 Cond = MxOp.getValue(2);
2317 else
2318 Cond = MxOp.getValue(1);
2319
2320 CC = DAG.getConstant(MxCond, DL, MVT::i8);
2321 addTest = false;
2322 }
2323
2324 if (addTest) {
2325 // Look past the truncate if the high bits are known zero.
2327 Cond = Cond.getOperand(0);
2328
2329 // We know the result of AND is compared against zero. Try to match
2330 // it to BT.
2331 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
2332 if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) {
2333 CC = NewSetCC.getOperand(0);
2334 Cond = NewSetCC.getOperand(1);
2335 addTest = false;
2336 }
2337 }
2338 }
2339
2340 if (addTest) {
2341 CC = DAG.getConstant(M68k::COND_NE, DL, MVT::i8);
2342 Cond = EmitTest(Cond, M68k::COND_NE, DL, DAG);
2343 }
2344
2345 // a < b ? -1 : 0 -> RES = ~setcc_carry
2346 // a < b ? 0 : -1 -> RES = setcc_carry
2347 // a >= b ? -1 : 0 -> RES = setcc_carry
2348 // a >= b ? 0 : -1 -> RES = ~setcc_carry
2349 if (Cond.getOpcode() == M68kISD::SUB) {
2350 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
2351
2352 if ((CondCode == M68k::COND_CC || CondCode == M68k::COND_CS) &&
2353 (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
2354 (isNullConstant(Op1) || isNullConstant(Op2))) {
2355 SDValue Res =
2356 DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(),
2357 DAG.getConstant(M68k::COND_CS, DL, MVT::i8), Cond);
2358 if (isAllOnesConstant(Op1) != (CondCode == M68k::COND_CS))
2359 return DAG.getNOT(DL, Res, Res.getValueType());
2360 return Res;
2361 }
2362 }
2363
2364 // M68k doesn't have an i8 cmov. If both operands are the result of a
2365 // truncate widen the cmov and push the truncate through. This avoids
2366 // introducing a new branch during isel and doesn't add any extensions.
2367 if (Op.getValueType() == MVT::i8 && Op1.getOpcode() == ISD::TRUNCATE &&
2368 Op2.getOpcode() == ISD::TRUNCATE) {
2369 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
2370 if (T1.getValueType() == T2.getValueType() &&
2371 // Block CopyFromReg so partial register stalls are avoided.
2372 T1.getOpcode() != ISD::CopyFromReg &&
2373 T2.getOpcode() != ISD::CopyFromReg) {
2374 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
2375 SDValue Cmov = DAG.getNode(M68kISD::CMOV, DL, VTs, T2, T1, CC, Cond);
2376 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
2377 }
2378 }
2379
2380 // M68kISD::CMOV means set the result (which is operand 1) to the RHS if
2381 // condition is true.
2382 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
2383 SDValue Ops[] = {Op2, Op1, CC, Cond};
2384 return DAG.getNode(M68kISD::CMOV, DL, VTs, Ops);
2385}
2386
2387/// Return true if node is an ISD::AND or ISD::OR of two M68k::SETcc nodes
2388/// each of which has no other use apart from the AND / OR.
2389static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
2390 Opc = Op.getOpcode();
2391 if (Opc != ISD::OR && Opc != ISD::AND)
2392 return false;
2393 return (M68k::IsSETCC(Op.getOperand(0).getOpcode()) &&
2394 Op.getOperand(0).hasOneUse() &&
2395 M68k::IsSETCC(Op.getOperand(1).getOpcode()) &&
2396 Op.getOperand(1).hasOneUse());
2397}
2398
2399/// Return true if node is an ISD::XOR of a M68kISD::SETCC and 1 and that the
2400/// SETCC node has a single use.
2402 if (Op.getOpcode() != ISD::XOR)
2403 return false;
2404 if (isOneConstant(Op.getOperand(1)))
2405 return Op.getOperand(0).getOpcode() == M68kISD::SETCC &&
2406 Op.getOperand(0).hasOneUse();
2407 return false;
2408}
2409
2410SDValue M68kTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
2411 bool AddTest = true;
2412 SDValue Chain = Op.getOperand(0);
2413 SDValue Cond = Op.getOperand(1);
2414 SDValue Dest = Op.getOperand(2);
2415 SDLoc DL(Op);
2416 SDValue CC;
2417 bool Inverted = false;
2418
2419 if (Cond.getOpcode() == ISD::SETCC) {
2420 // Check for setcc([su]{add,sub}o == 0).
2421 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
2422 isNullConstant(Cond.getOperand(1)) &&
2423 Cond.getOperand(0).getResNo() == 1 &&
2424 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
2425 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
2426 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
2427 Cond.getOperand(0).getOpcode() == ISD::USUBO)) {
2428 Inverted = true;
2429 Cond = Cond.getOperand(0);
2430 } else {
2431 if (SDValue NewCond = LowerSETCC(Cond, DAG))
2432 Cond = NewCond;
2433 }
2434 }
2435
2436 // Look pass (and (setcc_carry (cmp ...)), 1).
2437 if (Cond.getOpcode() == ISD::AND &&
2438 Cond.getOperand(0).getOpcode() == M68kISD::SETCC_CARRY &&
2439 isOneConstant(Cond.getOperand(1)))
2440 Cond = Cond.getOperand(0);
2441
2442 // If condition flag is set by a M68kISD::CMP, then use it as the condition
2443 // setting operand in place of the M68kISD::SETCC.
2444 unsigned CondOpcode = Cond.getOpcode();
2445 if (CondOpcode == M68kISD::SETCC || CondOpcode == M68kISD::SETCC_CARRY) {
2446 CC = Cond.getOperand(0);
2447
2448 SDValue Cmp = Cond.getOperand(1);
2449 unsigned Opc = Cmp.getOpcode();
2450
2451 if (isM68kLogicalCmp(Cmp) || Opc == M68kISD::BTST) {
2452 Cond = Cmp;
2453 AddTest = false;
2454 } else {
2455 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
2456 default:
2457 break;
2458 case M68k::COND_VS:
2459 case M68k::COND_CS:
2460 // These can only come from an arithmetic instruction with overflow,
2461 // e.g. SADDO, UADDO.
2462 Cond = Cond.getNode()->getOperand(1);
2463 AddTest = false;
2464 break;
2465 }
2466 }
2467 }
2468 CondOpcode = Cond.getOpcode();
2469 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
2470 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO) {
2471 SDValue LHS = Cond.getOperand(0);
2472 SDValue RHS = Cond.getOperand(1);
2473 unsigned MxOpcode;
2474 unsigned MxCond;
2475 SDVTList VTs;
2476 // Keep this in sync with LowerXALUO, otherwise we might create redundant
2477 // instructions that can't be removed afterwards (i.e. M68kISD::ADD and
2478 // M68kISD::INC).
2479 switch (CondOpcode) {
2480 case ISD::UADDO:
2481 MxOpcode = M68kISD::ADD;
2482 MxCond = M68k::COND_CS;
2483 break;
2484 case ISD::SADDO:
2485 MxOpcode = M68kISD::ADD;
2486 MxCond = M68k::COND_VS;
2487 break;
2488 case ISD::USUBO:
2489 MxOpcode = M68kISD::SUB;
2490 MxCond = M68k::COND_CS;
2491 break;
2492 case ISD::SSUBO:
2493 MxOpcode = M68kISD::SUB;
2494 MxCond = M68k::COND_VS;
2495 break;
2496 case ISD::UMULO:
2497 MxOpcode = M68kISD::UMUL;
2498 MxCond = M68k::COND_VS;
2499 break;
2500 case ISD::SMULO:
2501 MxOpcode = M68kISD::SMUL;
2502 MxCond = M68k::COND_VS;
2503 break;
2504 default:
2505 llvm_unreachable("unexpected overflowing operator");
2506 }
2507
2508 if (Inverted)
2510
2511 if (CondOpcode == ISD::UMULO)
2512 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), MVT::i8);
2513 else
2514 VTs = DAG.getVTList(LHS.getValueType(), MVT::i8);
2515
2516 SDValue MxOp = DAG.getNode(MxOpcode, DL, VTs, LHS, RHS);
2517
2518 if (CondOpcode == ISD::UMULO)
2519 Cond = MxOp.getValue(2);
2520 else
2521 Cond = MxOp.getValue(1);
2522
2523 CC = DAG.getConstant(MxCond, DL, MVT::i8);
2524 AddTest = false;
2525 } else {
2526 unsigned CondOpc;
2527 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
2528 SDValue Cmp = Cond.getOperand(0).getOperand(1);
2529 if (CondOpc == ISD::OR) {
2530 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
2531 // two branches instead of an explicit OR instruction with a
2532 // separate test.
2533 if (Cmp == Cond.getOperand(1).getOperand(1) && isM68kLogicalCmp(Cmp)) {
2534 CC = Cond.getOperand(0).getOperand(0);
2535 Chain = DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain,
2536 Dest, CC, Cmp);
2537 CC = Cond.getOperand(1).getOperand(0);
2538 Cond = Cmp;
2539 AddTest = false;
2540 }
2541 } else { // ISD::AND
2542 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
2543 // two branches instead of an explicit AND instruction with a
2544 // separate test. However, we only do this if this block doesn't
2545 // have a fall-through edge, because this requires an explicit
2546 // jmp when the condition is false.
2547 if (Cmp == Cond.getOperand(1).getOperand(1) && isM68kLogicalCmp(Cmp) &&
2548 Op.getNode()->hasOneUse()) {
2549 M68k::CondCode CCode =
2550 (M68k::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
2551 CCode = M68k::GetOppositeBranchCondition(CCode);
2552 CC = DAG.getConstant(CCode, DL, MVT::i8);
2553 SDNode *User = *Op.getNode()->use_begin();
2554 // Look for an unconditional branch following this conditional branch.
2555 // We need this because we need to reverse the successors in order
2556 // to implement FCMP_OEQ.
2557 if (User->getOpcode() == ISD::BR) {
2558 SDValue FalseBB = User->getOperand(1);
2559 SDNode *NewBR =
2560 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
2561 assert(NewBR == User);
2562 (void)NewBR;
2563 Dest = FalseBB;
2564
2565 Chain = DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain,
2566 Dest, CC, Cmp);
2567 M68k::CondCode CCode =
2568 (M68k::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
2569 CCode = M68k::GetOppositeBranchCondition(CCode);
2570 CC = DAG.getConstant(CCode, DL, MVT::i8);
2571 Cond = Cmp;
2572 AddTest = false;
2573 }
2574 }
2575 }
2576 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
2577 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
2578 // It should be transformed during dag combiner except when the condition
2579 // is set by a arithmetics with overflow node.
2580 M68k::CondCode CCode =
2581 (M68k::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
2582 CCode = M68k::GetOppositeBranchCondition(CCode);
2583 CC = DAG.getConstant(CCode, DL, MVT::i8);
2584 Cond = Cond.getOperand(0).getOperand(1);
2585 AddTest = false;
2586 }
2587 }
2588
2589 if (AddTest) {
2590 // Look pass the truncate if the high bits are known zero.
2592 Cond = Cond.getOperand(0);
2593
2594 // We know the result is compared against zero. Try to match it to BT.
2595 if (Cond.hasOneUse()) {
2596 if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) {
2597 CC = NewSetCC.getOperand(0);
2598 Cond = NewSetCC.getOperand(1);
2599 AddTest = false;
2600 }
2601 }
2602 }
2603
2604 if (AddTest) {
2605 M68k::CondCode MxCond = Inverted ? M68k::COND_EQ : M68k::COND_NE;
2606 CC = DAG.getConstant(MxCond, DL, MVT::i8);
2607 Cond = EmitTest(Cond, MxCond, DL, DAG);
2608 }
2609 return DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain, Dest, CC,
2610 Cond);
2611}
2612
2613SDValue M68kTargetLowering::LowerADDC_ADDE_SUBC_SUBE(SDValue Op,
2614 SelectionDAG &DAG) const {
2615 MVT VT = Op.getNode()->getSimpleValueType(0);
2616
2617 // Let legalize expand this if it isn't a legal type yet.
2618 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
2619 return SDValue();
2620
2621 SDVTList VTs = DAG.getVTList(VT, MVT::i8);
2622
2623 unsigned Opc;
2624 bool ExtraOp = false;
2625 switch (Op.getOpcode()) {
2626 default:
2627 llvm_unreachable("Invalid code");
2628 case ISD::ADDC:
2629 Opc = M68kISD::ADD;
2630 break;
2631 case ISD::ADDE:
2632 Opc = M68kISD::ADDX;
2633 ExtraOp = true;
2634 break;
2635 case ISD::SUBC:
2636 Opc = M68kISD::SUB;
2637 break;
2638 case ISD::SUBE:
2639 Opc = M68kISD::SUBX;
2640 ExtraOp = true;
2641 break;
2642 }
2643
2644 if (!ExtraOp)
2645 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
2646 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
2647 Op.getOperand(2));
2648}
2649
2650// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2651// their target countpart wrapped in the M68kISD::Wrapper node. Suppose N is
2652// one of the above mentioned nodes. It has to be wrapped because otherwise
2653// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2654// be used to form addressing mode. These wrapped nodes will be selected
2655// into MOV32ri.
2656SDValue M68kTargetLowering::LowerConstantPool(SDValue Op,
2657 SelectionDAG &DAG) const {
2658 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2659
2660 // In PIC mode (unless we're in PCRel PIC mode) we add an offset to the
2661 // global base reg.
2662 unsigned char OpFlag = Subtarget.classifyLocalReference(nullptr);
2663
2664 unsigned WrapperKind = M68kISD::Wrapper;
2665 if (M68kII::isPCRelGlobalReference(OpFlag)) {
2666 WrapperKind = M68kISD::WrapperPC;
2667 }
2668
2669 MVT PtrVT = getPointerTy(DAG.getDataLayout());
2671 CP->getConstVal(), PtrVT, CP->getAlign(), CP->getOffset(), OpFlag);
2672
2673 SDLoc DL(CP);
2674 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
2675
2676 // With PIC, the address is actually $g + Offset.
2678 Result = DAG.getNode(ISD::ADD, DL, PtrVT,
2679 DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(), PtrVT),
2680 Result);
2681 }
2682
2683 return Result;
2684}
2685
2686SDValue M68kTargetLowering::LowerExternalSymbol(SDValue Op,
2687 SelectionDAG &DAG) const {
2688 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
2689
2690 // In PIC mode (unless we're in PCRel PIC mode) we add an offset to the
2691 // global base reg.
2693 unsigned char OpFlag = Subtarget.classifyExternalReference(*Mod);
2694
2695 unsigned WrapperKind = M68kISD::Wrapper;
2696 if (M68kII::isPCRelGlobalReference(OpFlag)) {
2697 WrapperKind = M68kISD::WrapperPC;
2698 }
2699
2700 auto PtrVT = getPointerTy(DAG.getDataLayout());
2701 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
2702
2703 SDLoc DL(Op);
2704 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
2705
2706 // With PIC, the address is actually $g + Offset.
2708 Result = DAG.getNode(ISD::ADD, DL, PtrVT,
2709 DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(), PtrVT),
2710 Result);
2711 }
2712
2713 // For symbols that require a load from a stub to get the address, emit the
2714 // load.
2715 if (M68kII::isGlobalStubReference(OpFlag)) {
2716 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2718 }
2719
2720 return Result;
2721}
2722
2723SDValue M68kTargetLowering::LowerBlockAddress(SDValue Op,
2724 SelectionDAG &DAG) const {
2725 unsigned char OpFlags = Subtarget.classifyBlockAddressReference();
2726 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2727 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
2728 SDLoc DL(Op);
2729 auto PtrVT = getPointerTy(DAG.getDataLayout());
2730
2731 // Create the TargetBlockAddressAddress node.
2732 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
2733
2734 if (M68kII::isPCRelBlockReference(OpFlags)) {
2735 Result = DAG.getNode(M68kISD::WrapperPC, DL, PtrVT, Result);
2736 } else {
2737 Result = DAG.getNode(M68kISD::Wrapper, DL, PtrVT, Result);
2738 }
2739
2740 // With PIC, the address is actually $g + Offset.
2741 if (M68kII::isGlobalRelativeToPICBase(OpFlags)) {
2742 Result =
2743 DAG.getNode(ISD::ADD, DL, PtrVT,
2744 DAG.getNode(M68kISD::GLOBAL_BASE_REG, DL, PtrVT), Result);
2745 }
2746
2747 return Result;
2748}
2749
2750SDValue M68kTargetLowering::LowerGlobalAddress(const GlobalValue *GV,
2751 const SDLoc &DL, int64_t Offset,
2752 SelectionDAG &DAG) const {
2753 unsigned char OpFlags = Subtarget.classifyGlobalReference(GV);
2754 auto PtrVT = getPointerTy(DAG.getDataLayout());
2755
2756 // Create the TargetGlobalAddress node, folding in the constant
2757 // offset if it is legal.
2759 if (M68kII::isDirectGlobalReference(OpFlags)) {
2760 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Offset);
2761 Offset = 0;
2762 } else {
2763 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2764 }
2765
2766 if (M68kII::isPCRelGlobalReference(OpFlags))
2767 Result = DAG.getNode(M68kISD::WrapperPC, DL, PtrVT, Result);
2768 else
2769 Result = DAG.getNode(M68kISD::Wrapper, DL, PtrVT, Result);
2770
2771 // With PIC, the address is actually $g + Offset.
2772 if (M68kII::isGlobalRelativeToPICBase(OpFlags)) {
2773 Result =
2774 DAG.getNode(ISD::ADD, DL, PtrVT,
2775 DAG.getNode(M68kISD::GLOBAL_BASE_REG, DL, PtrVT), Result);
2776 }
2777
2778 // For globals that require a load from a stub to get the address, emit the
2779 // load.
2780 if (M68kII::isGlobalStubReference(OpFlags)) {
2781 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2783 }
2784
2785 // If there was a non-zero offset that we didn't fold, create an explicit
2786 // addition for it.
2787 if (Offset != 0) {
2788 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
2789 DAG.getConstant(Offset, DL, PtrVT));
2790 }
2791
2792 return Result;
2793}
2794
2795SDValue M68kTargetLowering::LowerGlobalAddress(SDValue Op,
2796 SelectionDAG &DAG) const {
2797 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2798 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
2799 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
2800}
2801
2802//===----------------------------------------------------------------------===//
2803// Custom Lower Jump Table
2804//===----------------------------------------------------------------------===//
2805
2806SDValue M68kTargetLowering::LowerJumpTable(SDValue Op,
2807 SelectionDAG &DAG) const {
2808 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2809
2810 // In PIC mode (unless we're in PCRel PIC mode) we add an offset to the
2811 // global base reg.
2812 unsigned char OpFlag = Subtarget.classifyLocalReference(nullptr);
2813
2814 unsigned WrapperKind = M68kISD::Wrapper;
2815 if (M68kII::isPCRelGlobalReference(OpFlag)) {
2816 WrapperKind = M68kISD::WrapperPC;
2817 }
2818
2819 auto PtrVT = getPointerTy(DAG.getDataLayout());
2820 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
2821 SDLoc DL(JT);
2822 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
2823
2824 // With PIC, the address is actually $g + Offset.
2826 Result = DAG.getNode(ISD::ADD, DL, PtrVT,
2827 DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(), PtrVT),
2828 Result);
2829 }
2830
2831 return Result;
2832}
2833
2835 return Subtarget.getJumpTableEncoding();
2836}
2837
2839 const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB,
2840 unsigned uid, MCContext &Ctx) const {
2842 Ctx);
2843}
2844
2846 SelectionDAG &DAG) const {
2850
2851 // MachineJumpTableInfo::EK_LabelDifference32 entry
2852 return Table;
2853}
2854
2855// NOTE This only used for MachineJumpTableInfo::EK_LabelDifference32 entries
2857 const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const {
2858 return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
2859}
2860
2863 if (Constraint.size() > 0) {
2864 switch (Constraint[0]) {
2865 case 'a':
2866 case 'd':
2867 return C_RegisterClass;
2868 case 'I':
2869 case 'J':
2870 case 'K':
2871 case 'L':
2872 case 'M':
2873 case 'N':
2874 case 'O':
2875 case 'P':
2876 return C_Immediate;
2877 case 'C':
2878 if (Constraint.size() == 2)
2879 switch (Constraint[1]) {
2880 case '0':
2881 case 'i':
2882 case 'j':
2883 return C_Immediate;
2884 default:
2885 break;
2886 }
2887 break;
2888 case 'Q':
2889 case 'U':
2890 return C_Memory;
2891 default:
2892 break;
2893 }
2894 }
2895
2896 return TargetLowering::getConstraintType(Constraint);
2897}
2898
2900 std::string &Constraint,
2901 std::vector<SDValue> &Ops,
2902 SelectionDAG &DAG) const {
2903 SDValue Result;
2904
2905 if (Constraint.size() == 1) {
2906 // Constant constraints
2907 switch (Constraint[0]) {
2908 case 'I':
2909 case 'J':
2910 case 'K':
2911 case 'L':
2912 case 'M':
2913 case 'N':
2914 case 'O':
2915 case 'P': {
2916 auto *C = dyn_cast<ConstantSDNode>(Op);
2917 if (!C)
2918 return;
2919
2920 int64_t Val = C->getSExtValue();
2921 switch (Constraint[0]) {
2922 case 'I': // constant integer in the range [1,8]
2923 if (Val > 0 && Val <= 8)
2924 break;
2925 return;
2926 case 'J': // constant signed 16-bit integer
2927 if (isInt<16>(Val))
2928 break;
2929 return;
2930 case 'K': // constant that is NOT in the range of [-0x80, 0x80)
2931 if (Val < -0x80 || Val >= 0x80)
2932 break;
2933 return;
2934 case 'L': // constant integer in the range [-8,-1]
2935 if (Val < 0 && Val >= -8)
2936 break;
2937 return;
2938 case 'M': // constant that is NOT in the range of [-0x100, 0x100]
2939 if (Val < -0x100 || Val >= 0x100)
2940 break;
2941 return;
2942 case 'N': // constant integer in the range [24,31]
2943 if (Val >= 24 && Val <= 31)
2944 break;
2945 return;
2946 case 'O': // constant integer 16
2947 if (Val == 16)
2948 break;
2949 return;
2950 case 'P': // constant integer in the range [8,15]
2951 if (Val >= 8 && Val <= 15)
2952 break;
2953 return;
2954 default:
2955 llvm_unreachable("Unhandled constant constraint");
2956 }
2957
2958 Result = DAG.getTargetConstant(Val, SDLoc(Op), Op.getValueType());
2959 break;
2960 }
2961 default:
2962 break;
2963 }
2964 }
2965
2966 if (Constraint.size() == 2) {
2967 switch (Constraint[0]) {
2968 case 'C':
2969 // Constant constraints start with 'C'
2970 switch (Constraint[1]) {
2971 case '0':
2972 case 'i':
2973 case 'j': {
2974 auto *C = dyn_cast<ConstantSDNode>(Op);
2975 if (!C)
2976 break;
2977
2978 int64_t Val = C->getSExtValue();
2979 switch (Constraint[1]) {
2980 case '0': // constant integer 0
2981 if (!Val)
2982 break;
2983 return;
2984 case 'i': // constant integer
2985 break;
2986 case 'j': // integer constant that doesn't fit in 16 bits
2987 if (!isInt<16>(C->getSExtValue()))
2988 break;
2989 return;
2990 default:
2991 llvm_unreachable("Unhandled constant constraint");
2992 }
2993
2994 Result = DAG.getTargetConstant(Val, SDLoc(Op), Op.getValueType());
2995 break;
2996 }
2997 default:
2998 break;
2999 }
3000 break;
3001 default:
3002 break;
3003 }
3004 }
3005
3006 if (Result.getNode()) {
3007 Ops.push_back(Result);
3008 return;
3009 }
3010
3011 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3012}
3013
3014std::pair<unsigned, const TargetRegisterClass *>
3016 StringRef Constraint,
3017 MVT VT) const {
3018 if (Constraint.size() == 1) {
3019 switch (Constraint[0]) {
3020 case 'r':
3021 case 'd':
3022 switch (VT.SimpleTy) {
3023 case MVT::i8:
3024 return std::make_pair(0U, &M68k::DR8RegClass);
3025 case MVT::i16:
3026 return std::make_pair(0U, &M68k::DR16RegClass);
3027 case MVT::i32:
3028 return std::make_pair(0U, &M68k::DR32RegClass);
3029 default:
3030 break;
3031 }
3032 break;
3033 case 'a':
3034 switch (VT.SimpleTy) {
3035 case MVT::i16:
3036 return std::make_pair(0U, &M68k::AR16RegClass);
3037 case MVT::i32:
3038 return std::make_pair(0U, &M68k::AR32RegClass);
3039 default:
3040 break;
3041 }
3042 break;
3043 default:
3044 break;
3045 }
3046 }
3047
3048 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3049}
3050
3051/// Determines whether the callee is required to pop its own arguments.
3052/// Callee pop is necessary to support tail calls.
3053bool M68k::isCalleePop(CallingConv::ID CallingConv, bool IsVarArg,
3054 bool GuaranteeTCO) {
3055 return false;
3056}
3057
3058// Return true if it is OK for this CMOV pseudo-opcode to be cascaded
3059// together with other CMOV pseudo-opcodes into a single basic-block with
3060// conditional jump around it.
3062 switch (MI.getOpcode()) {
3063 case M68k::CMOV8d:
3064 case M68k::CMOV16d:
3065 case M68k::CMOV32r:
3066 return true;
3067
3068 default:
3069 return false;
3070 }
3071}
3072
3073// The CCR operand of SelectItr might be missing a kill marker
3074// because there were multiple uses of CCR, and ISel didn't know
3075// which to mark. Figure out whether SelectItr should have had a
3076// kill marker, and set it if it should. Returns the correct kill
3077// marker value.
3080 const TargetRegisterInfo *TRI) {
3081 // Scan forward through BB for a use/def of CCR.
3082 MachineBasicBlock::iterator miI(std::next(SelectItr));
3083 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
3084 const MachineInstr &mi = *miI;
3085 if (mi.readsRegister(M68k::CCR))
3086 return false;
3087 if (mi.definesRegister(M68k::CCR))
3088 break; // Should have kill-flag - update below.
3089 }
3090
3091 // If we hit the end of the block, check whether CCR is live into a
3092 // successor.
3093 if (miI == BB->end())
3094 for (const auto *SBB : BB->successors())
3095 if (SBB->isLiveIn(M68k::CCR))
3096 return false;
3097
3098 // We found a def, or hit the end of the basic block and CCR wasn't live
3099 // out. SelectMI should have a kill flag on CCR.
3100 SelectItr->addRegisterKilled(M68k::CCR, TRI);
3101 return true;
3102}
3103
3105M68kTargetLowering::EmitLoweredSelect(MachineInstr &MI,
3106 MachineBasicBlock *MBB) const {
3107 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3108 DebugLoc DL = MI.getDebugLoc();
3109
3110 // To "insert" a SELECT_CC instruction, we actually have to insert the
3111 // diamond control-flow pattern. The incoming instruction knows the
3112 // destination vreg to set, the condition code register to branch on, the
3113 // true/false values to select between, and a branch opcode to use.
3114 const BasicBlock *BB = MBB->getBasicBlock();
3116
3117 // ThisMBB:
3118 // ...
3119 // TrueVal = ...
3120 // cmp ccX, r1, r2
3121 // bcc Copy1MBB
3122 // fallthrough --> Copy0MBB
3123 MachineBasicBlock *ThisMBB = MBB;
3125
3126 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
3127 // as described above, by inserting a MBB, and then making a PHI at the join
3128 // point to select the true and false operands of the CMOV in the PHI.
3129 //
3130 // The code also handles two different cases of multiple CMOV opcodes
3131 // in a row.
3132 //
3133 // Case 1:
3134 // In this case, there are multiple CMOVs in a row, all which are based on
3135 // the same condition setting (or the exact opposite condition setting).
3136 // In this case we can lower all the CMOVs using a single inserted MBB, and
3137 // then make a number of PHIs at the join point to model the CMOVs. The only
3138 // trickiness here, is that in a case like:
3139 //
3140 // t2 = CMOV cond1 t1, f1
3141 // t3 = CMOV cond1 t2, f2
3142 //
3143 // when rewriting this into PHIs, we have to perform some renaming on the
3144 // temps since you cannot have a PHI operand refer to a PHI result earlier
3145 // in the same block. The "simple" but wrong lowering would be:
3146 //
3147 // t2 = PHI t1(BB1), f1(BB2)
3148 // t3 = PHI t2(BB1), f2(BB2)
3149 //
3150 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
3151 // renaming is to note that on the path through BB1, t2 is really just a
3152 // copy of t1, and do that renaming, properly generating:
3153 //
3154 // t2 = PHI t1(BB1), f1(BB2)
3155 // t3 = PHI t1(BB1), f2(BB2)
3156 //
3157 // Case 2, we lower cascaded CMOVs such as
3158 //
3159 // (CMOV (CMOV F, T, cc1), T, cc2)
3160 //
3161 // to two successives branches.
3162 MachineInstr *CascadedCMOV = nullptr;
3163 MachineInstr *LastCMOV = &MI;
3164 M68k::CondCode CC = M68k::CondCode(MI.getOperand(3).getImm());
3167 std::next(MachineBasicBlock::iterator(MI));
3168
3169 // Check for case 1, where there are multiple CMOVs with the same condition
3170 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
3171 // number of jumps the most.
3172
3173 if (isCMOVPseudo(MI)) {
3174 // See if we have a string of CMOVS with the same condition.
3175 while (NextMIIt != MBB->end() && isCMOVPseudo(*NextMIIt) &&
3176 (NextMIIt->getOperand(3).getImm() == CC ||
3177 NextMIIt->getOperand(3).getImm() == OppCC)) {
3178 LastCMOV = &*NextMIIt;
3179 ++NextMIIt;
3180 }
3181 }
3182
3183 // This checks for case 2, but only do this if we didn't already find
3184 // case 1, as indicated by LastCMOV == MI.
3185 if (LastCMOV == &MI && NextMIIt != MBB->end() &&
3186 NextMIIt->getOpcode() == MI.getOpcode() &&
3187 NextMIIt->getOperand(2).getReg() == MI.getOperand(2).getReg() &&
3188 NextMIIt->getOperand(1).getReg() == MI.getOperand(0).getReg() &&
3189 NextMIIt->getOperand(1).isKill()) {
3190 CascadedCMOV = &*NextMIIt;
3191 }
3192
3193 MachineBasicBlock *Jcc1MBB = nullptr;
3194
3195 // If we have a cascaded CMOV, we lower it to two successive branches to
3196 // the same block. CCR is used by both, so mark it as live in the second.
3197 if (CascadedCMOV) {
3198 Jcc1MBB = F->CreateMachineBasicBlock(BB);
3199 F->insert(It, Jcc1MBB);
3200 Jcc1MBB->addLiveIn(M68k::CCR);
3201 }
3202
3203 MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(BB);
3204 MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(BB);
3205 F->insert(It, Copy0MBB);
3206 F->insert(It, SinkMBB);
3207
3208 // Set the call frame size on entry to the new basic blocks.
3209 unsigned CallFrameSize = TII->getCallFrameSizeAt(MI);
3210 Copy0MBB->setCallFrameSize(CallFrameSize);
3211 SinkMBB->setCallFrameSize(CallFrameSize);
3212
3213 // If the CCR register isn't dead in the terminator, then claim that it's
3214 // live into the sink and copy blocks.
3215 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3216
3217 MachineInstr *LastCCRSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
3218 if (!LastCCRSUser->killsRegister(M68k::CCR) &&
3219 !checkAndUpdateCCRKill(LastCCRSUser, MBB, TRI)) {
3220 Copy0MBB->addLiveIn(M68k::CCR);
3221 SinkMBB->addLiveIn(M68k::CCR);
3222 }
3223
3224 // Transfer the remainder of MBB and its successor edges to SinkMBB.
3225 SinkMBB->splice(SinkMBB->begin(), MBB,
3226 std::next(MachineBasicBlock::iterator(LastCMOV)), MBB->end());
3228
3229 // Add the true and fallthrough blocks as its successors.
3230 if (CascadedCMOV) {
3231 // The fallthrough block may be Jcc1MBB, if we have a cascaded CMOV.
3232 MBB->addSuccessor(Jcc1MBB);
3233
3234 // In that case, Jcc1MBB will itself fallthrough the Copy0MBB, and
3235 // jump to the SinkMBB.
3236 Jcc1MBB->addSuccessor(Copy0MBB);
3237 Jcc1MBB->addSuccessor(SinkMBB);
3238 } else {
3239 MBB->addSuccessor(Copy0MBB);
3240 }
3241
3242 // The true block target of the first (or only) branch is always SinkMBB.
3243 MBB->addSuccessor(SinkMBB);
3244
3245 // Create the conditional branch instruction.
3246 unsigned Opc = M68k::GetCondBranchFromCond(CC);
3247 BuildMI(MBB, DL, TII->get(Opc)).addMBB(SinkMBB);
3248
3249 if (CascadedCMOV) {
3250 unsigned Opc2 = M68k::GetCondBranchFromCond(
3251 (M68k::CondCode)CascadedCMOV->getOperand(3).getImm());
3252 BuildMI(Jcc1MBB, DL, TII->get(Opc2)).addMBB(SinkMBB);
3253 }
3254
3255 // Copy0MBB:
3256 // %FalseValue = ...
3257 // # fallthrough to SinkMBB
3258 Copy0MBB->addSuccessor(SinkMBB);
3259
3260 // SinkMBB:
3261 // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ]
3262 // ...
3265 std::next(MachineBasicBlock::iterator(LastCMOV));
3266 MachineBasicBlock::iterator SinkInsertionPoint = SinkMBB->begin();
3269
3270 // As we are creating the PHIs, we have to be careful if there is more than
3271 // one. Later CMOVs may reference the results of earlier CMOVs, but later
3272 // PHIs have to reference the individual true/false inputs from earlier PHIs.
3273 // That also means that PHI construction must work forward from earlier to
3274 // later, and that the code must maintain a mapping from earlier PHI's
3275 // destination registers, and the registers that went into the PHI.
3276
3277 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
3278 Register DestReg = MIIt->getOperand(0).getReg();
3279 Register Op1Reg = MIIt->getOperand(1).getReg();
3280 Register Op2Reg = MIIt->getOperand(2).getReg();
3281
3282 // If this CMOV we are generating is the opposite condition from
3283 // the jump we generated, then we have to swap the operands for the
3284 // PHI that is going to be generated.
3285 if (MIIt->getOperand(3).getImm() == OppCC)
3286 std::swap(Op1Reg, Op2Reg);
3287
3288 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
3289 Op1Reg = RegRewriteTable[Op1Reg].first;
3290
3291 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
3292 Op2Reg = RegRewriteTable[Op2Reg].second;
3293
3294 MIB =
3295 BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(M68k::PHI), DestReg)
3296 .addReg(Op1Reg)
3297 .addMBB(Copy0MBB)
3298 .addReg(Op2Reg)
3299 .addMBB(ThisMBB);
3300
3301 // Add this PHI to the rewrite table.
3302 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
3303 }
3304
3305 // If we have a cascaded CMOV, the second Jcc provides the same incoming
3306 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
3307 if (CascadedCMOV) {
3308 MIB.addReg(MI.getOperand(2).getReg()).addMBB(Jcc1MBB);
3309 // Copy the PHI result to the register defined by the second CMOV.
3310 BuildMI(*SinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
3311 DL, TII->get(TargetOpcode::COPY),
3312 CascadedCMOV->getOperand(0).getReg())
3313 .addReg(MI.getOperand(0).getReg());
3314 CascadedCMOV->eraseFromParent();
3315 }
3316
3317 // Now remove the CMOV(s).
3318 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd;)
3319 (MIIt++)->eraseFromParent();
3320
3321 return SinkMBB;
3322}
3323
3325M68kTargetLowering::EmitLoweredSegAlloca(MachineInstr &MI,
3326 MachineBasicBlock *BB) const {
3327 llvm_unreachable("Cannot lower Segmented Stack Alloca with stack-split on");
3328}
3329
3332 MachineBasicBlock *BB) const {
3333 switch (MI.getOpcode()) {
3334 default:
3335 llvm_unreachable("Unexpected instr type to insert");
3336 case M68k::CMOV8d:
3337 case M68k::CMOV16d:
3338 case M68k::CMOV32r:
3339 return EmitLoweredSelect(MI, BB);
3340 case M68k::SALLOCA:
3341 return EmitLoweredSegAlloca(MI, BB);
3342 }
3343}
3344
3345SDValue M68kTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3347 auto PtrVT = getPointerTy(MF.getDataLayout());
3349
3350 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3351 SDLoc DL(Op);
3352
3353 // vastart just stores the address of the VarArgsFrameIndex slot into the
3354 // memory location argument.
3355 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3356 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3357 MachinePointerInfo(SV));
3358}
3359
3360SDValue M68kTargetLowering::LowerATOMICFENCE(SDValue Op,
3361 SelectionDAG &DAG) const {
3362 // Lower to a memory barrier created from inline asm.
3363 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3364 LLVMContext &Ctx = *DAG.getContext();
3365
3366 const unsigned Flags = InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore |
3368 const SDValue AsmOperands[4] = {
3369 Op.getOperand(0), // Input chain
3371 "", TLI.getProgramPointerTy(
3372 DAG.getDataLayout())), // Empty inline asm string
3373 DAG.getMDNode(MDNode::get(Ctx, {})), // (empty) srcloc
3374 DAG.getTargetConstant(Flags, SDLoc(Op),
3375 TLI.getPointerTy(DAG.getDataLayout())), // Flags
3376 };
3377
3378 return DAG.getNode(ISD::INLINEASM, SDLoc(Op),
3379 DAG.getVTList(MVT::Other, MVT::Glue), AsmOperands);
3380}
3381
3382// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
3383// Calls to _alloca are needed to probe the stack when allocating more than 4k
3384// bytes in one go. Touching the stack at 4K increments is necessary to ensure
3385// that the guard pages used by the OS virtual memory manager are allocated in
3386// correct sequence.
3387SDValue M68kTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3388 SelectionDAG &DAG) const {
3390 bool SplitStack = MF.shouldSplitStack();
3391
3392 SDLoc DL(Op);
3393
3394 // Get the inputs.
3395 SDNode *Node = Op.getNode();
3396 SDValue Chain = Op.getOperand(0);
3397 SDValue Size = Op.getOperand(1);
3398 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
3399 EVT VT = Node->getValueType(0);
3400
3401 // Chain the dynamic stack allocation so that it doesn't modify the stack
3402 // pointer when other instructions are using the stack.
3403 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
3404
3406 if (SplitStack) {
3407 auto &MRI = MF.getRegInfo();
3408 auto SPTy = getPointerTy(DAG.getDataLayout());
3409 auto *ARClass = getRegClassFor(SPTy);
3410 Register Vreg = MRI.createVirtualRegister(ARClass);
3411 Chain = DAG.getCopyToReg(Chain, DL, Vreg, Size);
3412 Result = DAG.getNode(M68kISD::SEG_ALLOCA, DL, SPTy, Chain,
3413 DAG.getRegister(Vreg, SPTy));
3414 } else {
3415 auto &TLI = DAG.getTargetLoweringInfo();
3417 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
3418 " not tell us which reg is the stack pointer!");
3419
3420 SDValue SP = DAG.getCopyFromReg(Chain, DL, SPReg, VT);
3421 Chain = SP.getValue(1);
3422 const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
3423 unsigned StackAlign = TFI.getStackAlignment();
3424 Result = DAG.getNode(ISD::SUB, DL, VT, SP, Size); // Value
3425 if (Align > StackAlign)
3426 Result = DAG.getNode(ISD::AND, DL, VT, Result,
3427 DAG.getConstant(-(uint64_t)Align, DL, VT));
3428 Chain = DAG.getCopyToReg(Chain, DL, SPReg, Result); // Output chain
3429 }
3430
3431 Chain = DAG.getCALLSEQ_END(Chain, 0, 0, SDValue(), DL);
3432
3433 SDValue Ops[2] = {Result, Chain};
3434 return DAG.getMergeValues(Ops, DL);
3435}
3436
3437SDValue M68kTargetLowering::LowerShiftLeftParts(SDValue Op,
3438 SelectionDAG &DAG) const {
3439 SDLoc DL(Op);
3440 SDValue Lo = Op.getOperand(0);
3441 SDValue Hi = Op.getOperand(1);
3442 SDValue Shamt = Op.getOperand(2);
3443 EVT VT = Lo.getValueType();
3444
3445 // if Shamt - register size < 0: // Shamt < register size
3446 // Lo = Lo << Shamt
3447 // Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (register size - 1 ^ Shamt))
3448 // else:
3449 // Lo = 0
3450 // Hi = Lo << (Shamt - register size)
3451
3452 SDValue Zero = DAG.getConstant(0, DL, VT);
3453 SDValue One = DAG.getConstant(1, DL, VT);
3454 SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);
3455 SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);
3456 SDValue ShamtMinusRegisterSize =
3457 DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);
3458 SDValue RegisterSizeMinus1Shamt =
3459 DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);
3460
3461 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
3462 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One);
3463 SDValue ShiftRightLo =
3464 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, RegisterSizeMinus1Shamt);
3465 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
3466 SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
3467 SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusRegisterSize);
3468
3469 SDValue CC =
3470 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);
3471
3472 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);
3473 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
3474
3475 return DAG.getMergeValues({Lo, Hi}, DL);
3476}
3477
3478SDValue M68kTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
3479 bool IsSRA) const {
3480 SDLoc DL(Op);
3481 SDValue Lo = Op.getOperand(0);
3482 SDValue Hi = Op.getOperand(1);
3483 SDValue Shamt = Op.getOperand(2);
3484 EVT VT = Lo.getValueType();
3485
3486 // SRA expansion:
3487 // if Shamt - register size < 0: // Shamt < register size
3488 // Lo = (Lo >>u Shamt) | ((Hi << 1) << (register size - 1 ^ Shamt))
3489 // Hi = Hi >>s Shamt
3490 // else:
3491 // Lo = Hi >>s (Shamt - register size);
3492 // Hi = Hi >>s (register size - 1)
3493 //
3494 // SRL expansion:
3495 // if Shamt - register size < 0: // Shamt < register size
3496 // Lo = (Lo >>u Shamt) | ((Hi << 1) << (register size - 1 ^ Shamt))
3497 // Hi = Hi >>u Shamt
3498 // else:
3499 // Lo = Hi >>u (Shamt - register size);
3500 // Hi = 0;
3501
3502 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;
3503
3504 SDValue Zero = DAG.getConstant(0, DL, VT);
3505 SDValue One = DAG.getConstant(1, DL, VT);
3506 SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);
3507 SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);
3508 SDValue ShamtMinusRegisterSize =
3509 DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);
3510 SDValue RegisterSizeMinus1Shamt =
3511 DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);
3512
3513 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
3514 SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);
3515 SDValue ShiftLeftHi =
3516 DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, RegisterSizeMinus1Shamt);
3517 SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);
3518 SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);
3519 SDValue LoFalse =
3520 DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusRegisterSize);
3521 SDValue HiFalse =
3522 IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, RegisterSizeMinus1) : Zero;
3523
3524 SDValue CC =
3525 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);
3526
3527 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
3528 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
3529
3530 return DAG.getMergeValues({Lo, Hi}, DL);
3531}
3532
3533//===----------------------------------------------------------------------===//
3534// DAG Combine
3535//===----------------------------------------------------------------------===//
3536
3538 SelectionDAG &DAG) {
3539 return DAG.getNode(M68kISD::SETCC, dl, MVT::i8,
3540 DAG.getConstant(Cond, dl, MVT::i8), CCR);
3541}
3542// When legalizing carry, we create carries via add X, -1
3543// If that comes from an actual carry, via setcc, we use the
3544// carry directly.
3546 if (CCR.getOpcode() == M68kISD::ADD) {
3547 if (isAllOnesConstant(CCR.getOperand(1))) {
3548 SDValue Carry = CCR.getOperand(0);
3549 while (Carry.getOpcode() == ISD::TRUNCATE ||
3550 Carry.getOpcode() == ISD::ZERO_EXTEND ||
3551 Carry.getOpcode() == ISD::SIGN_EXTEND ||
3552 Carry.getOpcode() == ISD::ANY_EXTEND ||
3553 (Carry.getOpcode() == ISD::AND &&
3554 isOneConstant(Carry.getOperand(1))))
3555 Carry = Carry.getOperand(0);
3556 if (Carry.getOpcode() == M68kISD::SETCC ||
3557 Carry.getOpcode() == M68kISD::SETCC_CARRY) {
3558 if (Carry.getConstantOperandVal(0) == M68k::COND_CS)
3559 return Carry.getOperand(1);
3560 }
3561 }
3562 }
3563
3564 return SDValue();
3565}
3566
3567/// Optimize a CCR definition used according to the condition code \p CC into
3568/// a simpler CCR value, potentially returning a new \p CC and replacing uses
3569/// of chain values.
3571 SelectionDAG &DAG,
3572 const M68kSubtarget &Subtarget) {
3573 if (CC == M68k::COND_CS)
3574 if (SDValue Flags = combineCarryThroughADD(CCR))
3575 return Flags;
3576
3577 return SDValue();
3578}
3579
3580// Optimize RES = M68kISD::SETCC CONDCODE, CCR_INPUT
3582 const M68kSubtarget &Subtarget) {
3583 SDLoc DL(N);
3584 M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(0));
3585 SDValue CCR = N->getOperand(1);
3586
3587 // Try to simplify the CCR and condition code operands.
3588 if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget))
3589 return getSETCC(CC, Flags, DL, DAG);
3590
3591 return SDValue();
3592}
3594 const M68kSubtarget &Subtarget) {
3595 SDLoc DL(N);
3596 M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(2));
3597 SDValue CCR = N->getOperand(3);
3598
3599 // Try to simplify the CCR and condition code operands.
3600 // Make sure to not keep references to operands, as combineSetCCCCR can
3601 // RAUW them under us.
3602 if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget)) {
3603 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
3604 return DAG.getNode(M68kISD::BRCOND, DL, N->getVTList(), N->getOperand(0),
3605 N->getOperand(1), Cond, Flags);
3606 }
3607
3608 return SDValue();
3609}
3610
3612 if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
3613 MVT VT = N->getSimpleValueType(0);
3614 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
3615 return DAG.getNode(M68kISD::SUBX, SDLoc(N), VTs, N->getOperand(0),
3616 N->getOperand(1), Flags);
3617 }
3618
3619 return SDValue();
3620}
3621
3622// Optimize RES, CCR = M68kISD::ADDX LHS, RHS, CCR
3625 if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
3626 MVT VT = N->getSimpleValueType(0);
3627 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
3628 return DAG.getNode(M68kISD::ADDX, SDLoc(N), VTs, N->getOperand(0),
3629 N->getOperand(1), Flags);
3630 }
3631
3632 return SDValue();
3633}
3634
3635SDValue M68kTargetLowering::PerformDAGCombine(SDNode *N,
3636 DAGCombinerInfo &DCI) const {
3637 SelectionDAG &DAG = DCI.DAG;
3638 switch (N->getOpcode()) {
3639 case M68kISD::SUBX:
3640 return combineSUBX(N, DAG);
3641 case M68kISD::ADDX:
3642 return combineADDX(N, DAG, DCI);
3643 case M68kISD::SETCC:
3644 return combineM68kSetCC(N, DAG, Subtarget);
3645 case M68kISD::BRCOND:
3646 return combineM68kBrCond(N, DAG, Subtarget);
3647 }
3648
3649 return SDValue();
3650}
3651
3652//===----------------------------------------------------------------------===//
3653// M68kISD Node Names
3654//===----------------------------------------------------------------------===//
3655const char *M68kTargetLowering::getTargetNodeName(unsigned Opcode) const {
3656 switch (Opcode) {
3657 case M68kISD::CALL:
3658 return "M68kISD::CALL";
3659 case M68kISD::TAIL_CALL:
3660 return "M68kISD::TAIL_CALL";
3661 case M68kISD::RET:
3662 return "M68kISD::RET";
3663 case M68kISD::TC_RETURN:
3664 return "M68kISD::TC_RETURN";
3665 case M68kISD::ADD:
3666 return "M68kISD::ADD";
3667 case M68kISD::SUB:
3668 return "M68kISD::SUB";
3669 case M68kISD::ADDX:
3670 return "M68kISD::ADDX";
3671 case M68kISD::SUBX:
3672 return "M68kISD::SUBX";
3673 case M68kISD::SMUL:
3674 return "M68kISD::SMUL";
3675 case M68kISD::UMUL:
3676 return "M68kISD::UMUL";
3677 case M68kISD::OR:
3678 return "M68kISD::OR";
3679 case M68kISD::XOR:
3680 return "M68kISD::XOR";
3681 case M68kISD::AND:
3682 return "M68kISD::AND";
3683 case M68kISD::CMP:
3684 return "M68kISD::CMP";
3685 case M68kISD::BTST:
3686 return "M68kISD::BTST";
3687 case M68kISD::SELECT:
3688 return "M68kISD::SELECT";
3689 case M68kISD::CMOV:
3690 return "M68kISD::CMOV";
3691 case M68kISD::BRCOND:
3692 return "M68kISD::BRCOND";
3693 case M68kISD::SETCC:
3694 return "M68kISD::SETCC";
3696 return "M68kISD::SETCC_CARRY";
3698 return "M68kISD::GLOBAL_BASE_REG";
3699 case M68kISD::Wrapper:
3700 return "M68kISD::Wrapper";
3701 case M68kISD::WrapperPC:
3702 return "M68kISD::WrapperPC";
3704 return "M68kISD::SEG_ALLOCA";
3705 default:
3706 return NULL;
3707 }
3708}
3709
3711 bool IsVarArg) const {
3712 if (Return)
3713 return RetCC_M68k_C;
3714 else
3715 return CC_M68k_C;
3716}
unsigned const MachineRegisterInfo * MRI
static SDValue getSETCC(AArch64CC::CondCode CC, SDValue NZCV, const SDLoc &DL, SelectionDAG &DAG)
Helper function to create 'CSET', which is equivalent to 'CSINC <Wd>, WZR, WZR, invert(<cond>)'.
static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls)
Return true if the calling convention is one that we can guarantee TCO for.
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII)
MatchingStackOffset - Return true if the given stack call argument is already available in the same p...
return RetTy
uint64_t Addr
uint64_t Size
Symbol * Sym
Definition: ELF_riscv.cpp:468
const HexagonInstrInfo * TII
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst...
IRTranslator LLVM IR MI
static LVOptions Options
Definition: LVOptions.cpp:25
This file contains the custom routines for the M68k Calling Convention that aren't done by tablegen.
static SDValue LowerTruncateToBTST(SDValue Op, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
static SDValue combineADDX(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc)
Return true if node is an ISD::AND or ISD::OR of two M68k::SETcc nodes each of which has no other use...
static bool hasNonFlagsUse(SDValue Op)
return true if Op has a use that doesn't just read flags.
static bool isM68kCCUnsigned(unsigned M68kCC)
Return true if the condition is an unsigned comparison operation.
static StructReturnType callIsStructReturn(const SmallVectorImpl< ISD::OutputArg > &Outs)
static bool isXor1OfSetCC(SDValue Op)
Return true if node is an ISD::XOR of a M68kISD::SETCC and 1 and that the SETCC node has a single use...
static SDValue LowerAndToBTST(SDValue And, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
Result of 'and' is compared against zero. Change to a BTST node if possible.
static SDValue combineM68kBrCond(SDNode *N, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
static M68k::CondCode TranslateIntegerM68kCC(ISD::CondCode SetCCOpcode)
static StructReturnType argsAreStructReturn(const SmallVectorImpl< ISD::InputArg > &Ins)
Determines whether a function uses struct return semantics.
static bool isCMOVPseudo(MachineInstr &MI)
static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt)
Return true if the function is being made into a tailcall target by changing its ABI.
static bool isM68kLogicalCmp(SDValue Op)
Return true if opcode is a M68k logical comparison.
static SDValue combineM68kSetCC(SDNode *N, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
static SDValue combineSetCCCCR(SDValue CCR, M68k::CondCode &CC, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
Optimize a CCR definition used according to the condition code CC into a simpler CCR value,...
static SDValue combineCarryThroughADD(SDValue CCR)
static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
Create a BTST (Bit Test) node - Test bit BitNo in Src and set condition according to equal/not-equal ...
StructReturnType
@ NotStructReturn
@ RegStructReturn
@ StackStructReturn
static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG)
static bool checkAndUpdateCCRKill(MachineBasicBlock::iterator SelectItr, MachineBasicBlock *BB, const TargetRegisterInfo *TRI)
static SDValue combineSUBX(SDNode *N, SelectionDAG &DAG)
static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL, bool IsFP, SDValue &LHS, SDValue &RHS, SelectionDAG &DAG)
Do a one-to-one translation of a ISD::CondCode to the M68k-specific condition code,...
This file defines the interfaces that M68k uses to lower LLVM code into a selection DAG.
This file declares the M68k specific subclass of MachineFunctionInfo.
This file declares the M68k specific subclass of TargetSubtargetInfo.
This file declares the M68k specific subclass of TargetMachine.
This file contains declarations for M68k ELF object file lowering.
#define F(x, y, z)
Definition: MD5.cpp:55
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
#define T1
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:167
Value * RHS
Value * LHS
Class for arbitrary precision integers.
Definition: APInt.h:76
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
Definition: APInt.h:212
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
Definition: APInt.h:274
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
LLVM Basic Block Representation.
Definition: BasicBlock.h:56
The address of a basic block.
Definition: Constants.h:874
CCState - This class holds information needed while lowering arguments and return values.
static bool resultsCompatible(CallingConv::ID CalleeCC, CallingConv::ID CallerCC, MachineFunction &MF, LLVMContext &C, const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn CalleeFn, CCAssignFn CallerFn)
Returns true if the results of the two calling conventions are compatible.
CCValAssign - Represent assignment of one arg/retval to a location.
bool isRegLoc() const
Register getLocReg() const
LocInfo getLocInfo() const
bool isMemLoc() const
bool isExtInLoc() const
int64_t getLocMemOffset() const
unsigned getValNo() const
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
A debug info location.
Definition: DebugLoc.h:33
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:155
iterator end()
Definition: DenseMap.h:84
iterator_range< arg_iterator > args()
Definition: Function.h:802
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.cpp:671
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:644
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:239
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:628
const GlobalValue * getGlobal() const
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:274
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:652
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
SmallVectorImpl< ForwardedRegister > & getForwardedMustTailRegParms()
void setBytesToPopOnReturn(unsigned bytes)
void setArgumentStackSize(unsigned size)
unsigned char classifyExternalReference(const Module &M) const
Classify a external variable reference for the current subtarget according to how we should reference...
unsigned char classifyBlockAddressReference() const
Classify a blockaddress reference for the current subtarget according to how we should reference it i...
unsigned getSlotSize() const
getSlotSize - Stack slot size in bytes.
const M68kInstrInfo * getInstrInfo() const override
unsigned char classifyGlobalReference(const GlobalValue *GV, const Module &M) const
Classify a global variable reference for the current subtarget according to how we should reference i...
unsigned getJumpTableEncoding() const
unsigned char classifyLocalReference(const GlobalValue *GV) const
Classify a global variable reference for the current subtarget according to how we should reference i...
const M68kRegisterInfo * getRegisterInfo() const override
bool atLeastM68020() const
Definition: M68kSubtarget.h:89
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const Module &M) const
Classify a global function reference for the current subtarget.
bool isTargetELF() const
const M68kFrameLowering * getFrameLowering() const override
ConstraintType getConstraintType(StringRef ConstraintStr) const override
Given a constraint, return the type of constraint it is for this target.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
CCAssignFn * getCCAssignFn(CallingConv::ID CC, bool Return, bool IsVarArg) const
M68kTargetLowering(const M68kTargetMachine &TM, const M68kSubtarget &STI)
InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:389
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Definition: Metadata.h:1416
Machine Value Type.
SimpleValueType SimpleTy
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
static MVT getIntegerVT(unsigned BitWidth)
MVT getScalarType() const
If this is a vector, return the element type, otherwise return this.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
void setCallFrameSize(unsigned N)
Set the call frame size on entry to this basic block.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< succ_iterator > successors()
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineInstrBundleIterator< MachineInstr > iterator
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
void setObjectZExt(int ObjectIdx, bool IsZExt)
void setObjectSExt(int ObjectIdx, bool IsSExt)
void setHasTailCall(bool V=true)
bool isObjectZExt(int ObjectIdx) const
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isObjectSExt(int ObjectIdx) const
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MCSymbol * getJTISymbol(unsigned JTI, MCContext &Ctx, bool isLinkerPrivate=false) const
getJTISymbol - Return the MCSymbol for the specified non-empty jump table.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool shouldSplitStack() const
Should we be emitting segmented stack stuff for the function.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Representation of each machine instruction.
Definition: MachineInstr.h:68
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:553
@ EK_Custom32
EK_Custom32 - Each entry is a 32-bit value that is custom lowered by the TargetLowering::LowerCustomJ...
int64_t getImm() const
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Class to represent pointers.
Definition: DerivedTypes.h:643
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
This class provides iterator support for SDUse operands that use a specific SDNode.
Represents one node in the SelectionDAG.
bool hasOneUse() const
Return true if there is exactly one use of this node.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
uint64_t getConstantOperandVal(unsigned i) const
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:720
SDValue getStackArgumentTokenFactor(SDValue Chain)
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:478
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:730
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:472
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getMDNode(const MDNode *MD)
Return an MDNodeSDNode which holds an MDNode.
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:473
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:771
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:674
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:766
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:469
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:797
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
LLVMContext * getContext() const
Definition: SelectionDAG.h:485
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:737
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:554
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:941
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Information about stack frame layout on the target.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.