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42 #define DEBUG_TYPE "M68k-isel"
44 STATISTIC(NumTailCalls,
"Number of tail calls");
179 #include "M68kGenCallingConv.inc"
251 unsigned Bytes =
Arg.getValueType().getSizeInBits() / 8;
255 unsigned Op =
Arg.getOpcode();
261 const SDValue &TruncInput =
Arg.getOperand(0);
263 cast<VTSDNode>(TruncInput.
getOperand(1))->getVT() ==
264 Arg.getValueType()) {
274 Register VR = cast<RegisterSDNode>(
Arg.getOperand(1))->getReg();
284 unsigned Opcode =
Def->getOpcode();
285 if ((Opcode == M68k::LEA32p || Opcode == M68k::LEA32f) &&
286 Def->getOperand(1).isFI()) {
287 FI =
Def->getOperand(1).getIndex();
292 }
else if (
auto *Ld = dyn_cast<LoadSDNode>(
Arg)) {
300 SDValue Ptr = Ld->getBasePtr();
332 M68kTargetLowering::getReturnAddressFrameIndex(
SelectionDAG &DAG)
const {
337 if (ReturnAddrIndex == 0) {
341 SlotSize, -(int64_t)SlotSize,
false);
351 bool IsTailCall,
int FPDiff,
354 OutRetAddr = getReturnAddressFrameIndex(DAG);
361 SDValue M68kTargetLowering::EmitTailCallStoreRetAddr(
363 EVT PtrVT,
unsigned SlotSize,
int FPDiff,
const SDLoc &
DL)
const {
369 SlotSize, (int64_t)FPDiff - SlotSize,
false);
374 Chain,
DL, RetFI, NewFI,
385 unsigned ArgIdx)
const {
416 bool IsImmutable = !AlwaysUseMutable && !Flags.
isByVal();
442 ValVT,
DL, Chain, FIN,
462 Chain,
DL,
Arg, PtrOff,
485 bool IsSibcall =
false;
493 if (Attr.getValueAsBool())
504 }
else if (IsTailCall) {
506 IsTailCall = IsEligibleForTailCallOptimization(
521 "Var args not supported with calling convention fastcc");
528 M68kCCState CCInfo(ArgTypes, CallConv, IsVarArg, MF, ArgLocs,
530 CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
533 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
540 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
544 if (IsTailCall && !IsSibcall && !IsMustTail) {
548 FPDiff = NumBytesCallerPushed - NumBytes;
552 if (FPDiff < MFI->getTCReturnAddrDelta())
556 unsigned NumBytesToPush = NumBytes;
557 unsigned NumBytesToPop = NumBytes;
562 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
564 if (!ArgLocs.back().isMemLoc())
567 if (ArgLocs.back().getLocMemOffset() != 0)
569 "the only memory argument");
574 NumBytes - NumBytesToPush,
DL);
578 if (IsTailCall && FPDiff)
579 Chain = EmitTailCallLoadRetAddr(DAG, RetFI, Chain, IsTailCall, FPDiff,
DL);
588 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
598 bool IsByVal = Flags.
isByVal();
621 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
623 Chain,
DL,
Arg, SpillSlot,
631 RegsToPass.push_back(std::make_pair(VA.
getLocReg(),
Arg));
632 }
else if (!IsSibcall && (!IsTailCall || IsByVal)) {
638 MemOpChains.push_back(
639 LowerMemOpCallTo(Chain, StackPtr,
Arg,
DL, DAG, VA, Flags));
643 if (!MemOpChains.empty())
650 if (IsVarArg && IsMustTail) {
652 for (
const auto &
F : Forwards) {
654 RegsToPass.push_back(std::make_pair(
unsigned(
F.PReg), Val));
661 if (!IsSibcall && IsTailCall) {
673 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
699 MemOpChains2.push_back(
703 MemOpChains2.push_back(DAG.
getStore(
704 ArgChain,
DL,
Arg, FIN,
709 if (!MemOpChains2.empty())
713 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetFI,
721 for (
unsigned i = 0,
e = RegsToPass.size();
i !=
e; ++
i) {
723 RegsToPass[
i].second, InFlag);
756 unsigned char OpFlags =
767 if (!IsSibcall && IsTailCall) {
774 Ops.push_back(Chain);
775 Ops.push_back(Callee);
782 for (
unsigned i = 0,
e = RegsToPass.size();
i !=
e; ++
i)
784 RegsToPass[
i].second.getValueType()));
788 assert(
Mask &&
"Missing call preserved mask for calling convention");
793 Ops.push_back(InFlag);
804 unsigned NumBytesForCalleeToPop;
807 NumBytesForCalleeToPop = NumBytes;
811 NumBytesForCalleeToPop = 4;
813 NumBytesForCalleeToPop = 0;
819 NumBytesForCalleeToPop = NumBytes;
832 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg,
Ins,
DL, DAG,
836 SDValue M68kTargetLowering::LowerCallResult(
845 CCInfo.AnalyzeCallResult(
Ins, RetCC_M68k);
848 for (
unsigned i = 0,
e = RVLocs.size();
i !=
e; ++
i) {
861 InVals.push_back(Val);
871 SDValue M68kTargetLowering::LowerFormalArguments(
888 CCInfo.AnalyzeFormalArguments(
Ins, CC_M68k);
890 unsigned LastVal = ~0U;
892 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
894 assert(VA.
getValNo() != LastVal &&
"Same value in different locations");
902 RC = &M68k::XR32RegClass;
927 ArgValue = LowerMemArgument(Chain, CCID,
Ins,
DL, DAG, VA, MFI,
i);
936 InVals.push_back(ArgValue);
939 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
961 unsigned StackSize = CCInfo.getNextStackOffset();
964 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
969 if (MFI.hasVAStart()) {
973 if (IsVarArg && MFI.hasMustTailInVarArgFunc()) {
977 RegParmTypes.push_back(IntVT);
983 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_M68k);
1025 CCInfo.AnalyzeReturn(Outs, RetCC_M68k);
1030 RetOps.push_back(Chain);
1036 for (
unsigned i = 0,
e = RVLocs.size();
i !=
e; ++
i) {
1097 unsigned RetValReg = M68k::D0;
1109 RetOps.push_back(
Flag);
1147 M68kTargetLowering::GetAlignedArgumentStackSize(
unsigned StackSize,
1151 uint64_t AlignMask = StackAlignment - 1;
1152 int64_t
Offset = StackSize;
1154 if ((Offset & AlignMask) <= (StackAlignment - SlotSize)) {
1156 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1160 ((~AlignMask) & Offset) + StackAlignment + (StackAlignment - SlotSize);
1167 bool M68kTargetLowering::IsEligibleForTailCallOptimization(
1169 bool IsCalleeStructRet,
bool IsCallerStructRet,
Type *RetTy,
1181 bool CCMatch = CallerCC == CalleeCC;
1195 if (RegInfo->hasStackRealignment(MF))
1200 if (IsCalleeStructRet || IsCallerStructRet)
1206 if (IsVarArg && !Outs.empty()) {
1209 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs,
C);
1211 CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
1212 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i)
1213 if (!ArgLocs[
i].isRegLoc())
1231 unsigned StackArgsSize = 0;
1235 if (!Outs.empty()) {
1239 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs,
C);
1241 CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
1242 StackArgsSize = CCInfo.getNextStackOffset();
1244 if (CCInfo.getNextStackOffset()) {
1250 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
1270 if ((!isa<GlobalAddressSDNode>(Callee) &&
1271 !isa<ExternalSymbolSDNode>(Callee)) ||
1272 PositionIndependent) {
1273 unsigned NumInRegs = 0;
1276 unsigned MaxInRegs = PositionIndependent ? 1 : 2;
1278 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
1288 if (++NumInRegs == MaxInRegs)
1303 if (
unsigned BytesToPop =
1306 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
1307 if (!CalleePopMatches)
1309 }
else if (CalleeWillPop && StackArgsSize > 0) {
1323 switch (
Op.getOpcode()) {
1332 return LowerXALUO(
Op, DAG);
1334 return LowerSETCC(
Op, DAG);
1336 return LowerSETCCCARRY(
Op, DAG);
1338 return LowerSELECT(
Op, DAG);
1340 return LowerBRCOND(
Op, DAG);
1345 return LowerADDC_ADDE_SUBC_SUBE(
Op, DAG);
1347 return LowerConstantPool(
Op, DAG);
1349 return LowerGlobalAddress(
Op, DAG);
1351 return LowerExternalSymbol(
Op, DAG);
1353 return LowerBlockAddress(
Op, DAG);
1355 return LowerJumpTable(
Op, DAG);
1357 return LowerVASTART(
Op, DAG);
1359 return LowerDYNAMIC_STACKALLOC(
Op, DAG);
1361 return LowerShiftLeftParts(
Op, DAG);
1363 return LowerShiftRightParts(
Op, DAG,
true);
1365 return LowerShiftRightParts(
Op, DAG,
false);
1387 unsigned BaseOp = 0;
1390 switch (
Op.getOpcode()) {
1462 unsigned AndBitWidth =
And.getValueSizeInBits();
1465 if (Known.countMinLeadingZeros() <
BitWidth - AndBitWidth)
1471 }
else if (
auto *AndRHS = dyn_cast<ConstantSDNode>(Op1)) {
1472 uint64_t AndRHSVal = AndRHS->getZExtValue();
1494 switch (SetCCOpcode) {
1528 if (SetCCOpcode ==
ISD::SETGT && RHSC->isAllOnesValue()) {
1533 if (SetCCOpcode ==
ISD::SETLT && RHSC->isNullValue()) {
1537 if (SetCCOpcode ==
ISD::SETLT && RHSC->getZExtValue() == 1) {
1555 switch (SetCCOpcode) {
1572 switch (SetCCOpcode) {
1608 "Expected TRUNCATE to i1 node");
1610 if (
Op.getOperand(0).getOpcode() !=
ISD::SRL)
1623 unsigned UOpNo = UI.getOperandNo();
1642 bool NeedCF =
false;
1643 bool NeedOF =
false;
1662 switch (
Op->getOpcode()) {
1667 if (
Op.getNode()->getFlags().hasNoSignedWrap())
1681 if (
Op.getResNo() != 0 || NeedOF || NeedCF) {
1686 unsigned Opcode = 0;
1687 unsigned NumOperands = 0;
1692 bool NeedTruncation =
false;
1706 NeedTruncation =
true;
1726 Op->hasOneUse() && isa<ConstantSDNode>(
Op->getOperand(1)) &&
1728 EVT VT =
Op.getValueType();
1730 unsigned ShAmt =
Op->getConstantOperandVal(1);
1736 if (!
Mask.isSignedIntN(32))
1755 if ( !IsAndn || !IsLegalAndnType)
1764 for (
const auto *U :
Op.getNode()->uses())
1801 if (NeedTruncation) {
1802 EVT VT =
Op.getValueType();
1805 unsigned ConvertedOp = 0;
1875 return EmitTest(Op0, M68kCC,
DL, DAG);
1878 "Unexpected comparison operation for MVT::i1 operands");
1885 (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1))) &&
1913 MVT VT =
Op.getSimpleValueType();
1914 assert(VT ==
MVT::i8 &&
"SetCC type must be 8-bit integer");
1928 if (
SDValue NewSetCC = LowerToBTST(Op0, CC,
DL, DAG)) {
1973 SDValue CCR = EmitCmp(Op0, Op1, M68kCC,
DL, DAG);
1986 assert(
LHS.getSimpleValueType().isInteger() &&
"SETCCCARRY is integer only.");
2004 unsigned Opc =
Op.getNode()->getOpcode();
2007 if (
Op.getResNo() == 1 &&
2031 bool addTest =
true;
2053 cast<ConstantSDNode>(
Cond.getOperand(0))->getZExtValue();
2102 unsigned CondOpcode =
Cond.getOpcode();
2104 CC =
Cond.getOperand(0);
2107 unsigned Opc =
Cmp.getOpcode();
2109 bool IllegalFPCMov =
false;
2123 switch (CondOpcode) {
2177 Cond = NewSetCC.getOperand(1);
2193 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
2213 if (
T1.getValueType() == T2.getValueType() &&
2233 Opc =
Op.getOpcode();
2237 Op.getOperand(0).hasOneUse() &&
2239 Op.getOperand(1).hasOneUse());
2249 Op.getOperand(0).hasOneUse();
2254 bool AddTest =
true;
2260 bool Inverted =
false;
2264 if (cast<CondCodeSDNode>(
Cond.getOperand(2))->get() ==
ISD::SETEQ &&
2266 Cond.getOperand(0).getResNo() == 1 &&
2287 unsigned CondOpcode =
Cond.getOpcode();
2289 CC =
Cond.getOperand(0);
2292 unsigned Opc =
Cmp.getOpcode();
2298 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
2305 Cond =
Cond.getNode()->getOperand(1);
2311 CondOpcode =
Cond.getOpcode();
2322 switch (CondOpcode) {
2377 CC =
Cond.getOperand(0).getOperand(0);
2380 CC =
Cond.getOperand(1).getOperand(0);
2391 Op.getNode()->hasOneUse()) {
2427 Cond =
Cond.getOperand(0).getOperand(1);
2438 if (
Cond.hasOneUse()) {
2441 Cond = NewSetCC.getOperand(1);
2458 MVT VT =
Op.getNode()->getSimpleValueType(0);
2467 bool ExtraOp =
false;
2468 switch (
Op.getOpcode()) {
2514 CP->getConstVal(), PtrVT,
CP->getAlign(),
CP->getOffset(), OpFlag);
2531 const char *Sym = cast<ExternalSymbolSDNode>(
Op)->getSymbol();
2569 const BlockAddress *BA = cast<BlockAddressSDNode>(
Op)->getBlockAddress();
2570 int64_t
Offset = cast<BlockAddressSDNode>(
Op)->getOffset();
2594 const SDLoc &
DL, int64_t Offset,
2640 const GlobalValue *GV = cast<GlobalAddressSDNode>(
Op)->getGlobal();
2641 int64_t
Offset = cast<GlobalAddressSDNode>(
Op)->getOffset();
2642 return LowerGlobalAddress(GV,
SDLoc(
Op), Offset, DAG);
2706 if (Constraint.
size() > 0) {
2707 switch (Constraint[0]) {
2721 if (Constraint.
size() == 2)
2722 switch (Constraint[1]) {
2740 std::string &Constraint,
2741 std::vector<SDValue> &Ops,
2745 if (Constraint.size() == 1) {
2747 switch (Constraint[0]) {
2756 auto *
C = dyn_cast<ConstantSDNode>(
Op);
2760 int64_t Val =
C->getSExtValue();
2761 switch (Constraint[0]) {
2763 if (Val > 0 && Val <= 8)
2771 if (Val < -0x80 || Val >= 0x80)
2775 if (Val < 0 && Val >= -8)
2779 if (Val < -0x100 || Val >= 0x100)
2783 if (Val >= 24 && Val <= 31)
2791 if (Val >= 8 && Val <= 15)
2806 if (Constraint.size() == 2) {
2807 switch (Constraint[0]) {
2810 switch (Constraint[1]) {
2814 auto *
C = dyn_cast<ConstantSDNode>(
Op);
2818 int64_t Val =
C->getSExtValue();
2819 switch (Constraint[1]) {
2846 if (Result.getNode()) {
2847 Ops.push_back(Result);
2854 std::pair<unsigned, const TargetRegisterClass *>
2858 if (Constraint.
size() == 1) {
2859 switch (Constraint[0]) {
2864 return std::make_pair(0U, &M68k::DR8RegClass);
2866 return std::make_pair(0U, &M68k::DR16RegClass);
2868 return std::make_pair(0U, &M68k::DR32RegClass);
2876 return std::make_pair(0U, &M68k::AR16RegClass);
2878 return std::make_pair(0U, &M68k::AR32RegClass);
2894 bool GuaranteeTCO) {
2902 switch (
MI.getOpcode()) {
2933 if (miI ==
BB->end())
2934 for (
const auto *SBB :
BB->successors())
2935 if (SBB->isLiveIn(M68k::CCR))
2940 SelectItr->addRegisterKilled(M68k::CCR,
TRI);
3016 (NextMIIt->getOperand(3).getImm() == CC ||
3017 NextMIIt->getOperand(3).getImm() == OppCC)) {
3018 LastCMOV = &*NextMIIt;
3025 if (LastCMOV == &
MI && NextMIIt !=
MBB->
end() &&
3026 NextMIIt->getOpcode() ==
MI.getOpcode() &&
3027 NextMIIt->getOperand(2).getReg() ==
MI.getOperand(2).getReg() &&
3028 NextMIIt->getOperand(1).getReg() ==
MI.getOperand(0).getReg() &&
3029 NextMIIt->getOperand(1).isKill()) {
3030 CascadedCMOV = &*NextMIIt;
3038 Jcc1MBB =
F->CreateMachineBasicBlock(
BB);
3039 F->insert(It, Jcc1MBB);
3045 F->insert(It, Copy0MBB);
3046 F->insert(It, SinkMBB);
3052 MachineInstr *LastCCRSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
3113 Register DestReg = MIIt->getOperand(0).getReg();
3114 Register Op1Reg = MIIt->getOperand(1).getReg();
3115 Register Op2Reg = MIIt->getOperand(2).getReg();
3120 if (MIIt->getOperand(3).getImm() == OppCC)
3123 if (RegRewriteTable.
find(Op1Reg) != RegRewriteTable.
end())
3124 Op1Reg = RegRewriteTable[Op1Reg].first;
3126 if (RegRewriteTable.
find(Op2Reg) != RegRewriteTable.
end())
3127 Op2Reg = RegRewriteTable[Op2Reg].second;
3130 BuildMI(*SinkMBB, SinkInsertionPoint,
DL,
TII->get(M68k::PHI), DestReg)
3137 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
3146 DL,
TII->get(TargetOpcode::COPY),
3148 .
addReg(
MI.getOperand(0).getReg());
3154 (MIIt++)->eraseFromParent();
3162 llvm_unreachable(
"Cannot lower Segmented Stack Alloca with stack-split on");
3168 switch (
MI.getOpcode()) {
3174 return EmitLoweredSelect(
MI,
BB);
3176 return EmitLoweredSegAlloca(
MI,
BB);
3185 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
3211 unsigned Align = cast<ConstantSDNode>(
Op.getOperand(2))->getZExtValue();
3212 EVT VT = Node->getValueType(0);
3230 assert(SPReg &&
"Target cannot require DYNAMIC_STACKALLOC expansion and"
3231 " not tell us which reg is the stack pointer!");
3257 EVT VT =
Lo.getValueType();
3270 SDValue ShamtMinusRegisterSize =
3272 SDValue RegisterSizeMinus1Shamt =
3298 EVT VT =
Lo.getValueType();
3322 SDValue ShamtMinusRegisterSize =
3324 SDValue RegisterSizeMinus1Shamt =
3334 DAG.
getNode(ShiftRightOp,
DL, VT, Hi, ShamtMinusRegisterSize);
3419 N->getOperand(1),
Cond, Flags);
3427 MVT VT =
N->getSimpleValueType(0);
3430 N->getOperand(1), Flags);
3440 MVT VT =
N->getSimpleValueType(0);
3443 N->getOperand(1), Flags);
3450 DAGCombinerInfo &DCI)
const {
3452 switch (
N->getOpcode()) {
3472 return "M68kISD::CALL";
3474 return "M68kISD::TAIL_CALL";
3476 return "M68kISD::RET";
3478 return "M68kISD::TC_RETURN";
3480 return "M68kISD::ADD";
3482 return "M68kISD::SUB";
3484 return "M68kISD::ADDX";
3486 return "M68kISD::SUBX";
3488 return "M68kISD::SMUL";
3490 return "M68kISD::UMUL";
3492 return "M68kISD::OR";
3494 return "M68kISD::XOR";
3496 return "M68kISD::AND";
3498 return "M68kISD::CMP";
3500 return "M68kISD::BTST";
3502 return "M68kISD::SELECT";
3504 return "M68kISD::CMOV";
3506 return "M68kISD::BRCOND";
3508 return "M68kISD::SETCC";
3510 return "M68kISD::SETCC_CARRY";
3512 return "M68kISD::GLOBAL_BASE_REG";
3514 return "M68kISD::Wrapper";
3516 return "M68kISD::WrapperPC";
3518 return "M68kISD::SEG_ALLOCA";
3525 bool IsVarArg)
const {
3527 return RetCC_M68k_C;
bool isObjectZExt(int ObjectIdx) const
This class represents an incoming formal argument to a Function.
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
CCAssignFn * getCCAssignFn(CallingConv::ID CC, bool Return, bool IsVarArg) const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
@ Wrapper
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
static M68k::CondCode TranslateIntegerM68kCC(ISD::CondCode SetCCOpcode)
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
static SDValue LowerAndToBTST(SDValue And, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
Result of 'and' is compared against zero. Change to a BTST node if possible.
This is an optimization pass for GlobalISel generic memory operations.
@ BRCOND
M68k conditional branches.
void setArgumentStackSize(unsigned size)
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
iterator_range< arg_iterator > args()
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
Information about stack frame layout on the target.
bool hasOneUse() const
Return true if there is exactly one use of this value.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
@ BR_JT
BR_JT - Jumptable branch.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
CCState - This class holds information needed while lowering arguments and return values.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
SDNode * getNode() const
get the SDNode which holds the desired result
bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
Context object for machine code objects.
@ BSWAP
Byte Swap and Counting operators.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
SDValue getValueType(EVT)
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL, bool IsFP, SDValue &LHS, SDValue &RHS, SelectionDAG &DAG)
Do a one-to-one translation of a ISD::CondCode to the M68k-specific condition code,...
CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
Custom state to propagate llvm type info to register CC assigner.
bool isBitwiseNot(SDValue V, bool AllowUndefs=false)
Returns true if V is a bitwise not operation.
Reg
All possible values of the reg field in the ModR/M byte.
@ M68k_INTR
M68k_INTR - Calling convention used for M68k interrupt routines.
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Represents one node in the SelectionDAG.
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
static bool isPCRelBlockReference(unsigned char Flag)
Return True if the Block is referenced using PC.
unsigned getStackRegister() const
This class provides iterator support for SDUse operands that use a specific SDNode.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static SDValue LowerTruncateToBTST(SDValue Op, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
bool isPositionIndependent() const
The instances of the Type class are immutable: once they are created, they are never changed.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
static bool isXor1OfSetCC(SDValue Op)
Return true if node is an ISD::XOR of a M68kISD::SETCC and 1 and that the SETCC node has a single use...
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
static bool isDirectGlobalReference(unsigned char Flag)
Return True if the specified GlobalValue is a direct reference for a symbol.
static bool hasNonFlagsUse(SDValue Op)
return true if Op has a use that doesn't just read flags.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
MCSymbol * getJTISymbol(unsigned JTI, MCContext &Ctx, bool isLinkerPrivate=false) const
getJTISymbol - Return the MCSymbol for the specified non-empty jump table.
const M68kRegisterInfo * getRegisterInfo() const override
bool bitsLE(EVT VT) const
Return true if this has no more bits than VT.
SmallVectorImpl< ForwardedRegister > & getForwardedMustTailRegParms()
@ EK_Custom32
EK_Custom32 - Each entry is a 32-bit value that is custom lowered by the TargetLowering::LowerCustomJ...
unsigned const TargetRegisterInfo * TRI
static SDValue combineCarryThroughADD(SDValue CCR)
LLVMContext * getContext() const
bool isCalleePop(CallingConv::ID CallingConv, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
@ BRCOND
BRCOND - Conditional branch.
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
SDValue getRegister(unsigned Reg, EVT VT)
LLVM Basic Block Representation.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
static bool isGlobalStubReference(unsigned char TargetFlag)
Return true if the specified TargetFlag operand is a reference to a stub for a global,...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static auto integer_valuetypes()
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt)
Return true if the function is being made into a tailcall target by changing its ABI.
@ BR_CC
BR_CC - Conditional branch.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned char classifyBlockAddressReference() const
Classify a blockaddress reference for the current subtarget according to how we should reference it i...
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
TargetInstrInfo - Interface to description of machine instruction set.
@ And
Bitwise or logical AND of integers.
EVT getValueType() const
Return the ValueType of the referenced return value.
CCValAssign - Represent assignment of one arg/retval to a location.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const M68kInstrInfo * getInstrInfo() const override
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
bool hasOneUse() const
Return true if there is exactly one use of this node.
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Register getLocReg() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
const TargetLowering & getTargetLoweringInfo() const
(vector float) vec_cmpeq(*A, *B) C
const MachineOperand & getOperand(unsigned i) const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc)
Return true if node is an ISD::AND or ISD::OR of two M68k::SETcc nodes each of which has no other use...
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
void setSRetReturnReg(unsigned Reg)
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
const HexagonInstrInfo * TII
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
static StructReturnType argsAreStructReturn(const SmallVectorImpl< ISD::InputArg > &Ins)
Determines whether a function uses struct return semantics.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
static SDValue combineM68kSetCC(SDNode *N, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
void setTCReturnAddrDelta(int delta)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
STATISTIC(NumFunctions, "Total number of functions")
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
bool shouldSplitStack() const
Should we be emitting segmented stack stuff for the function.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
LocInfo getLocInfo() const
@ SMULO
Same for multiplication.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
unsigned getLocMemOffset() const
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t getConstantOperandVal(unsigned i) const
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
unsigned getSRetReturnReg() const
MVT getScalarType() const
If this is a vector, return the element type, otherwise return this.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
static bool checkAndUpdateCCRKill(MachineBasicBlock::iterator SelectItr, MachineBasicBlock *BB, const TargetRegisterInfo *TRI)
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
@ CMOV
M68k conditional moves.
SmallVector< ISD::OutputArg, 32 > Outs
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Representation of each machine instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Module * getParent()
Get the module that this global value is contained inside of...
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Describes a register that needs to be forwarded from the prologue to a musttail call.
static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
Create a BTST (Bit Test) node - Test bit BitNo in Src and set condition according to equal/not-equal ...
This class contains a discriminated union of information about pointers in memory operands,...
This is an important class for using LLVM in a threaded context.
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
Return true if the specified global value reference is relative to a 32-bit PIC base (M68kISD::GLOBAL...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
const SDValue & getOperand(unsigned Num) const
static unsigned GetCondBranchFromCond(M68k::CondCode CC)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
static SDValue combineM68kBrCond(SDNode *N, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
static bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI, const MachineRegisterInfo *MRI, const M68kInstrInfo *TII, const CCValAssign &VA)
Return true if the given stack call argument is already available in the same position (relatively) o...
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
@ BTST
M68k bit-test instructions.
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
unsigned Log2_64_Ceil(uint64_t Value)
Return the ceil log base 2 of the specified value, 64 if the value is zero.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
constexpr bool isUInt< 32 >(uint64_t x)
iterator find(const_arg_type_t< KeyT > Val)
static bool isPCRelGlobalReference(unsigned char Flag)
Return True if the specified GlobalValue requires PC addressing mode.
void setHasTailCall(bool V=true)
const M68kFrameLowering * getFrameLowering() const override
SDValue getValue(unsigned R) const
This structure contains all information that is necessary for lowering calls.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
A Module instance is used to store all the information related to an LLVM module.
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
static SDValue combineSUBX(SDNode *N, SelectionDAG &DAG)
static bool canGuaranteeTCO(CallingConv::ID CC)
Return true if the calling convention is one that we can guarantee TCO for.
Class for arbitrary precision integers.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
static bool resultsCompatible(CallingConv::ID CalleeCC, CallingConv::ID CallerCC, MachineFunction &MF, LLVMContext &C, const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn CalleeFn, CCAssignFn CallerFn)
Returns true if the results of the two calling conventions are compatible.
static bool isM68kLogicalCmp(SDValue Op)
Return true if opcode is a M68k logical comparison.
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
@ C
C - The default llvm calling convention, compatible with C.
SmallVector< ISD::InputArg, 32 > Ins
unsigned getValNo() const
The address of a basic block.
void setVarArgsFrameIndex(int Index)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0)
static StructReturnType callIsStructReturn(const SmallVectorImpl< ISD::OutputArg > &Outs)
MachineInstrBundleIterator< MachineInstr > iterator
bool isVector() const
Return true if this is a vector value type.
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
SmallVector< MachineOperand, 4 > Cond
StringRef - Represent a constant reference to a string, i.e.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
uint64_t getScalarSizeInBits() const
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const SDValue & getOperand(unsigned i) const
self_iterator getIterator()
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
unsigned getSlotSize() const
getSlotSize - Stack slot size in bytes.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const Module &M) const
Classify a global function reference for the current subtarget.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
bool isObjectSExt(int ObjectIdx) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
@ WrapperPC
Special wrapper used under M68k PIC mode for PC relative displacements.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
amdgpu Simplify well known AMD library false FunctionCallee Callee
const TargetMachine & getTargetMachine() const
constexpr bool isInt< 16 >(int64_t x)
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
unsigned char classifyLocalReference(const GlobalValue *GV) const
Classify a global variable reference for the current subtarget according to how we should reference i...
void setBytesToPopOnReturn(unsigned bytes)
unsigned getByValSize() const
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Should compile to something r4 addze r3 instead we get
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
static bool IsSETCC(unsigned SETCC)
@ BR
Control flow instructions. These all have token chains.
Iterator for intrusive lists based on ilist_node.
void setRAIndex(int Index)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
const DataLayout & getDataLayout() const
void setObjectSExt(int ObjectIdx, bool IsSExt)
constexpr unsigned BitWidth
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
@ ZeroOrOneBooleanContent
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ CMP
M68k compare and logical compare instructions.
@ ADD
Simple integer binary arithmetic operators.
static SDValue combineADDX(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
@ SSUBO
Same for subtraction.
M68kTargetLowering(const M68kTargetMachine &TM, const M68kSubtarget &STI)
unsigned getBytesToPopOnReturn() const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
EVT getVectorElementType() const
Given a vector type, return the type of each element.
static bool isCMOVPseudo(MachineInstr &MI)
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
static bool isM68kCCUnsigned(unsigned M68kCC)
Return true if the condition is an unsigned comparison operation.
@ SHL
Shift and rotation operations.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
Align getNonZeroByValAlign() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getJumpTableEncoding() const
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
static SDValue combineSetCCCCR(SDValue CCR, M68k::CondCode &CC, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
Optimize a CCR definition used according to the condition code CC into a simpler CCR value,...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
SDValue getRegisterMask(const uint32_t *RegMask)
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.