LLVM 18.0.0git
HexagonISelLowering.cpp
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1//===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the interfaces that Hexagon uses to lower LLVM code
10// into a selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonISelLowering.h"
15#include "Hexagon.h"
17#include "HexagonRegisterInfo.h"
18#include "HexagonSubtarget.h"
21#include "llvm/ADT/APInt.h"
22#include "llvm/ADT/ArrayRef.h"
34#include "llvm/IR/BasicBlock.h"
35#include "llvm/IR/CallingConv.h"
36#include "llvm/IR/DataLayout.h"
40#include "llvm/IR/Function.h"
41#include "llvm/IR/GlobalValue.h"
42#include "llvm/IR/InlineAsm.h"
45#include "llvm/IR/Intrinsics.h"
46#include "llvm/IR/IntrinsicsHexagon.h"
47#include "llvm/IR/IRBuilder.h"
48#include "llvm/IR/Module.h"
49#include "llvm/IR/Type.h"
50#include "llvm/IR/Value.h"
55#include "llvm/Support/Debug.h"
60#include <algorithm>
61#include <cassert>
62#include <cstddef>
63#include <cstdint>
64#include <limits>
65#include <utility>
66
67using namespace llvm;
68
69#define DEBUG_TYPE "hexagon-lowering"
70
71static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
72 cl::init(true), cl::Hidden,
73 cl::desc("Control jump table emission on Hexagon target"));
74
75static cl::opt<bool>
76 EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden,
77 cl::desc("Enable Hexagon SDNode scheduling"));
78
80 cl::desc("Enable Fast Math processing"));
81
82static cl::opt<int> MinimumJumpTables("minimum-jump-tables", cl::Hidden,
83 cl::init(5),
84 cl::desc("Set minimum jump tables"));
85
86static cl::opt<int>
87 MaxStoresPerMemcpyCL("max-store-memcpy", cl::Hidden, cl::init(6),
88 cl::desc("Max #stores to inline memcpy"));
89
90static cl::opt<int>
92 cl::desc("Max #stores to inline memcpy"));
93
94static cl::opt<int>
95 MaxStoresPerMemmoveCL("max-store-memmove", cl::Hidden, cl::init(6),
96 cl::desc("Max #stores to inline memmove"));
97
98static cl::opt<int>
100 cl::init(4),
101 cl::desc("Max #stores to inline memmove"));
102
103static cl::opt<int>
104 MaxStoresPerMemsetCL("max-store-memset", cl::Hidden, cl::init(8),
105 cl::desc("Max #stores to inline memset"));
106
107static cl::opt<int>
109 cl::desc("Max #stores to inline memset"));
110
111static cl::opt<bool> AlignLoads("hexagon-align-loads",
112 cl::Hidden, cl::init(false),
113 cl::desc("Rewrite unaligned loads as a pair of aligned loads"));
114
115static cl::opt<bool>
116 DisableArgsMinAlignment("hexagon-disable-args-min-alignment", cl::Hidden,
117 cl::init(false),
118 cl::desc("Disable minimum alignment of 1 for "
119 "arguments passed by value on stack"));
120
121namespace {
122
123 class HexagonCCState : public CCState {
124 unsigned NumNamedVarArgParams = 0;
125
126 public:
127 HexagonCCState(CallingConv::ID CC, bool IsVarArg, MachineFunction &MF,
129 unsigned NumNamedArgs)
130 : CCState(CC, IsVarArg, MF, locs, C),
131 NumNamedVarArgParams(NumNamedArgs) {}
132 unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
133 };
134
135} // end anonymous namespace
136
137
138// Implement calling convention for Hexagon.
139
140static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
141 CCValAssign::LocInfo &LocInfo,
142 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
143 static const MCPhysReg ArgRegs[] = {
144 Hexagon::R0, Hexagon::R1, Hexagon::R2,
145 Hexagon::R3, Hexagon::R4, Hexagon::R5
146 };
147 const unsigned NumArgRegs = std::size(ArgRegs);
148 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
149
150 // RegNum is an index into ArgRegs: skip a register if RegNum is odd.
151 if (RegNum != NumArgRegs && RegNum % 2 == 1)
152 State.AllocateReg(ArgRegs[RegNum]);
153
154 // Always return false here, as this function only makes sure that the first
155 // unallocated register has an even register number and does not actually
156 // allocate a register for the current argument.
157 return false;
158}
159
160#include "HexagonGenCallingConv.inc"
161
162
165 const {
166 return SDValue();
167}
168
169/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
170/// by "Src" to address "Dst" of size "Size". Alignment information is
171/// specified by the specific parameter attribute. The copy will be passed as
172/// a byval function parameter. Sometimes what we are copying is the end of a
173/// larger object, the part that does not fit in registers.
175 SDValue Chain, ISD::ArgFlagsTy Flags,
176 SelectionDAG &DAG, const SDLoc &dl) {
177 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
178 return DAG.getMemcpy(
179 Chain, dl, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
180 /*isVolatile=*/false, /*AlwaysInline=*/false,
181 /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo());
182}
183
184bool
186 CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
188 LLVMContext &Context) const {
190 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
191
193 return CCInfo.CheckReturn(Outs, RetCC_Hexagon_HVX);
194 return CCInfo.CheckReturn(Outs, RetCC_Hexagon);
195}
196
197// LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
198// passed by value, the function prototype is modified to return void and
199// the value is stored in memory pointed by a pointer passed by caller.
202 bool IsVarArg,
204 const SmallVectorImpl<SDValue> &OutVals,
205 const SDLoc &dl, SelectionDAG &DAG) const {
206 // CCValAssign - represent the assignment of the return value to locations.
208
209 // CCState - Info about the registers and stack slot.
210 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
211 *DAG.getContext());
212
213 // Analyze return values of ISD::RET
214 if (Subtarget.useHVXOps())
215 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon_HVX);
216 else
217 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
218
219 SDValue Glue;
220 SmallVector<SDValue, 4> RetOps(1, Chain);
221
222 // Copy the result values into the output registers.
223 for (unsigned i = 0; i != RVLocs.size(); ++i) {
224 CCValAssign &VA = RVLocs[i];
225 SDValue Val = OutVals[i];
226
227 switch (VA.getLocInfo()) {
228 default:
229 // Loc info must be one of Full, BCvt, SExt, ZExt, or AExt.
230 llvm_unreachable("Unknown loc info!");
232 break;
234 Val = DAG.getBitcast(VA.getLocVT(), Val);
235 break;
237 Val = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Val);
238 break;
240 Val = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Val);
241 break;
243 Val = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Val);
244 break;
245 }
246
247 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Val, Glue);
248
249 // Guarantee that all emitted copies are stuck together with flags.
250 Glue = Chain.getValue(1);
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
252 }
253
254 RetOps[0] = Chain; // Update chain.
255
256 // Add the glue if we have it.
257 if (Glue.getNode())
258 RetOps.push_back(Glue);
259
260 return DAG.getNode(HexagonISD::RET_GLUE, dl, MVT::Other, RetOps);
261}
262
264 // If either no tail call or told not to tail call at all, don't.
265 return CI->isTailCall();
266}
267
269 const char* RegName, LLT VT, const MachineFunction &) const {
270 // Just support r19, the linux kernel uses it.
272 .Case("r0", Hexagon::R0)
273 .Case("r1", Hexagon::R1)
274 .Case("r2", Hexagon::R2)
275 .Case("r3", Hexagon::R3)
276 .Case("r4", Hexagon::R4)
277 .Case("r5", Hexagon::R5)
278 .Case("r6", Hexagon::R6)
279 .Case("r7", Hexagon::R7)
280 .Case("r8", Hexagon::R8)
281 .Case("r9", Hexagon::R9)
282 .Case("r10", Hexagon::R10)
283 .Case("r11", Hexagon::R11)
284 .Case("r12", Hexagon::R12)
285 .Case("r13", Hexagon::R13)
286 .Case("r14", Hexagon::R14)
287 .Case("r15", Hexagon::R15)
288 .Case("r16", Hexagon::R16)
289 .Case("r17", Hexagon::R17)
290 .Case("r18", Hexagon::R18)
291 .Case("r19", Hexagon::R19)
292 .Case("r20", Hexagon::R20)
293 .Case("r21", Hexagon::R21)
294 .Case("r22", Hexagon::R22)
295 .Case("r23", Hexagon::R23)
296 .Case("r24", Hexagon::R24)
297 .Case("r25", Hexagon::R25)
298 .Case("r26", Hexagon::R26)
299 .Case("r27", Hexagon::R27)
300 .Case("r28", Hexagon::R28)
301 .Case("r29", Hexagon::R29)
302 .Case("r30", Hexagon::R30)
303 .Case("r31", Hexagon::R31)
304 .Case("r1:0", Hexagon::D0)
305 .Case("r3:2", Hexagon::D1)
306 .Case("r5:4", Hexagon::D2)
307 .Case("r7:6", Hexagon::D3)
308 .Case("r9:8", Hexagon::D4)
309 .Case("r11:10", Hexagon::D5)
310 .Case("r13:12", Hexagon::D6)
311 .Case("r15:14", Hexagon::D7)
312 .Case("r17:16", Hexagon::D8)
313 .Case("r19:18", Hexagon::D9)
314 .Case("r21:20", Hexagon::D10)
315 .Case("r23:22", Hexagon::D11)
316 .Case("r25:24", Hexagon::D12)
317 .Case("r27:26", Hexagon::D13)
318 .Case("r29:28", Hexagon::D14)
319 .Case("r31:30", Hexagon::D15)
320 .Case("sp", Hexagon::R29)
321 .Case("fp", Hexagon::R30)
322 .Case("lr", Hexagon::R31)
323 .Case("p0", Hexagon::P0)
324 .Case("p1", Hexagon::P1)
325 .Case("p2", Hexagon::P2)
326 .Case("p3", Hexagon::P3)
327 .Case("sa0", Hexagon::SA0)
328 .Case("lc0", Hexagon::LC0)
329 .Case("sa1", Hexagon::SA1)
330 .Case("lc1", Hexagon::LC1)
331 .Case("m0", Hexagon::M0)
332 .Case("m1", Hexagon::M1)
333 .Case("usr", Hexagon::USR)
334 .Case("ugp", Hexagon::UGP)
335 .Case("cs0", Hexagon::CS0)
336 .Case("cs1", Hexagon::CS1)
337 .Default(Register());
338 if (Reg)
339 return Reg;
340
341 report_fatal_error("Invalid register name global variable");
342}
343
344/// LowerCallResult - Lower the result values of an ISD::CALL into the
345/// appropriate copies out of appropriate physical registers. This assumes that
346/// Chain/Glue are the input chain/glue to use, and that TheCall is the call
347/// being lowered. Returns a SDNode with the same number of values as the
348/// ISD::CALL.
350 SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool IsVarArg,
351 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
353 const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const {
354 // Assign locations to each value returned by this call.
356
357 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
358 *DAG.getContext());
359
360 if (Subtarget.useHVXOps())
361 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon_HVX);
362 else
363 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
364
365 // Copy all of the result registers out of their specified physreg.
366 for (unsigned i = 0; i != RVLocs.size(); ++i) {
367 SDValue RetVal;
368 if (RVLocs[i].getValVT() == MVT::i1) {
369 // Return values of type MVT::i1 require special handling. The reason
370 // is that MVT::i1 is associated with the PredRegs register class, but
371 // values of that type are still returned in R0. Generate an explicit
372 // copy into a predicate register from R0, and treat the value of the
373 // predicate register as the call result.
374 auto &MRI = DAG.getMachineFunction().getRegInfo();
375 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
376 MVT::i32, Glue);
377 // FR0 = (Value, Chain, Glue)
378 Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
379 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
380 FR0.getValue(0), FR0.getValue(2));
381 // TPR = (Chain, Glue)
382 // Don't glue this CopyFromReg, because it copies from a virtual
383 // register. If it is glued to the call, InstrEmitter will add it
384 // as an implicit def to the call (EmitMachineNode).
385 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
386 Glue = TPR.getValue(1);
387 Chain = TPR.getValue(0);
388 } else {
389 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
390 RVLocs[i].getValVT(), Glue);
391 Glue = RetVal.getValue(2);
392 Chain = RetVal.getValue(1);
393 }
394 InVals.push_back(RetVal.getValue(0));
395 }
396
397 return Chain;
398}
399
400/// LowerCall - Functions arguments are copied from virtual regs to
401/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
404 SmallVectorImpl<SDValue> &InVals) const {
405 SelectionDAG &DAG = CLI.DAG;
406 SDLoc &dl = CLI.DL;
408 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
410 SDValue Chain = CLI.Chain;
411 SDValue Callee = CLI.Callee;
412 CallingConv::ID CallConv = CLI.CallConv;
413 bool IsVarArg = CLI.IsVarArg;
414 bool DoesNotReturn = CLI.DoesNotReturn;
415
416 bool IsStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
418 MachineFrameInfo &MFI = MF.getFrameInfo();
419 auto PtrVT = getPointerTy(MF.getDataLayout());
420
421 unsigned NumParams = CLI.CB ? CLI.CB->getFunctionType()->getNumParams() : 0;
422 if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee))
423 Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32);
424
425 // Linux ABI treats var-arg calls the same way as regular ones.
426 bool TreatAsVarArg = !Subtarget.isEnvironmentMusl() && IsVarArg;
427
428 // Analyze operands of the call, assigning locations to each operand.
430 HexagonCCState CCInfo(CallConv, TreatAsVarArg, MF, ArgLocs, *DAG.getContext(),
431 NumParams);
432
433 if (Subtarget.useHVXOps())
434 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_HVX);
436 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_Legacy);
437 else
438 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
439
440 if (CLI.IsTailCall) {
441 bool StructAttrFlag = MF.getFunction().hasStructRetAttr();
442 CLI.IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
443 IsVarArg, IsStructRet, StructAttrFlag, Outs,
444 OutVals, Ins, DAG);
445 for (const CCValAssign &VA : ArgLocs) {
446 if (VA.isMemLoc()) {
447 CLI.IsTailCall = false;
448 break;
449 }
450 }
451 LLVM_DEBUG(dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n"
452 : "Argument must be passed on stack. "
453 "Not eligible for Tail Call\n"));
454 }
455 // Get a count of how many bytes are to be pushed on the stack.
456 unsigned NumBytes = CCInfo.getStackSize();
458 SmallVector<SDValue, 8> MemOpChains;
459
460 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
461 SDValue StackPtr =
462 DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
463
464 bool NeedsArgAlign = false;
465 Align LargestAlignSeen;
466 // Walk the register/memloc assignments, inserting copies/loads.
467 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
468 CCValAssign &VA = ArgLocs[i];
469 SDValue Arg = OutVals[i];
470 ISD::ArgFlagsTy Flags = Outs[i].Flags;
471 // Record if we need > 8 byte alignment on an argument.
472 bool ArgAlign = Subtarget.isHVXVectorType(VA.getValVT());
473 NeedsArgAlign |= ArgAlign;
474
475 // Promote the value if needed.
476 switch (VA.getLocInfo()) {
477 default:
478 // Loc info must be one of Full, BCvt, SExt, ZExt, or AExt.
479 llvm_unreachable("Unknown loc info!");
481 break;
483 Arg = DAG.getBitcast(VA.getLocVT(), Arg);
484 break;
486 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
487 break;
489 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
490 break;
492 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
493 break;
494 }
495
496 if (VA.isMemLoc()) {
497 unsigned LocMemOffset = VA.getLocMemOffset();
498 SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
499 StackPtr.getValueType());
500 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
501 if (ArgAlign)
502 LargestAlignSeen = std::max(
503 LargestAlignSeen, Align(VA.getLocVT().getStoreSizeInBits() / 8));
504 if (Flags.isByVal()) {
505 // The argument is a struct passed by value. According to LLVM, "Arg"
506 // is a pointer.
507 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
508 Flags, DAG, dl));
509 } else {
511 DAG.getMachineFunction(), LocMemOffset);
512 SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI);
513 MemOpChains.push_back(S);
514 }
515 continue;
516 }
517
518 // Arguments that can be passed on register must be kept at RegsToPass
519 // vector.
520 if (VA.isRegLoc())
521 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
522 }
523
524 if (NeedsArgAlign && Subtarget.hasV60Ops()) {
525 LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n");
526 Align VecAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
527 LargestAlignSeen = std::max(LargestAlignSeen, VecAlign);
528 MFI.ensureMaxAlignment(LargestAlignSeen);
529 }
530 // Transform all store nodes into one single node because all store
531 // nodes are independent of each other.
532 if (!MemOpChains.empty())
533 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
534
535 SDValue Glue;
536 if (!CLI.IsTailCall) {
537 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
538 Glue = Chain.getValue(1);
539 }
540
541 // Build a sequence of copy-to-reg nodes chained together with token
542 // chain and flag operands which copy the outgoing args into registers.
543 // The Glue is necessary since all emitted instructions must be
544 // stuck together.
545 if (!CLI.IsTailCall) {
546 for (const auto &R : RegsToPass) {
547 Chain = DAG.getCopyToReg(Chain, dl, R.first, R.second, Glue);
548 Glue = Chain.getValue(1);
549 }
550 } else {
551 // For tail calls lower the arguments to the 'real' stack slot.
552 //
553 // Force all the incoming stack arguments to be loaded from the stack
554 // before any new outgoing arguments are stored to the stack, because the
555 // outgoing stack slots may alias the incoming argument stack slots, and
556 // the alias isn't otherwise explicit. This is slightly more conservative
557 // than necessary, because it means that each store effectively depends
558 // on every argument instead of just those arguments it would clobber.
559 //
560 // Do not flag preceding copytoreg stuff together with the following stuff.
561 Glue = SDValue();
562 for (const auto &R : RegsToPass) {
563 Chain = DAG.getCopyToReg(Chain, dl, R.first, R.second, Glue);
564 Glue = Chain.getValue(1);
565 }
566 Glue = SDValue();
567 }
568
569 bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
570 unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
571
572 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
573 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
574 // node so that legalize doesn't hack it.
575 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
576 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
577 } else if (ExternalSymbolSDNode *S =
578 dyn_cast<ExternalSymbolSDNode>(Callee)) {
579 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
580 }
581
582 // Returns a chain & a flag for retval copy to use.
583 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
585 Ops.push_back(Chain);
586 Ops.push_back(Callee);
587
588 // Add argument registers to the end of the list so that they are
589 // known live into the call.
590 for (const auto &R : RegsToPass)
591 Ops.push_back(DAG.getRegister(R.first, R.second.getValueType()));
592
593 const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv);
594 assert(Mask && "Missing call preserved mask for calling convention");
595 Ops.push_back(DAG.getRegisterMask(Mask));
596
597 if (Glue.getNode())
598 Ops.push_back(Glue);
599
600 if (CLI.IsTailCall) {
601 MFI.setHasTailCall();
602 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
603 }
604
605 // Set this here because we need to know this for "hasFP" in frame lowering.
606 // The target-independent code calls getFrameRegister before setting it, and
607 // getFrameRegister uses hasFP to determine whether the function has FP.
608 MFI.setHasCalls(true);
609
610 unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
611 Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
612 Glue = Chain.getValue(1);
613
614 // Create the CALLSEQ_END node.
615 Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, Glue, dl);
616 Glue = Chain.getValue(1);
617
618 // Handle result values, copying them out of physregs into vregs that we
619 // return.
620 return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
621 InVals, OutVals, Callee);
622}
623
624/// Returns true by value, base pointer and offset pointer and addressing
625/// mode by reference if this node can be combined with a load / store to
626/// form a post-indexed load / store.
629 SelectionDAG &DAG) const {
630 LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(N);
631 if (!LSN)
632 return false;
633 EVT VT = LSN->getMemoryVT();
634 if (!VT.isSimple())
635 return false;
636 bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
637 VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 ||
638 VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
639 VT == MVT::v4i16 || VT == MVT::v8i8 ||
640 Subtarget.isHVXVectorType(VT.getSimpleVT());
641 if (!IsLegalType)
642 return false;
643
644 if (Op->getOpcode() != ISD::ADD)
645 return false;
646 Base = Op->getOperand(0);
647 Offset = Op->getOperand(1);
648 if (!isa<ConstantSDNode>(Offset.getNode()))
649 return false;
650 AM = ISD::POST_INC;
651
652 int32_t V = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
653 return Subtarget.getInstrInfo()->isValidAutoIncImm(VT, V);
654}
655
659 auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
660 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
661 unsigned LR = HRI.getRARegister();
662
663 if ((Op.getOpcode() != ISD::INLINEASM &&
664 Op.getOpcode() != ISD::INLINEASM_BR) || HMFI.hasClobberLR())
665 return Op;
666
667 unsigned NumOps = Op.getNumOperands();
668 if (Op.getOperand(NumOps-1).getValueType() == MVT::Glue)
669 --NumOps; // Ignore the flag operand.
670
671 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
672 const InlineAsm::Flag Flags(
673 cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue());
674 unsigned NumVals = Flags.getNumOperandRegisters();
675 ++i; // Skip the ID value.
676
677 switch (Flags.getKind()) {
678 default:
679 llvm_unreachable("Bad flags!");
683 i += NumVals;
684 break;
688 for (; NumVals; --NumVals, ++i) {
689 Register Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
690 if (Reg != LR)
691 continue;
692 HMFI.setHasClobberLR(true);
693 return Op;
694 }
695 break;
696 }
697 }
698 }
699
700 return Op;
701}
702
703// Need to transform ISD::PREFETCH into something that doesn't inherit
704// all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
705// SDNPMayStore.
707 SelectionDAG &DAG) const {
708 SDValue Chain = Op.getOperand(0);
709 SDValue Addr = Op.getOperand(1);
710 // Lower it to DCFETCH($reg, #0). A "pat" will try to merge the offset in,
711 // if the "reg" is fed by an "add".
712 SDLoc DL(Op);
713 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
714 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
715}
716
717// Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
718// is marked as having side-effects, while the register read on Hexagon does
719// not have any. TableGen refuses to accept the direct pattern from that node
720// to the A4_tfrcpp.
722 SelectionDAG &DAG) const {
723 SDValue Chain = Op.getOperand(0);
724 SDLoc dl(Op);
725 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other);
726 return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
727}
728
730 SelectionDAG &DAG) const {
731 SDValue Chain = Op.getOperand(0);
732 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
733 // Lower the hexagon_prefetch builtin to DCFETCH, as above.
734 if (IntNo == Intrinsic::hexagon_prefetch) {
735 SDValue Addr = Op.getOperand(2);
736 SDLoc DL(Op);
737 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
738 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
739 }
740 return SDValue();
741}
742
745 SelectionDAG &DAG) const {
746 SDValue Chain = Op.getOperand(0);
747 SDValue Size = Op.getOperand(1);
748 SDValue Align = Op.getOperand(2);
749 SDLoc dl(Op);
750
751 ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
752 assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
753
754 unsigned A = AlignConst->getSExtValue();
755 auto &HFI = *Subtarget.getFrameLowering();
756 // "Zero" means natural stack alignment.
757 if (A == 0)
758 A = HFI.getStackAlign().value();
759
760 LLVM_DEBUG({
761 dbgs () << __func__ << " Align: " << A << " Size: ";
762 Size.getNode()->dump(&DAG);
763 dbgs() << "\n";
764 });
765
766 SDValue AC = DAG.getConstant(A, dl, MVT::i32);
767 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
768 SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
769
771 return AA;
772}
773
775 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
776 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
777 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
779 MachineFrameInfo &MFI = MF.getFrameInfo();
781
782 // Linux ABI treats var-arg calls the same way as regular ones.
783 bool TreatAsVarArg = !Subtarget.isEnvironmentMusl() && IsVarArg;
784
785 // Assign locations to all of the incoming arguments.
787 HexagonCCState CCInfo(CallConv, TreatAsVarArg, MF, ArgLocs,
788 *DAG.getContext(),
790
791 if (Subtarget.useHVXOps())
792 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_HVX);
794 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_Legacy);
795 else
796 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
797
798 // For LLVM, in the case when returning a struct by value (>8byte),
799 // the first argument is a pointer that points to the location on caller's
800 // stack where the return value will be stored. For Hexagon, the location on
801 // caller's stack is passed only when the struct size is smaller than (and
802 // equal to) 8 bytes. If not, no address will be passed into callee and
803 // callee return the result direclty through R0/R1.
804 auto NextSingleReg = [] (const TargetRegisterClass &RC, unsigned Reg) {
805 switch (RC.getID()) {
806 case Hexagon::IntRegsRegClassID:
807 return Reg - Hexagon::R0 + 1;
808 case Hexagon::DoubleRegsRegClassID:
809 return (Reg - Hexagon::D0 + 1) * 2;
810 case Hexagon::HvxVRRegClassID:
811 return Reg - Hexagon::V0 + 1;
812 case Hexagon::HvxWRRegClassID:
813 return (Reg - Hexagon::W0 + 1) * 2;
814 }
815 llvm_unreachable("Unexpected register class");
816 };
817
818 auto &HFL = const_cast<HexagonFrameLowering&>(*Subtarget.getFrameLowering());
819 auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
820 HFL.FirstVarArgSavedReg = 0;
822
823 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
824 CCValAssign &VA = ArgLocs[i];
825 ISD::ArgFlagsTy Flags = Ins[i].Flags;
826 bool ByVal = Flags.isByVal();
827
828 // Arguments passed in registers:
829 // 1. 32- and 64-bit values and HVX vectors are passed directly,
830 // 2. Large structs are passed via an address, and the address is
831 // passed in a register.
832 if (VA.isRegLoc() && ByVal && Flags.getByValSize() <= 8)
833 llvm_unreachable("ByValSize must be bigger than 8 bytes");
834
835 bool InReg = VA.isRegLoc() &&
836 (!ByVal || (ByVal && Flags.getByValSize() > 8));
837
838 if (InReg) {
839 MVT RegVT = VA.getLocVT();
840 if (VA.getLocInfo() == CCValAssign::BCvt)
841 RegVT = VA.getValVT();
842
843 const TargetRegisterClass *RC = getRegClassFor(RegVT);
844 Register VReg = MRI.createVirtualRegister(RC);
845 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
846
847 // Treat values of type MVT::i1 specially: they are passed in
848 // registers of type i32, but they need to remain as values of
849 // type i1 for consistency of the argument lowering.
850 if (VA.getValVT() == MVT::i1) {
851 assert(RegVT.getSizeInBits() <= 32);
852 SDValue T = DAG.getNode(ISD::AND, dl, RegVT,
853 Copy, DAG.getConstant(1, dl, RegVT));
854 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT),
855 ISD::SETNE);
856 } else {
857#ifndef NDEBUG
858 unsigned RegSize = RegVT.getSizeInBits();
859 assert(RegSize == 32 || RegSize == 64 ||
860 Subtarget.isHVXVectorType(RegVT));
861#endif
862 }
863 InVals.push_back(Copy);
864 MRI.addLiveIn(VA.getLocReg(), VReg);
865 HFL.FirstVarArgSavedReg = NextSingleReg(*RC, VA.getLocReg());
866 } else {
867 assert(VA.isMemLoc() && "Argument should be passed in memory");
868
869 // If it's a byval parameter, then we need to compute the
870 // "real" size, not the size of the pointer.
871 unsigned ObjSize = Flags.isByVal()
872 ? Flags.getByValSize()
873 : VA.getLocVT().getStoreSizeInBits() / 8;
874
875 // Create the frame index object for this incoming parameter.
877 int FI = MFI.CreateFixedObject(ObjSize, Offset, true);
878 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
879
880 if (Flags.isByVal()) {
881 // If it's a pass-by-value aggregate, then do not dereference the stack
882 // location. Instead, we should generate a reference to the stack
883 // location.
884 InVals.push_back(FIN);
885 } else {
886 SDValue L = DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
888 InVals.push_back(L);
889 }
890 }
891 }
892
893 if (IsVarArg && Subtarget.isEnvironmentMusl()) {
894 for (int i = HFL.FirstVarArgSavedReg; i < 6; i++)
895 MRI.addLiveIn(Hexagon::R0+i);
896 }
897
898 if (IsVarArg && Subtarget.isEnvironmentMusl()) {
899 HMFI.setFirstNamedArgFrameIndex(HMFI.getFirstNamedArgFrameIndex() - 1);
900 HMFI.setLastNamedArgFrameIndex(-int(MFI.getNumFixedObjects()));
901
902 // Create Frame index for the start of register saved area.
903 int NumVarArgRegs = 6 - HFL.FirstVarArgSavedReg;
904 bool RequiresPadding = (NumVarArgRegs & 1);
905 int RegSaveAreaSizePlusPadding = RequiresPadding
906 ? (NumVarArgRegs + 1) * 4
907 : NumVarArgRegs * 4;
908
909 if (RegSaveAreaSizePlusPadding > 0) {
910 // The offset to saved register area should be 8 byte aligned.
911 int RegAreaStart = HEXAGON_LRFP_SIZE + CCInfo.getStackSize();
912 if (!(RegAreaStart % 8))
913 RegAreaStart = (RegAreaStart + 7) & -8;
914
915 int RegSaveAreaFrameIndex =
916 MFI.CreateFixedObject(RegSaveAreaSizePlusPadding, RegAreaStart, true);
917 HMFI.setRegSavedAreaStartFrameIndex(RegSaveAreaFrameIndex);
918
919 // This will point to the next argument passed via stack.
920 int Offset = RegAreaStart + RegSaveAreaSizePlusPadding;
921 int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true);
922 HMFI.setVarArgsFrameIndex(FI);
923 } else {
924 // This will point to the next argument passed via stack, when
925 // there is no saved register area.
926 int Offset = HEXAGON_LRFP_SIZE + CCInfo.getStackSize();
927 int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true);
928 HMFI.setRegSavedAreaStartFrameIndex(FI);
929 HMFI.setVarArgsFrameIndex(FI);
930 }
931 }
932
933
934 if (IsVarArg && !Subtarget.isEnvironmentMusl()) {
935 // This will point to the next argument passed via stack.
936 int Offset = HEXAGON_LRFP_SIZE + CCInfo.getStackSize();
937 int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true);
938 HMFI.setVarArgsFrameIndex(FI);
939 }
940
941 return Chain;
942}
943
946 // VASTART stores the address of the VarArgsFrameIndex slot into the
947 // memory location argument.
950 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
951 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
952
953 if (!Subtarget.isEnvironmentMusl()) {
954 return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1),
956 }
957 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
958 auto &HFL = *Subtarget.getFrameLowering();
959 SDLoc DL(Op);
961
962 // Get frame index of va_list.
963 SDValue FIN = Op.getOperand(1);
964
965 // If first Vararg register is odd, add 4 bytes to start of
966 // saved register area to point to the first register location.
967 // This is because the saved register area has to be 8 byte aligned.
968 // Incase of an odd start register, there will be 4 bytes of padding in
969 // the beginning of saved register area. If all registers area used up,
970 // the following condition will handle it correctly.
971 SDValue SavedRegAreaStartFrameIndex =
972 DAG.getFrameIndex(FuncInfo.getRegSavedAreaStartFrameIndex(), MVT::i32);
973
974 auto PtrVT = getPointerTy(DAG.getDataLayout());
975
976 if (HFL.FirstVarArgSavedReg & 1)
977 SavedRegAreaStartFrameIndex =
978 DAG.getNode(ISD::ADD, DL, PtrVT,
979 DAG.getFrameIndex(FuncInfo.getRegSavedAreaStartFrameIndex(),
980 MVT::i32),
981 DAG.getIntPtrConstant(4, DL));
982
983 // Store the saved register area start pointer.
984 SDValue Store =
985 DAG.getStore(Op.getOperand(0), DL,
986 SavedRegAreaStartFrameIndex,
987 FIN, MachinePointerInfo(SV));
988 MemOps.push_back(Store);
989
990 // Store saved register area end pointer.
991 FIN = DAG.getNode(ISD::ADD, DL, PtrVT,
992 FIN, DAG.getIntPtrConstant(4, DL));
993 Store = DAG.getStore(Op.getOperand(0), DL,
994 DAG.getFrameIndex(FuncInfo.getVarArgsFrameIndex(),
995 PtrVT),
996 FIN, MachinePointerInfo(SV, 4));
997 MemOps.push_back(Store);
998
999 // Store overflow area pointer.
1000 FIN = DAG.getNode(ISD::ADD, DL, PtrVT,
1001 FIN, DAG.getIntPtrConstant(4, DL));
1002 Store = DAG.getStore(Op.getOperand(0), DL,
1003 DAG.getFrameIndex(FuncInfo.getVarArgsFrameIndex(),
1004 PtrVT),
1005 FIN, MachinePointerInfo(SV, 8));
1006 MemOps.push_back(Store);
1007
1008 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
1009}
1010
1011SDValue
1013 // Assert that the linux ABI is enabled for the current compilation.
1014 assert(Subtarget.isEnvironmentMusl() && "Linux ABI should be enabled");
1015 SDValue Chain = Op.getOperand(0);
1016 SDValue DestPtr = Op.getOperand(1);
1017 SDValue SrcPtr = Op.getOperand(2);
1018 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1019 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1020 SDLoc DL(Op);
1021 // Size of the va_list is 12 bytes as it has 3 pointers. Therefore,
1022 // we need to memcopy 12 bytes from va_list to another similar list.
1023 return DAG.getMemcpy(Chain, DL, DestPtr, SrcPtr,
1024 DAG.getIntPtrConstant(12, DL), Align(4),
1025 /*isVolatile*/ false, false, false,
1026 MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV));
1027}
1028
1030 const SDLoc &dl(Op);
1031 SDValue LHS = Op.getOperand(0);
1032 SDValue RHS = Op.getOperand(1);
1033 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1034 MVT ResTy = ty(Op);
1035 MVT OpTy = ty(LHS);
1036
1037 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1038 MVT ElemTy = OpTy.getVectorElementType();
1039 assert(ElemTy.isScalarInteger());
1041 OpTy.getVectorNumElements());
1042 return DAG.getSetCC(dl, ResTy,
1043 DAG.getSExtOrTrunc(LHS, SDLoc(LHS), WideTy),
1044 DAG.getSExtOrTrunc(RHS, SDLoc(RHS), WideTy), CC);
1045 }
1046
1047 // Treat all other vector types as legal.
1048 if (ResTy.isVector())
1049 return Op;
1050
1051 // Comparisons of short integers should use sign-extend, not zero-extend,
1052 // since we can represent small negative values in the compare instructions.
1053 // The LLVM default is to use zero-extend arbitrarily in these cases.
1054 auto isSExtFree = [this](SDValue N) {
1055 switch (N.getOpcode()) {
1056 case ISD::TRUNCATE: {
1057 // A sign-extend of a truncate of a sign-extend is free.
1058 SDValue Op = N.getOperand(0);
1059 if (Op.getOpcode() != ISD::AssertSext)
1060 return false;
1061 EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT();
1062 unsigned ThisBW = ty(N).getSizeInBits();
1063 unsigned OrigBW = OrigTy.getSizeInBits();
1064 // The type that was sign-extended to get the AssertSext must be
1065 // narrower than the type of N (so that N has still the same value
1066 // as the original).
1067 return ThisBW >= OrigBW;
1068 }
1069 case ISD::LOAD:
1070 // We have sign-extended loads.
1071 return true;
1072 }
1073 return false;
1074 };
1075
1076 if (OpTy == MVT::i8 || OpTy == MVT::i16) {
1077 ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
1078 bool IsNegative = C && C->getAPIntValue().isNegative();
1079 if (IsNegative || isSExtFree(LHS) || isSExtFree(RHS))
1080 return DAG.getSetCC(dl, ResTy,
1081 DAG.getSExtOrTrunc(LHS, SDLoc(LHS), MVT::i32),
1082 DAG.getSExtOrTrunc(RHS, SDLoc(RHS), MVT::i32), CC);
1083 }
1084
1085 return SDValue();
1086}
1087
1088SDValue
1090 SDValue PredOp = Op.getOperand(0);
1091 SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
1092 MVT OpTy = ty(Op1);
1093 const SDLoc &dl(Op);
1094
1095 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1096 MVT ElemTy = OpTy.getVectorElementType();
1097 assert(ElemTy.isScalarInteger());
1099 OpTy.getVectorNumElements());
1100 // Generate (trunc (select (_, sext, sext))).
1101 return DAG.getSExtOrTrunc(
1102 DAG.getSelect(dl, WideTy, PredOp,
1103 DAG.getSExtOrTrunc(Op1, dl, WideTy),
1104 DAG.getSExtOrTrunc(Op2, dl, WideTy)),
1105 dl, OpTy);
1106 }
1107
1108 return SDValue();
1109}
1110
1111SDValue
1113 EVT ValTy = Op.getValueType();
1114 ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
1115 Constant *CVal = nullptr;
1116 bool isVTi1Type = false;
1117 if (auto *CV = dyn_cast<ConstantVector>(CPN->getConstVal())) {
1118 if (cast<VectorType>(CV->getType())->getElementType()->isIntegerTy(1)) {
1119 IRBuilder<> IRB(CV->getContext());
1121 unsigned VecLen = CV->getNumOperands();
1122 assert(isPowerOf2_32(VecLen) &&
1123 "conversion only supported for pow2 VectorSize");
1124 for (unsigned i = 0; i < VecLen; ++i)
1125 NewConst.push_back(IRB.getInt8(CV->getOperand(i)->isZeroValue()));
1126
1127 CVal = ConstantVector::get(NewConst);
1128 isVTi1Type = true;
1129 }
1130 }
1131 Align Alignment = CPN->getAlign();
1132 bool IsPositionIndependent = isPositionIndependent();
1133 unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
1134
1135 unsigned Offset = 0;
1136 SDValue T;
1137 if (CPN->isMachineConstantPoolEntry())
1138 T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Alignment,
1139 Offset, TF);
1140 else if (isVTi1Type)
1141 T = DAG.getTargetConstantPool(CVal, ValTy, Alignment, Offset, TF);
1142 else
1143 T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Alignment, Offset,
1144 TF);
1145
1146 assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&
1147 "Inconsistent target flag encountered");
1148
1149 if (IsPositionIndependent)
1150 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
1151 return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
1152}
1153
1154SDValue
1156 EVT VT = Op.getValueType();
1157 int Idx = cast<JumpTableSDNode>(Op)->getIndex();
1158 if (isPositionIndependent()) {
1160 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
1161 }
1162
1163 SDValue T = DAG.getTargetJumpTable(Idx, VT);
1164 return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
1165}
1166
1167SDValue
1169 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1171 MachineFrameInfo &MFI = MF.getFrameInfo();
1172 MFI.setReturnAddressIsTaken(true);
1173
1175 return SDValue();
1176
1177 EVT VT = Op.getValueType();
1178 SDLoc dl(Op);
1179 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1180 if (Depth) {
1181 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1182 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1183 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1184 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1186 }
1187
1188 // Return LR, which contains the return address. Mark it an implicit live-in.
1189 Register Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
1190 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1191}
1192
1193SDValue
1195 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1197 MFI.setFrameAddressIsTaken(true);
1198
1199 EVT VT = Op.getValueType();
1200 SDLoc dl(Op);
1201 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1202 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1203 HRI.getFrameRegister(), VT);
1204 while (Depth--)
1205 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1207 return FrameAddr;
1208}
1209
1210SDValue
1212 SDLoc dl(Op);
1213 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1214}
1215
1216SDValue
1218 SDLoc dl(Op);
1219 auto *GAN = cast<GlobalAddressSDNode>(Op);
1220 auto PtrVT = getPointerTy(DAG.getDataLayout());
1221 auto *GV = GAN->getGlobal();
1222 int64_t Offset = GAN->getOffset();
1223
1224 auto &HLOF = *HTM.getObjFileLowering();
1226
1227 if (RM == Reloc::Static) {
1228 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1229 const GlobalObject *GO = GV->getAliaseeObject();
1230 if (GO && Subtarget.useSmallData() && HLOF.isGlobalInSmallSection(GO, HTM))
1231 return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1232 return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1233 }
1234
1235 bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1236 if (UsePCRel) {
1237 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
1239 return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1240 }
1241
1242 // Use GOT index.
1243 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1244 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1245 SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
1246 return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1247}
1248
1249// Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1250SDValue
1252 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1253 SDLoc dl(Op);
1254 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1255
1257 if (RM == Reloc::Static) {
1258 SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
1259 return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
1260 }
1261
1263 return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1264}
1265
1266SDValue
1268 const {
1269 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1272 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1273}
1274
1275SDValue
1277 GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg,
1278 unsigned char OperandFlags) const {
1280 MachineFrameInfo &MFI = MF.getFrameInfo();
1281 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1282 SDLoc dl(GA);
1283 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
1284 GA->getValueType(0),
1285 GA->getOffset(),
1286 OperandFlags);
1287 // Create Operands for the call.The Operands should have the following:
1288 // 1. Chain SDValue
1289 // 2. Callee which in this case is the Global address value.
1290 // 3. Registers live into the call.In this case its R0, as we
1291 // have just one argument to be passed.
1292 // 4. Glue.
1293 // Note: The order is important.
1294
1295 const auto &HRI = *Subtarget.getRegisterInfo();
1296 const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallingConv::C);
1297 assert(Mask && "Missing call preserved mask for calling convention");
1298 SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT),
1299 DAG.getRegisterMask(Mask), Glue };
1300 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1301
1302 // Inform MFI that function has calls.
1303 MFI.setAdjustsStack(true);
1304
1305 Glue = Chain.getValue(1);
1306 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue);
1307}
1308
1309//
1310// Lower using the intial executable model for TLS addresses
1311//
1312SDValue
1314 SelectionDAG &DAG) const {
1315 SDLoc dl(GA);
1316 int64_t Offset = GA->getOffset();
1317 auto PtrVT = getPointerTy(DAG.getDataLayout());
1318
1319 // Get the thread pointer.
1320 SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1321
1322 bool IsPositionIndependent = isPositionIndependent();
1323 unsigned char TF =
1324 IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;
1325
1326 // First generate the TLS symbol address
1327 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
1328 Offset, TF);
1329
1330 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1331
1332 if (IsPositionIndependent) {
1333 // Generate the GOT pointer in case of position independent code
1335
1336 // Add the TLS Symbol address to GOT pointer.This gives
1337 // GOT relative relocation for the symbol.
1338 Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1339 }
1340
1341 // Load the offset value for TLS symbol.This offset is relative to
1342 // thread pointer.
1343 SDValue LoadOffset =
1344 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Sym, MachinePointerInfo());
1345
1346 // Address of the thread local variable is the add of thread
1347 // pointer and the offset of the variable.
1348 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1349}
1350
1351//
1352// Lower using the local executable model for TLS addresses
1353//
1354SDValue
1356 SelectionDAG &DAG) const {
1357 SDLoc dl(GA);
1358 int64_t Offset = GA->getOffset();
1359 auto PtrVT = getPointerTy(DAG.getDataLayout());
1360
1361 // Get the thread pointer.
1362 SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1363 // Generate the TLS symbol address
1364 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1366 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1367
1368 // Address of the thread local variable is the add of thread
1369 // pointer and the offset of the variable.
1370 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1371}
1372
1373//
1374// Lower using the general dynamic model for TLS addresses
1375//
1376SDValue
1378 SelectionDAG &DAG) const {
1379 SDLoc dl(GA);
1380 int64_t Offset = GA->getOffset();
1381 auto PtrVT = getPointerTy(DAG.getDataLayout());
1382
1383 // First generate the TLS symbol address
1384 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1386
1387 // Then, generate the GOT pointer
1388 SDValue GOT = LowerGLOBAL_OFFSET_TABLE(TGA, DAG);
1389
1390 // Add the TLS symbol and the GOT pointer
1391 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1392 SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1393
1394 // Copy over the argument to R0
1395 SDValue InGlue;
1396 Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InGlue);
1397 InGlue = Chain.getValue(1);
1398
1399 unsigned Flags = DAG.getSubtarget<HexagonSubtarget>().useLongCalls()
1402
1403 return GetDynamicTLSAddr(DAG, Chain, GA, InGlue, PtrVT,
1404 Hexagon::R0, Flags);
1405}
1406
1407//
1408// Lower TLS addresses.
1409//
1410// For now for dynamic models, we only support the general dynamic model.
1411//
1412SDValue
1414 SelectionDAG &DAG) const {
1415 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1416
1417 switch (HTM.getTLSModel(GA->getGlobal())) {
1420 return LowerToTLSGeneralDynamicModel(GA, DAG);
1422 return LowerToTLSInitialExecModel(GA, DAG);
1424 return LowerToTLSLocalExecModel(GA, DAG);
1425 }
1426 llvm_unreachable("Bogus TLS model");
1427}
1428
1429//===----------------------------------------------------------------------===//
1430// TargetLowering Implementation
1431//===----------------------------------------------------------------------===//
1432
1434 const HexagonSubtarget &ST)
1435 : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1436 Subtarget(ST) {
1437 auto &HRI = *Subtarget.getRegisterInfo();
1438
1442 setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1445
1448
1451 else
1453
1454 // Limits for inline expansion of memcpy/memmove
1461
1462 //
1463 // Set up register classes.
1464 //
1465
1466 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1467 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1468 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1469 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1470 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1471 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1472 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1473 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1474 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1475 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1476 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1477
1478 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1479 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1480
1481 //
1482 // Handling of scalar operations.
1483 //
1484 // All operations default to "legal", except:
1485 // - indexed loads and stores (pre-/post-incremented),
1486 // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1487 // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1488 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1489 // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1490 // which default to "expand" for at least one type.
1491
1492 // Misc operations.
1495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1509
1510 // Custom legalize GlobalAddress nodes into CONST32.
1514
1515 // Hexagon needs to optimize cases with negative constants.
1519 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1520
1521 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1523 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1524 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1525 if (Subtarget.isEnvironmentMusl())
1527 else
1529
1533
1534 if (EmitJumpTables)
1536 else
1537 setMinimumJumpTableEntries(std::numeric_limits<unsigned>::max());
1538 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1539
1540 for (unsigned LegalIntOp :
1542 setOperationAction(LegalIntOp, MVT::i32, Legal);
1543 setOperationAction(LegalIntOp, MVT::i64, Legal);
1544 }
1545
1546 // Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit,
1547 // but they only operate on i64.
1548 for (MVT VT : MVT::integer_valuetypes()) {
1555 }
1558
1563
1564 // Popcount can count # of 1s in i64 but returns i32.
1569
1574
1579
1580 for (unsigned IntExpOp :
1585 for (MVT VT : MVT::integer_valuetypes())
1586 setOperationAction(IntExpOp, VT, Expand);
1587 }
1588
1589 for (unsigned FPExpOp :
1592 for (MVT VT : MVT::fp_valuetypes())
1593 setOperationAction(FPExpOp, VT, Expand);
1594 }
1595
1596 // No extending loads from i32.
1597 for (MVT VT : MVT::integer_valuetypes()) {
1598 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1599 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
1600 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
1601 }
1602 // Turn FP truncstore into trunc + store.
1603 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1604 // Turn FP extload into load/fpextend.
1605 for (MVT VT : MVT::fp_valuetypes())
1606 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1607
1608 // Expand BR_CC and SELECT_CC for all integer and fp types.
1609 for (MVT VT : MVT::integer_valuetypes()) {
1612 }
1613 for (MVT VT : MVT::fp_valuetypes()) {
1616 }
1617 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1618
1619 //
1620 // Handling of vector operations.
1621 //
1622
1623 // Set the action for vector operations to "expand", then override it with
1624 // either "custom" or "legal" for specific cases.
1625 static const unsigned VectExpOps[] = {
1626 // Integer arithmetic:
1630 // Logical/bit:
1633 // Floating point arithmetic/math functions:
1640 // Misc:
1642 // Vector:
1648 };
1649
1651 for (unsigned VectExpOp : VectExpOps)
1652 setOperationAction(VectExpOp, VT, Expand);
1653
1654 // Expand all extending loads and truncating stores:
1655 for (MVT TargetVT : MVT::fixedlen_vector_valuetypes()) {
1656 if (TargetVT == VT)
1657 continue;
1658 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1659 setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1660 setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
1661 setTruncStoreAction(VT, TargetVT, Expand);
1662 }
1663
1664 // Normalize all inputs to SELECT to be vectors of i32.
1665 if (VT.getVectorElementType() != MVT::i32) {
1666 MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
1668 AddPromotedToType(ISD::SELECT, VT, VT32);
1669 }
1673 }
1674
1675 // Extending loads from (native) vectors of i8 into (native) vectors of i16
1676 // are legal.
1677 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1678 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1679 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1680 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1681 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1682 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1683
1687
1688 // Types natively supported:
1689 for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
1690 MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
1697
1698 setOperationAction(ISD::ADD, NativeVT, Legal);
1699 setOperationAction(ISD::SUB, NativeVT, Legal);
1700 setOperationAction(ISD::MUL, NativeVT, Legal);
1701 setOperationAction(ISD::AND, NativeVT, Legal);
1702 setOperationAction(ISD::OR, NativeVT, Legal);
1703 setOperationAction(ISD::XOR, NativeVT, Legal);
1704
1705 if (NativeVT.getVectorElementType() != MVT::i1) {
1709 }
1710 }
1711
1712 for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) {
1717 }
1718
1719 // Custom lower unaligned loads.
1720 // Also, for both loads and stores, verify the alignment of the address
1721 // in case it is a compile-time constant. This is a usability feature to
1722 // provide a meaningful error message to users.
1723 for (MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8,
1724 MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
1727 }
1728
1729 // Custom-lower load/stores of boolean vectors.
1730 for (MVT VT : {MVT::v2i1, MVT::v4i1, MVT::v8i1}) {
1733 }
1734
1735 // Normalize integer compares to EQ/GT/UGT
1736 for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16,
1737 MVT::v2i32}) {
1745 }
1746
1747 // Normalize boolean compares to [U]LE/[U]LT
1748 for (MVT VT : {MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1}) {
1753 }
1754
1755 // Custom-lower bitcasts from i8 to v8i1.
1757 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1763
1764 // V5+.
1769
1772
1785
1786 // Special handling for half-precision floating point conversions.
1787 // Lower half float conversions into library calls.
1792
1793 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
1794 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
1795 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1796 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1797
1798 // Handling of indexed loads/stores: default is "expand".
1799 //
1800 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64, MVT::f32, MVT::f64,
1801 MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) {
1804 }
1805
1806 // Subtarget-specific operation actions.
1807 //
1808 if (Subtarget.hasV60Ops()) {
1813 }
1814 if (Subtarget.hasV66Ops()) {
1817 }
1818 if (Subtarget.hasV67Ops()) {
1822 }
1823
1827
1828 if (Subtarget.useHVXOps())
1829 initializeHVXLowering();
1830
1832
1833 //
1834 // Library calls for unsupported operations
1835 //
1836 bool FastMath = EnableFastMath;
1837
1838 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1839 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1840 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1841 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1842 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1843 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1844 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1845 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1846
1847 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1848 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1849 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1850 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1851 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1852 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1853
1854 // This is the only fast library function for sqrtd.
1855 if (FastMath)
1856 setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
1857
1858 // Prefix is: nothing for "slow-math",
1859 // "fast2_" for V5+ fast-math double-precision
1860 // (actually, keep fast-math and fast-math2 separate for now)
1861 if (FastMath) {
1862 setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
1863 setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
1864 setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
1865 setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
1866 setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
1867 } else {
1868 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1869 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1870 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1871 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1872 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1873 }
1874
1875 if (FastMath)
1876 setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
1877 else
1878 setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
1879
1880 // Routines to handle fp16 storage type.
1881 setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
1882 setLibcallName(RTLIB::FPROUND_F64_F16, "__truncdfhf2");
1883 setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
1884
1885 // These cause problems when the shift amount is non-constant.
1886 setLibcallName(RTLIB::SHL_I128, nullptr);
1887 setLibcallName(RTLIB::SRL_I128, nullptr);
1888 setLibcallName(RTLIB::SRA_I128, nullptr);
1889}
1890
1891const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1892 switch ((HexagonISD::NodeType)Opcode) {
1893 case HexagonISD::ADDC: return "HexagonISD::ADDC";
1894 case HexagonISD::SUBC: return "HexagonISD::SUBC";
1895 case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
1896 case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
1897 case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
1898 case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
1899 case HexagonISD::CALL: return "HexagonISD::CALL";
1900 case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
1901 case HexagonISD::CALLR: return "HexagonISD::CALLR";
1902 case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
1903 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1904 case HexagonISD::CONST32: return "HexagonISD::CONST32";
1905 case HexagonISD::CP: return "HexagonISD::CP";
1906 case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
1907 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1908 case HexagonISD::TSTBIT: return "HexagonISD::TSTBIT";
1909 case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
1910 case HexagonISD::INSERT: return "HexagonISD::INSERT";
1911 case HexagonISD::JT: return "HexagonISD::JT";
1912 case HexagonISD::RET_GLUE: return "HexagonISD::RET_GLUE";
1913 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1914 case HexagonISD::VASL: return "HexagonISD::VASL";
1915 case HexagonISD::VASR: return "HexagonISD::VASR";
1916 case HexagonISD::VLSR: return "HexagonISD::VLSR";
1917 case HexagonISD::MFSHL: return "HexagonISD::MFSHL";
1918 case HexagonISD::MFSHR: return "HexagonISD::MFSHR";
1919 case HexagonISD::SSAT: return "HexagonISD::SSAT";
1920 case HexagonISD::USAT: return "HexagonISD::USAT";
1921 case HexagonISD::SMUL_LOHI: return "HexagonISD::SMUL_LOHI";
1922 case HexagonISD::UMUL_LOHI: return "HexagonISD::UMUL_LOHI";
1923 case HexagonISD::USMUL_LOHI: return "HexagonISD::USMUL_LOHI";
1924 case HexagonISD::VEXTRACTW: return "HexagonISD::VEXTRACTW";
1925 case HexagonISD::VINSERTW0: return "HexagonISD::VINSERTW0";
1926 case HexagonISD::VROR: return "HexagonISD::VROR";
1927 case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE";
1928 case HexagonISD::PTRUE: return "HexagonISD::PTRUE";
1929 case HexagonISD::PFALSE: return "HexagonISD::PFALSE";
1930 case HexagonISD::D2P: return "HexagonISD::D2P";
1931 case HexagonISD::P2D: return "HexagonISD::P2D";
1932 case HexagonISD::V2Q: return "HexagonISD::V2Q";
1933 case HexagonISD::Q2V: return "HexagonISD::Q2V";
1934 case HexagonISD::QCAT: return "HexagonISD::QCAT";
1935 case HexagonISD::QTRUE: return "HexagonISD::QTRUE";
1936 case HexagonISD::QFALSE: return "HexagonISD::QFALSE";
1937 case HexagonISD::TL_EXTEND: return "HexagonISD::TL_EXTEND";
1938 case HexagonISD::TL_TRUNCATE: return "HexagonISD::TL_TRUNCATE";
1939 case HexagonISD::TYPECAST: return "HexagonISD::TYPECAST";
1940 case HexagonISD::VALIGN: return "HexagonISD::VALIGN";
1941 case HexagonISD::VALIGNADDR: return "HexagonISD::VALIGNADDR";
1942 case HexagonISD::ISEL: return "HexagonISD::ISEL";
1943 case HexagonISD::OP_END: break;
1944 }
1945 return nullptr;
1946}
1947
1948bool
1949HexagonTargetLowering::validateConstPtrAlignment(SDValue Ptr, Align NeedAlign,
1950 const SDLoc &dl, SelectionDAG &DAG) const {
1951 auto *CA = dyn_cast<ConstantSDNode>(Ptr);
1952 if (!CA)
1953 return true;
1954 unsigned Addr = CA->getZExtValue();
1955 Align HaveAlign =
1956 Addr != 0 ? Align(1ull << llvm::countr_zero(Addr)) : NeedAlign;
1957 if (HaveAlign >= NeedAlign)
1958 return true;
1959
1960 static int DK_MisalignedTrap = llvm::getNextAvailablePluginDiagnosticKind();
1961
1962 struct DiagnosticInfoMisalignedTrap : public DiagnosticInfo {
1963 DiagnosticInfoMisalignedTrap(StringRef M)
1964 : DiagnosticInfo(DK_MisalignedTrap, DS_Remark), Msg(M) {}
1965 void print(DiagnosticPrinter &DP) const override {
1966 DP << Msg;
1967 }
1968 static bool classof(const DiagnosticInfo *DI) {
1969 return DI->getKind() == DK_MisalignedTrap;
1970 }
1971 StringRef Msg;
1972 };
1973
1974 std::string ErrMsg;
1975 raw_string_ostream O(ErrMsg);
1976 O << "Misaligned constant address: " << format_hex(Addr, 10)
1977 << " has alignment " << HaveAlign.value()
1978 << ", but the memory access requires " << NeedAlign.value();
1979 if (DebugLoc DL = dl.getDebugLoc())
1980 DL.print(O << ", at ");
1981 O << ". The instruction has been replaced with a trap.";
1982
1983 DAG.getContext()->diagnose(DiagnosticInfoMisalignedTrap(O.str()));
1984 return false;
1985}
1986
1987SDValue
1988HexagonTargetLowering::replaceMemWithUndef(SDValue Op, SelectionDAG &DAG)
1989 const {
1990 const SDLoc &dl(Op);
1991 auto *LS = cast<LSBaseSDNode>(Op.getNode());
1992 assert(!LS->isIndexed() && "Not expecting indexed ops on constant address");
1993
1994 SDValue Chain = LS->getChain();
1995 SDValue Trap = DAG.getNode(ISD::TRAP, dl, MVT::Other, Chain);
1996 if (LS->getOpcode() == ISD::LOAD)
1997 return DAG.getMergeValues({DAG.getUNDEF(ty(Op)), Trap}, dl);
1998 return Trap;
1999}
2000
2001// Bit-reverse Load Intrinsic: Check if the instruction is a bit reverse load
2002// intrinsic.
2003static bool isBrevLdIntrinsic(const Value *Inst) {
2004 unsigned ID = cast<IntrinsicInst>(Inst)->getIntrinsicID();
2005 return (ID == Intrinsic::hexagon_L2_loadrd_pbr ||
2006 ID == Intrinsic::hexagon_L2_loadri_pbr ||
2007 ID == Intrinsic::hexagon_L2_loadrh_pbr ||
2008 ID == Intrinsic::hexagon_L2_loadruh_pbr ||
2009 ID == Intrinsic::hexagon_L2_loadrb_pbr ||
2010 ID == Intrinsic::hexagon_L2_loadrub_pbr);
2011}
2012
2013// Bit-reverse Load Intrinsic :Crawl up and figure out the object from previous
2014// instruction. So far we only handle bitcast, extract value and bit reverse
2015// load intrinsic instructions. Should we handle CGEP ?
2017 if (Operator::getOpcode(V) == Instruction::ExtractValue ||
2018 Operator::getOpcode(V) == Instruction::BitCast)
2019 V = cast<Operator>(V)->getOperand(0);
2020 else if (isa<IntrinsicInst>(V) && isBrevLdIntrinsic(V))
2021 V = cast<Instruction>(V)->getOperand(0);
2022 return V;
2023}
2024
2025// Bit-reverse Load Intrinsic: For a PHI Node return either an incoming edge or
2026// a back edge. If the back edge comes from the intrinsic itself, the incoming
2027// edge is returned.
2028static Value *returnEdge(const PHINode *PN, Value *IntrBaseVal) {
2029 const BasicBlock *Parent = PN->getParent();
2030 int Idx = -1;
2031 for (unsigned i = 0, e = PN->getNumIncomingValues(); i < e; ++i) {
2032 BasicBlock *Blk = PN->getIncomingBlock(i);
2033 // Determine if the back edge is originated from intrinsic.
2034 if (Blk == Parent) {
2035 Value *BackEdgeVal = PN->getIncomingValue(i);
2036 Value *BaseVal;
2037 // Loop over till we return the same Value or we hit the IntrBaseVal.
2038 do {
2039 BaseVal = BackEdgeVal;
2040 BackEdgeVal = getBrevLdObject(BackEdgeVal);
2041 } while ((BaseVal != BackEdgeVal) && (IntrBaseVal != BackEdgeVal));
2042 // If the getBrevLdObject returns IntrBaseVal, we should return the
2043 // incoming edge.
2044 if (IntrBaseVal == BackEdgeVal)
2045 continue;
2046 Idx = i;
2047 break;
2048 } else // Set the node to incoming edge.
2049 Idx = i;
2050 }
2051 assert(Idx >= 0 && "Unexpected index to incoming argument in PHI");
2052 return PN->getIncomingValue(Idx);
2053}
2054
2055// Bit-reverse Load Intrinsic: Figure out the underlying object the base
2056// pointer points to, for the bit-reverse load intrinsic. Setting this to
2057// memoperand might help alias analysis to figure out the dependencies.
2059 Value *IntrBaseVal = V;
2060 Value *BaseVal;
2061 // Loop over till we return the same Value, implies we either figure out
2062 // the object or we hit a PHI
2063 do {
2064 BaseVal = V;
2065 V = getBrevLdObject(V);
2066 } while (BaseVal != V);
2067
2068 // Identify the object from PHINode.
2069 if (const PHINode *PN = dyn_cast<PHINode>(V))
2070 return returnEdge(PN, IntrBaseVal);
2071 // For non PHI nodes, the object is the last value returned by getBrevLdObject
2072 else
2073 return V;
2074}
2075
2076/// Given an intrinsic, checks if on the target the intrinsic will need to map
2077/// to a MemIntrinsicNode (touches memory). If this is the case, it returns
2078/// true and store the intrinsic information into the IntrinsicInfo that was
2079/// passed to the function.
2081 const CallInst &I,
2082 MachineFunction &MF,
2083 unsigned Intrinsic) const {
2084 switch (Intrinsic) {
2085 case Intrinsic::hexagon_L2_loadrd_pbr:
2086 case Intrinsic::hexagon_L2_loadri_pbr:
2087 case Intrinsic::hexagon_L2_loadrh_pbr:
2088 case Intrinsic::hexagon_L2_loadruh_pbr:
2089 case Intrinsic::hexagon_L2_loadrb_pbr:
2090 case Intrinsic::hexagon_L2_loadrub_pbr: {
2092 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
2093 auto &Cont = I.getCalledFunction()->getParent()->getContext();
2094 // The intrinsic function call is of the form { ElTy, i8* }
2095 // @llvm.hexagon.L2.loadXX.pbr(i8*, i32). The pointer and memory access type
2096 // should be derived from ElTy.
2097 Type *ElTy = I.getCalledFunction()->getReturnType()->getStructElementType(0);
2098 Info.memVT = MVT::getVT(ElTy);
2099 llvm::Value *BasePtrVal = I.getOperand(0);
2100 Info.ptrVal = getUnderLyingObjectForBrevLdIntr(BasePtrVal);
2101 // The offset value comes through Modifier register. For now, assume the
2102 // offset is 0.
2103 Info.offset = 0;
2104 Info.align = DL.getABITypeAlign(Info.memVT.getTypeForEVT(Cont));
2106 return true;
2107 }
2108 case Intrinsic::hexagon_V6_vgathermw:
2109 case Intrinsic::hexagon_V6_vgathermw_128B:
2110 case Intrinsic::hexagon_V6_vgathermh:
2111 case Intrinsic::hexagon_V6_vgathermh_128B:
2112 case Intrinsic::hexagon_V6_vgathermhw:
2113 case Intrinsic::hexagon_V6_vgathermhw_128B:
2114 case Intrinsic::hexagon_V6_vgathermwq:
2115 case Intrinsic::hexagon_V6_vgathermwq_128B:
2116 case Intrinsic::hexagon_V6_vgathermhq:
2117 case Intrinsic::hexagon_V6_vgathermhq_128B:
2118 case Intrinsic::hexagon_V6_vgathermhwq:
2119 case Intrinsic::hexagon_V6_vgathermhwq_128B: {
2120 const Module &M = *I.getParent()->getParent()->getParent();
2122 Type *VecTy = I.getArgOperand(1)->getType();
2123 Info.memVT = MVT::getVT(VecTy);
2124 Info.ptrVal = I.getArgOperand(0);
2125 Info.offset = 0;
2126 Info.align =
2127 MaybeAlign(M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8);
2131 return true;
2132 }
2133 default:
2134 break;
2135 }
2136 return false;
2137}
2138
2140 return X.getValueType().isScalarInteger(); // 'tstbit'
2141}
2142
2144 return isTruncateFree(EVT::getEVT(Ty1), EVT::getEVT(Ty2));
2145}
2146
2148 if (!VT1.isSimple() || !VT2.isSimple())
2149 return false;
2150 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32;
2151}
2152
2154 const MachineFunction &MF, EVT VT) const {
2156}
2157
2158// Should we expand the build vector with shuffles?
2160 unsigned DefinedValues) const {
2161 return false;
2162}
2163
2165 unsigned Index) const {
2167 if (!ResVT.isSimple() || !SrcVT.isSimple())
2168 return false;
2169
2170 MVT ResTy = ResVT.getSimpleVT(), SrcTy = SrcVT.getSimpleVT();
2171 if (ResTy.getVectorElementType() != MVT::i1)
2172 return true;
2173
2174 // Non-HVX bool vectors are relatively cheap.
2175 return SrcTy.getVectorNumElements() <= 8;
2176}
2177
2179 return Op.getOpcode() == ISD::CONCAT_VECTORS ||
2181}
2182
2184 EVT VT) const {
2185 return true;
2186}
2187
2190 unsigned VecLen = VT.getVectorMinNumElements();
2191 MVT ElemTy = VT.getVectorElementType();
2192
2193 if (VecLen == 1 || VT.isScalableVector())
2195
2196 if (Subtarget.useHVXOps()) {
2197 unsigned Action = getPreferredHvxVectorAction(VT);
2198 if (Action != ~0u)
2199 return static_cast<TargetLoweringBase::LegalizeTypeAction>(Action);
2200 }
2201
2202 // Always widen (remaining) vectors of i1.
2203 if (ElemTy == MVT::i1)
2205 // Widen non-power-of-2 vectors. Such types cannot be split right now,
2206 // and computeRegisterProperties will override "split" with "widen",
2207 // which can cause other issues.
2208 if (!isPowerOf2_32(VecLen))
2210
2212}
2213
2216 if (Subtarget.useHVXOps()) {
2217 unsigned Action = getCustomHvxOperationAction(Op);
2218 if (Action != ~0u)
2219 return static_cast<TargetLoweringBase::LegalizeAction>(Action);
2220 }
2222}
2223
2224std::pair<SDValue, int>
2225HexagonTargetLowering::getBaseAndOffset(SDValue Addr) const {
2226 if (Addr.getOpcode() == ISD::ADD) {
2227 SDValue Op1 = Addr.getOperand(1);
2228 if (auto *CN = dyn_cast<const ConstantSDNode>(Op1.getNode()))
2229 return { Addr.getOperand(0), CN->getSExtValue() };
2230 }
2231 return { Addr, 0 };
2232}
2233
2234// Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
2235// to select data from, V3 is the permutation.
2236SDValue
2238 const {
2239 const auto *SVN = cast<ShuffleVectorSDNode>(Op);
2240 ArrayRef<int> AM = SVN->getMask();
2241 assert(AM.size() <= 8 && "Unexpected shuffle mask");
2242 unsigned VecLen = AM.size();
2243
2244 MVT VecTy = ty(Op);
2245 assert(!Subtarget.isHVXVectorType(VecTy, true) &&
2246 "HVX shuffles should be legal");
2247 assert(VecTy.getSizeInBits() <= 64 && "Unexpected vector length");
2248
2249 SDValue Op0 = Op.getOperand(0);
2250 SDValue Op1 = Op.getOperand(1);
2251 const SDLoc &dl(Op);
2252
2253 // If the inputs are not the same as the output, bail. This is not an
2254 // error situation, but complicates the handling and the default expansion
2255 // (into BUILD_VECTOR) should be adequate.
2256 if (ty(Op0) != VecTy || ty(Op1) != VecTy)
2257 return SDValue();
2258
2259 // Normalize the mask so that the first non-negative index comes from
2260 // the first operand.
2261 SmallVector<int,8> Mask(AM.begin(), AM.end());
2262 unsigned F = llvm::find_if(AM, [](int M) { return M >= 0; }) - AM.data();
2263 if (F == AM.size())
2264 return DAG.getUNDEF(VecTy);
2265 if (AM[F] >= int(VecLen)) {
2267 std::swap(Op0, Op1);
2268 }
2269
2270 // Express the shuffle mask in terms of bytes.
2271 SmallVector<int,8> ByteMask;
2272 unsigned ElemBytes = VecTy.getVectorElementType().getSizeInBits() / 8;
2273 for (int M : Mask) {
2274 if (M < 0) {
2275 for (unsigned j = 0; j != ElemBytes; ++j)
2276 ByteMask.push_back(-1);
2277 } else {
2278 for (unsigned j = 0; j != ElemBytes; ++j)
2279 ByteMask.push_back(M*ElemBytes + j);
2280 }
2281 }
2282 assert(ByteMask.size() <= 8);
2283
2284 // All non-undef (non-negative) indexes are well within [0..127], so they
2285 // fit in a single byte. Build two 64-bit words:
2286 // - MaskIdx where each byte is the corresponding index (for non-negative
2287 // indexes), and 0xFF for negative indexes, and
2288 // - MaskUnd that has 0xFF for each negative index.
2289 uint64_t MaskIdx = 0;
2290 uint64_t MaskUnd = 0;
2291 for (unsigned i = 0, e = ByteMask.size(); i != e; ++i) {
2292 unsigned S = 8*i;
2293 uint64_t M = ByteMask[i] & 0xFF;
2294 if (M == 0xFF)
2295 MaskUnd |= M << S;
2296 MaskIdx |= M << S;
2297 }
2298
2299 if (ByteMask.size() == 4) {
2300 // Identity.
2301 if (MaskIdx == (0x03020100 | MaskUnd))
2302 return Op0;
2303 // Byte swap.
2304 if (MaskIdx == (0x00010203 | MaskUnd)) {
2305 SDValue T0 = DAG.getBitcast(MVT::i32, Op0);
2306 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i32, T0);
2307 return DAG.getBitcast(VecTy, T1);
2308 }
2309
2310 // Byte packs.
2311 SDValue Concat10 =
2312 getCombine(Op1, Op0, dl, typeJoin({ty(Op1), ty(Op0)}), DAG);
2313 if (MaskIdx == (0x06040200 | MaskUnd))
2314 return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat10}, DAG);
2315 if (MaskIdx == (0x07050301 | MaskUnd))
2316 return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat10}, DAG);
2317
2318 SDValue Concat01 =
2319 getCombine(Op0, Op1, dl, typeJoin({ty(Op0), ty(Op1)}), DAG);
2320 if (MaskIdx == (0x02000604 | MaskUnd))
2321 return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat01}, DAG);
2322 if (MaskIdx == (0x03010705 | MaskUnd))
2323 return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat01}, DAG);
2324 }
2325
2326 if (ByteMask.size() == 8) {
2327 // Identity.
2328 if (MaskIdx == (0x0706050403020100ull | MaskUnd))
2329 return Op0;
2330 // Byte swap.
2331 if (MaskIdx == (0x0001020304050607ull | MaskUnd)) {
2332 SDValue T0 = DAG.getBitcast(MVT::i64, Op0);
2333 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i64, T0);
2334 return DAG.getBitcast(VecTy, T1);
2335 }
2336
2337 // Halfword picks.
2338 if (MaskIdx == (0x0d0c050409080100ull | MaskUnd))
2339 return getInstr(Hexagon::S2_shuffeh, dl, VecTy, {Op1, Op0}, DAG);
2340 if (MaskIdx == (0x0f0e07060b0a0302ull | MaskUnd))
2341 return getInstr(Hexagon::S2_shuffoh, dl, VecTy, {Op1, Op0}, DAG);
2342 if (MaskIdx == (0x0d0c090805040100ull | MaskUnd))
2343 return getInstr(Hexagon::S2_vtrunewh, dl, VecTy, {Op1, Op0}, DAG);
2344 if (MaskIdx == (0x0f0e0b0a07060302ull | MaskUnd))
2345 return getInstr(Hexagon::S2_vtrunowh, dl, VecTy, {Op1, Op0}, DAG);
2346 if (MaskIdx == (0x0706030205040100ull | MaskUnd)) {
2347 VectorPair P = opSplit(Op0, dl, DAG);
2348 return getInstr(Hexagon::S2_packhl, dl, VecTy, {P.second, P.first}, DAG);
2349 }
2350
2351 // Byte packs.
2352 if (MaskIdx == (0x0e060c040a020800ull | MaskUnd))
2353 return getInstr(Hexagon::S2_shuffeb, dl, VecTy, {Op1, Op0}, DAG);
2354 if (MaskIdx == (0x0f070d050b030901ull | MaskUnd))
2355 return getInstr(Hexagon::S2_shuffob, dl, VecTy, {Op1, Op0}, DAG);
2356 }
2357
2358 return SDValue();
2359}
2360
2361SDValue
2362HexagonTargetLowering::getSplatValue(SDValue Op, SelectionDAG &DAG) const {
2363 switch (Op.getOpcode()) {
2364 case ISD::BUILD_VECTOR:
2365 if (SDValue S = cast<BuildVectorSDNode>(Op)->getSplatValue())
2366 return S;
2367 break;
2368 case ISD::SPLAT_VECTOR:
2369 return Op.getOperand(0);
2370 }
2371 return SDValue();
2372}
2373
2374// Create a Hexagon-specific node for shifting a vector by an integer.
2375SDValue
2376HexagonTargetLowering::getVectorShiftByInt(SDValue Op, SelectionDAG &DAG)
2377 const {
2378 unsigned NewOpc;
2379 switch (Op.getOpcode()) {
2380 case ISD::SHL:
2381 NewOpc = HexagonISD::VASL;
2382 break;
2383 case ISD::SRA:
2384 NewOpc = HexagonISD::VASR;
2385 break;
2386 case ISD::SRL:
2387 NewOpc = HexagonISD::VLSR;
2388 break;
2389 default:
2390 llvm_unreachable("Unexpected shift opcode");
2391 }
2392
2393 if (SDValue Sp = getSplatValue(Op.getOperand(1), DAG))
2394 return DAG.getNode(NewOpc, SDLoc(Op), ty(Op), Op.getOperand(0), Sp);
2395 return SDValue();
2396}
2397
2398SDValue
2400 const SDLoc &dl(Op);
2401
2402 // First try to convert the shift (by vector) to a shift by a scalar.
2403 // If we first split the shift, the shift amount will become 'extract
2404 // subvector', and will no longer be recognized as scalar.
2405 SDValue Res = Op;
2406 if (SDValue S = getVectorShiftByInt(Op, DAG))
2407 Res = S;
2408
2409 unsigned Opc = Res.getOpcode();
2410 switch (Opc) {
2411 case HexagonISD::VASR:
2412 case HexagonISD::VLSR:
2413 case HexagonISD::VASL:
2414 break;
2415 default:
2416 // No instructions for shifts by non-scalars.
2417 return SDValue();
2418 }
2419
2420 MVT ResTy = ty(Res);
2421 if (ResTy.getVectorElementType() != MVT::i8)
2422 return Res;
2423
2424 // For shifts of i8, extend the inputs to i16, then truncate back to i8.
2425 assert(ResTy.getVectorElementType() == MVT::i8);
2426 SDValue Val = Res.getOperand(0), Amt = Res.getOperand(1);
2427
2428 auto ShiftPartI8 = [&dl, &DAG, this](unsigned Opc, SDValue V, SDValue A) {
2429 MVT Ty = ty(V);
2430 MVT ExtTy = MVT::getVectorVT(MVT::i16, Ty.getVectorNumElements());
2431 SDValue ExtV = Opc == HexagonISD::VASR ? DAG.getSExtOrTrunc(V, dl, ExtTy)
2432 : DAG.getZExtOrTrunc(V, dl, ExtTy);
2433 SDValue ExtS = DAG.getNode(Opc, dl, ExtTy, {ExtV, A});
2434 return DAG.getZExtOrTrunc(ExtS, dl, Ty);
2435 };
2436
2437 if (ResTy.getSizeInBits() == 32)
2438 return ShiftPartI8(Opc, Val, Amt);
2439
2440 auto [LoV, HiV] = opSplit(Val, dl, DAG);
2441 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy,
2442 {ShiftPartI8(Opc, LoV, Amt), ShiftPartI8(Opc, HiV, Amt)});
2443}
2444
2445SDValue
2447 if (isa<ConstantSDNode>(Op.getOperand(1).getNode()))
2448 return Op;
2449 return SDValue();
2450}
2451
2452SDValue
2454 MVT ResTy = ty(Op);
2455 SDValue InpV = Op.getOperand(0);
2456 MVT InpTy = ty(InpV);
2457 assert(ResTy.getSizeInBits() == InpTy.getSizeInBits());
2458 const SDLoc &dl(Op);
2459
2460 // Handle conversion from i8 to v8i1.
2461 if (InpTy == MVT::i8) {
2462 if (ResTy == MVT::v8i1) {
2463 SDValue Sc = DAG.getBitcast(tyScalar(InpTy), InpV);
2464 SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32);
2465 return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
2466 }
2467 return SDValue();
2468 }
2469
2470 return Op;
2471}
2472
2473bool
2474HexagonTargetLowering::getBuildVectorConstInts(ArrayRef<SDValue> Values,
2475 MVT VecTy, SelectionDAG &DAG,
2476 MutableArrayRef<ConstantInt*> Consts) const {
2477 MVT ElemTy = VecTy.getVectorElementType();
2478 unsigned ElemWidth = ElemTy.getSizeInBits();
2479 IntegerType *IntTy = IntegerType::get(*DAG.getContext(), ElemWidth);
2480 bool AllConst = true;
2481
2482 for (unsigned i = 0, e = Values.size(); i != e; ++i) {
2483 SDValue V = Values[i];
2484 if (V.isUndef()) {
2485 Consts[i] = ConstantInt::get(IntTy, 0);
2486 continue;
2487 }
2488 // Make sure to always cast to IntTy.
2489 if (auto *CN = dyn_cast<ConstantSDNode>(V.getNode())) {
2490 const ConstantInt *CI = CN->getConstantIntValue();
2491 Consts[i] = ConstantInt::get(IntTy, CI->getValue().getSExtValue());
2492 } else if (auto *CN = dyn_cast<ConstantFPSDNode>(V.getNode())) {
2493 const ConstantFP *CF = CN->getConstantFPValue();
2495 Consts[i] = ConstantInt::get(IntTy, A.getZExtValue());
2496 } else {
2497 AllConst = false;
2498 }
2499 }
2500 return AllConst;
2501}
2502
2503SDValue
2504HexagonTargetLowering::buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl,
2505 MVT VecTy, SelectionDAG &DAG) const {
2506 MVT ElemTy = VecTy.getVectorElementType();
2507 assert(VecTy.getVectorNumElements() == Elem.size());
2508
2509 SmallVector<ConstantInt*,4> Consts(Elem.size());
2510 bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2511
2512 unsigned First, Num = Elem.size();
2513 for (First = 0; First != Num; ++First) {
2514 if (!isUndef(Elem[First]))
2515 break;
2516 }
2517 if (First == Num)
2518 return DAG.getUNDEF(VecTy);
2519
2520 if (AllConst &&
2521 llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2522 return getZero(dl, VecTy, DAG);
2523
2524 if (ElemTy == MVT::i16 || ElemTy == MVT::f16) {
2525 assert(Elem.size() == 2);
2526 if (AllConst) {
2527 // The 'Consts' array will have all values as integers regardless
2528 // of the vector element type.
2529 uint32_t V = (Consts[0]->getZExtValue() & 0xFFFF) |
2530 Consts[1]->getZExtValue() << 16;
2531 return DAG.getBitcast(VecTy, DAG.getConstant(V, dl, MVT::i32));
2532 }
2533 SDValue E0, E1;
2534 if (ElemTy == MVT::f16) {
2535 E0 = DAG.getZExtOrTrunc(DAG.getBitcast(MVT::i16, Elem[0]), dl, MVT::i32);
2536 E1 = DAG.getZExtOrTrunc(DAG.getBitcast(MVT::i16, Elem[1]), dl, MVT::i32);
2537 } else {
2538 E0 = Elem[0];
2539 E1 = Elem[1];
2540 }
2541 SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {E1, E0}, DAG);
2542 return DAG.getBitcast(VecTy, N);
2543 }
2544
2545 if (ElemTy == MVT::i8) {
2546 // First try generating a constant.
2547 if (AllConst) {
2548 int32_t V = (Consts[0]->getZExtValue() & 0xFF) |
2549 (Consts[1]->getZExtValue() & 0xFF) << 8 |
2550 (Consts[2]->getZExtValue() & 0xFF) << 16 |
2551 Consts[3]->getZExtValue() << 24;
2552 return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32));
2553 }
2554
2555 // Then try splat.
2556 bool IsSplat = true;
2557 for (unsigned i = First+1; i != Num; ++i) {
2558 if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2559 continue;
2560 IsSplat = false;
2561 break;
2562 }
2563 if (IsSplat) {
2564 // Legalize the operand of SPLAT_VECTOR.
2565 SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
2566 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext);
2567 }
2568
2569 // Generate
2570 // (zxtb(Elem[0]) | (zxtb(Elem[1]) << 8)) |
2571 // (zxtb(Elem[2]) | (zxtb(Elem[3]) << 8)) << 16
2572 assert(Elem.size() == 4);
2573 SDValue Vs[4];
2574 for (unsigned i = 0; i != 4; ++i) {
2575 Vs[i] = DAG.getZExtOrTrunc(Elem[i], dl, MVT::i32);
2576 Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8);
2577 }
2578 SDValue S8 = DAG.getConstant(8, dl, MVT::i32);
2579 SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8});
2580 SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8});
2581 SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0});
2582 SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1});
2583
2584 SDValue R = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG);
2585 return DAG.getBitcast(MVT::v4i8, R);
2586 }
2587
2588#ifndef NDEBUG
2589 dbgs() << "VecTy: " << VecTy << '\n';
2590#endif
2591 llvm_unreachable("Unexpected vector element type");
2592}
2593
2594SDValue
2595HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl,
2596 MVT VecTy, SelectionDAG &DAG) const {
2597 MVT ElemTy = VecTy.getVectorElementType();
2598 assert(VecTy.getVectorNumElements() == Elem.size());
2599
2600 SmallVector<ConstantInt*,8> Consts(Elem.size());
2601 bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2602
2603 unsigned First, Num = Elem.size();
2604 for (First = 0; First != Num; ++First) {
2605 if (!isUndef(Elem[First]))
2606 break;
2607 }
2608 if (First == Num)
2609 return DAG.getUNDEF(VecTy);
2610
2611 if (AllConst &&
2612 llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2613 return getZero(dl, VecTy, DAG);
2614
2615 // First try splat if possible.
2616 if (ElemTy == MVT::i16 || ElemTy == MVT::f16) {
2617 bool IsSplat = true;
2618 for (unsigned i = First+1; i != Num; ++i) {
2619 if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2620 continue;
2621 IsSplat = false;
2622 break;
2623 }
2624 if (IsSplat) {
2625 // Legalize the operand of SPLAT_VECTOR
2626 SDValue S = ElemTy == MVT::f16 ? DAG.getBitcast(MVT::i16, Elem[First])
2627 : Elem[First];
2628 SDValue Ext = DAG.getZExtOrTrunc(S, dl, MVT::i32);
2629 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext);
2630 }
2631 }
2632
2633 // Then try constant.
2634 if (AllConst) {
2635 uint64_t Val = 0;
2636 unsigned W = ElemTy.getSizeInBits();
2637 uint64_t Mask = (1ull << W) - 1;
2638 for (unsigned i = 0; i != Num; ++i)
2639 Val = (Val << W) | (Consts[Num-1-i]->getZExtValue() & Mask);
2640 SDValue V0 = DAG.getConstant(Val, dl, MVT::i64);
2641 return DAG.getBitcast(VecTy, V0);
2642 }
2643
2644 // Build two 32-bit vectors and concatenate.
2645 MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2);
2646 SDValue L = (ElemTy == MVT::i32)
2647 ? Elem[0]
2648 : buildVector32(Elem.take_front(Num/2), dl, HalfTy, DAG);
2649 SDValue H = (ElemTy == MVT::i32)
2650 ? Elem[1]
2651 : buildVector32(Elem.drop_front(Num/2), dl, HalfTy, DAG);
2652 return getCombine(H, L, dl, VecTy, DAG);
2653}
2654
2655SDValue
2656HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV,
2657 const SDLoc &dl, MVT ValTy, MVT ResTy,
2658 SelectionDAG &DAG) const {
2659 MVT VecTy = ty(VecV);
2660 assert(!ValTy.isVector() ||
2661 VecTy.getVectorElementType() == ValTy.getVectorElementType());
2662 if (VecTy.getVectorElementType() == MVT::i1)
2663 return extractVectorPred(VecV, IdxV, dl, ValTy, ResTy, DAG);
2664
2665 unsigned VecWidth = VecTy.getSizeInBits();
2666 unsigned ValWidth = ValTy.getSizeInBits();
2667 unsigned ElemWidth = VecTy.getVectorElementType().getSizeInBits();
2668 assert((VecWidth % ElemWidth) == 0);
2669 assert(VecWidth == 32 || VecWidth == 64);
2670
2671 // Cast everything to scalar integer types.
2672 MVT ScalarTy = tyScalar(VecTy);
2673 VecV = DAG.getBitcast(ScalarTy, VecV);
2674
2675 SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2676 SDValue ExtV;
2677
2678 if (auto *IdxN = dyn_cast<ConstantSDNode>(IdxV)) {
2679 unsigned Off = IdxN->getZExtValue() * ElemWidth;
2680 if (VecWidth == 64 && ValWidth == 32) {
2681 assert(Off == 0 || Off == 32);
2682 ExtV = Off == 0 ? LoHalf(VecV, DAG) : HiHalf(VecV, DAG);
2683 } else if (Off == 0 && (ValWidth % 8) == 0) {
2684 ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy));
2685 } else {
2686 SDValue OffV = DAG.getConstant(Off, dl, MVT::i32);
2687 // The return type of EXTRACTU must be the same as the type of the
2688 // input vector.
2689 ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2690 {VecV, WidthV, OffV});
2691 }
2692 } else {
2693 if (ty(IdxV) != MVT::i32)
2694 IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2695 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2696 DAG.getConstant(ElemWidth, dl, MVT::i32));
2697 ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2698 {VecV, WidthV, OffV});
2699 }
2700
2701 // Cast ExtV to the requested result type.
2702 ExtV = DAG.getZExtOrTrunc(ExtV, dl, tyScalar(ResTy));
2703 ExtV = DAG.getBitcast(ResTy, ExtV);
2704 return ExtV;
2705}
2706
2707SDValue
2708HexagonTargetLowering::extractVectorPred(SDValue VecV, SDValue IdxV,
2709 const SDLoc &dl, MVT ValTy, MVT ResTy,
2710 SelectionDAG &DAG) const {
2711 // Special case for v{8,4,2}i1 (the only boolean vectors legal in Hexagon
2712 // without any coprocessors).
2713 MVT VecTy = ty(VecV);
2714 unsigned VecWidth = VecTy.getSizeInBits();
2715 unsigned ValWidth = ValTy.getSizeInBits();
2716 assert(VecWidth == VecTy.getVectorNumElements() &&
2717 "Vector elements should equal vector width size");
2718 assert(VecWidth == 8 || VecWidth == 4 || VecWidth == 2);
2719
2720 // Check if this is an extract of the lowest bit.
2721 if (isNullConstant(IdxV) && ValTy.getSizeInBits() == 1) {
2722 // Extracting the lowest bit is a no-op, but it changes the type,
2723 // so it must be kept as an operation to avoid errors related to
2724 // type mismatches.
2725 return DAG.getNode(HexagonISD::TYPECAST, dl, MVT::i1, VecV);
2726 }
2727
2728 // If the value extracted is a single bit, use tstbit.
2729 if (ValWidth == 1) {
2730 SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
2731 SDValue M0 = DAG.getConstant(8 / VecWidth, dl, MVT::i32);
2732 SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0);
2733 return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, I0);
2734 }
2735
2736 // Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in
2737 // a predicate register. The elements of the vector are repeated
2738 // in the register (if necessary) so that the total number is 8.
2739 // The extracted subvector will need to be expanded in such a way.
2740 unsigned Scale = VecWidth / ValWidth;
2741
2742 // Generate (p2d VecV) >> 8*Idx to move the interesting bytes to
2743 // position 0.
2744 assert(ty(IdxV) == MVT::i32);
2745 unsigned VecRep = 8 / VecWidth;
2746 SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2747 DAG.getConstant(8*VecRep, dl, MVT::i32));
2748 SDValue T0 = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2749 SDValue T1 = DAG.getNode(ISD::SRL, dl, MVT::i64, T0, S0);
2750 while (Scale > 1) {
2751 // The longest possible subvector is at most 32 bits, so it is always
2752 // contained in the low subregister.
2753 T1 = LoHalf(T1, DAG);
2754 T1 = expandPredicate(T1, dl, DAG);
2755 Scale /= 2;
2756 }
2757
2758 return DAG.getNode(HexagonISD::D2P, dl, ResTy, T1);
2759}
2760
2761SDValue
2762HexagonTargetLowering::insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
2763 const SDLoc &dl, MVT ValTy,
2764 SelectionDAG &DAG) const {
2765 MVT VecTy = ty(VecV);
2766 if (VecTy.getVectorElementType() == MVT::i1)
2767 return insertVectorPred(VecV, ValV, IdxV, dl, ValTy, DAG);
2768
2769 unsigned VecWidth = VecTy.getSizeInBits();
2770 unsigned ValWidth = ValTy.getSizeInBits();
2771 assert(VecWidth == 32 || VecWidth == 64);
2772 assert((VecWidth % ValWidth) == 0);
2773
2774 // Cast everything to scalar integer types.
2775 MVT ScalarTy = MVT::getIntegerVT(VecWidth);
2776 // The actual type of ValV may be different than ValTy (which is related
2777 // to the vector type).
2778 unsigned VW = ty(ValV).getSizeInBits();
2779 ValV = DAG.getBitcast(MVT::getIntegerVT(VW), ValV);
2780 VecV = DAG.getBitcast(ScalarTy, VecV);
2781 if (VW != VecWidth)
2782 ValV = DAG.getAnyExtOrTrunc(ValV, dl, ScalarTy);
2783
2784 SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2785 SDValue InsV;
2786
2787 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(IdxV)) {
2788 unsigned W = C->getZExtValue() * ValWidth;
2789 SDValue OffV = DAG.getConstant(W, dl, MVT::i32);
2790 InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2791 {VecV, ValV, WidthV, OffV});
2792 } else {
2793 if (ty(IdxV) != MVT::i32)
2794 IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2795 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV);
2796 InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2797 {VecV, ValV, WidthV, OffV});
2798 }
2799
2800 return DAG.getNode(ISD::BITCAST, dl, VecTy, InsV);
2801}
2802
2803SDValue
2804HexagonTargetLowering::insertVectorPred(SDValue VecV, SDValue ValV,
2805 SDValue IdxV, const SDLoc &dl,
2806 MVT ValTy, SelectionDAG &DAG) const {
2807 MVT VecTy = ty(VecV);
2808 unsigned VecLen = VecTy.getVectorNumElements();
2809
2810 if (ValTy == MVT::i1) {
2811 SDValue ToReg = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
2812 SDValue Ext = DAG.getSExtOrTrunc(ValV, dl, MVT::i32);
2813 SDValue Width = DAG.getConstant(8 / VecLen, dl, MVT::i32);
2814 SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, Width);
2815 SDValue Ins =
2816 DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, {ToReg, Ext, Width, Idx});
2817 return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Ins}, DAG);
2818 }
2819
2820 assert(ValTy.getVectorElementType() == MVT::i1);
2821 SDValue ValR = ValTy.isVector()
2822 ? DAG.getNode(HexagonISD::P2D, dl, MVT::i64, ValV)
2823 : DAG.getSExtOrTrunc(ValV, dl, MVT::i64);
2824
2825 unsigned Scale = VecLen / ValTy.getVectorNumElements();
2826 assert(Scale > 1);
2827
2828 for (unsigned R = Scale; R > 1; R /= 2) {
2829 ValR = contractPredicate(ValR, dl, DAG);
2830 ValR = getCombine(DAG.getUNDEF(MVT::i32), ValR, dl, MVT::i64, DAG);
2831 }
2832
2833 SDValue Width = DAG.getConstant(64 / Scale, dl, MVT::i32);
2834 SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, Width);
2835 SDValue VecR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2836 SDValue Ins =
2837 DAG.getNode(HexagonISD::INSERT, dl, MVT::i64, {VecR, ValR, Width, Idx});
2838 return DAG.getNode(HexagonISD::D2P, dl, VecTy, Ins);
2839}
2840
2841SDValue
2842HexagonTargetLowering::expandPredicate(SDValue Vec32, const SDLoc &dl,
2843 SelectionDAG &DAG) const {
2844 assert(ty(Vec32).getSizeInBits() == 32);
2845 if (isUndef(Vec32))
2846 return DAG.getUNDEF(MVT::i64);
2847 SDValue P = DAG.getBitcast(MVT::v4i8, Vec32);
2848 SDValue X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i16, P);
2849 return DAG.getBitcast(MVT::i64, X);
2850}
2851
2852SDValue
2853HexagonTargetLowering::contractPredicate(SDValue Vec64, const SDLoc &dl,
2854 SelectionDAG &DAG) const {
2855 assert(ty(Vec64).getSizeInBits() == 64);
2856 if (isUndef(Vec64))
2857 return DAG.getUNDEF(MVT::i32);
2858 // Collect even bytes:
2859 SDValue A = DAG.getBitcast(MVT::v8i8, Vec64);
2860 SDValue S = DAG.getVectorShuffle(MVT::v8i8, dl, A, DAG.getUNDEF(MVT::v8i8),
2861 {0, 2, 4, 6, 1, 3, 5, 7});
2862 return extractVector(S, DAG.getConstant(0, dl, MVT::i32), dl, MVT::v4i8,
2863 MVT::i32, DAG);
2864}
2865
2866SDValue
2867HexagonTargetLowering::getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG)
2868 const {
2869 if (Ty.isVector()) {
2870 unsigned W = Ty.getSizeInBits();
2871 if (W <= 64)
2872 return DAG.getBitcast(Ty, DAG.getConstant(0, dl, MVT::getIntegerVT(W)));
2873 return DAG.getNode(ISD::SPLAT_VECTOR, dl, Ty, getZero(dl, MVT::i32, DAG));
2874 }
2875
2876 if (Ty.isInteger())
2877 return DAG.getConstant(0, dl, Ty);
2878 if (Ty.isFloatingPoint())
2879 return DAG.getConstantFP(0.0, dl, Ty);
2880 llvm_unreachable("Invalid type for zero");
2881}
2882
2883SDValue
2884HexagonTargetLowering::appendUndef(SDValue Val, MVT ResTy, SelectionDAG &DAG)
2885 const {
2886 MVT ValTy = ty(Val);
2888
2889 unsigned ValLen = ValTy.getVectorNumElements();
2890 unsigned ResLen = ResTy.getVectorNumElements();
2891 if (ValLen == ResLen)
2892 return Val;
2893
2894 const SDLoc &dl(Val);
2895 assert(ValLen < ResLen);
2896 assert(ResLen % ValLen == 0);
2897
2898 SmallVector<SDValue, 4> Concats = {Val};
2899 for (unsigned i = 1, e = ResLen / ValLen; i < e; ++i)
2900 Concats.push_back(DAG.getUNDEF(ValTy));
2901
2902 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, Concats);
2903}
2904
2905SDValue
2906HexagonTargetLowering::getCombine(SDValue Hi, SDValue Lo, const SDLoc &dl,
2907 MVT ResTy, SelectionDAG &DAG) const {
2908 MVT ElemTy = ty(Hi);
2909 assert(ElemTy == ty(Lo));
2910
2911 if (!ElemTy.isVector()) {
2912 assert(ElemTy.isScalarInteger());
2913 MVT PairTy = MVT::getIntegerVT(2 * ElemTy.getSizeInBits());
2914 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Lo, Hi);
2915 return DAG.getBitcast(ResTy, Pair);
2916 }
2917
2918 unsigned Width = ElemTy.getSizeInBits();
2919 MVT IntTy = MVT::getIntegerVT(Width);
2920 MVT PairTy = MVT::getIntegerVT(2 * Width);
2921 SDValue Pair =
2923 {DAG.getBitcast(IntTy, Lo), DAG.getBitcast(IntTy, Hi)});
2924 return DAG.getBitcast(ResTy, Pair);
2925}
2926
2927SDValue
2929 MVT VecTy = ty(Op);
2930 unsigned BW = VecTy.getSizeInBits();
2931 const SDLoc &dl(Op);
2933 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
2934 Ops.push_back(Op.getOperand(i));
2935
2936 if (BW == 32)
2937 return buildVector32(Ops, dl, VecTy, DAG);
2938 if (BW == 64)
2939 return buildVector64(Ops, dl, VecTy, DAG);
2940
2941 if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
2942 // Check if this is a special case or all-0 or all-1.
2943 bool All0 = true, All1 = true;
2944 for (SDValue P : Ops) {
2945 auto *CN = dyn_cast<ConstantSDNode>(P.getNode());
2946 if (CN == nullptr) {
2947 All0 = All1 = false;
2948 break;
2949 }
2950 uint32_t C = CN->getZExtValue();
2951 All0 &= (C == 0);
2952 All1 &= (C == 1);
2953 }
2954 if (All0)
2955 return DAG.getNode(HexagonISD::PFALSE, dl, VecTy);
2956 if (All1)
2957 return DAG.getNode(HexagonISD::PTRUE, dl, VecTy);
2958
2959 // For each i1 element in the resulting predicate register, put 1
2960 // shifted by the index of the element into a general-purpose register,
2961 // then or them together and transfer it back into a predicate register.
2962 SDValue Rs[8];
2963 SDValue Z = getZero(dl, MVT::i32, DAG);
2964 // Always produce 8 bits, repeat inputs if necessary.
2965 unsigned Rep = 8 / VecTy.getVectorNumElements();
2966 for (unsigned i = 0; i != 8; ++i) {
2967 SDValue S = DAG.getConstant(1ull << i, dl, MVT::i32);
2968 Rs[i] = DAG.getSelect(dl, MVT::i32, Ops[i/Rep], S, Z);
2969 }
2970 for (ArrayRef<SDValue> A(Rs); A.size() != 1; A = A.drop_back(A.size()/2)) {
2971 for (unsigned i = 0, e = A.size()/2; i != e; ++i)
2972 Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]);
2973 }
2974 // Move the value directly to a predicate register.
2975 return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
2976 }
2977
2978 return SDValue();
2979}
2980
2981SDValue
2983 SelectionDAG &DAG) const {
2984 MVT VecTy = ty(Op);
2985 const SDLoc &dl(Op);
2986 if (VecTy.getSizeInBits() == 64) {
2987 assert(Op.getNumOperands() == 2);
2988 return getCombine(Op.getOperand(1), Op.getOperand(0), dl, VecTy, DAG);
2989 }
2990
2991 MVT ElemTy = VecTy.getVectorElementType();
2992 if (ElemTy == MVT::i1) {
2993 assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1);
2994 MVT OpTy = ty(Op.getOperand(0));
2995 // Scale is how many times the operands need to be contracted to match
2996 // the representation in the target register.
2997 unsigned Scale = VecTy.getVectorNumElements() / OpTy.getVectorNumElements();
2998 assert(Scale == Op.getNumOperands() && Scale > 1);
2999
3000 // First, convert all bool vectors to integers, then generate pairwise
3001 // inserts to form values of doubled length. Up until there are only
3002 // two values left to concatenate, all of these values will fit in a
3003 // 32-bit integer, so keep them as i32 to use 32-bit inserts.
3004 SmallVector<SDValue,4> Words[2];
3005 unsigned IdxW = 0;
3006
3007 for (SDValue P : Op.getNode()->op_values()) {
3008 SDValue W = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, P);
3009 for (unsigned R = Scale; R > 1; R /= 2) {
3010 W = contractPredicate(W, dl, DAG);
3011 W = getCombine(DAG.getUNDEF(MVT::i32), W, dl, MVT::i64, DAG);
3012 }
3013 W = LoHalf(W, DAG);
3014 Words[IdxW].push_back(W);
3015 }
3016
3017 while (Scale > 2) {
3018 SDValue WidthV = DAG.getConstant(64 / Scale, dl, MVT::i32);
3019 Words[IdxW ^ 1].clear();
3020
3021 for (unsigned i = 0, e = Words[IdxW].size(); i != e; i += 2) {
3022 SDValue W0 = Words[IdxW][i], W1 = Words[IdxW][i+1];
3023 // Insert W1 into W0 right next to the significant bits of W0.
3024 SDValue T = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32,
3025 {W0, W1, WidthV, WidthV});
3026 Words[IdxW ^ 1].push_back(T);
3027 }
3028 IdxW ^= 1;
3029 Scale /= 2;
3030 }
3031
3032 // At this point there should only be two words left, and Scale should be 2.
3033 assert(Scale == 2 && Words[IdxW].size() == 2);
3034
3035 SDValue WW = getCombine(Words[IdxW][1], Words[IdxW][0], dl, MVT::i64, DAG);
3036 return DAG.getNode(HexagonISD::D2P, dl, VecTy, WW);
3037 }
3038
3039 return SDValue();
3040}
3041
3042SDValue
3044 SelectionDAG &DAG) const {
3045 SDValue Vec = Op.getOperand(0);
3046 MVT ElemTy = ty(Vec).getVectorElementType();
3047 return extractVector(Vec, Op.getOperand(1), SDLoc(Op), ElemTy, ty(Op), DAG);
3048}
3049
3050SDValue
3052 SelectionDAG &DAG) const {
3053 return extractVector(Op.getOperand(0), Op.getOperand(1), SDLoc(Op),
3054 ty(Op), ty(Op), DAG);
3055}
3056
3057SDValue
3059 SelectionDAG &DAG) const {
3060 return insertVector(Op.getOperand(0), Op.getOperand(1), Op.getOperand(2),
3061 SDLoc(Op), ty(Op).getVectorElementType(), DAG);
3062}
3063
3064SDValue
3066 SelectionDAG &DAG) const {
3067 SDValue ValV = Op.getOperand(1);
3068 return insertVector(Op.getOperand(0), ValV, Op.getOperand(2),
3069 SDLoc(Op), ty(ValV), DAG);
3070}
3071
3072bool
3074 // Assuming the caller does not have either a signext or zeroext modifier, and
3075 // only one value is accepted, any reasonable truncation is allowed.
3076 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
3077 return false;
3078
3079 // FIXME: in principle up to 64-bit could be made safe, but it would be very
3080 // fragile at the moment: any support for multiple value returns would be
3081 // liable to disallow tail calls involving i64 -> iN truncation in many cases.
3082 return Ty1->getPrimitiveSizeInBits() <= 32;
3083}
3084
3085SDValue
3087 MVT Ty = ty(Op);
3088 const SDLoc &dl(Op);
3089 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
3090 MVT MemTy = LN->getMemoryVT().getSimpleVT();
3092
3093 bool LoadPred = MemTy == MVT::v2i1 || MemTy == MVT::v4i1 || MemTy == MVT::v8i1;
3094 if (LoadPred) {
3095 SDValue NL = DAG.getLoad(
3096 LN->getAddressingMode(), ISD::ZEXTLOAD, MVT::i32, dl, LN->getChain(),
3097 LN->getBasePtr(), LN->getOffset(), LN->getPointerInfo(),
3098 /*MemoryVT*/ MVT::i8, LN->getAlign(), LN->getMemOperand()->getFlags(),
3099 LN->getAAInfo(), LN->getRanges());
3100 LN = cast<LoadSDNode>(NL.getNode());
3101 }
3102
3103 Align ClaimAlign = LN->getAlign();
3104 if (!validateConstPtrAlignment(LN->getBasePtr(), ClaimAlign, dl, DAG))
3105 return replaceMemWithUndef(Op, DAG);
3106
3107 // Call LowerUnalignedLoad for all loads, it recognizes loads that
3108 // don't need extra aligning.
3109 SDValue LU = LowerUnalignedLoad(SDValue(LN, 0), DAG);
3110 if (LoadPred) {
3111 SDValue TP = getInstr(Hexagon::C2_tfrrp, dl, MemTy, {LU}, DAG);
3112 if (ET == ISD::SEXTLOAD) {
3113 TP = DAG.getSExtOrTrunc(TP, dl, Ty);
3114 } else if (ET != ISD::NON_EXTLOAD) {
3115 TP = DAG.getZExtOrTrunc(TP, dl, Ty);
3116 }
3117 SDValue Ch = cast<LoadSDNode>(LU.getNode())->getChain();
3118 return DAG.getMergeValues({TP, Ch}, dl);
3119 }
3120 return LU;
3121}
3122
3123SDValue
3125 const SDLoc &dl(Op);
3126 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
3127 SDValue Val = SN->getValue();
3128 MVT Ty = ty(Val);
3129
3130 if (Ty == MVT::v2i1 || Ty == MVT::v4i1 || Ty == MVT::v8i1) {
3131 // Store the exact predicate (all bits).
3132 SDValue TR = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {Val}, DAG);
3133 SDValue NS = DAG.getTruncStore(SN->getChain(), dl, TR, SN->getBasePtr(),
3134 MVT::i8, SN->getMemOperand());
3135 if (SN->isIndexed()) {
3136 NS = DAG.getIndexedStore(NS, dl, SN->getBasePtr(), SN->getOffset(),
3137 SN->getAddressingMode());
3138 }
3139 SN = cast<StoreSDNode>(NS.getNode());
3140 }
3141
3142 Align ClaimAlign = SN->getAlign();
3143 if (!validateConstPtrAlignment(SN->getBasePtr(), ClaimAlign, dl, DAG))
3144 return replaceMemWithUndef(Op, DAG);
3145
3146 MVT StoreTy = SN->getMemoryVT().getSimpleVT();
3147 Align NeedAlign = Subtarget.getTypeAlignment(StoreTy);
3148 if (ClaimAlign < NeedAlign)
3149 return expandUnalignedStore(SN, DAG);
3150 return SDValue(SN, 0);
3151}
3152
3153SDValue
3155 const {
3156 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
3157 MVT LoadTy = ty(Op);
3158 unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy).value();
3159 unsigned HaveAlign = LN->getAlign().value();
3160 if (HaveAlign >= NeedAlign)
3161 return Op;
3162
3163 const SDLoc &dl(Op);
3164 const DataLayout &DL = DAG.getDataLayout();
3165 LLVMContext &Ctx = *DAG.getContext();
3166
3167 // If the load aligning is disabled or the load can be broken up into two
3168 // smaller legal loads, do the default (target-independent) expansion.
3169 bool DoDefault = false;
3170 // Handle it in the default way if this is an indexed load.
3171 if (!LN->isUnindexed())
3172 DoDefault = true;
3173
3174 if (!AlignLoads) {
3176 *LN->getMemOperand()))
3177 return Op;
3178 DoDefault = true;
3179 }
3180 if (!DoDefault && (2 * HaveAlign) == NeedAlign) {
3181 // The PartTy is the equivalent of "getLoadableTypeOfSize(HaveAlign)".
3182 MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8 * HaveAlign)
3183 : MVT::getVectorVT(MVT::i8, HaveAlign);
3184 DoDefault =
3185 allowsMemoryAccessForAlignment(Ctx, DL, PartTy, *LN->getMemOperand());
3186 }
3187 if (DoDefault) {
3188 std::pair<SDValue, SDValue> P = expandUnalignedLoad(LN, DAG);
3189 return DAG.getMergeValues({P.first, P.second}, dl);
3190 }
3191
3192 // The code below generates two loads, both aligned as NeedAlign, and
3193 // with the distance of NeedAlign between them. For that to cover the
3194 // bits that need to be loaded (and without overlapping), the size of
3195 // the loads should be equal to NeedAlign. This is true for all loadable
3196 // types, but add an assertion in case something changes in the future.
3197 assert(LoadTy.getSizeInBits() == 8*NeedAlign);
3198
3199 unsigned LoadLen = NeedAlign;
3200 SDValue Base = LN->getBasePtr();
3201 SDValue Chain = LN->getChain();
3202 auto BO = getBaseAndOffset(Base);
3203 unsigned BaseOpc = BO.first.getOpcode();
3204 if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0)
3205 return Op;
3206
3207 if (BO.second % LoadLen != 0) {
3208 BO.first = DAG.getNode(ISD::ADD, dl, MVT::i32, BO.first,
3209 DAG.getConstant(BO.second % LoadLen, dl, MVT::i32));
3210 BO.second -= BO.second % LoadLen;
3211 }
3212 SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR)
3213 ? DAG.getNode(HexagonISD::VALIGNADDR, dl, MVT::i32, BO.first,
3214 DAG.getConstant(NeedAlign, dl, MVT::i32))
3215 : BO.first;
3216 SDValue Base0 =
3217 DAG.getMemBasePlusOffset(BaseNoOff, TypeSize::Fixed(BO.second), dl);
3218 SDValue Base1 = DAG.getMemBasePlusOffset(
3219 BaseNoOff, TypeSize::Fixed(BO.second + LoadLen), dl);
3220
3221 MachineMemOperand *WideMMO = nullptr;
3222 if (MachineMemOperand *MMO = LN->getMemOperand()) {
3224 WideMMO = MF.getMachineMemOperand(
3225 MMO->getPointerInfo(), MMO->getFlags(), 2 * LoadLen, Align(LoadLen),
3226 MMO->getAAInfo(), MMO->getRanges(), MMO->getSyncScopeID(),
3227 MMO->getSuccessOrdering(), MMO->getFailureOrdering());
3228 }
3229
3230 SDValue Load0 = DAG.getLoad(LoadTy, dl, Chain, Base0, WideMMO);
3231 SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO);
3232
3233 SDValue Aligned = DAG.getNode(HexagonISD::VALIGN, dl, LoadTy,
3234 {Load1, Load0, BaseNoOff.getOperand(0)});
3235 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3236 Load0.getValue(1), Load1.getValue(1));
3237 SDValue M = DAG.getMergeValues({Aligned, NewChain}, dl);
3238 return M;
3239}
3240
3241SDValue
3243 SDValue X = Op.getOperand(0), Y = Op.getOperand(1);
3244 auto *CY = dyn_cast<ConstantSDNode>(Y);
3245 if (!CY)
3246 return SDValue();
3247
3248 const SDLoc &dl(Op);
3249 SDVTList VTs = Op.getNode()->getVTList();
3250 assert(VTs.NumVTs == 2);
3251 assert(VTs.VTs[1] == MVT::i1);
3252 unsigned Opc = Op.getOpcode();
3253
3254 if (CY) {
3255 uint64_t VY = CY->getZExtValue();
3256 assert(VY != 0 && "This should have been folded");
3257 // X +/- 1
3258 if (VY != 1)
3259 return SDValue();
3260
3261 if (Opc == ISD::UADDO) {
3262 SDValue Op = DAG.getNode(ISD::ADD, dl, VTs.VTs[0], {X, Y});
3263 SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op, getZero(dl, ty(Op), DAG),
3264 ISD::SETEQ);
3265 return DAG.getMergeValues({Op, Ov}, dl);
3266 }
3267 if (Opc == ISD::USUBO) {
3268 SDValue Op = DAG.getNode(ISD::SUB, dl, VTs.VTs[0], {X, Y});
3269 SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op,
3270 DAG.getConstant(-1, dl, ty(Op)), ISD::SETEQ);
3271 return DAG.getMergeValues({Op, Ov}, dl);
3272 }
3273 }
3274
3275 return SDValue();
3276}
3277
3279 SelectionDAG &DAG) const {
3280 const SDLoc &dl(Op);
3281 unsigned Opc = Op.getOpcode();
3282 SDValue X = Op.getOperand(0), Y = Op.getOperand(1), C = Op.getOperand(2);
3283
3284 if (Opc == ISD::UADDO_CARRY)
3285 return DAG.getNode(HexagonISD::ADDC, dl, Op.getNode()->getVTList(),
3286 { X, Y, C });
3287
3288 EVT CarryTy = C.getValueType();
3289 SDValue SubC = DAG.getNode(HexagonISD::SUBC, dl, Op.getNode()->getVTList(),
3290 { X, Y, DAG.getLogicalNOT(dl, C, CarryTy) });
3291 SDValue Out[] = { SubC.getValue(0),
3292 DAG.getLogicalNOT(dl, SubC.getValue(1), CarryTy) };
3293 return DAG.getMergeValues(Out, dl);
3294}
3295
3296SDValue
3298 SDValue Chain = Op.getOperand(0);
3299 SDValue Offset = Op.getOperand(1);
3300 SDValue Handler = Op.getOperand(2);
3301 SDLoc dl(Op);
3302 auto PtrVT = getPointerTy(DAG.getDataLayout());
3303
3304 // Mark function as containing a call to EH_RETURN.
3305 HexagonMachineFunctionInfo *FuncInfo =
3307 FuncInfo->setHasEHReturn();
3308
3309 unsigned OffsetReg = Hexagon::R28;
3310
3311 SDValue StoreAddr =
3312 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
3313 DAG.getIntPtrConstant(4, dl));
3314 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
3315 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
3316
3317 // Not needed we already use it as explict input to EH_RETURN.
3318 // MF.getRegInfo().addLiveOut(OffsetReg);
3319
3320 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
3321}
3322
3323SDValue
3325 unsigned Opc = Op.getOpcode();
3326
3327 // Handle INLINEASM first.
3328 if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR)
3329 return LowerINLINEASM(Op, DAG);
3330
3331 if (isHvxOperation(Op.getNode(), DAG)) {
3332 // If HVX lowering returns nothing, try the default lowering.
3333 if (SDValue V = LowerHvxOperation(Op, DAG))
3334 return V;
3335 }
3336
3337 switch (Opc) {
3338 default:
3339#ifndef NDEBUG
3340 Op.getNode()->dumpr(&DAG);
3341 if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
3342 errs() << "Error: check for a non-legal type in this operation\n";
3343#endif
3344 llvm_unreachable("Should not custom lower this!");
3345 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3350 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3351 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3352 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
3353 case ISD::LOAD: return LowerLoad(Op, DAG);
3354 case ISD::STORE: return LowerStore(Op, DAG);
3355 case ISD::UADDO:
3356 case ISD::USUBO: return LowerUAddSubO(Op, DAG);
3357 case ISD::UADDO_CARRY:
3358 case ISD::USUBO_CARRY: return LowerUAddSubOCarry(Op, DAG);
3359 case ISD::SRA:
3360 case ISD::SHL:
3361 case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
3362 case ISD::ROTL: return LowerROTL(Op, DAG);
3363 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3364 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3365 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
3366 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3367 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3369 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
3370 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
3371 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3373 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
3374 case ISD::VASTART: return LowerVASTART(Op, DAG);
3376 case ISD::SETCC: return LowerSETCC(Op, DAG);
3377 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
3379 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
3380 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
3382 break;
3383 }
3384
3385 return SDValue();
3386}
3387
3388void
3391 SelectionDAG &DAG) const {
3392 if (isHvxOperation(N, DAG)) {
3393 LowerHvxOperationWrapper(N, Results, DAG);
3394 if (!Results.empty())
3395 return;
3396 }
3397
3398 SDValue Op(N, 0);
3399 unsigned Opc = N->getOpcode();
3400
3401 switch (Opc) {
3402 case HexagonISD::SSAT:
3403 case HexagonISD::USAT:
3404 Results.push_back(opJoin(SplitVectorOp(Op, DAG), SDLoc(Op), DAG));
3405 break;
3406 case ISD::STORE:
3407 // We are only custom-lowering stores to verify the alignment of the
3408 // address if it is a compile-time constant. Since a store can be
3409 // modified during type-legalization (the value being stored may need
3410 // legalization), return empty Results here to indicate that we don't
3411 // really make any changes in the custom lowering.
3412 return;
3413 default:
3415 break;
3416 }
3417}
3418
3419void
3422 SelectionDAG &DAG) const {
3423 if (isHvxOperation(N, DAG)) {
3424 ReplaceHvxNodeResults(N, Results, DAG);
3425 if (!Results.empty())
3426 return;
3427 }
3428
3429 const SDLoc &dl(N);
3430 switch (N->getOpcode()) {
3431 case ISD::SRL:
3432 case ISD::SRA:
3433 case ISD::SHL:
3434 return;
3435 case ISD::BITCAST:
3436 // Handle a bitcast from v8i1 to i8.
3437 if (N->getValueType(0) == MVT::i8) {
3438 if (N->getOperand(0).getValueType() == MVT::v8i1) {
3439 SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
3440 N->getOperand(0), DAG);
3441 SDValue T = DAG.getAnyExtOrTrunc(P, dl, MVT::i8);
3442 Results.push_back(T);
3443 }
3444 }
3445 break;
3446 }
3447}
3448
3449SDValue
3451 DAGCombinerInfo &DCI) const {
3452 if (isHvxOperation(N, DCI.DAG)) {
3453 if (SDValue V = PerformHvxDAGCombine(N, DCI))
3454 return V;
3455 return SDValue();
3456 }
3457
3458 SDValue Op(N, 0);
3459 const SDLoc &dl(Op);
3460 unsigned Opc = Op.getOpcode();
3461
3462 if (Opc == ISD::TRUNCATE) {
3463 SDValue Op0 = Op.getOperand(0);
3464 // fold (truncate (build pair x, y)) -> (truncate x) or x
3465 if (Op0.getOpcode() == ISD::BUILD_PAIR) {
3466 EVT TruncTy = Op.getValueType();
3467 SDValue Elem0 = Op0.getOperand(0);
3468 // if we match the low element of the pair, just return it.
3469 if (Elem0.getValueType() == TruncTy)
3470 return Elem0;
3471 // otherwise, if the low part is still too large, apply the truncate.
3472 if (Elem0.getValueType().bitsGT(TruncTy))
3473 return DCI.DAG.getNode(ISD::TRUNCATE, dl, TruncTy, Elem0);
3474 }
3475 }
3476
3477 if (DCI.isBeforeLegalizeOps())
3478 return SDValue();
3479
3480 if (Opc == HexagonISD::P2D) {
3481 SDValue P = Op.getOperand(0);
3482 switch (P.getOpcode()) {
3483 case HexagonISD::PTRUE:
3484 return DCI.DAG.getConstant(-1, dl, ty(Op));
3485 case HexagonISD::PFALSE:
3486 return getZero(dl, ty(Op), DCI.DAG);
3487 default:
3488 break;
3489 }
3490 } else if (Opc == ISD::VSELECT) {
3491 // This is pretty much duplicated in HexagonISelLoweringHVX...
3492 //
3493 // (vselect (xor x, ptrue), v0, v1) -> (vselect x, v1, v0)
3494 SDValue Cond = Op.getOperand(0);
3495 if (Cond->getOpcode() == ISD::XOR) {
3496 SDValue C0 = Cond.getOperand(0), C1 = Cond.getOperand(1);
3497 if (C1->getOpcode() == HexagonISD::PTRUE) {
3498 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0,
3499 Op.getOperand(2), Op.getOperand(1));
3500 return VSel;
3501 }
3502 }
3503 } else if (Opc == ISD::TRUNCATE) {
3504 SDValue Op0 = Op.getOperand(0);
3505 // fold (truncate (build pair x, y)) -> (truncate x) or x
3506 if (Op0.getOpcode() == ISD::BUILD_PAIR) {
3507 MVT TruncTy = ty(Op);
3508 SDValue Elem0 = Op0.getOperand(0);
3509 // if we match the low element of the pair, just return it.
3510 if (ty(Elem0) == TruncTy)
3511 return Elem0;
3512 // otherwise, if the low part is still too large, apply the truncate.
3513 if (ty(Elem0).bitsGT(TruncTy))
3514 return DCI.DAG.getNode(ISD::TRUNCATE, dl, TruncTy, Elem0);
3515 }
3516 } else if (Opc == ISD::OR) {
3517 // fold (or (shl xx, s), (zext y)) -> (COMBINE (shl xx, s-32), y)
3518 // if s >= 32
3519 auto fold0 = [&, this](SDValue Op) {
3520 if (ty(Op) != MVT::i64)
3521 return SDValue();
3522 SDValue Shl = Op.getOperand(0);
3523 SDValue Zxt = Op.getOperand(1);
3524 if (Shl.getOpcode() != ISD::SHL)
3525 std::swap(Shl, Zxt);
3526
3527 if (Shl.getOpcode() != ISD::SHL || Zxt.getOpcode() != ISD::ZERO_EXTEND)
3528 return SDValue();
3529
3530 SDValue Z = Zxt.getOperand(0);
3531 auto *Amt = dyn_cast<ConstantSDNode>(Shl.getOperand(1));
3532 if (Amt && Amt->getZExtValue() >= 32 && ty(Z).getSizeInBits() <= 32) {
3533 unsigned A = Amt->getZExtValue();
3534 SDValue S = Shl.getOperand(0);
3535 SDValue T0 = DCI.DAG.getNode(ISD::SHL, dl, ty(S), S,
3536 DCI.DAG.getConstant(32 - A, dl, MVT::i32));
3537 SDValue T1 = DCI.DAG.getZExtOrTrunc(T0, dl, MVT::i32);
3538 SDValue T2 = DCI.DAG.getZExtOrTrunc(Z, dl, MVT::i32);
3539 return DCI.DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, {T1, T2});
3540 }
3541 return SDValue();
3542 };
3543
3544 if (SDValue R = fold0(Op))
3545 return R;
3546 }
3547
3548 return SDValue();
3549}
3550
3551/// Returns relocation base for the given PIC jumptable.
3552SDValue
3554 SelectionDAG &DAG) const {
3555 int Idx = cast<JumpTableSDNode>(Table)->getIndex();
3556 EVT VT = Table.getValueType();
3558 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
3559}
3560
3561//===----------------------------------------------------------------------===//
3562// Inline Assembly Support
3563//===----------------------------------------------------------------------===//
3564
3567 if (Constraint.size() == 1) {
3568 switch (Constraint[0]) {
3569 case 'q':
3570 case 'v':
3571 if (Subtarget.useHVXOps())
3572 return C_RegisterClass;
3573 break;
3574 case 'a':
3575 return C_RegisterClass;
3576 default:
3577 break;
3578 }
3579 }
3580 return TargetLowering::getConstraintType(Constraint);
3581}
3582
3583std::pair<unsigned, const TargetRegisterClass*>
3585 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
3586
3587 if (Constraint.size() == 1) {
3588 switch (Constraint[0]) {
3589 case 'r': // R0-R31
3590 switch (VT.SimpleTy) {
3591 default:
3592 return {0u, nullptr};
3593 case MVT::i1:
3594 case MVT::i8:
3595 case MVT::i16:
3596 case MVT::i32:
3597 case MVT::f32:
3598 return {0u, &Hexagon::IntRegsRegClass};
3599 case MVT::i64:
3600 case MVT::f64:
3601 return {0u, &Hexagon::DoubleRegsRegClass};
3602 }
3603 break;
3604 case 'a': // M0-M1
3605 if (VT != MVT::i32)
3606 return {0u, nullptr};
3607 return {0u, &Hexagon::ModRegsRegClass};
3608 case 'q': // q0-q3
3609 switch (VT.getSizeInBits()) {
3610 default:
3611 return {0u, nullptr};
3612 case 64:
3613 case 128:
3614 return {0u, &Hexagon::HvxQRRegClass};
3615 }
3616 break;
3617 case 'v': // V0-V31
3618 switch (VT.getSizeInBits()) {
3619 default:
3620 return {0u, nullptr};
3621 case 512:
3622 return {0u, &Hexagon::HvxVRRegClass};
3623 case 1024:
3624 if (Subtarget.hasV60Ops() && Subtarget.useHVX128BOps())
3625 return {0u, &Hexagon::HvxVRRegClass};
3626 return {0u, &Hexagon::HvxWRRegClass};
3627 case 2048:
3628 return {0u, &Hexagon::HvxWRRegClass};
3629 }
3630 break;
3631 default:
3632 return {0u, nullptr};
3633 }
3634 }
3635
3636 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3637}
3638
3639/// isFPImmLegal - Returns true if the target can instruction select the
3640/// specified FP immediate natively. If false, the legalizer will
3641/// materialize the FP immediate as a load from a constant pool.
3643 bool ForCodeSize) const {
3644 return true;
3645}
3646
3647/// isLegalAddressingMode - Return true if the addressing mode represented by
3648/// AM is legal for this target, for a load/store of the specified type.
3650 const AddrMode &AM, Type *Ty,
3651 unsigned AS, Instruction *I) const {
3652 if (Ty->isSized()) {
3653 // When LSR detects uses of the same base address to access different
3654 // types (e.g. unions), it will assume a conservative type for these
3655 // uses:
3656 // LSR Use: Kind=Address of void in addrspace(4294967295), ...
3657 // The type Ty passed here would then be "void". Skip the alignment
3658 // checks, but do not return false right away, since that confuses
3659 // LSR into crashing.
3660 Align A = DL.getABITypeAlign(Ty);
3661 // The base offset must be a multiple of the alignment.
3662 if (!isAligned(A, AM.BaseOffs))
3663 return false;
3664 // The shifted offset must fit in 11 bits.
3665 if (!isInt<11>(AM.BaseOffs >> Log2(A)))
3666 return false;
3667 }
3668
3669 // No global is ever allowed as a base.
3670 if (AM.BaseGV)
3671 return false;
3672
3673 int Scale = AM.Scale;
3674 if (Scale < 0)
3675 Scale = -Scale;
3676 switch (Scale) {
3677 case 0: // No scale reg, "r+i", "r", or just "i".
3678 break;
3679 default: // No scaled addressing mode.
3680 return false;
3681 }
3682 return true;
3683}
3684
3685/// Return true if folding a constant offset with the given GlobalAddress is
3686/// legal. It is frequently not legal in PIC relocation models.
3688 const {
3689 return HTM.getRelocationModel() == Reloc::Static;
3690}
3691
3692/// isLegalICmpImmediate - Return true if the specified immediate is legal
3693/// icmp immediate, that is the target has icmp instructions which can compare
3694/// a register against the immediate without having to materialize the
3695/// immediate into a register.
3697 return Imm >= -512 && Imm <= 511;
3698}
3699
3700/// IsEligibleForTailCallOptimization - Check whether the call is eligible
3701/// for tail call optimization. Targets which want to do tail call
3702/// optimization should implement this function.
3704 SDValue Callee,
3705 CallingConv::ID CalleeCC,
3706 bool IsVarArg,
3707 bool IsCalleeStructRet,
3708 bool IsCallerStructRet,
3710 const SmallVectorImpl<SDValue> &OutVals,
3712 SelectionDAG& DAG) const {
3713 const Function &CallerF = DAG.getMachineFunction().getFunction();
3714 CallingConv::ID CallerCC = CallerF.getCallingConv();
3715 bool CCMatch = CallerCC == CalleeCC;
3716
3717 // ***************************************************************************
3718 // Look for obvious safe cases to perform tail call optimization that do not
3719 // require ABI changes.
3720 // ***************************************************************************
3721
3722 // If this is a tail call via a function pointer, then don't do it!
3723 if (!isa<GlobalAddressSDNode>(Callee) &&
3724 !isa<ExternalSymbolSDNode>(Callee)) {
3725 return false;
3726 }
3727
3728 // Do not optimize if the calling conventions do not match and the conventions
3729 // used are not C or Fast.
3730 if (!CCMatch) {
3731 bool R = (CallerCC == CallingConv::C || CallerCC == CallingConv::Fast);
3732 bool E = (CalleeCC == CallingConv::C || CalleeCC == CallingConv::Fast);
3733 // If R & E, then ok.
3734 if (!R || !E)
3735 return false;
3736 }
3737
3738 // Do not tail call optimize vararg calls.
3739 if (IsVarArg)
3740 return false;
3741
3742 // Also avoid tail call optimization if either caller or callee uses struct
3743 // return semantics.
3744 if (IsCalleeStructRet || IsCallerStructRet)
3745 return false;
3746
3747 // In addition to the cases above, we also disable Tail Call Optimization if
3748 // the calling convention code that at least one outgoing argument needs to
3749 // go on the stack. We cannot check that here because at this point that
3750 // information is not available.
3751 return true;
3752}
3753
3754/// Returns the target specific optimal type for load and store operations as
3755/// a result of memset, memcpy, and memmove lowering.
3756///
3757/// If DstAlign is zero that means it's safe to destination alignment can
3758/// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
3759/// a need to check it against alignment requirement, probably because the
3760/// source does not need to be loaded. If 'IsMemset' is true, that means it's
3761/// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
3762/// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
3763/// does not need to be loaded. It returns EVT::Other if the type should be
3764/// determined using generic target-independent logic.
3766 const MemOp &Op, const AttributeList &FuncAttributes) const {
3767 if (Op.size() >= 8 && Op.isAligned(Align(8)))
3768 return MVT::i64;
3769 if (Op.size() >= 4 && Op.isAligned(Align(4)))
3770 return MVT::i32;
3771 if (Op.size() >= 2 && Op.isAligned(Align(2)))
3772 return MVT::i16;
3773 return MVT::Other;
3774}
3775
3777 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
3778 Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const {
3779 MVT SVT = VT.getSimpleVT();
3780 if (Subtarget.isHVXVectorType(SVT, true))
3781 return allowsHvxMemoryAccess(SVT, Flags, Fast);
3783 Context, DL, VT, AddrSpace, Alignment, Flags, Fast);
3784}
3785
3787 EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
3788 unsigned *Fast) const {
3789 MVT SVT = VT.getSimpleVT();
3790 if (Subtarget.isHVXVectorType(SVT, true))
3791 return allowsHvxMisalignedMemoryAccesses(SVT, Flags, Fast);
3792 if (Fast)
3793 *Fast = 0;
3794 return false;
3795}
3796
3797std::pair<const TargetRegisterClass*, uint8_t>
3798HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
3799 MVT VT) const {
3800 if (Subtarget.isHVXVectorType(VT, true)) {
3801 unsigned BitWidth = VT.getSizeInBits();
3802 unsigned VecWidth = Subtarget.getVectorLength() * 8;
3803
3804 if (VT.getVectorElementType() == MVT::i1)
3805 return std::make_pair(&Hexagon::HvxQRRegClass, 1);
3806 if (BitWidth == VecWidth)
3807 return std::make_pair(&Hexagon::HvxVRRegClass, 1);
3808 assert(BitWidth == 2 * VecWidth);
3809 return std::make_pair(&Hexagon::HvxWRRegClass, 1);
3810 }
3811
3813}
3814
3816 ISD::LoadExtType ExtTy, EVT NewVT) const {
3817 // TODO: This may be worth removing. Check regression tests for diffs.
3818 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT))
3819 return false;
3820
3821 auto *L = cast<LoadSDNode>(Load);
3822 std::pair<SDValue,int> BO = getBaseAndOffset(L->getBasePtr());
3823 // Small-data object, do not shrink.
3824 if (BO.first.getOpcode() == HexagonISD::CONST32_GP)
3825 return false;
3826 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(BO.first)) {
3827 auto &HTM = static_cast<const HexagonTargetMachine&>(getTargetMachine());
3828 const auto *GO = dyn_cast_or_null<const GlobalObject>(GA->getGlobal());
3829 return !GO || !HTM.getObjFileLowering()->isGlobalInSmallSection(GO, HTM);
3830 }
3831 return true;
3832}
3833
3835 SDNode *Node) const {
3836 AdjustHvxInstrPostInstrSelection(MI, Node);
3837}
3838
3840 Type *ValueTy, Value *Addr,
3841 AtomicOrdering Ord) const {
3842 BasicBlock *BB = Builder.GetInsertBlock();
3843 Module *M = BB->getParent()->getParent();
3844 unsigned SZ = ValueTy->getPrimitiveSizeInBits();
3845 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
3846 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3847 : Intrinsic::hexagon_L4_loadd_locked;
3848 Function *Fn = Intrinsic::getDeclaration(M, IntID);
3849
3850 Value *Call = Builder.CreateCall(Fn, Addr, "larx");
3851
3852 return Builder.CreateBitCast(Call, ValueTy);
3853}
3854
3855/// Perform a store-conditional operation to Addr. Return the status of the
3856/// store. This should be 0 if the store succeeded, non-zero otherwise.
3858 Value *Val, Value *Addr,
3859 AtomicOrdering Ord) const {
3860 BasicBlock *BB = Builder.GetInsertBlock();
3861 Module *M = BB->getParent()->getParent();
3862 Type *Ty = Val->getType();
3863 unsigned SZ = Ty->getPrimitiveSizeInBits();
3864
3865 Type *CastTy = Builder.getIntNTy(SZ);
3866 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
3867 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3868 : Intrinsic::hexagon_S4_stored_locked;
3869 Function *Fn = Intrinsic::getDeclaration(M, IntID);
3870
3871 Val = Builder.CreateBitCast(Val, CastTy);
3872
3873 Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
3874 Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
3875 Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
3876 return Ext;
3877}
3878
3881 // Do not expand loads and stores that don't exceed 64 bits.
3882 return LI->getType()->getPrimitiveSizeInBits() > 64
3885}
3886
3889 // Do not expand loads and stores that don't exceed 64 bits.
3890 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64
3893}
3894
3897 AtomicCmpXchgInst *AI) const {
3899}
unsigned const MachineRegisterInfo * MRI
unsigned RegSize
aarch64 promote const
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file implements a class to represent arbitrary precision integral constant values and operations...
Function Alias Analysis Results
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
assume Assume Builder
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define LLVM_DEBUG(X)
Definition: Debug.h:101
#define NL
uint64_t Addr
uint64_t Size
Symbol * Sym
Definition: ELF_riscv.cpp:468
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< int > MaxStoresPerMemcpyCL("max-store-memcpy", cl::Hidden, cl::init(6), cl::desc("Max #stores to inline memcpy"))
static Value * getUnderLyingObjectForBrevLdIntr(Value *V)
static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static cl::opt< bool > AlignLoads("hexagon-align-loads", cl::Hidden, cl::init(false), cl::desc("Rewrite unaligned loads as a pair of aligned loads"))
static bool isBrevLdIntrinsic(const Value *Inst)
static cl::opt< int > MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os", cl::Hidden, cl::init(4), cl::desc("Max #stores to inline memmove"))
static cl::opt< int > MaxStoresPerMemmoveCL("max-store-memmove", cl::Hidden, cl::init(6), cl::desc("Max #stores to inline memmove"))
static Value * getBrevLdObject(Value *V)
static cl::opt< int > MaxStoresPerMemsetCL("max-store-memset", cl::Hidden, cl::init(8), cl::desc("Max #stores to inline memset"))
static cl::opt< bool > DisableArgsMinAlignment("hexagon-disable-args-min-alignment", cl::Hidden, cl::init(false), cl::desc("Disable minimum alignment of 1 for " "arguments passed by value on stack"))
static Value * returnEdge(const PHINode *PN, Value *IntrBaseVal)
static cl::opt< int > MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os", cl::Hidden, cl::init(4), cl::desc("Max #stores to inline memcpy"))
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst...
static cl::opt< int > MaxStoresPerMemsetOptSizeCL("max-store-memset-Os", cl::Hidden, cl::init(4), cl::desc("Max #stores to inline memset"))
static cl::opt< bool > EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, cl::desc("Control jump table emission on Hexagon target"))
static cl::opt< int > MinimumJumpTables("minimum-jump-tables", cl::Hidden, cl::init(5), cl::desc("Set minimum jump tables"))
static cl::opt< bool > EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden, cl::desc("Enable Hexagon SDNode scheduling"))
static cl::opt< bool > EnableFastMath("ffast-math", cl::Hidden, cl::desc("Enable Fast Math processing"))
#define Hexagon_PointerSize
#define HEXAGON_LRFP_SIZE
#define HEXAGON_GOT_SYM_NAME
IRTranslator LLVM IR MI
#define RegName(no)
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
#define G(x, y, z)
Definition: MD5.cpp:56
#define H(x, y, z)
Definition: MD5.cpp:57
std::pair< MCSymbol *, MachineModuleInfoImpl::StubValueTy > PairTy
unsigned const TargetRegisterInfo * TRI
#define T1
Module.h This file contains the declarations for the Module class.
LLVMContext & Context
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
#define P(N)
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static llvm::Type * getVectorElementType(llvm::Type *Ty)
Value * RHS
Value * LHS
APInt bitcastToAPInt() const
Definition: APFloat.h:1208
Class for arbitrary precision integers.
Definition: APInt.h:76
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1507
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
ArrayRef< T > take_front(size_t N=1) const
Return a copy of *this with only the first N elements.
Definition: ArrayRef.h:228
ArrayRef< T > drop_front(size_t N=1) const
Drop the first N elements of the array.
Definition: ArrayRef.h:204
iterator end() const
Definition: ArrayRef.h:154
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
iterator begin() const
Definition: ArrayRef.h:153
const T * data() const
Definition: ArrayRef.h:162
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:513
LLVM Basic Block Representation.
Definition: BasicBlock.h:56
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:112
The address of a basic block.
Definition: Constants.h:874
CCState - This class holds information needed while lowering arguments and return values.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
CCValAssign - Represent assignment of one arg/retval to a location.
bool isRegLoc() const
Register getLocReg() const
LocInfo getLocInfo() const
bool isMemLoc() const
int64_t getLocMemOffset() const
FunctionType * getFunctionType() const
Definition: InstrTypes.h:1270
This class represents a function call, abstracting a target machine's calling convention.
bool isTailCall() const
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:260
const APFloat & getValueAPF() const
Definition: Constants.h:296
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
Definition: Constants.h:197
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:888
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:136
MachineConstantPoolValue * getMachineCPVal() const
bool isMachineConstantPoolEntry() const
const Constant * getConstVal() const
int64_t getSExtValue() const
static Constant * get(ArrayRef< Constant * > V)
Definition: Constants.cpp:1342
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
A debug info location.
Definition: DebugLoc.h:33
This is the base abstract class for diagnostic reporting in the backend.
Interface for custom diagnostic printing.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
bool empty() const
Definition: Function.h:769
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:176
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:239
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:628
const GlobalValue * getGlobal() const
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:652
const GlobalObject * getAliaseeObject() const
Definition: Globals.cpp:367
bool isValidAutoIncImm(const EVT VT, const int Offset) const
Hexagon target-specific information for each MachineFunction.
Register getFrameRegister(const MachineFunction &MF) const override
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
const HexagonInstrInfo * getInstrInfo() const override
const HexagonFrameLowering * getFrameLowering() const override
const HexagonRegisterInfo * getRegisterInfo() const override
bool isHVXVectorType(EVT VecTy, bool IncludeBool=false) const
Align getTypeAlignment(MVT Ty) const
unsigned getVectorLength() const