LLVM  13.0.0git
VETargetTransformInfo.h
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1 //===- VETargetTransformInfo.h - VE specific TTI ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file a TargetTransformInfo::Concept conforming object specific to the
10 /// VE target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
18 
19 #include "VE.h"
20 #include "VETargetMachine.h"
23 
24 namespace llvm {
25 
26 class VETTIImpl : public BasicTTIImplBase<VETTIImpl> {
28  friend BaseT;
29 
30  const VESubtarget *ST;
31  const VETargetLowering *TLI;
32 
33  const VESubtarget *getST() const { return ST; }
34  const VETargetLowering *getTLI() const { return TLI; }
35 
36  bool enableVPU() const { return getST()->enableVPU(); }
37 
38 public:
39  explicit VETTIImpl(const VETargetMachine *TM, const Function &F)
40  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
41  TLI(ST->getTargetLowering()) {}
42 
43  unsigned getNumberOfRegisters(unsigned ClassID) const {
44  bool VectorRegs = (ClassID == 1);
45  if (VectorRegs) {
46  // TODO report vregs once vector isel is stable.
47  return 0;
48  }
49 
50  return 64;
51  }
52 
53  unsigned getRegisterBitWidth(bool Vector) const {
54  if (Vector) {
55  // TODO report vregs once vector isel is stable.
56  return 0;
57  }
58  return 64;
59  }
60 
61  unsigned getMinVectorRegisterBitWidth() const {
62  // TODO report vregs once vector isel is stable.
63  return 0;
64  }
65 };
66 
67 } // namespace llvm
68 
69 #endif // LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
llvm
This class represents lattice values for constants.
Definition: AllocatorList.h:23
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::Function
Definition: Function.h:61
llvm::VESubtarget::enableVPU
bool enableVPU() const
Definition: VESubtarget.h:65
llvm::VETTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: VETargetTransformInfo.h:61
llvm::VETTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: VETargetTransformInfo.h:43
llvm::VETTIImpl
Definition: VETargetTransformInfo.h:26
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:48
llvm::VETTIImpl::getRegisterBitWidth
unsigned getRegisterBitWidth(bool Vector) const
Definition: VETargetTransformInfo.h:53
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:75
llvm::VETTIImpl::VETTIImpl
VETTIImpl(const VETargetMachine *TM, const Function &F)
Definition: VETargetTransformInfo.h:39
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:780
llvm::VETargetMachine
Definition: VETargetMachine.h:22
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
VE.h
llvm::VESubtarget
Definition: VESubtarget.h:31
TargetTransformInfo.h
VETargetMachine.h
llvm::VETargetLowering
Definition: VEISelLowering.h:50
BasicTTIImpl.h