LLVM  15.0.0git
VEISelLowering.h
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1 //===-- VEISelLowering.h - VE DAG Lowering Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that VE uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_VE_VEISELLOWERING_H
15 #define LLVM_LIB_TARGET_VE_VEISELLOWERING_H
16 
17 #include "VE.h"
19 
20 namespace llvm {
21 class VESubtarget;
22 
23 namespace VEISD {
24 enum NodeType : unsigned {
26 
27  CALL, // A call instruction.
28  EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
29  EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
30  EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
31  GETFUNPLT, // Load function address through %plt insturction.
32  GETTLSADDR, // Load address for TLS access.
33  GETSTACKTOP, // Retrieve address of stack top (first address of
34  // locals and temporaries).
35  GLOBAL_BASE_REG, // Global base reg for PIC.
36  Hi, // Hi/Lo operations, typically on a global address.
37  Lo, // Hi/Lo operations, typically on a global address.
38  MEMBARRIER, // Compiler barrier only; generate a no-op.
39  RET_FLAG, // Return with a flag operand.
40  TS1AM, // A TS1AM instruction used for 1/2 bytes swap.
41  VEC_UNPACK_LO, // unpack the lo v256 slice of a packed v512 vector.
42  VEC_UNPACK_HI, // unpack the hi v256 slice of a packed v512 vector.
43  // 0: v512 vector, 1: AVL
44  VEC_PACK, // pack a lo and a hi vector into one v512 vector
45  // 0: v256 lo vector, 1: v256 hi vector, 2: AVL
46 
47  VEC_BROADCAST, // A vector broadcast instruction.
48  // 0: scalar value, 1: VL
50  REPL_F32, // Replicate subregister to other half.
51 
52  // Annotation as a wrapper. LEGALAVL(VL) means that VL refers to 64bit of
53  // data, whereas the raw EVL coming in from VP nodes always refers to number
54  // of elements, regardless of their size.
56 
57 // VVP_* nodes.
58 #define ADD_VVP_OP(VVP_NAME, ...) VVP_NAME,
59 #include "VVPNodes.def"
60 };
61 }
62 
63 class VECustomDAG;
64 
66  const VESubtarget *Subtarget;
67 
68  void initRegisterClasses();
69  void initSPUActions();
70  void initVPUActions();
71 
72 public:
73  VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);
74 
75  const char *getTargetNodeName(unsigned Opcode) const override;
76  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
77  return MVT::i32;
78  }
79 
80  Register getRegisterByName(const char *RegName, LLT VT,
81  const MachineFunction &MF) const override;
82 
83  /// getSetCCResultType - Return the ISD::SETCC ValueType
85  EVT VT) const override;
86 
88  bool isVarArg,
90  const SDLoc &dl, SelectionDAG &DAG,
91  SmallVectorImpl<SDValue> &InVals) const override;
92 
94  SmallVectorImpl<SDValue> &InVals) const override;
95 
97  bool isVarArg,
98  const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
99  LLVMContext &Context) const override;
100  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
102  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
103  SelectionDAG &DAG) const override;
104 
105  /// Helper functions for atomic operations.
106  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
107  // VE uses release consistency, so need fence for each atomics.
108  return true;
109  }
111  AtomicOrdering Ord) const override;
113  AtomicOrdering Ord) const override;
115  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
117  return ISD::ANY_EXTEND;
118  }
119 
120  /// Custom Lower {
122  getCustomOperationAction(SDNode &) const override;
123 
124  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
125  unsigned getJumpTableEncoding() const override;
127  const MachineBasicBlock *MBB,
128  unsigned Uid,
129  MCContext &Ctx) const override;
131  SelectionDAG &DAG) const override;
132  // VE doesn't need getPICJumpTableRelocBaseExpr since it is used for only
133  // EK_LabelDifference32.
134 
147  SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
152 
156  /// } Custom Lower
157 
158  /// Replace the results of node with an illegal result
159  /// type with new values built out of custom code.
160  ///
162  SelectionDAG &DAG) const override;
163 
164  /// Custom Inserter {
167  MachineBasicBlock *MBB) const override;
169  MachineBasicBlock *MBB) const;
171  MachineBasicBlock *MBB) const;
173  MachineBasicBlock *BB) const;
174 
176  MachineBasicBlock *DispatchBB, int FI,
177  int Offset) const;
178  // Setup basic block address.
180  MachineBasicBlock *TargetBB, const DebugLoc &DL) const;
181  // Prepare function/variable address.
183  StringRef Symbol, const DebugLoc &DL, bool IsLocal,
184  bool IsCall) const;
185  /// } Custom Inserter
186 
187  /// VVP Lowering {
191 
198  /// } VVPLowering
199 
200  /// Custom DAGCombine {
201  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
202 
203  SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
204  /// } Custom DAGCombine
205 
206  SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
207  SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
208  SelectionDAG &DAG) const;
210 
211  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
212  bool isFPImmLegal(const APFloat &Imm, EVT VT,
213  bool ForCodeSize) const override;
214  /// Returns true if the target allows unaligned memory accesses of the
215  /// specified type.
216  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A,
218  bool *Fast) const override;
219 
220  /// Inline Assembly {
221 
222  ConstraintType getConstraintType(StringRef Constraint) const override;
223  std::pair<unsigned, const TargetRegisterClass *>
225  StringRef Constraint, MVT VT) const override;
226 
227  /// } Inline Assembly
228 
229  /// Target Optimization {
230 
231  // Return lower limit for number of blocks in a jump table.
232  unsigned getMinimumJumpTableEntries() const override;
233 
234  // SX-Aurora VE's s/udiv is 5-9 times slower than multiply.
235  bool isIntDivCheap(EVT, AttributeList) const override { return false; }
236  // VE doesn't have rem.
237  bool hasStandaloneRem(EVT) const override { return false; }
238  // VE LDZ instruction returns 64 if the input is zero.
239  bool isCheapToSpeculateCtlz() const override { return true; }
240  // VE LDZ instruction is fast.
241  bool isCtlzFast() const override { return true; }
242  // VE has NND instruction.
243  bool hasAndNot(SDValue Y) const override;
244 
245  /// } Target Optimization
246 };
247 } // namespace llvm
248 
249 #endif // LLVM_LIB_TARGET_VE_VEISELLOWERING_H
llvm::VETargetLowering::legalizeInternalVectorOp
SDValue legalizeInternalVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: VVPISelLowering.cpp:323
llvm::VETargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: VEISelLowering.cpp:2692
llvm::VETargetLowering::makeHiLoPair
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:979
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::VETargetLowering::prepareSymbol
Register prepareSymbol(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, StringRef Symbol, const DebugLoc &DL, bool IsLocal, bool IsCall) const
Definition: VEISelLowering.cpp:1929
llvm::VETargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: VEISelLowering.cpp:349
llvm::VEISD::REPL_F32
@ REPL_F32
Definition: VEISelLowering.h:50
llvm::VETargetLowering::lowerBUILD_VECTOR
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1687
llvm::VEISD::REPL_I32
@ REPL_I32
Definition: VEISelLowering.h:49
llvm::VETargetLowering::emitEHSjLjSetJmp
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: VEISelLowering.cpp:2035
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1090
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::VETargetLowering::lowerVVP_LOAD_STORE
SDValue lowerVVP_LOAD_STORE(SDValue Op, VECustomDAG &) const
Definition: VVPISelLowering.cpp:123
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4362
llvm::VEISD::NodeType
NodeType
Definition: VEISelLowering.h:24
llvm::VETargetLowering::splitVectorOp
SDValue splitVectorOp(SDValue Op, VECustomDAG &CDAG) const
Definition: VVPISelLowering.cpp:344
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:74
llvm::VEISD::CALL
@ CALL
Definition: VEISelLowering.h:27
llvm::VETargetLowering::legalizePackedAVL
SDValue legalizePackedAVL(SDValue Op, VECustomDAG &CDAG) const
Definition: VVPISelLowering.cpp:396
llvm::VETargetLowering::lowerATOMIC_SWAP
SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1172
llvm::VEISD::Hi
@ Hi
Definition: VEISelLowering.h:36
llvm::VETargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: VEISelLowering.cpp:1855
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:232
llvm::VETargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: VEISelLowering.cpp:1059
llvm::VETargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Inline Assembly {.
Definition: VEISelLowering.cpp:2679
llvm::AttributeList
Definition: Attributes.h:408
llvm::VETargetLowering::lowerToTLSGeneralDynamicModel
SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1249
llvm::VETargetLowering::shouldExpandAtomicRMWInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: VEISelLowering.cpp:1124
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:848
llvm::VETargetLowering::lowerATOMIC_FENCE
SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1078
llvm::VEISD::GETFUNPLT
@ GETFUNPLT
Definition: VEISelLowering.h:31
llvm::VEISD::GETSTACKTOP
@ GETSTACKTOP
Definition: VEISelLowering.h:33
llvm::TargetLoweringBase::LegalizeAction
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
Definition: TargetLowering.h:195
llvm::VETargetLowering::withTargetFlags
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
} Custom DAGCombine
Definition: VEISelLowering.cpp:953
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::VEISD::LEGALAVL
@ LEGALAVL
Definition: VEISelLowering.h:55
llvm::VEISD::VEC_UNPACK_LO
@ VEC_UNPACK_LO
Definition: VEISelLowering.h:41
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::VETargetLowering::prepareMBB
Register prepareMBB(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TargetBB, const DebugLoc &DL) const
Definition: VEISelLowering.cpp:1880
llvm::VETargetLowering::VETargetLowering
VETargetLowering(const TargetMachine &TM, const VESubtarget &STI)
Definition: VEISelLowering.cpp:881
llvm::VETargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: VEISelLowering.cpp:563
TargetLowering.h
llvm::VETargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: VEISelLowering.cpp:910
llvm::VEISD::GLOBAL_BASE_REG
@ GLOBAL_BASE_REG
Definition: VEISelLowering.h:35
llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:2749
llvm::VETargetLowering::lowerGlobalAddress
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1233
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::VETargetLowering::lowerEH_SJLJ_SETJMP
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1567
llvm::VEISD::VEC_BROADCAST
@ VEC_BROADCAST
Definition: VEISelLowering.h:47
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::VETargetLowering::splitMaskArithmetic
SDValue splitMaskArithmetic(SDValue Op, SelectionDAG &DAG) const
Definition: VVPISelLowering.cpp:21
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3362
llvm::VETargetLowering::lowerVAARG
SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1442
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::VETargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
Definition: VEISelLowering.cpp:855
llvm::VETargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: VEISelLowering.cpp:423
llvm::VETargetLowering::hasAndNot
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
Definition: VEISelLowering.cpp:2725
llvm::VEISD::VEC_UNPACK_HI
@ VEC_UNPACK_HI
Definition: VEISelLowering.h:42
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::Instruction
Definition: Instruction.h:42
llvm::VETargetLowering::emitSjLjDispatchBlock
MachineBasicBlock * emitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: VEISelLowering.cpp:2233
llvm::VETargetLowering::lowerEH_SJLJ_SETUP_DISPATCH
SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1575
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1495
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::VETargetLowering::LowerCustomJumpTableEntry
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned Uid, MCContext &Ctx) const override
Definition: VEISelLowering.cpp:1842
llvm::VETargetLowering::lowerBlockAddress
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1238
llvm::VETargetLowering::hasStandaloneRem
bool hasStandaloneRem(EVT) const override
Return true if the target can handle a standalone remainder operation.
Definition: VEISelLowering.h:237
llvm::VEISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
Definition: VEISelLowering.h:29
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::APFloat
Definition: APFloat.h:700
llvm::VETargetLowering::lowerSTORE
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1400
llvm::VETargetLowering::getMinimumJumpTableEntries
unsigned getMinimumJumpTableEntries() const override
} Inline Assembly
Definition: VEISelLowering.cpp:2717
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::VEISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: VEISelLowering.h:25
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::VETargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: VEISelLowering.h:76
llvm::VETargetLowering::lowerJumpTable
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1298
llvm::VETargetLowering::lowerConstantPool
SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1243
llvm::VEISD::MEMBARRIER
@ MEMBARRIER
Definition: VEISelLowering.h:38
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:129
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3952
llvm::VETargetLowering::isIntDivCheap
bool isIntDivCheap(EVT, AttributeList) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
Definition: VEISelLowering.h:235
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1623
llvm::VETargetLowering::lowerGlobalTLSAddress
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1288
llvm::VETargetLowering::lowerLOAD
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1342
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::VETargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: VEISelLowering.h:116
llvm::VETargetLowering::makeAddress
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:990
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::VETargetLowering::lowerVASTART
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1423
llvm::VETargetLowering::getCustomOperationAction
TargetLoweringBase::LegalizeAction getCustomOperationAction(SDNode &) const override
Custom Lower {.
Definition: VEISelLowering.cpp:1713
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::VEISD::GETTLSADDR
@ GETTLSADDR
Definition: VEISelLowering.h:32
llvm::VETargetLowering::emitEHSjLjLongJmp
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: VEISelLowering.cpp:2166
llvm::VECustomDAG
Definition: VECustomDAG.h:142
llvm::VETargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Helper functions for atomic operations.
Definition: VEISelLowering.h:106
llvm::VETargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
Definition: VEISelLowering.cpp:947
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:93
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::VETargetLowering::lowerEH_SJLJ_LONGJMP
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1560
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1287
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:727
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::VEISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
Definition: VEISelLowering.h:28
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::VEISD::VEC_PACK
@ VEC_PACK
Definition: VEISelLowering.h:44
llvm::VETargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: VEISelLowering.cpp:843
llvm::VEISD::RET_FLAG
@ RET_FLAG
Definition: VEISelLowering.h:39
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1734
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
llvm::VETargetLowering::setupEntryBlockForSjLj
void setupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI, int Offset) const
Definition: VEISelLowering.cpp:2017
llvm::VEISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
Definition: VEISelLowering.h:30
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:326
llvm::VETargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Custom Lower {.
Definition: VEISelLowering.cpp:1038
llvm::VETargetLowering::legalizeInternalLoadStoreOp
SDValue legalizeInternalLoadStoreOp(SDValue Op, VECustomDAG &CDAG) const
Definition: VVPISelLowering.cpp:311
llvm::VEISD::TS1AM
@ TS1AM
Definition: VEISelLowering.h:40
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::VETargetLowering::lowerVVP_GATHER_SCATTER
SDValue lowerVVP_GATHER_SCATTER(SDValue Op, VECustomDAG &) const
Definition: VVPISelLowering.cpp:263
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::VEISD::Lo
@ Lo
Definition: VEISelLowering.h:37
llvm::VETargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A, MachineMemOperand::Flags Flags, bool *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: VEISelLowering.cpp:869
llvm::VETargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
JumpTable for VE.
Definition: VEISelLowering.cpp:1833
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
VE.h
llvm::VETargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: VEISelLowering.cpp:67
llvm::VETargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
} Custom Lower
Definition: VEISelLowering.cpp:1810
llvm::VETargetLowering::splitPackedLoadStore
SDValue splitPackedLoadStore(SDValue Op, VECustomDAG &CDAG) const
Definition: VVPISelLowering.cpp:176
llvm::VETargetLowering::lowerINSERT_VECTOR_ELT
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:2794
llvm::VETargetLowering::combineTRUNCATE
SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const
Definition: VEISelLowering.cpp:2623
llvm::VESubtarget
Definition: VESubtarget.h:31
N
#define N
llvm::VETargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
Custom Inserter {.
Definition: VEISelLowering.cpp:2537
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
RegName
#define RegName(no)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::VETargetLowering
Definition: VEISelLowering.h:65
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::VETargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: VEISelLowering.cpp:1729
llvm::VETargetLowering::isCtlzFast
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
Definition: VEISelLowering.h:241
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
llvm::VETargetLowering::lowerToVVP
SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const
} Custom Inserter
Definition: VVPISelLowering.cpp:38
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::VETargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: VEISelLowering.h:239
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::VETargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
} VVPLowering
Definition: VEISelLowering.cpp:2662
llvm::VETargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: VEISelLowering.cpp:539
llvm::LLT
Definition: LowLevelTypeImpl.h:39