LLVM  16.0.0git
VEISelLowering.h
Go to the documentation of this file.
1 //===-- VEISelLowering.h - VE DAG Lowering Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that VE uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_VE_VEISELLOWERING_H
15 #define LLVM_LIB_TARGET_VE_VEISELLOWERING_H
16 
17 #include "VE.h"
19 
20 namespace llvm {
21 class VESubtarget;
22 
23 namespace VEISD {
24 enum NodeType : unsigned {
26 
27  CMPI, // Compare between two signed integer values.
28  CMPU, // Compare between two unsigned integer values.
29  CMPF, // Compare between two floating-point values.
30  CMPQ, // Compare between two quad floating-point values.
31  CMOV, // Select between two values using the result of comparison.
32 
33  CALL, // A call instruction.
34  EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
35  EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
36  EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
37  GETFUNPLT, // Load function address through %plt insturction.
38  GETTLSADDR, // Load address for TLS access.
39  GETSTACKTOP, // Retrieve address of stack top (first address of
40  // locals and temporaries).
41  GLOBAL_BASE_REG, // Global base reg for PIC.
42  Hi, // Hi/Lo operations, typically on a global address.
43  Lo, // Hi/Lo operations, typically on a global address.
44  MEMBARRIER, // Compiler barrier only; generate a no-op.
45  RET_FLAG, // Return with a flag operand.
46  TS1AM, // A TS1AM instruction used for 1/2 bytes swap.
47  VEC_UNPACK_LO, // unpack the lo v256 slice of a packed v512 vector.
48  VEC_UNPACK_HI, // unpack the hi v256 slice of a packed v512 vector.
49  // 0: v512 vector, 1: AVL
50  VEC_PACK, // pack a lo and a hi vector into one v512 vector
51  // 0: v256 lo vector, 1: v256 hi vector, 2: AVL
52 
53  VEC_BROADCAST, // A vector broadcast instruction.
54  // 0: scalar value, 1: VL
56  REPL_F32, // Replicate subregister to other half.
57 
58  // Annotation as a wrapper. LEGALAVL(VL) means that VL refers to 64bit of
59  // data, whereas the raw EVL coming in from VP nodes always refers to number
60  // of elements, regardless of their size.
62 
63 // VVP_* nodes.
64 #define ADD_VVP_OP(VVP_NAME, ...) VVP_NAME,
65 #include "VVPNodes.def"
66 };
67 }
68 
69 class VECustomDAG;
70 
72  const VESubtarget *Subtarget;
73 
74  void initRegisterClasses();
75  void initSPUActions();
76  void initVPUActions();
77 
78 public:
79  VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);
80 
81  const char *getTargetNodeName(unsigned Opcode) const override;
82  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
83  return MVT::i32;
84  }
85 
86  Register getRegisterByName(const char *RegName, LLT VT,
87  const MachineFunction &MF) const override;
88 
89  /// getSetCCResultType - Return the ISD::SETCC ValueType
91  EVT VT) const override;
92 
94  bool isVarArg,
96  const SDLoc &dl, SelectionDAG &DAG,
97  SmallVectorImpl<SDValue> &InVals) const override;
98 
100  SmallVectorImpl<SDValue> &InVals) const override;
101 
103  bool isVarArg,
104  const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
105  LLVMContext &Context) const override;
106  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
108  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
109  SelectionDAG &DAG) const override;
110 
111  /// Helper functions for atomic operations.
112  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
113  // VE uses release consistency, so need fence for each atomics.
114  return true;
115  }
117  AtomicOrdering Ord) const override;
119  AtomicOrdering Ord) const override;
121  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
123  return ISD::ANY_EXTEND;
124  }
125 
126  /// Custom Lower {
128  getCustomOperationAction(SDNode &) const override;
129 
130  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
131  unsigned getJumpTableEncoding() const override;
133  const MachineBasicBlock *MBB,
134  unsigned Uid,
135  MCContext &Ctx) const override;
137  SelectionDAG &DAG) const override;
138  // VE doesn't need getPICJumpTableRelocBaseExpr since it is used for only
139  // EK_LabelDifference32.
140 
153  SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
158 
162  /// } Custom Lower
163 
164  /// Replace the results of node with an illegal result
165  /// type with new values built out of custom code.
166  ///
168  SelectionDAG &DAG) const override;
169 
170  /// Custom Inserter {
173  MachineBasicBlock *MBB) const override;
175  MachineBasicBlock *MBB) const;
177  MachineBasicBlock *MBB) const;
179  MachineBasicBlock *BB) const;
180 
182  MachineBasicBlock *DispatchBB, int FI,
183  int Offset) const;
184  // Setup basic block address.
186  MachineBasicBlock *TargetBB, const DebugLoc &DL) const;
187  // Prepare function/variable address.
189  StringRef Symbol, const DebugLoc &DL, bool IsLocal,
190  bool IsCall) const;
191  /// } Custom Inserter
192 
193  /// VVP Lowering {
197 
204  /// } VVPLowering
205 
206  /// Custom DAGCombine {
207  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
208 
209  SDValue combineSelect(SDNode *N, DAGCombinerInfo &DCI) const;
210  SDValue combineSelectCC(SDNode *N, DAGCombinerInfo &DCI) const;
211  SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
212  /// } Custom DAGCombine
213 
214  SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
215  SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
216  SelectionDAG &DAG) const;
218 
219  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
220  bool isFPImmLegal(const APFloat &Imm, EVT VT,
221  bool ForCodeSize) const override;
222  /// Returns true if the target allows unaligned memory accesses of the
223  /// specified type.
224  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A,
226  unsigned *Fast) const override;
227 
228  /// Inline Assembly {
229 
230  ConstraintType getConstraintType(StringRef Constraint) const override;
231  std::pair<unsigned, const TargetRegisterClass *>
233  StringRef Constraint, MVT VT) const override;
234 
235  /// } Inline Assembly
236 
237  /// Target Optimization {
238 
239  // Return lower limit for number of blocks in a jump table.
240  unsigned getMinimumJumpTableEntries() const override;
241 
242  // SX-Aurora VE's s/udiv is 5-9 times slower than multiply.
243  bool isIntDivCheap(EVT, AttributeList) const override { return false; }
244  // VE doesn't have rem.
245  bool hasStandaloneRem(EVT) const override { return false; }
246  // VE LDZ instruction returns 64 if the input is zero.
247  bool isCheapToSpeculateCtlz(Type *) const override { return true; }
248  // VE LDZ instruction is fast.
249  bool isCtlzFast() const override { return true; }
250  // VE has NND instruction.
251  bool hasAndNot(SDValue Y) const override;
252 
253  /// } Target Optimization
254 };
255 } // namespace llvm
256 
257 #endif // LLVM_LIB_TARGET_VE_VEISELLOWERING_H
llvm::VETargetLowering::legalizeInternalVectorOp
SDValue legalizeInternalVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: VVPISelLowering.cpp:323
llvm::VETargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: VEISelLowering.cpp:3065
llvm::VETargetLowering::makeHiLoPair
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1003
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::VETargetLowering::prepareSymbol
Register prepareSymbol(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, StringRef Symbol, const DebugLoc &DL, bool IsLocal, bool IsCall) const
Definition: VEISelLowering.cpp:2073
llvm::VETargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: VEISelLowering.cpp:367
llvm::VEISD::REPL_F32
@ REPL_F32
Definition: VEISelLowering.h:56
llvm::VETargetLowering::lowerBUILD_VECTOR
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1831
llvm::VEISD::REPL_I32
@ REPL_I32
Definition: VEISelLowering.h:55
llvm::VETargetLowering::emitEHSjLjSetJmp
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: VEISelLowering.cpp:2179
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1105
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::VETargetLowering::lowerVVP_LOAD_STORE
SDValue lowerVVP_LOAD_STORE(SDValue Op, VECustomDAG &) const
Definition: VVPISelLowering.cpp:123
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4550
llvm::VEISD::NodeType
NodeType
Definition: VEISelLowering.h:24
llvm::VEISD::CMPU
@ CMPU
Definition: VEISelLowering.h:28
llvm::VETargetLowering::splitVectorOp
SDValue splitVectorOp(SDValue Op, VECustomDAG &CDAG) const
Definition: VVPISelLowering.cpp:344
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::VEISD::CALL
@ CALL
Definition: VEISelLowering.h:33
llvm::VETargetLowering::legalizePackedAVL
SDValue legalizePackedAVL(SDValue Op, VECustomDAG &CDAG) const
Definition: VVPISelLowering.cpp:396
llvm::VETargetLowering::lowerATOMIC_SWAP
SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1196
llvm::VEISD::Hi
@ Hi
Definition: VEISelLowering.h:42
llvm::VETargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: VEISelLowering.cpp:1999
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::VETargetLowering::combineSelectCC
SDValue combineSelectCC(SDNode *N, DAGCombinerInfo &DCI) const
Definition: VEISelLowering.cpp:2832
llvm::VETargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: VEISelLowering.cpp:1083
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::VETargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Inline Assembly {.
Definition: VEISelLowering.cpp:3052
llvm::AttributeList
Definition: Attributes.h:430
llvm::VETargetLowering::lowerToTLSGeneralDynamicModel
SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1273
llvm::VETargetLowering::shouldExpandAtomicRMWInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: VEISelLowering.cpp:1148
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:772
llvm::VETargetLowering::lowerATOMIC_FENCE
SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1102
llvm::VEISD::GETFUNPLT
@ GETFUNPLT
Definition: VEISelLowering.h:37
llvm::VEISD::GETSTACKTOP
@ GETSTACKTOP
Definition: VEISelLowering.h:39
llvm::TargetLoweringBase::LegalizeAction
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
Definition: TargetLowering.h:195
llvm::VETargetLowering::withTargetFlags
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
} Custom DAGCombine
Definition: VEISelLowering.cpp:977
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::VEISD::LEGALAVL
@ LEGALAVL
Definition: VEISelLowering.h:61
llvm::VEISD::VEC_UNPACK_LO
@ VEC_UNPACK_LO
Definition: VEISelLowering.h:47
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::VETargetLowering::prepareMBB
Register prepareMBB(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TargetBB, const DebugLoc &DL) const
Definition: VEISelLowering.cpp:2024
llvm::VETargetLowering::VETargetLowering
VETargetLowering(const TargetMachine &TM, const VESubtarget &STI)
Definition: VEISelLowering.cpp:898
llvm::VETargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: VEISelLowering.cpp:581
TargetLowering.h
llvm::VETargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: VEISelLowering.cpp:929
llvm::VEISD::GLOBAL_BASE_REG
@ GLOBAL_BASE_REG
Definition: VEISelLowering.h:41
llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:3122
llvm::VETargetLowering::lowerGlobalAddress
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1257
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::VETargetLowering::lowerEH_SJLJ_SETJMP
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1711
llvm::VEISD::VEC_BROADCAST
@ VEC_BROADCAST
Definition: VEISelLowering.h:53
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::VETargetLowering::splitMaskArithmetic
SDValue splitMaskArithmetic(SDValue Op, SelectionDAG &DAG) const
Definition: VVPISelLowering.cpp:21
llvm::VETargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: VEISelLowering.cpp:886
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3486
llvm::VETargetLowering::lowerVAARG
SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1587
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::VETargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
Definition: VEISelLowering.cpp:872
llvm::VETargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: VEISelLowering.cpp:441
llvm::VETargetLowering::hasAndNot
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
Definition: VEISelLowering.cpp:3098
llvm::VEISD::VEC_UNPACK_HI
@ VEC_UNPACK_HI
Definition: VEISelLowering.h:48
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::Instruction
Definition: Instruction.h:42
llvm::VETargetLowering::emitSjLjDispatchBlock
MachineBasicBlock * emitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: VEISelLowering.cpp:2377
llvm::VETargetLowering::lowerEH_SJLJ_SETUP_DISPATCH
SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1719
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1640
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::VETargetLowering::LowerCustomJumpTableEntry
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned Uid, MCContext &Ctx) const override
Definition: VEISelLowering.cpp:1986
llvm::VETargetLowering::lowerBlockAddress
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1262
llvm::VETargetLowering::hasStandaloneRem
bool hasStandaloneRem(EVT) const override
Return true if the target can handle a standalone remainder operation.
Definition: VEISelLowering.h:245
llvm::VEISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
Definition: VEISelLowering.h:35
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::APFloat
Definition: APFloat.h:716
llvm::VETargetLowering::lowerSTORE
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1543
llvm::VETargetLowering::getMinimumJumpTableEntries
unsigned getMinimumJumpTableEntries() const override
} Inline Assembly
Definition: VEISelLowering.cpp:3090
llvm::VEISD::CMPF
@ CMPF
Definition: VEISelLowering.h:29
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::VEISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: VEISelLowering.h:25
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::VETargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: VEISelLowering.h:82
llvm::VETargetLowering::lowerJumpTable
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1320
llvm::VEISD::CMPQ
@ CMPQ
Definition: VEISelLowering.h:30
llvm::VETargetLowering::lowerConstantPool
SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1267
llvm::VEISD::MEMBARRIER
@ MEMBARRIER
Definition: VEISelLowering.h:44
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:4134
llvm::VETargetLowering::isIntDivCheap
bool isIntDivCheap(EVT, AttributeList) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
Definition: VEISelLowering.h:243
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1767
llvm::VETargetLowering::lowerGlobalTLSAddress
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1310
llvm::VETargetLowering::lowerLOAD
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1430
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::VETargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: VEISelLowering.h:122
llvm::VETargetLowering::makeAddress
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1014
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::VETargetLowering::lowerVASTART
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1568
llvm::VETargetLowering::getCustomOperationAction
TargetLoweringBase::LegalizeAction getCustomOperationAction(SDNode &) const override
Custom Lower {.
Definition: VEISelLowering.cpp:1857
llvm::VETargetLowering::combineSelect
SDValue combineSelect(SDNode *N, DAGCombinerInfo &DCI) const
Definition: VEISelLowering.cpp:2791
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::VEISD::GETTLSADDR
@ GETTLSADDR
Definition: VEISelLowering.h:38
llvm::VETargetLowering::emitEHSjLjLongJmp
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: VEISelLowering.cpp:2310
llvm::VECustomDAG
Definition: VECustomDAG.h:142
llvm::VETargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Helper functions for atomic operations.
Definition: VEISelLowering.h:112
llvm::VETargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
Definition: VEISelLowering.cpp:971
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:93
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::VETargetLowering::lowerEH_SJLJ_LONGJMP
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1704
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1307
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:714
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::VEISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
Definition: VEISelLowering.h:34
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::VEISD::CMOV
@ CMOV
Definition: VEISelLowering.h:31
llvm::VEISD::VEC_PACK
@ VEC_PACK
Definition: VEISelLowering.h:50
llvm::VETargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: VEISelLowering.cpp:860
llvm::VEISD::RET_FLAG
@ RET_FLAG
Definition: VEISelLowering.h:45
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1758
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
llvm::VETargetLowering::setupEntryBlockForSjLj
void setupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI, int Offset) const
Definition: VEISelLowering.cpp:2161
llvm::VEISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
Definition: VEISelLowering.h:36
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::VETargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Custom Lower {.
Definition: VEISelLowering.cpp:1062
llvm::VETargetLowering::legalizeInternalLoadStoreOp
SDValue legalizeInternalLoadStoreOp(SDValue Op, VECustomDAG &CDAG) const
Definition: VVPISelLowering.cpp:311
llvm::VEISD::TS1AM
@ TS1AM
Definition: VEISelLowering.h:46
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::VETargetLowering::lowerVVP_GATHER_SCATTER
SDValue lowerVVP_GATHER_SCATTER(SDValue Op, VECustomDAG &) const
Definition: VVPISelLowering.cpp:263
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::VEISD::CMPI
@ CMPI
Definition: VEISelLowering.h:27
llvm::VEISD::Lo
@ Lo
Definition: VEISelLowering.h:43
llvm::VETargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
JumpTable for VE.
Definition: VEISelLowering.cpp:1977
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
VE.h
llvm::VETargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: VEISelLowering.cpp:67
llvm::VETargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: VEISelLowering.h:247
llvm::VETargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
} Custom Lower
Definition: VEISelLowering.cpp:1954
llvm::VETargetLowering::splitPackedLoadStore
SDValue splitPackedLoadStore(SDValue Op, VECustomDAG &CDAG) const
Definition: VVPISelLowering.cpp:176
llvm::VETargetLowering::lowerINSERT_VECTOR_ELT
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:3167
llvm::VETargetLowering::combineTRUNCATE
SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const
Definition: VEISelLowering.cpp:2992
llvm::VESubtarget
Definition: VESubtarget.h:31
N
#define N
llvm::VETargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
Custom Inserter {.
Definition: VEISelLowering.cpp:2681
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
RegName
#define RegName(no)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::VETargetLowering
Definition: VEISelLowering.h:71
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::VETargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: VEISelLowering.cpp:1873
llvm::VETargetLowering::isCtlzFast
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
Definition: VEISelLowering.h:249
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
llvm::VETargetLowering::lowerToVVP
SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const
} Custom Inserter
Definition: VVPISelLowering.cpp:38
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::VETargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
} VVPLowering
Definition: VEISelLowering.cpp:3031
llvm::VETargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: VEISelLowering.cpp:557
llvm::LLT
Definition: LowLevelTypeImpl.h:39