LLVM  14.0.0git
VEISelLowering.h
Go to the documentation of this file.
1 //===-- VEISelLowering.h - VE DAG Lowering Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that VE uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_VE_VEISELLOWERING_H
15 #define LLVM_LIB_TARGET_VE_VEISELLOWERING_H
16 
17 #include "VE.h"
19 
20 namespace llvm {
21 class VESubtarget;
22 
23 namespace VEISD {
24 enum NodeType : unsigned {
26 
27  CALL, // A call instruction.
28  EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
29  EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
30  EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
31  GETFUNPLT, // Load function address through %plt insturction.
32  GETTLSADDR, // Load address for TLS access.
33  GETSTACKTOP, // Retrieve address of stack top (first address of
34  // locals and temporaries).
35  GLOBAL_BASE_REG, // Global base reg for PIC.
36  Hi, // Hi/Lo operations, typically on a global address.
37  Lo, // Hi/Lo operations, typically on a global address.
38  MEMBARRIER, // Compiler barrier only; generate a no-op.
39  RET_FLAG, // Return with a flag operand.
40  TS1AM, // A TS1AM instruction used for 1/2 bytes swap.
41  VEC_BROADCAST, // A vector broadcast instruction.
42  // 0: scalar value, 1: VL
43 
44 // VVP_* nodes.
45 #define ADD_VVP_OP(VVP_NAME, ...) VVP_NAME,
46 #include "VVPNodes.def"
47 };
48 }
49 
51  const VESubtarget *Subtarget;
52 
53  void initRegisterClasses();
54  void initSPUActions();
55  void initVPUActions();
56 
57 public:
58  VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);
59 
60  const char *getTargetNodeName(unsigned Opcode) const override;
61  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
62  return MVT::i32;
63  }
64 
65  Register getRegisterByName(const char *RegName, LLT VT,
66  const MachineFunction &MF) const override;
67 
68  /// getSetCCResultType - Return the ISD::SETCC ValueType
70  EVT VT) const override;
71 
73  bool isVarArg,
75  const SDLoc &dl, SelectionDAG &DAG,
76  SmallVectorImpl<SDValue> &InVals) const override;
77 
79  SmallVectorImpl<SDValue> &InVals) const override;
80 
82  bool isVarArg,
83  const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
84  LLVMContext &Context) const override;
85  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
87  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
88  SelectionDAG &DAG) const override;
89 
90  /// Helper functions for atomic operations.
91  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
92  // VE uses release consistency, so need fence for each atomics.
93  return true;
94  }
96  AtomicOrdering Ord) const override;
98  AtomicOrdering Ord) const override;
100  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
102  return ISD::ANY_EXTEND;
103  }
104 
105  /// Custom Lower {
106  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
107  unsigned getJumpTableEncoding() const override;
109  const MachineBasicBlock *MBB,
110  unsigned Uid,
111  MCContext &Ctx) const override;
113  SelectionDAG &DAG) const override;
114  // VE doesn't need getPICJumpTableRelocBaseExpr since it is used for only
115  // EK_LabelDifference32.
116 
129  SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
134 
138  /// } Custom Lower
139 
140  /// Replace the results of node with an illegal result
141  /// type with new values built out of custom code.
142  ///
144  SelectionDAG &DAG) const override;
145 
146  /// Custom Inserter {
149  MachineBasicBlock *MBB) const override;
151  MachineBasicBlock *MBB) const;
153  MachineBasicBlock *MBB) const;
155  MachineBasicBlock *BB) const;
156 
158  MachineBasicBlock *DispatchBB, int FI,
159  int Offset) const;
160  // Setup basic block address.
162  MachineBasicBlock *TargetBB, const DebugLoc &DL) const;
163  // Prepare function/variable address.
165  StringRef Symbol, const DebugLoc &DL, bool IsLocal,
166  bool IsCall) const;
167  /// } Custom Inserter
168 
169  /// VVP Lowering {
171  /// } VVPLowering
172 
173  /// Custom DAGCombine {
174  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
175 
176  SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
177  /// } Custom DAGCombine
178 
179  SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
180  SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
181  SelectionDAG &DAG) const;
183 
184  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
185  bool isFPImmLegal(const APFloat &Imm, EVT VT,
186  bool ForCodeSize) const override;
187  /// Returns true if the target allows unaligned memory accesses of the
188  /// specified type.
189  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A,
191  bool *Fast) const override;
192 
193  /// Inline Assembly {
194 
195  ConstraintType getConstraintType(StringRef Constraint) const override;
196  std::pair<unsigned, const TargetRegisterClass *>
198  StringRef Constraint, MVT VT) const override;
199 
200  /// } Inline Assembly
201 
202  /// Target Optimization {
203 
204  // Return lower limit for number of blocks in a jump table.
205  unsigned getMinimumJumpTableEntries() const override;
206 
207  // SX-Aurora VE's s/udiv is 5-9 times slower than multiply.
208  bool isIntDivCheap(EVT, AttributeList) const override { return false; }
209  // VE doesn't have rem.
210  bool hasStandaloneRem(EVT) const override { return false; }
211  // VE LDZ instruction returns 64 if the input is zero.
212  bool isCheapToSpeculateCtlz() const override { return true; }
213  // VE LDZ instruction is fast.
214  bool isCtlzFast() const override { return true; }
215  // VE has NND instruction.
216  bool hasAndNot(SDValue Y) const override;
217 
218  /// } Target Optimization
219 };
220 } // namespace llvm
221 
222 #endif // VE_ISELLOWERING_H
llvm::VETargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: VEISelLowering.cpp:2612
llvm::VETargetLowering::makeHiLoPair
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:942
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::VETargetLowering::prepareSymbol
Register prepareSymbol(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, StringRef Symbol, const DebugLoc &DL, bool IsLocal, bool IsCall) const
Definition: VEISelLowering.cpp:1849
llvm::VETargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: VEISelLowering.cpp:319
llvm::VETargetLowering::lowerBUILD_VECTOR
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1641
llvm::VETargetLowering::emitEHSjLjSetJmp
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: VEISelLowering.cpp:1955
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1085
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4222
llvm::VEISD::NodeType
NodeType
Definition: VEISelLowering.h:24
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::VEISD::CALL
@ CALL
Definition: VEISelLowering.h:27
llvm::VETargetLowering::lowerATOMIC_SWAP
SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1135
llvm::VEISD::Hi
@ Hi
Definition: VEISelLowering.h:36
llvm::VETargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: VEISelLowering.cpp:1775
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:732
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::VETargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: VEISelLowering.cpp:1022
llvm::VETargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Inline Assembly {.
Definition: VEISelLowering.cpp:2599
llvm::AttributeList
Definition: Attributes.h:398
llvm::VETargetLowering::lowerToTLSGeneralDynamicModel
SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1212
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::VETargetLowering::shouldExpandAtomicRMWInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: VEISelLowering.cpp:1087
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:847
llvm::VETargetLowering::lowerATOMIC_FENCE
SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1041
llvm::VEISD::GETFUNPLT
@ GETFUNPLT
Definition: VEISelLowering.h:31
llvm::VEISD::GETSTACKTOP
@ GETSTACKTOP
Definition: VEISelLowering.h:33
llvm::VETargetLowering::withTargetFlags
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
} Custom DAGCombine
Definition: VEISelLowering.cpp:916
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
llvm::VETargetLowering::prepareMBB
Register prepareMBB(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TargetBB, const DebugLoc &DL) const
Definition: VEISelLowering.cpp:1800
llvm::VETargetLowering::VETargetLowering
VETargetLowering(const TargetMachine &TM, const VESubtarget &STI)
Definition: VEISelLowering.cpp:851
llvm::VETargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: VEISelLowering.cpp:533
TargetLowering.h
llvm::VETargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: VEISelLowering.cpp:880
llvm::VEISD::GLOBAL_BASE_REG
@ GLOBAL_BASE_REG
Definition: VEISelLowering.h:35
llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:2736
llvm::VETargetLowering::lowerGlobalAddress
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1196
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::VETargetLowering::lowerEH_SJLJ_SETJMP
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1521
llvm::VEISD::VEC_BROADCAST
@ VEC_BROADCAST
Definition: VEISelLowering.h:41
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3254
llvm::VETargetLowering::lowerVAARG
SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1396
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::VETargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
Definition: VEISelLowering.cpp:825
llvm::VETargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: VEISelLowering.cpp:393
llvm::VETargetLowering::hasAndNot
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
Definition: VEISelLowering.cpp:2645
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::Instruction
Definition: Instruction.h:45
llvm::VETargetLowering::emitSjLjDispatchBlock
MachineBasicBlock * emitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: VEISelLowering.cpp:2153
llvm::VETargetLowering::lowerEH_SJLJ_SETUP_DISPATCH
SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1529
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1449
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::VETargetLowering::LowerCustomJumpTableEntry
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned Uid, MCContext &Ctx) const override
Definition: VEISelLowering.cpp:1762
llvm::VETargetLowering::lowerBlockAddress
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1201
llvm::VETargetLowering::hasStandaloneRem
bool hasStandaloneRem(EVT) const override
Return true if the target can handle a standalone remainder operation.
Definition: VEISelLowering.h:210
llvm::VEISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
Definition: VEISelLowering.h:29
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::APFloat
Definition: APFloat.h:701
llvm::VETargetLowering::lowerSTORE
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1358
llvm::VETargetLowering::getMinimumJumpTableEntries
unsigned getMinimumJumpTableEntries() const override
} Inline Assembly
Definition: VEISelLowering.cpp:2637
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::VEISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: VEISelLowering.h:25
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::VETargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: VEISelLowering.h:61
llvm::VETargetLowering::lowerJumpTable
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1261
llvm::VETargetLowering::lowerConstantPool
SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1206
llvm::VEISD::MEMBARRIER
@ MEMBARRIER
Definition: VEISelLowering.h:38
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3812
llvm::VETargetLowering::isIntDivCheap
bool isIntDivCheap(EVT, AttributeList) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
Definition: VEISelLowering.h:208
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1577
llvm::VETargetLowering::lowerGlobalTLSAddress
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1251
llvm::VETargetLowering::lowerLOAD
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1305
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::VETargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: VEISelLowering.h:101
llvm::VETargetLowering::makeAddress
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:953
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:650
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::VETargetLowering::lowerVASTART
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1377
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::VEISD::GETTLSADDR
@ GETTLSADDR
Definition: VEISelLowering.h:32
llvm::VETargetLowering::emitEHSjLjLongJmp
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: VEISelLowering.cpp:2086
llvm::VETargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Helper functions for atomic operations.
Definition: VEISelLowering.h:91
llvm::VETargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
Definition: VEISelLowering.cpp:910
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:95
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::VETargetLowering::lowerEH_SJLJ_LONGJMP
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1514
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1249
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:726
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::VEISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
Definition: VEISelLowering.h:28
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::VETargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: VEISelLowering.cpp:813
llvm::VEISD::RET_FLAG
@ RET_FLAG
Definition: VEISelLowering.h:39
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1717
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:250
llvm::VETargetLowering::setupEntryBlockForSjLj
void setupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI, int Offset) const
Definition: VEISelLowering.cpp:1937
llvm::VEISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
Definition: VEISelLowering.h:30
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::VETargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Custom Lower {.
Definition: VEISelLowering.cpp:1001
llvm::VEISD::TS1AM
@ TS1AM
Definition: VEISelLowering.h:40
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::VEISD::Lo
@ Lo
Definition: VEISelLowering.h:37
llvm::VETargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A, MachineMemOperand::Flags Flags, bool *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: VEISelLowering.cpp:839
llvm::VETargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
JumpTable for VE.
Definition: VEISelLowering.cpp:1753
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
VE.h
llvm::VETargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: VEISelLowering.cpp:66
llvm::VETargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
} Custom Lower
Definition: VEISelLowering.cpp:1730
llvm::VETargetLowering::lowerINSERT_VECTOR_ELT
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:2781
llvm::VETargetLowering::combineTRUNCATE
SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const
Definition: VEISelLowering.cpp:2543
llvm::VESubtarget
Definition: VESubtarget.h:31
N
#define N
llvm::VETargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
Custom Inserter {.
Definition: VEISelLowering.cpp:2457
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
RegName
#define RegName(no)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::VETargetLowering
Definition: VEISelLowering.h:50
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::VETargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Custom Lower {.
Definition: VEISelLowering.cpp:1671
llvm::VETargetLowering::isCtlzFast
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
Definition: VEISelLowering.h:214
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
llvm::VETargetLowering::lowerToVVP
SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const
} Custom Inserter
Definition: VEISelLowering.cpp:2684
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::VETargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: VEISelLowering.h:212
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::VETargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
} VVPLowering
Definition: VEISelLowering.cpp:2582
llvm::VETargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: VEISelLowering.cpp:509
llvm::LLT
Definition: LowLevelTypeImpl.h:40