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14 #ifndef LLVM_LIB_TARGET_VE_VEISELLOWERING_H
15 #define LLVM_LIB_TARGET_VE_VEISELLOWERING_H
58 #define ADD_VVP_OP(VVP_NAME, ...) VVP_NAME,
59 #include "VVPNodes.def"
68 void initRegisterClasses();
69 void initSPUActions();
70 void initVPUActions();
85 EVT VT)
const override;
213 bool ForCodeSize)
const override;
218 bool *Fast)
const override;
223 std::pair<unsigned, const TargetRegisterClass *>
249 #endif // LLVM_LIB_TARGET_VE_VEISELLOWERING_H
SDValue legalizeInternalVectorOp(SDValue Op, SelectionDAG &DAG) const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
This is an optimization pass for GlobalISel generic memory operations.
Register prepareSymbol(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, StringRef Symbol, const DebugLoc &DL, bool IsLocal, bool IsCall) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
SDValue lowerVVP_LOAD_STORE(SDValue Op, VECustomDAG &) const
SDValue splitVectorOp(SDValue Op, VECustomDAG &CDAG) const
Context object for machine code objects.
SDValue legalizePackedAVL(SDValue Op, VECustomDAG &CDAG) const
SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Represents one node in the SelectionDAG.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
ConstraintType getConstraintType(StringRef Constraint) const override
Inline Assembly {.
SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Function Alias Analysis Results
SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
} Custom DAGCombine
unsigned const TargetRegisterInfo * TRI
Register prepareMBB(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TargetBB, const DebugLoc &DL) const
VETargetLowering(const TargetMachine &TM, const VESubtarget &STI)
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const
SDValue splitMaskArithmetic(SDValue Op, SelectionDAG &DAG) const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
MachineBasicBlock * emitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *BB) const
SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const
This struct is a compact representation of a valid (non-zero power of two) alignment.
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned Uid, MCContext &Ctx) const override
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
bool hasStandaloneRem(EVT) const override
Return true if the target can handle a standalone remainder operation.
AtomicOrdering
Atomic ordering for LLVM's memory model.
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
unsigned getMinimumJumpTableEntries() const override
} Inline Assembly
Representation of each machine instruction.
This is an important class for using LLVM in a threaded context.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Flags
Flags values. These may be or'd together.
This structure contains all information that is necessary for lowering calls.
bool isIntDivCheap(EVT, AttributeList) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
Primary interface to the complete machine description for the target machine.
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const
TargetLoweringBase::LegalizeAction getCustomOperationAction(SDNode &) const override
Custom Lower {.
StringRef - Represent a constant reference to a string, i.e.
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Helper functions for atomic operations.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
Common base class shared among various IRBuilders.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
an instruction that atomically reads a memory location, combines it with another value,...
Wrapper class representing virtual and physical registers.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void setupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI, int Offset) const
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Custom Lower {.
SDValue legalizeInternalLoadStoreOp(SDValue Op, VECustomDAG &CDAG) const
SDValue lowerVVP_GATHER_SCATTER(SDValue Op, VECustomDAG &) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A, MachineMemOperand::Flags Flags, bool *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
unsigned getJumpTableEncoding() const override
JumpTable for VE.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
} Custom Lower
SDValue splitPackedLoadStore(SDValue Op, VECustomDAG &CDAG) const
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
Custom Inserter {.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
const char LLVMTargetMachineRef TM
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const
} Custom Inserter
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Base class for the full range of assembler expressions which are needed for parsing.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
} VVPLowering
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.