LLVM 20.0.0git
VEISelLowering.h
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1//===-- VEISelLowering.h - VE DAG Lowering Interface ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that VE uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_VE_VEISELLOWERING_H
15#define LLVM_LIB_TARGET_VE_VEISELLOWERING_H
16
17#include "VE.h"
19
20namespace llvm {
21class VESubtarget;
22
23namespace VEISD {
24enum NodeType : unsigned {
26
27 CMPI, // Compare between two signed integer values.
28 CMPU, // Compare between two unsigned integer values.
29 CMPF, // Compare between two floating-point values.
30 CMPQ, // Compare between two quad floating-point values.
31 CMOV, // Select between two values using the result of comparison.
32
33 CALL, // A call instruction.
34 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
35 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
36 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
37 GETFUNPLT, // Load function address through %plt insturction.
38 GETTLSADDR, // Load address for TLS access.
39 GETSTACKTOP, // Retrieve address of stack top (first address of
40 // locals and temporaries).
41 GLOBAL_BASE_REG, // Global base reg for PIC.
42 Hi, // Hi/Lo operations, typically on a global address.
43 Lo, // Hi/Lo operations, typically on a global address.
44 RET_GLUE, // Return with a flag operand.
45 TS1AM, // A TS1AM instruction used for 1/2 bytes swap.
46 VEC_UNPACK_LO, // unpack the lo v256 slice of a packed v512 vector.
47 VEC_UNPACK_HI, // unpack the hi v256 slice of a packed v512 vector.
48 // 0: v512 vector, 1: AVL
49 VEC_PACK, // pack a lo and a hi vector into one v512 vector
50 // 0: v256 lo vector, 1: v256 hi vector, 2: AVL
51
52 VEC_BROADCAST, // A vector broadcast instruction.
53 // 0: scalar value, 1: VL
55 REPL_F32, // Replicate subregister to other half.
56
57 // Annotation as a wrapper. LEGALAVL(VL) means that VL refers to 64bit of
58 // data, whereas the raw EVL coming in from VP nodes always refers to number
59 // of elements, regardless of their size.
61
62// VVP_* nodes.
63#define ADD_VVP_OP(VVP_NAME, ...) VVP_NAME,
64#include "VVPNodes.def"
65};
66}
67
68/// Convert a DAG integer condition code to a VE ICC condition.
70 switch (CC) {
71 default:
72 llvm_unreachable("Unknown integer condition code!");
73 case ISD::SETEQ:
74 return VECC::CC_IEQ;
75 case ISD::SETNE:
76 return VECC::CC_INE;
77 case ISD::SETLT:
78 return VECC::CC_IL;
79 case ISD::SETGT:
80 return VECC::CC_IG;
81 case ISD::SETLE:
82 return VECC::CC_ILE;
83 case ISD::SETGE:
84 return VECC::CC_IGE;
85 case ISD::SETULT:
86 return VECC::CC_IL;
87 case ISD::SETULE:
88 return VECC::CC_ILE;
89 case ISD::SETUGT:
90 return VECC::CC_IG;
91 case ISD::SETUGE:
92 return VECC::CC_IGE;
93 }
94}
95
96/// Convert a DAG floating point condition code to a VE FCC condition.
98 switch (CC) {
99 default:
100 llvm_unreachable("Unknown fp condition code!");
101 case ISD::SETFALSE:
102 return VECC::CC_AF;
103 case ISD::SETEQ:
104 case ISD::SETOEQ:
105 return VECC::CC_EQ;
106 case ISD::SETNE:
107 case ISD::SETONE:
108 return VECC::CC_NE;
109 case ISD::SETLT:
110 case ISD::SETOLT:
111 return VECC::CC_L;
112 case ISD::SETGT:
113 case ISD::SETOGT:
114 return VECC::CC_G;
115 case ISD::SETLE:
116 case ISD::SETOLE:
117 return VECC::CC_LE;
118 case ISD::SETGE:
119 case ISD::SETOGE:
120 return VECC::CC_GE;
121 case ISD::SETO:
122 return VECC::CC_NUM;
123 case ISD::SETUO:
124 return VECC::CC_NAN;
125 case ISD::SETUEQ:
126 return VECC::CC_EQNAN;
127 case ISD::SETUNE:
128 return VECC::CC_NENAN;
129 case ISD::SETULT:
130 return VECC::CC_LNAN;
131 case ISD::SETUGT:
132 return VECC::CC_GNAN;
133 case ISD::SETULE:
134 return VECC::CC_LENAN;
135 case ISD::SETUGE:
136 return VECC::CC_GENAN;
137 case ISD::SETTRUE:
138 return VECC::CC_AT;
139 }
140}
141
142/// getImmVal - get immediate representation of integer value
143inline static uint64_t getImmVal(const ConstantSDNode *N) {
144 return N->getSExtValue();
145}
146
147/// getFpImmVal - get immediate representation of floating point value
148inline static uint64_t getFpImmVal(const ConstantFPSDNode *N) {
149 const APInt &Imm = N->getValueAPF().bitcastToAPInt();
150 uint64_t Val = Imm.getZExtValue();
151 if (Imm.getBitWidth() == 32) {
152 // Immediate value of float place places at higher bits on VE.
153 Val <<= 32;
154 }
155 return Val;
156}
157
158class VECustomDAG;
159
161 const VESubtarget *Subtarget;
162
163 void initRegisterClasses();
164 void initSPUActions();
165 void initVPUActions();
166
167public:
168 VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);
169
170 const char *getTargetNodeName(unsigned Opcode) const override;
171 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
172 return MVT::i32;
173 }
174
175 Register getRegisterByName(const char *RegName, LLT VT,
176 const MachineFunction &MF) const override;
177
178 /// getSetCCResultType - Return the ISD::SETCC ValueType
180 EVT VT) const override;
181
183 bool isVarArg,
185 const SDLoc &dl, SelectionDAG &DAG,
186 SmallVectorImpl<SDValue> &InVals) const override;
187
189 SmallVectorImpl<SDValue> &InVals) const override;
190
192 bool isVarArg,
193 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
194 LLVMContext &Context) const override;
195 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
197 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
198 SelectionDAG &DAG) const override;
199
200 /// Helper functions for atomic operations.
201 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
202 // VE uses release consistency, so need fence for each atomics.
203 return true;
204 }
206 AtomicOrdering Ord) const override;
208 AtomicOrdering Ord) const override;
210 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
212 return ISD::ANY_EXTEND;
213 }
214
215 /// Custom Lower {
217 getCustomOperationAction(SDNode &) const override;
218
219 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
220 unsigned getJumpTableEncoding() const override;
222 const MachineBasicBlock *MBB,
223 unsigned Uid,
224 MCContext &Ctx) const override;
226 SelectionDAG &DAG) const override;
227 // VE doesn't need getPICJumpTableRelocBaseExpr since it is used for only
228 // EK_LabelDifference32.
229
247
251 /// } Custom Lower
252
253 /// Replace the results of node with an illegal result
254 /// type with new values built out of custom code.
255 ///
257 SelectionDAG &DAG) const override;
258
259 /// Custom Inserter {
262 MachineBasicBlock *MBB) const override;
264 MachineBasicBlock *MBB) const;
266 MachineBasicBlock *MBB) const;
268 MachineBasicBlock *BB) const;
269
271 MachineBasicBlock *DispatchBB, int FI,
272 int Offset) const;
273 // Setup basic block address.
275 MachineBasicBlock *TargetBB, const DebugLoc &DL) const;
276 // Prepare function/variable address.
278 StringRef Symbol, const DebugLoc &DL, bool IsLocal,
279 bool IsCall) const;
280 /// } Custom Inserter
281
282 /// VVP Lowering {
286
293 /// } VVPLowering
294
295 /// Custom DAGCombine {
296 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
297
298 SDValue combineSelect(SDNode *N, DAGCombinerInfo &DCI) const;
299 SDValue combineSelectCC(SDNode *N, DAGCombinerInfo &DCI) const;
300 SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
301 /// } Custom DAGCombine
302
303 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
304 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
305 SelectionDAG &DAG) const;
307
308 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
309 bool isFPImmLegal(const APFloat &Imm, EVT VT,
310 bool ForCodeSize) const override;
311 /// Returns true if the target allows unaligned memory accesses of the
312 /// specified type.
313 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A,
315 unsigned *Fast) const override;
316
317 /// Inline Assembly {
318
319 ConstraintType getConstraintType(StringRef Constraint) const override;
320 std::pair<unsigned, const TargetRegisterClass *>
322 StringRef Constraint, MVT VT) const override;
323
324 /// } Inline Assembly
325
326 /// Target Optimization {
327
328 // Return lower limit for number of blocks in a jump table.
329 unsigned getMinimumJumpTableEntries() const override;
330
331 // SX-Aurora VE's s/udiv is 5-9 times slower than multiply.
332 bool isIntDivCheap(EVT, AttributeList) const override { return false; }
333 // VE doesn't have rem.
334 bool hasStandaloneRem(EVT) const override { return false; }
335 // VE LDZ instruction returns 64 if the input is zero.
336 bool isCheapToSpeculateCtlz(Type *) const override { return true; }
337 // VE LDZ instruction is fast.
338 bool isCtlzFast() const override { return true; }
339 // VE has NND instruction.
340 bool hasAndNot(SDValue Y) const override;
341
342 /// } Target Optimization
343};
344} // namespace llvm
345
346#endif // LLVM_LIB_TARGET_VE_VEISELLOWERING_H
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
IRTranslator LLVM IR MI
#define RegName(no)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
Definition: APInt.h:78
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:696
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:63
A debug info location.
Definition: DebugLoc.h:33
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:91
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Context object for machine code objects.
Definition: MCContext.h:83
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:69
Flags
Flags values. These may be or'd together.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:226
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
SDValue splitMaskArithmetic(SDValue Op, SelectionDAG &DAG) const
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SDValue lowerVVP_GATHER_SCATTER(SDValue Op, VECustomDAG &) const
bool isCheapToSpeculateCtlz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const
} Custom Inserter
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
SDValue lowerVVP_LOAD_STORE(SDValue Op, VECustomDAG &) const
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Helper functions for atomic operations.
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const
SDValue combineSelect(SDNode *N, DAGCombinerInfo &DCI) const
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Custom Lower {.
SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
SDValue legalizePackedAVL(SDValue Op, VECustomDAG &CDAG) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
} VVPLowering
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
SDValue combineSelectCC(SDNode *N, DAGCombinerInfo &DCI) const
SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const
unsigned getMinimumJumpTableEntries() const override
} Inline Assembly
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
MachineBasicBlock * emitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Register prepareMBB(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TargetBB, const DebugLoc &DL) const
void setupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI, int Offset) const
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
Custom Inserter {.
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const
bool hasStandaloneRem(EVT) const override
Return true if the target can handle a standalone remainder operation.
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
TargetLoweringBase::LegalizeAction getCustomOperationAction(SDNode &) const override
Custom Lower {.
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
SDValue splitPackedLoadStore(SDValue Op, VECustomDAG &CDAG) const
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
SDValue legalizeInternalVectorOp(SDValue Op, SelectionDAG &DAG) const
Register prepareSymbol(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, StringRef Symbol, const DebugLoc &DL, bool IsLocal, bool IsCall) const
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
} Custom Lower
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
SDValue splitVectorOp(SDValue Op, VECustomDAG &CDAG) const
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
} Custom DAGCombine
SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
SDValue legalizeInternalLoadStoreOp(SDValue Op, VECustomDAG &CDAG) const
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned Uid, MCContext &Ctx) const override
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const
unsigned getJumpTableEncoding() const override
JumpTable for VE.
SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const
bool isIntDivCheap(EVT, AttributeList) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
ConstraintType getConstraintType(StringRef Constraint) const override
Inline Assembly {.
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:813
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1480
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1603
CondCode
Definition: VE.h:42
@ CC_GENAN
Definition: VE.h:65
@ CC_EQNAN
Definition: VE.h:64
@ CC_G
Definition: VE.h:53
@ CC_NENAN
Definition: VE.h:63
@ CC_LE
Definition: VE.h:58
@ CC_LENAN
Definition: VE.h:66
@ CC_ILE
Definition: VE.h:49
@ CC_NUM
Definition: VE.h:59
@ CC_EQ
Definition: VE.h:56
@ CC_GNAN
Definition: VE.h:61
@ CC_IG
Definition: VE.h:44
@ CC_INE
Definition: VE.h:46
@ CC_AF
Definition: VE.h:52
@ CC_L
Definition: VE.h:54
@ CC_GE
Definition: VE.h:57
@ CC_NE
Definition: VE.h:55
@ CC_LNAN
Definition: VE.h:62
@ CC_IEQ
Definition: VE.h:47
@ CC_AT
Definition: VE.h:67
@ CC_NAN
Definition: VE.h:60
@ CC_IGE
Definition: VE.h:48
@ CC_IL
Definition: VE.h:45
@ EH_SJLJ_SETUP_DISPATCH
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static uint64_t getFpImmVal(const ConstantFPSDNode *N)
getFpImmVal - get immediate representation of floating point value
@ Offset
Definition: DWP.cpp:480
static uint64_t getImmVal(const ConstantSDNode *N)
getImmVal - get immediate representation of integer value
static VECC::CondCode fpCondCode2Fcc(ISD::CondCode CC)
Convert a DAG floating point condition code to a VE FCC condition.
AtomicOrdering
Atomic ordering for LLVM's memory model.
static VECC::CondCode intCondCode2Icc(ISD::CondCode CC)
Convert a DAG integer condition code to a VE ICC condition.
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:35
This structure contains all information that is necessary for lowering calls.