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14 #ifndef LLVM_LIB_TARGET_VE_VE_H
15 #define LLVM_LIB_TARGET_VE_VE_H
30 class VETargetMachine;
378 return static_cast<unsigned>(R);
407 return N->getSExtValue();
412 const APInt &
Imm =
N->getValueAPF().bitcastToAPInt();
414 if (
Imm.getBitWidth() == 32) {
453 if (Val & (UINT64_C(1) << 63))
462 if ((Val & 0x40) == 0)
463 return (
uint64_t)((INT64_C(1) << 63) >> (Val & 0x3f));
464 return ((
uint64_t)INT64_C(-1) >> (Val & 0x3f));
467 inline unsigned M0(
unsigned Val) {
return Val + 64; }
468 inline unsigned M1(
unsigned Val) {
return Val; }
StringSwitch & Case(StringLiteral S, T Value)
This is an optimization pass for GlobalISel generic memory operations.
static uint64_t getImmVal(const ConstantSDNode *N)
getImmVal - get immediate representation of integer value
static VECC::CondCode intCondCode2Icc(ISD::CondCode CC)
Convert a DAG integer condition code to a VE ICC condition.
static bool isIntVECondCode(VECC::CondCode CC)
static uint64_t val2MImm(uint64_t Val)
val2MImm - Convert an integer immediate value to target MImm immediate.
constexpr bool isShiftedMask_32(uint32_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (32 bit ver...
static bool isMImmVal(uint64_t Val)
void initializeVEDAGToDAGISelPass(PassRegistry &)
static unsigned VECondCodeToVal(VECC::CondCode CC)
static uint64_t getFpImmVal(const ConstantFPSDNode *N)
getFpImmVal - get immediate representation of floating point value
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
static bool isMImm32Val(uint32_t Val)
unsigned M0(unsigned Val)
static const unsigned StandardVectorWidth
static uint64_t mimm2Val(uint64_t Val)
mimm2Val - Convert a target MImm immediate to an integer immediate value.
FunctionPass * createLVLGenPass()
static const unsigned PackedVectorWidth
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
constexpr bool isMask_32(uint32_t Value)
Return true if the argument is a non-empty sequence of ones starting at the least significant bit wit...
static VECC::CondCode VEValToCondCode(unsigned Val, bool IsInteger)
Class for arbitrary precision integers.
static VECC::CondCode fpCondCode2Fcc(ISD::CondCode CC)
Convert a DAG floating point condition code to a VE FCC condition.
static unsigned VERDToVal(VERD::RoundingMode R)
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static VECC::CondCode stringToVEICondCode(StringRef S)
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
FunctionPass * createVEISelDag(VETargetMachine &TM)
createVEISelDag - This pass converts a legalized DAG into a VE-specific DAG, ready for instruction sc...
static VERD::RoundingMode stringToVERD(StringRef S)
unsigned countLeadingOnes(T Value)
Count the number of ones from the most significant bit to the first zero bit.
static VERD::RoundingMode VEValToRD(unsigned Val)
static const char * VECondCodeToString(VECC::CondCode CC)
unsigned countLeadingZeros(T Val)
Count number of 0's from the most significant bit to the least stopping at the first 1.
A switch()-like statement whose cases are string literals.
const char LLVMTargetMachineRef TM
void LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP)
static VECC::CondCode stringToVEFCondCode(StringRef S)
constexpr bool isMask_64(uint64_t Value)
Return true if the argument is a non-empty sequence of ones starting at the least significant bit wit...
unsigned M1(unsigned Val)
static const char * VERDToString(VERD::RoundingMode R)