23#define DEBUG_TYPE "ve-isel"
24#define PASS_NAME "VE DAG->DAG Pattern Instruction Selection"
39 VEDAGToDAGISel() =
delete;
62 std::vector<SDValue> &OutOps)
override;
65#include "VEGenDAGISel.inc"
68 SDNode *getGlobalBaseReg();
75char VEDAGToDAGISel::ID = 0;
89 if (matchADDRri(
Addr, LHS, RHS)) {
97 if (matchADDRrr(
Addr, LHS, RHS)) {
103 if (isa<FrameIndexSDNode>(RHS))
143 if (isa<FrameIndexSDNode>(
Addr))
150 if (
auto *CN = dyn_cast<ConstantSDNode>(
Addr)) {
151 if (isInt<32>(CN->getSExtValue())) {
155 CurDAG->getTargetConstant(CN->getZExtValue(),
SDLoc(
Addr), MVT::i32);
174 if (isa<FrameIndexSDNode>(
Addr))
181 if (
auto *CN = dyn_cast<ConstantSDNode>(
Addr)) {
182 if (isInt<32>(CN->getSExtValue())) {
185 CurDAG->getTargetConstant(CN->getZExtValue(),
SDLoc(
Addr), MVT::i32);
193 if (isa<FrameIndexSDNode>(
Addr))
205 if (!CurDAG->haveNoCommonBitsSet(
Addr.getOperand(0),
Addr.getOperand(1)))
221 auto AddrTy =
Addr->getValueType(0);
223 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), AddrTy);
232 if (CurDAG->isBaseWithConstantOffset(
Addr)) {
236 dyn_cast<FrameIndexSDNode>(
Addr.getOperand(0))) {
238 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), AddrTy);
250void VEDAGToDAGISel::Select(
SDNode *
N) {
252 if (
N->isMachineOpcode()) {
257 switch (
N->getOpcode()) {
261 ReplaceNode(
N,
N->getOperand(0).getNode());
266 MVT SplatResTy =
N->getSimpleValueType(0);
271 auto BConst = dyn_cast<ConstantSDNode>(
N->getOperand(0));
274 bool BCTrueMask = (BConst->getSExtValue() != 0);
281 New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
SDLoc(
N), VE::VM0,
284 New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
SDLoc(
N), VE::VMP0,
290 ReplaceNode(
N,
New.getNode());
295 ReplaceNode(
N, getGlobalBaseReg());
304bool VEDAGToDAGISel::SelectInlineAsmMemoryOperand(
306 std::vector<SDValue> &OutOps) {
308 switch (ConstraintID) {
311 case InlineAsm::ConstraintCode::o:
312 case InlineAsm::ConstraintCode::m:
315 if (selectADDRri(
Op, Op0, Op1)) {
316 OutOps.push_back(Op0);
317 OutOps.push_back(Op1);
321 OutOps.push_back(
Op);
322 OutOps.push_back(CurDAG->getTargetConstant(0,
SDLoc(
Op), MVT::i32));
328SDNode *VEDAGToDAGISel::getGlobalBaseReg() {
331 ->getRegister(GlobalBaseReg, TLI->getPointerTy(CurDAG->getDataLayout()))
339 return new VEDAGToDAGISel(
TM);
amdgpu AMDGPU Register Bank Select
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
uint64_t getZExtValue() const
int64_t getSExtValue() const
This class represents an Operation in the Expression.
FunctionPass class - This class is used to implement most global optimizations.
unsigned getVectorNumElements() const
MVT getVectorElementType() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps)
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ ADD
Simple integer binary arithmetic operators.
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
@ GlobalBaseReg
The result of the mflr at function entry, used for PIC code.
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createVEISelDag(VETargetMachine &TM)
createVEISelDag - This pass converts a legalized DAG into a VE-specific DAG, ready for instruction sc...
static const unsigned StandardVectorWidth
static const unsigned PackedVectorWidth
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.