LLVM 19.0.0git
TargetTransformInfoImpl.h
Go to the documentation of this file.
1//===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file provides helpers for the implementation of
10/// a TargetTransformInfo-conforming class.
11///
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
15#define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
16
20#include "llvm/IR/DataLayout.h"
23#include "llvm/IR/Operator.h"
25#include <optional>
26#include <utility>
27
28namespace llvm {
29
30class Function;
31
32/// Base class for use as a mix-in that aids implementing
33/// a TargetTransformInfo-compatible class.
35
36protected:
38
39 const DataLayout &DL;
40
42
43public:
44 // Provide value semantics. MSVC requires that we spell all of these out.
47
48 const DataLayout &getDataLayout() const { return DL; }
49
50 InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr,
53 // In the basic model, we just assume that all-constant GEPs will be folded
54 // into their uses via addressing modes.
55 for (const Value *Operand : Operands)
56 if (!isa<Constant>(Operand))
57 return TTI::TCC_Basic;
58
59 return TTI::TCC_Free;
60 }
61
63 unsigned &JTSize,
65 BlockFrequencyInfo *BFI) const {
66 (void)PSI;
67 (void)BFI;
68 JTSize = 0;
69 return SI.getNumCases();
70 }
71
72 unsigned getInliningThresholdMultiplier() const { return 1; }
75 return 8;
76 }
77 unsigned adjustInliningThreshold(const CallBase *CB) const { return 0; }
78 unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const {
79 return 0;
80 };
81
82 int getInlinerVectorBonusPercent() const { return 150; }
83
85 return TTI::TCC_Expensive;
86 }
87
89 return 64;
90 }
91
92 // Although this default value is arbitrary, it is not random. It is assumed
93 // that a condition that evaluates the same way by a higher percentage than
94 // this is best represented as control flow. Therefore, the default value N
95 // should be set such that the win from N% correct executions is greater than
96 // the loss from (100 - N)% mispredicted executions for the majority of
97 // intended targets.
99 return BranchProbability(99, 100);
100 }
101
102 bool hasBranchDivergence(const Function *F = nullptr) const { return false; }
103
104 bool isSourceOfDivergence(const Value *V) const { return false; }
105
106 bool isAlwaysUniform(const Value *V) const { return false; }
107
108 bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const {
109 return false;
110 }
111
112 bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const {
113 return true;
114 }
115
116 unsigned getFlatAddressSpace() const { return -1; }
117
119 Intrinsic::ID IID) const {
120 return false;
121 }
122
123 bool isNoopAddrSpaceCast(unsigned, unsigned) const { return false; }
125 return AS == 0;
126 };
127
128 unsigned getAssumedAddrSpace(const Value *V) const { return -1; }
129
130 bool isSingleThreaded() const { return false; }
131
132 std::pair<const Value *, unsigned>
134 return std::make_pair(nullptr, -1);
135 }
136
138 Value *NewV) const {
139 return nullptr;
140 }
141
142 bool isLoweredToCall(const Function *F) const {
143 assert(F && "A concrete function must be provided to this routine.");
144
145 // FIXME: These should almost certainly not be handled here, and instead
146 // handled with the help of TLI or the target itself. This was largely
147 // ported from existing analysis heuristics here so that such refactorings
148 // can take place in the future.
149
150 if (F->isIntrinsic())
151 return false;
152
153 if (F->hasLocalLinkage() || !F->hasName())
154 return true;
155
156 StringRef Name = F->getName();
157
158 // These will all likely lower to a single selection DAG node.
159 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl" ||
160 Name == "fabs" || Name == "fabsf" || Name == "fabsl" || Name == "sin" ||
161 Name == "fmin" || Name == "fminf" || Name == "fminl" ||
162 Name == "fmax" || Name == "fmaxf" || Name == "fmaxl" ||
163 Name == "sinf" || Name == "sinl" || Name == "cos" || Name == "cosf" ||
164 Name == "cosl" || Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl")
165 return false;
166
167 // These are all likely to be optimized into something smaller.
168 if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" ||
169 Name == "exp2l" || Name == "exp2f" || Name == "floor" ||
170 Name == "floorf" || Name == "ceil" || Name == "round" ||
171 Name == "ffs" || Name == "ffsl" || Name == "abs" || Name == "labs" ||
172 Name == "llabs")
173 return false;
174
175 return true;
176 }
177
180 HardwareLoopInfo &HWLoopInfo) const {
181 return false;
182 }
183
184 bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const { return false; }
185
187 getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const {
189 }
190
191 std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
192 IntrinsicInst &II) const {
193 return std::nullopt;
194 }
195
196 std::optional<Value *>
198 APInt DemandedMask, KnownBits &Known,
199 bool &KnownBitsComputed) const {
200 return std::nullopt;
201 }
202
204 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
205 APInt &UndefElts2, APInt &UndefElts3,
206 std::function<void(Instruction *, unsigned, APInt, APInt &)>
207 SimplifyAndSetOp) const {
208 return std::nullopt;
209 }
210
213 OptimizationRemarkEmitter *) const {}
214
216 TTI::PeelingPreferences &) const {}
217
218 bool isLegalAddImmediate(int64_t Imm) const { return false; }
219
220 bool isLegalAddScalableImmediate(int64_t Imm) const { return false; }
221
222 bool isLegalICmpImmediate(int64_t Imm) const { return false; }
223
224 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
225 bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
226 Instruction *I = nullptr,
227 int64_t ScalableOffset = 0) const {
228 // Guess that only reg and reg+reg addressing is allowed. This heuristic is
229 // taken from the implementation of LSR.
230 return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
231 }
232
233 bool isLSRCostLess(const TTI::LSRCost &C1, const TTI::LSRCost &C2) const {
234 return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
235 C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
236 std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
237 C2.ScaleCost, C2.ImmCost, C2.SetupCost);
238 }
239
240 bool isNumRegsMajorCostOfLSR() const { return true; }
241
242 bool shouldFoldTerminatingConditionAfterLSR() const { return false; }
243
244 bool shouldDropLSRSolutionIfLessProfitable() const { return false; }
245
246 bool isProfitableLSRChainElement(Instruction *I) const { return false; }
247
248 bool canMacroFuseCmp() const { return false; }
249
252 TargetLibraryInfo *LibInfo) const {
253 return false;
254 }
255
258 return TTI::AMK_None;
259 }
260
261 bool isLegalMaskedStore(Type *DataType, Align Alignment) const {
262 return false;
263 }
264
265 bool isLegalMaskedLoad(Type *DataType, Align Alignment) const {
266 return false;
267 }
269 bool isLegalNTStore(Type *DataType, Align Alignment) const {
270 // By default, assume nontemporal memory stores are available for stores
271 // that are aligned and have a size that is a power of 2.
272 unsigned DataSize = DL.getTypeStoreSize(DataType);
273 return Alignment >= DataSize && isPowerOf2_32(DataSize);
274 }
275
276 bool isLegalNTLoad(Type *DataType, Align Alignment) const {
277 // By default, assume nontemporal memory loads are available for loads that
278 // are aligned and have a size that is a power of 2.
279 unsigned DataSize = DL.getTypeStoreSize(DataType);
280 return Alignment >= DataSize && isPowerOf2_32(DataSize);
281 }
282
283 bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const {
284 return false;
285 }
286
287 bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
288 return false;
289 }
290
291 bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
292 return false;
293 }
294
295 bool forceScalarizeMaskedGather(VectorType *DataType, Align Alignment) const {
296 return false;
297 }
298
300 Align Alignment) const {
301 return false;
302 }
303
304 bool isLegalMaskedCompressStore(Type *DataType, Align Alignment) const {
305 return false;
306 }
307
308 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
309 const SmallBitVector &OpcodeMask) const {
310 return false;
311 }
312
313 bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const {
314 return false;
315 }
316
317 bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const {
318 return false;
319 }
320
321 bool isLegalMaskedVectorHistogram(Type *AddrType, Type *DataType) const {
322 return false;
323 }
324
325 bool enableOrderedReductions() const { return false; }
326
327 bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; }
328
329 bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const {
330 return false;
331 }
332
333 bool prefersVectorizedAddressing() const { return true; }
334
336 StackOffset BaseOffset, bool HasBaseReg,
337 int64_t Scale,
338 unsigned AddrSpace) const {
339 // Guess that all legal addressing mode are free.
340 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset.getFixed(), HasBaseReg,
341 Scale, AddrSpace, /*I=*/nullptr,
342 BaseOffset.getScalable()))
343 return 0;
344 return -1;
345 }
346
347 bool LSRWithInstrQueries() const { return false; }
348
349 bool isTruncateFree(Type *Ty1, Type *Ty2) const { return false; }
350
351 bool isProfitableToHoist(Instruction *I) const { return true; }
352
353 bool useAA() const { return false; }
354
355 bool isTypeLegal(Type *Ty) const { return false; }
356
357 unsigned getRegUsageForType(Type *Ty) const { return 1; }
358
359 bool shouldBuildLookupTables() const { return true; }
360
361 bool shouldBuildLookupTablesForConstant(Constant *C) const { return true; }
362
363 bool shouldBuildRelLookupTables() const { return false; }
364
365 bool useColdCCForColdCall(Function &F) const { return false; }
366
368 const APInt &DemandedElts,
369 bool Insert, bool Extract,
371 return 0;
372 }
373
378 return 0;
379 }
380
381 bool supportsEfficientVectorElementLoadStore() const { return false; }
382
383 bool supportsTailCalls() const { return true; }
384
385 bool enableAggressiveInterleaving(bool LoopHasReductions) const {
386 return false;
387 }
388
390 bool IsZeroCmp) const {
391 return {};
392 }
393
394 bool enableSelectOptimize() const { return true; }
395
397 // If the select is a logical-and/logical-or then it is better treated as a
398 // and/or by the backend.
399 using namespace llvm::PatternMatch;
400 return isa<SelectInst>(I) &&
403 }
404
405 bool enableInterleavedAccessVectorization() const { return false; }
406
407 bool enableMaskedInterleavedAccessVectorization() const { return false; }
408
409 bool isFPVectorizationPotentiallyUnsafe() const { return false; }
410
412 unsigned AddressSpace, Align Alignment,
413 unsigned *Fast) const {
414 return false;
415 }
416
417 TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const {
418 return TTI::PSK_Software;
419 }
420
421 bool haveFastSqrt(Type *Ty) const { return false; }
422
423 bool isExpensiveToSpeculativelyExecute(const Instruction *I) { return true; }
424
425 bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; }
426
429 }
430
431 InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
432 const APInt &Imm, Type *Ty) const {
433 return 0;
434 }
435
438 return TTI::TCC_Basic;
439 }
440
441 InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
442 const APInt &Imm, Type *Ty,
444 Instruction *Inst = nullptr) const {
445 return TTI::TCC_Free;
446 }
447
449 const APInt &Imm, Type *Ty,
451 return TTI::TCC_Free;
452 }
453
455 const Function &Fn) const {
456 return false;
457 }
458
459 unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; }
460
461 unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
462 return Vector ? 1 : 0;
463 };
464
465 const char *getRegisterClassName(unsigned ClassID) const {
466 switch (ClassID) {
467 default:
468 return "Generic::Unknown Register Class";
469 case 0:
470 return "Generic::ScalarRC";
471 case 1:
472 return "Generic::VectorRC";
473 }
474 }
475
477 return TypeSize::getFixed(32);
478 }
479
480 unsigned getMinVectorRegisterBitWidth() const { return 128; }
481
482 std::optional<unsigned> getMaxVScale() const { return std::nullopt; }
483 std::optional<unsigned> getVScaleForTuning() const { return std::nullopt; }
484 bool isVScaleKnownToBeAPowerOfTwo() const { return false; }
485
486 bool
488 return false;
489 }
490
491 ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const {
492 return ElementCount::get(0, IsScalable);
493 }
494
495 unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const { return 0; }
496 unsigned getStoreMinimumVF(unsigned VF, Type *, Type *) const { return VF; }
497
499 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
500 AllowPromotionWithoutCommonHeader = false;
501 return false;
502 }
503
504 unsigned getCacheLineSize() const { return 0; }
505 std::optional<unsigned>
507 switch (Level) {
509 [[fallthrough]];
511 return std::nullopt;
512 }
513 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
514 }
515
516 std::optional<unsigned>
518 switch (Level) {
520 [[fallthrough]];
522 return std::nullopt;
523 }
524
525 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
526 }
527
528 std::optional<unsigned> getMinPageSize() const { return {}; }
529
530 unsigned getPrefetchDistance() const { return 0; }
531 unsigned getMinPrefetchStride(unsigned NumMemAccesses,
532 unsigned NumStridedMemAccesses,
533 unsigned NumPrefetches, bool HasCall) const {
534 return 1;
535 }
536 unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; }
537 bool enableWritePrefetching() const { return false; }
538 bool shouldPrefetchAddressSpace(unsigned AS) const { return !AS; }
539
540 unsigned getMaxInterleaveFactor(ElementCount VF) const { return 1; }
541
543 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
546 const Instruction *CxtI = nullptr) const {
547 // Widenable conditions will eventually lower into constants, so some
548 // operations with them will be trivially optimized away.
549 auto IsWidenableCondition = [](const Value *V) {
550 if (auto *II = dyn_cast<IntrinsicInst>(V))
551 if (II->getIntrinsicID() == Intrinsic::experimental_widenable_condition)
552 return true;
553 return false;
554 };
555 // FIXME: A number of transformation tests seem to require these values
556 // which seems a little odd for how arbitary there are.
557 switch (Opcode) {
558 default:
559 break;
560 case Instruction::FDiv:
561 case Instruction::FRem:
562 case Instruction::SDiv:
563 case Instruction::SRem:
564 case Instruction::UDiv:
565 case Instruction::URem:
566 // FIXME: Unlikely to be true for CodeSize.
567 return TTI::TCC_Expensive;
568 case Instruction::And:
569 case Instruction::Or:
570 if (any_of(Args, IsWidenableCondition))
571 return TTI::TCC_Free;
572 break;
573 }
574
575 // Assume a 3cy latency for fp arithmetic ops.
577 if (Ty->getScalarType()->isFloatingPointTy())
578 return 3;
579
580 return 1;
581 }
582
584 unsigned Opcode1,
585 const SmallBitVector &OpcodeMask,
588 }
589
591 ArrayRef<int> Mask,
593 VectorType *SubTp,
594 ArrayRef<const Value *> Args = std::nullopt,
595 const Instruction *CxtI = nullptr) const {
596 return 1;
597 }
598
599 InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
602 const Instruction *I) const {
603 switch (Opcode) {
604 default:
605 break;
606 case Instruction::IntToPtr: {
607 unsigned SrcSize = Src->getScalarSizeInBits();
608 if (DL.isLegalInteger(SrcSize) &&
609 SrcSize <= DL.getPointerTypeSizeInBits(Dst))
610 return 0;
611 break;
612 }
613 case Instruction::PtrToInt: {
614 unsigned DstSize = Dst->getScalarSizeInBits();
615 if (DL.isLegalInteger(DstSize) &&
616 DstSize >= DL.getPointerTypeSizeInBits(Src))
617 return 0;
618 break;
619 }
620 case Instruction::BitCast:
621 if (Dst == Src || (Dst->isPointerTy() && Src->isPointerTy()))
622 // Identity and pointer-to-pointer casts are free.
623 return 0;
624 break;
625 case Instruction::Trunc: {
626 // trunc to a native type is free (assuming the target has compare and
627 // shift-right of the same width).
628 TypeSize DstSize = DL.getTypeSizeInBits(Dst);
629 if (!DstSize.isScalable() && DL.isLegalInteger(DstSize.getFixedValue()))
630 return 0;
631 break;
632 }
633 }
634 return 1;
635 }
636
638 VectorType *VecTy,
639 unsigned Index) const {
640 return 1;
641 }
642
644 const Instruction *I = nullptr) const {
645 // A phi would be free, unless we're costing the throughput because it
646 // will require a register.
647 if (Opcode == Instruction::PHI && CostKind != TTI::TCK_RecipThroughput)
648 return 0;
649 return 1;
650 }
651
652 InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
653 CmpInst::Predicate VecPred,
655 const Instruction *I) const {
656 return 1;
657 }
658
661 unsigned Index, Value *Op0,
662 Value *Op1) const {
663 return 1;
664 }
665
668 unsigned Index) const {
669 return 1;
670 }
671
672 unsigned getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF,
673 const APInt &DemandedDstElts,
675 return 1;
676 }
677
678 InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
679 unsigned AddressSpace,
682 const Instruction *I) const {
683 return 1;
684 }
685
686 InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
687 unsigned AddressSpace,
689 const Instruction *I) const {
690 return 1;
691 }
692
694 Align Alignment, unsigned AddressSpace,
696 return 1;
697 }
698
700 const Value *Ptr, bool VariableMask,
701 Align Alignment,
703 const Instruction *I = nullptr) const {
704 return 1;
705 }
706
708 const Value *Ptr, bool VariableMask,
709 Align Alignment,
711 const Instruction *I = nullptr) const {
713 }
714
716 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
717 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
718 bool UseMaskForCond, bool UseMaskForGaps) const {
719 return 1;
720 }
721
724 switch (ICA.getID()) {
725 default:
726 break;
727 case Intrinsic::allow_runtime_check:
728 case Intrinsic::allow_ubsan_check:
729 case Intrinsic::annotation:
730 case Intrinsic::assume:
731 case Intrinsic::sideeffect:
732 case Intrinsic::pseudoprobe:
733 case Intrinsic::arithmetic_fence:
734 case Intrinsic::dbg_assign:
735 case Intrinsic::dbg_declare:
736 case Intrinsic::dbg_value:
737 case Intrinsic::dbg_label:
738 case Intrinsic::invariant_start:
739 case Intrinsic::invariant_end:
740 case Intrinsic::launder_invariant_group:
741 case Intrinsic::strip_invariant_group:
742 case Intrinsic::is_constant:
743 case Intrinsic::lifetime_start:
744 case Intrinsic::lifetime_end:
745 case Intrinsic::experimental_noalias_scope_decl:
746 case Intrinsic::objectsize:
747 case Intrinsic::ptr_annotation:
748 case Intrinsic::var_annotation:
749 case Intrinsic::experimental_gc_result:
750 case Intrinsic::experimental_gc_relocate:
751 case Intrinsic::coro_alloc:
752 case Intrinsic::coro_begin:
753 case Intrinsic::coro_free:
754 case Intrinsic::coro_end:
755 case Intrinsic::coro_frame:
756 case Intrinsic::coro_size:
757 case Intrinsic::coro_align:
758 case Intrinsic::coro_suspend:
759 case Intrinsic::coro_subfn_addr:
760 case Intrinsic::threadlocal_address:
761 case Intrinsic::experimental_widenable_condition:
762 case Intrinsic::ssa_copy:
763 // These intrinsics don't actually represent code after lowering.
764 return 0;
765 }
766 return 1;
767 }
768
772 return 1;
773 }
774
775 // Assume that we have a register of the right size for the type.
776 unsigned getNumberOfParts(Type *Tp) const { return 1; }
777
779 const SCEV *) const {
780 return 0;
781 }
782
784 std::optional<FastMathFlags> FMF,
785 TTI::TargetCostKind) const {
786 return 1;
787 }
788
791 TTI::TargetCostKind) const {
792 return 1;
793 }
794
795 InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned,
796 Type *ResTy, VectorType *Ty,
797 FastMathFlags FMF,
799 return 1;
800 }
801
803 VectorType *Ty,
805 return 1;
806 }
807
809 return 0;
810 }
811
813 return false;
814 }
815
817 // Note for overrides: You must ensure for all element unordered-atomic
818 // memory intrinsics that all power-of-2 element sizes up to, and
819 // including, the return value of this method have a corresponding
820 // runtime lib call. These runtime lib call definitions can be found
821 // in RuntimeLibcalls.h
822 return 0;
823 }
824
826 Type *ExpectedType) const {
827 return nullptr;
828 }
829
830 Type *
832 unsigned SrcAddrSpace, unsigned DestAddrSpace,
833 unsigned SrcAlign, unsigned DestAlign,
834 std::optional<uint32_t> AtomicElementSize) const {
835 return AtomicElementSize ? Type::getIntNTy(Context, *AtomicElementSize * 8)
836 : Type::getInt8Ty(Context);
837 }
838
840 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
841 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
842 unsigned SrcAlign, unsigned DestAlign,
843 std::optional<uint32_t> AtomicCpySize) const {
844 unsigned OpSizeInBytes = AtomicCpySize ? *AtomicCpySize : 1;
845 Type *OpType = Type::getIntNTy(Context, OpSizeInBytes * 8);
846 for (unsigned i = 0; i != RemainingBytes; i += OpSizeInBytes)
847 OpsOut.push_back(OpType);
848 }
849
850 bool areInlineCompatible(const Function *Caller,
851 const Function *Callee) const {
852 return (Caller->getFnAttribute("target-cpu") ==
853 Callee->getFnAttribute("target-cpu")) &&
854 (Caller->getFnAttribute("target-features") ==
855 Callee->getFnAttribute("target-features"));
856 }
857
858 unsigned getInlineCallPenalty(const Function *F, const CallBase &Call,
859 unsigned DefaultCallPenalty) const {
860 return DefaultCallPenalty;
861 }
862
863 bool areTypesABICompatible(const Function *Caller, const Function *Callee,
864 const ArrayRef<Type *> &Types) const {
865 return (Caller->getFnAttribute("target-cpu") ==
866 Callee->getFnAttribute("target-cpu")) &&
867 (Caller->getFnAttribute("target-features") ==
868 Callee->getFnAttribute("target-features"));
869 }
870
872 const DataLayout &DL) const {
873 return false;
874 }
875
877 const DataLayout &DL) const {
878 return false;
879 }
880
881 unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; }
882
883 bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; }
884
885 bool isLegalToVectorizeStore(StoreInst *SI) const { return true; }
886
887 bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
888 unsigned AddrSpace) const {
889 return true;
890 }
891
892 bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
893 unsigned AddrSpace) const {
894 return true;
895 }
896
898 ElementCount VF) const {
899 return true;
900 }
901
902 bool isElementTypeLegalForScalableVector(Type *Ty) const { return true; }
903
904 unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
905 unsigned ChainSizeInBytes,
906 VectorType *VecTy) const {
907 return VF;
908 }
909
910 unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
911 unsigned ChainSizeInBytes,
912 VectorType *VecTy) const {
913 return VF;
914 }
915
916 bool preferInLoopReduction(unsigned Opcode, Type *Ty,
917 TTI::ReductionFlags Flags) const {
918 return false;
919 }
920
921 bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
922 TTI::ReductionFlags Flags) const {
923 return false;
924 }
925
927 return true;
928 }
929
930 bool shouldExpandReduction(const IntrinsicInst *II) const { return true; }
931
932 unsigned getGISelRematGlobalCost() const { return 1; }
933
934 unsigned getMinTripCountTailFoldingThreshold() const { return 0; }
935
936 bool supportsScalableVectors() const { return false; }
937
938 bool enableScalableVectorization() const { return false; }
939
940 bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
941 Align Alignment) const {
942 return false;
943 }
944
949 /* OperatorStrategy */ TargetTransformInfo::VPLegalization::Convert);
950 }
951
952 bool hasArmWideBranch(bool) const { return false; }
953
954 unsigned getMaxNumArgs() const { return UINT_MAX; }
955
956protected:
957 // Obtain the minimum required size to hold the value (without the sign)
958 // In case of a vector it returns the min required size for one element.
959 unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const {
960 if (isa<ConstantDataVector>(Val) || isa<ConstantVector>(Val)) {
961 const auto *VectorValue = cast<Constant>(Val);
962
963 // In case of a vector need to pick the max between the min
964 // required size for each element
965 auto *VT = cast<FixedVectorType>(Val->getType());
966
967 // Assume unsigned elements
968 isSigned = false;
969
970 // The max required size is the size of the vector element type
971 unsigned MaxRequiredSize =
972 VT->getElementType()->getPrimitiveSizeInBits().getFixedValue();
973
974 unsigned MinRequiredSize = 0;
975 for (unsigned i = 0, e = VT->getNumElements(); i < e; ++i) {
976 if (auto *IntElement =
977 dyn_cast<ConstantInt>(VectorValue->getAggregateElement(i))) {
978 bool signedElement = IntElement->getValue().isNegative();
979 // Get the element min required size.
980 unsigned ElementMinRequiredSize =
981 IntElement->getValue().getSignificantBits() - 1;
982 // In case one element is signed then all the vector is signed.
983 isSigned |= signedElement;
984 // Save the max required bit size between all the elements.
985 MinRequiredSize = std::max(MinRequiredSize, ElementMinRequiredSize);
986 } else {
987 // not an int constant element
988 return MaxRequiredSize;
989 }
990 }
991 return MinRequiredSize;
992 }
993
994 if (const auto *CI = dyn_cast<ConstantInt>(Val)) {
995 isSigned = CI->getValue().isNegative();
996 return CI->getValue().getSignificantBits() - 1;
997 }
998
999 if (const auto *Cast = dyn_cast<SExtInst>(Val)) {
1000 isSigned = true;
1001 return Cast->getSrcTy()->getScalarSizeInBits() - 1;
1002 }
1003
1004 if (const auto *Cast = dyn_cast<ZExtInst>(Val)) {
1005 isSigned = false;
1006 return Cast->getSrcTy()->getScalarSizeInBits();
1007 }
1008
1009 isSigned = false;
1010 return Val->getType()->getScalarSizeInBits();
1011 }
1012
1013 bool isStridedAccess(const SCEV *Ptr) const {
1014 return Ptr && isa<SCEVAddRecExpr>(Ptr);
1015 }
1016
1018 const SCEV *Ptr) const {
1019 if (!isStridedAccess(Ptr))
1020 return nullptr;
1021 const SCEVAddRecExpr *AddRec = cast<SCEVAddRecExpr>(Ptr);
1022 return dyn_cast<SCEVConstant>(AddRec->getStepRecurrence(*SE));
1023 }
1024
1026 int64_t MergeDistance) const {
1027 const SCEVConstant *Step = getConstantStrideStep(SE, Ptr);
1028 if (!Step)
1029 return false;
1030 APInt StrideVal = Step->getAPInt();
1031 if (StrideVal.getBitWidth() > 64)
1032 return false;
1033 // FIXME: Need to take absolute value for negative stride case.
1034 return StrideVal.getSExtValue() < MergeDistance;
1035 }
1036};
1037
1038/// CRTP base class for use as a mix-in that aids implementing
1039/// a TargetTransformInfo-compatible class.
1040template <typename T>
1042private:
1044
1045protected:
1047
1048public:
1050
1054 assert(PointeeType && Ptr && "can't get GEPCost of nullptr");
1055 auto *BaseGV = dyn_cast<GlobalValue>(Ptr->stripPointerCasts());
1056 bool HasBaseReg = (BaseGV == nullptr);
1057
1058 auto PtrSizeBits = DL.getPointerTypeSizeInBits(Ptr->getType());
1059 APInt BaseOffset(PtrSizeBits, 0);
1060 int64_t Scale = 0;
1061
1062 auto GTI = gep_type_begin(PointeeType, Operands);
1063 Type *TargetType = nullptr;
1064
1065 // Handle the case where the GEP instruction has a single operand,
1066 // the basis, therefore TargetType is a nullptr.
1067 if (Operands.empty())
1068 return !BaseGV ? TTI::TCC_Free : TTI::TCC_Basic;
1069
1070 for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
1071 TargetType = GTI.getIndexedType();
1072 // We assume that the cost of Scalar GEP with constant index and the
1073 // cost of Vector GEP with splat constant index are the same.
1074 const ConstantInt *ConstIdx = dyn_cast<ConstantInt>(*I);
1075 if (!ConstIdx)
1076 if (auto Splat = getSplatValue(*I))
1077 ConstIdx = dyn_cast<ConstantInt>(Splat);
1078 if (StructType *STy = GTI.getStructTypeOrNull()) {
1079 // For structures the index is always splat or scalar constant
1080 assert(ConstIdx && "Unexpected GEP index");
1081 uint64_t Field = ConstIdx->getZExtValue();
1082 BaseOffset += DL.getStructLayout(STy)->getElementOffset(Field);
1083 } else {
1084 // If this operand is a scalable type, bail out early.
1085 // TODO: Make isLegalAddressingMode TypeSize aware.
1086 if (TargetType->isScalableTy())
1087 return TTI::TCC_Basic;
1088 int64_t ElementSize =
1089 GTI.getSequentialElementStride(DL).getFixedValue();
1090 if (ConstIdx) {
1091 BaseOffset +=
1092 ConstIdx->getValue().sextOrTrunc(PtrSizeBits) * ElementSize;
1093 } else {
1094 // Needs scale register.
1095 if (Scale != 0)
1096 // No addressing mode takes two scale registers.
1097 return TTI::TCC_Basic;
1098 Scale = ElementSize;
1099 }
1100 }
1101 }
1102
1103 // If we haven't been provided a hint, use the target type for now.
1104 //
1105 // TODO: Take a look at potentially removing this: This is *slightly* wrong
1106 // as it's possible to have a GEP with a foldable target type but a memory
1107 // access that isn't foldable. For example, this load isn't foldable on
1108 // RISC-V:
1109 //
1110 // %p = getelementptr i32, ptr %base, i32 42
1111 // %x = load <2 x i32>, ptr %p
1112 if (!AccessType)
1113 AccessType = TargetType;
1114
1115 // If the final address of the GEP is a legal addressing mode for the given
1116 // access type, then we can fold it into its users.
1117 if (static_cast<T *>(this)->isLegalAddressingMode(
1118 AccessType, const_cast<GlobalValue *>(BaseGV),
1119 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale,
1120 Ptr->getType()->getPointerAddressSpace()))
1121 return TTI::TCC_Free;
1122
1123 // TODO: Instead of returning TCC_Basic here, we should use
1124 // getArithmeticInstrCost. Or better yet, provide a hook to let the target
1125 // model it.
1126 return TTI::TCC_Basic;
1127 }
1128
1130 const Value *Base,
1132 Type *AccessTy,
1135 // In the basic model we take into account GEP instructions only
1136 // (although here can come alloca instruction, a value, constants and/or
1137 // constant expressions, PHIs, bitcasts ... whatever allowed to be used as a
1138 // pointer). Typically, if Base is a not a GEP-instruction and all the
1139 // pointers are relative to the same base address, all the rest are
1140 // either GEP instructions, PHIs, bitcasts or constants. When we have same
1141 // base, we just calculate cost of each non-Base GEP as an ADD operation if
1142 // any their index is a non-const.
1143 // If no known dependecies between the pointers cost is calculated as a sum
1144 // of costs of GEP instructions.
1145 for (const Value *V : Ptrs) {
1146 const auto *GEP = dyn_cast<GetElementPtrInst>(V);
1147 if (!GEP)
1148 continue;
1149 if (Info.isSameBase() && V != Base) {
1150 if (GEP->hasAllConstantIndices())
1151 continue;
1152 Cost += static_cast<T *>(this)->getArithmeticInstrCost(
1153 Instruction::Add, GEP->getType(), CostKind,
1155 std::nullopt);
1156 } else {
1157 SmallVector<const Value *> Indices(GEP->indices());
1158 Cost += static_cast<T *>(this)->getGEPCost(GEP->getSourceElementType(),
1159 GEP->getPointerOperand(),
1160 Indices, AccessTy, CostKind);
1161 }
1162 }
1163 return Cost;
1164 }
1165
1169 using namespace llvm::PatternMatch;
1170
1171 auto *TargetTTI = static_cast<T *>(this);
1172 // Handle non-intrinsic calls, invokes, and callbr.
1173 // FIXME: Unlikely to be true for anything but CodeSize.
1174 auto *CB = dyn_cast<CallBase>(U);
1175 if (CB && !isa<IntrinsicInst>(U)) {
1176 if (const Function *F = CB->getCalledFunction()) {
1177 if (!TargetTTI->isLoweredToCall(F))
1178 return TTI::TCC_Basic; // Give a basic cost if it will be lowered
1179
1180 return TTI::TCC_Basic * (F->getFunctionType()->getNumParams() + 1);
1181 }
1182 // For indirect or other calls, scale cost by number of arguments.
1183 return TTI::TCC_Basic * (CB->arg_size() + 1);
1184 }
1185
1186 Type *Ty = U->getType();
1187 unsigned Opcode = Operator::getOpcode(U);
1188 auto *I = dyn_cast<Instruction>(U);
1189 switch (Opcode) {
1190 default:
1191 break;
1192 case Instruction::Call: {
1193 assert(isa<IntrinsicInst>(U) && "Unexpected non-intrinsic call");
1194 auto *Intrinsic = cast<IntrinsicInst>(U);
1195 IntrinsicCostAttributes CostAttrs(Intrinsic->getIntrinsicID(), *CB);
1196 return TargetTTI->getIntrinsicInstrCost(CostAttrs, CostKind);
1197 }
1198 case Instruction::Br:
1199 case Instruction::Ret:
1200 case Instruction::PHI:
1201 case Instruction::Switch:
1202 return TargetTTI->getCFInstrCost(Opcode, CostKind, I);
1203 case Instruction::ExtractValue:
1204 case Instruction::Freeze:
1205 return TTI::TCC_Free;
1206 case Instruction::Alloca:
1207 if (cast<AllocaInst>(U)->isStaticAlloca())
1208 return TTI::TCC_Free;
1209 break;
1210 case Instruction::GetElementPtr: {
1211 const auto *GEP = cast<GEPOperator>(U);
1212 Type *AccessType = nullptr;
1213 // For now, only provide the AccessType in the simple case where the GEP
1214 // only has one user.
1215 if (GEP->hasOneUser() && I)
1216 AccessType = I->user_back()->getAccessType();
1217
1218 return TargetTTI->getGEPCost(GEP->getSourceElementType(),
1219 Operands.front(), Operands.drop_front(),
1220 AccessType, CostKind);
1221 }
1222 case Instruction::Add:
1223 case Instruction::FAdd:
1224 case Instruction::Sub:
1225 case Instruction::FSub:
1226 case Instruction::Mul:
1227 case Instruction::FMul:
1228 case Instruction::UDiv:
1229 case Instruction::SDiv:
1230 case Instruction::FDiv:
1231 case Instruction::URem:
1232 case Instruction::SRem:
1233 case Instruction::FRem:
1234 case Instruction::Shl:
1235 case Instruction::LShr:
1236 case Instruction::AShr:
1237 case Instruction::And:
1238 case Instruction::Or:
1239 case Instruction::Xor:
1240 case Instruction::FNeg: {
1242 TTI::OperandValueInfo Op2Info;
1243 if (Opcode != Instruction::FNeg)
1244 Op2Info = TTI::getOperandInfo(Operands[1]);
1245 return TargetTTI->getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
1246 Op2Info, Operands, I);
1247 }
1248 case Instruction::IntToPtr:
1249 case Instruction::PtrToInt:
1250 case Instruction::SIToFP:
1251 case Instruction::UIToFP:
1252 case Instruction::FPToUI:
1253 case Instruction::FPToSI:
1254 case Instruction::Trunc:
1255 case Instruction::FPTrunc:
1256 case Instruction::BitCast:
1257 case Instruction::FPExt:
1258 case Instruction::SExt:
1259 case Instruction::ZExt:
1260 case Instruction::AddrSpaceCast: {
1261 Type *OpTy = Operands[0]->getType();
1262 return TargetTTI->getCastInstrCost(
1263 Opcode, Ty, OpTy, TTI::getCastContextHint(I), CostKind, I);
1264 }
1265 case Instruction::Store: {
1266 auto *SI = cast<StoreInst>(U);
1267 Type *ValTy = Operands[0]->getType();
1269 return TargetTTI->getMemoryOpCost(Opcode, ValTy, SI->getAlign(),
1270 SI->getPointerAddressSpace(), CostKind,
1271 OpInfo, I);
1272 }
1273 case Instruction::Load: {
1274 // FIXME: Arbitary cost which could come from the backend.
1276 return 4;
1277 auto *LI = cast<LoadInst>(U);
1278 Type *LoadType = U->getType();
1279 // If there is a non-register sized type, the cost estimation may expand
1280 // it to be several instructions to load into multiple registers on the
1281 // target. But, if the only use of the load is a trunc instruction to a
1282 // register sized type, the instruction selector can combine these
1283 // instructions to be a single load. So, in this case, we use the
1284 // destination type of the trunc instruction rather than the load to
1285 // accurately estimate the cost of this load instruction.
1286 if (CostKind == TTI::TCK_CodeSize && LI->hasOneUse() &&
1287 !LoadType->isVectorTy()) {
1288 if (const TruncInst *TI = dyn_cast<TruncInst>(*LI->user_begin()))
1289 LoadType = TI->getDestTy();
1290 }
1291 return TargetTTI->getMemoryOpCost(Opcode, LoadType, LI->getAlign(),
1293 {TTI::OK_AnyValue, TTI::OP_None}, I);
1294 }
1295 case Instruction::Select: {
1296 const Value *Op0, *Op1;
1297 if (match(U, m_LogicalAnd(m_Value(Op0), m_Value(Op1))) ||
1298 match(U, m_LogicalOr(m_Value(Op0), m_Value(Op1)))) {
1299 // select x, y, false --> x & y
1300 // select x, true, y --> x | y
1301 const auto Op1Info = TTI::getOperandInfo(Op0);
1302 const auto Op2Info = TTI::getOperandInfo(Op1);
1303 assert(Op0->getType()->getScalarSizeInBits() == 1 &&
1304 Op1->getType()->getScalarSizeInBits() == 1);
1305
1307 return TargetTTI->getArithmeticInstrCost(
1308 match(U, m_LogicalOr()) ? Instruction::Or : Instruction::And, Ty,
1309 CostKind, Op1Info, Op2Info, Operands, I);
1310 }
1311 Type *CondTy = Operands[0]->getType();
1312 return TargetTTI->getCmpSelInstrCost(Opcode, U->getType(), CondTy,
1314 CostKind, I);
1315 }
1316 case Instruction::ICmp:
1317 case Instruction::FCmp: {
1318 Type *ValTy = Operands[0]->getType();
1319 // TODO: Also handle ICmp/FCmp constant expressions.
1320 return TargetTTI->getCmpSelInstrCost(Opcode, ValTy, U->getType(),
1321 I ? cast<CmpInst>(I)->getPredicate()
1323 CostKind, I);
1324 }
1325 case Instruction::InsertElement: {
1326 auto *IE = dyn_cast<InsertElementInst>(U);
1327 if (!IE)
1328 return TTI::TCC_Basic; // FIXME
1329 unsigned Idx = -1;
1330 if (auto *CI = dyn_cast<ConstantInt>(Operands[2]))
1331 if (CI->getValue().getActiveBits() <= 32)
1332 Idx = CI->getZExtValue();
1333 return TargetTTI->getVectorInstrCost(*IE, Ty, CostKind, Idx);
1334 }
1335 case Instruction::ShuffleVector: {
1336 auto *Shuffle = dyn_cast<ShuffleVectorInst>(U);
1337 if (!Shuffle)
1338 return TTI::TCC_Basic; // FIXME
1339
1340 auto *VecTy = cast<VectorType>(U->getType());
1341 auto *VecSrcTy = cast<VectorType>(Operands[0]->getType());
1342 ArrayRef<int> Mask = Shuffle->getShuffleMask();
1343 int NumSubElts, SubIndex;
1344
1345 // TODO: move more of this inside improveShuffleKindFromMask.
1346 if (Shuffle->changesLength()) {
1347 // Treat a 'subvector widening' as a free shuffle.
1348 if (Shuffle->increasesLength() && Shuffle->isIdentityWithPadding())
1349 return 0;
1350
1351 if (Shuffle->isExtractSubvectorMask(SubIndex))
1352 return TargetTTI->getShuffleCost(TTI::SK_ExtractSubvector, VecSrcTy,
1353 Mask, CostKind, SubIndex, VecTy,
1354 Operands, Shuffle);
1355
1356 if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1357 return TargetTTI->getShuffleCost(
1358 TTI::SK_InsertSubvector, VecTy, Mask, CostKind, SubIndex,
1359 FixedVectorType::get(VecTy->getScalarType(), NumSubElts),
1360 Operands, Shuffle);
1361
1362 int ReplicationFactor, VF;
1363 if (Shuffle->isReplicationMask(ReplicationFactor, VF)) {
1364 APInt DemandedDstElts = APInt::getZero(Mask.size());
1365 for (auto I : enumerate(Mask)) {
1366 if (I.value() != PoisonMaskElem)
1367 DemandedDstElts.setBit(I.index());
1368 }
1369 return TargetTTI->getReplicationShuffleCost(
1370 VecSrcTy->getElementType(), ReplicationFactor, VF,
1371 DemandedDstElts, CostKind);
1372 }
1373
1374 bool IsUnary = isa<UndefValue>(Operands[1]);
1375 NumSubElts = VecSrcTy->getElementCount().getKnownMinValue();
1376 SmallVector<int, 16> AdjustMask(Mask.begin(), Mask.end());
1377
1378 // Widening shuffle - widening the source(s) to the new length
1379 // (treated as free - see above), and then perform the adjusted
1380 // shuffle at that width.
1381 if (Shuffle->increasesLength()) {
1382 for (int &M : AdjustMask)
1383 M = M >= NumSubElts ? (M + (Mask.size() - NumSubElts)) : M;
1384
1385 return TargetTTI->getShuffleCost(
1387 AdjustMask, CostKind, 0, nullptr, Operands, Shuffle);
1388 }
1389
1390 // Narrowing shuffle - perform shuffle at original wider width and
1391 // then extract the lower elements.
1392 AdjustMask.append(NumSubElts - Mask.size(), PoisonMaskElem);
1393
1394 InstructionCost ShuffleCost = TargetTTI->getShuffleCost(
1396 VecSrcTy, AdjustMask, CostKind, 0, nullptr, Operands, Shuffle);
1397
1398 SmallVector<int, 16> ExtractMask(Mask.size());
1399 std::iota(ExtractMask.begin(), ExtractMask.end(), 0);
1400 return ShuffleCost + TargetTTI->getShuffleCost(
1401 TTI::SK_ExtractSubvector, VecSrcTy,
1402 ExtractMask, CostKind, 0, VecTy, {}, Shuffle);
1403 }
1404
1405 if (Shuffle->isIdentity())
1406 return 0;
1407
1408 if (Shuffle->isReverse())
1409 return TargetTTI->getShuffleCost(TTI::SK_Reverse, VecTy, Mask, CostKind,
1410 0, nullptr, Operands, Shuffle);
1411
1412 if (Shuffle->isSelect())
1413 return TargetTTI->getShuffleCost(TTI::SK_Select, VecTy, Mask, CostKind,
1414 0, nullptr, Operands, Shuffle);
1415
1416 if (Shuffle->isTranspose())
1417 return TargetTTI->getShuffleCost(TTI::SK_Transpose, VecTy, Mask,
1418 CostKind, 0, nullptr, Operands,
1419 Shuffle);
1420
1421 if (Shuffle->isZeroEltSplat())
1422 return TargetTTI->getShuffleCost(TTI::SK_Broadcast, VecTy, Mask,
1423 CostKind, 0, nullptr, Operands,
1424 Shuffle);
1425
1426 if (Shuffle->isSingleSource())
1427 return TargetTTI->getShuffleCost(TTI::SK_PermuteSingleSrc, VecTy, Mask,
1428 CostKind, 0, nullptr, Operands,
1429 Shuffle);
1430
1431 if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1432 return TargetTTI->getShuffleCost(
1433 TTI::SK_InsertSubvector, VecTy, Mask, CostKind, SubIndex,
1434 FixedVectorType::get(VecTy->getScalarType(), NumSubElts), Operands,
1435 Shuffle);
1436
1437 if (Shuffle->isSplice(SubIndex))
1438 return TargetTTI->getShuffleCost(TTI::SK_Splice, VecTy, Mask, CostKind,
1439 SubIndex, nullptr, Operands, Shuffle);
1440
1441 return TargetTTI->getShuffleCost(TTI::SK_PermuteTwoSrc, VecTy, Mask,
1442 CostKind, 0, nullptr, Operands, Shuffle);
1443 }
1444 case Instruction::ExtractElement: {
1445 auto *EEI = dyn_cast<ExtractElementInst>(U);
1446 if (!EEI)
1447 return TTI::TCC_Basic; // FIXME
1448 unsigned Idx = -1;
1449 if (auto *CI = dyn_cast<ConstantInt>(Operands[1]))
1450 if (CI->getValue().getActiveBits() <= 32)
1451 Idx = CI->getZExtValue();
1452 Type *DstTy = Operands[0]->getType();
1453 return TargetTTI->getVectorInstrCost(*EEI, DstTy, CostKind, Idx);
1454 }
1455 }
1456
1457 // By default, just classify everything as 'basic' or -1 to represent that
1458 // don't know the throughput cost.
1460 }
1461
1463 auto *TargetTTI = static_cast<T *>(this);
1464 SmallVector<const Value *, 4> Ops(I->operand_values());
1465 InstructionCost Cost = TargetTTI->getInstructionCost(
1468 }
1469
1470 bool supportsTailCallFor(const CallBase *CB) const {
1471 return static_cast<const T *>(this)->supportsTailCalls();
1472 }
1473};
1474} // namespace llvm
1475
1476#endif
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
return RetTy
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
std::string Name
static bool isSigned(unsigned int Opcode)
Hexagon Common GEP
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
uint64_t IntrinsicInst * II
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static SymbolRef::Type getType(const Symbol *Sym)
Definition: TapiFile.cpp:40
This pass exposes codegen information to IR-level passes.
Class for arbitrary precision integers.
Definition: APInt.h:77
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
Definition: APInt.h:1309
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1447
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:1010
static APInt getZero(unsigned numBits)
Get the '0' value for the specified bit-width.
Definition: APInt.h:179
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1521
an instruction to allocate memory on the stack
Definition: Instructions.h:60
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A cache of @llvm.assume calls within a function.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Conditional or Unconditional Branch instruction.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1494
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:993
This is the shared class of boolean and integer constants.
Definition: Constants.h:81
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:155
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:146
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
bool isLegalInteger(uint64_t Width) const
Returns true if the specified type is known to be a native integer type supported by the CPU.
Definition: DataLayout.h:260
const StructLayout * getStructLayout(StructType *Ty) const
Returns a StructLayout object, indicating the alignment of the struct, its size, and the offsets of i...
Definition: DataLayout.cpp:720
unsigned getPointerTypeSizeInBits(Type *) const
Layout pointer size, in bits, based on the type.
Definition: DataLayout.cpp:763
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:672
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Definition: DataLayout.h:472
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:162
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
Definition: TypeSize.h:314
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:20
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
Definition: Type.cpp:692
The core instruction combiner logic.
Definition: InstCombiner.h:47
static InstructionCost getInvalid(CostType Val=0)
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:48
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:185
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:44
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
Definition: Operator.h:42
The optimization diagnostic interface.
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:71
This node represents a polynomial recurrence on the trip count of the specified loop.
const SCEV * getStepRecurrence(ScalarEvolution &SE) const
Constructs and returns the recurrence indicating how much this expression steps by.
This class represents a constant integer value.
const APInt & getAPInt() const
This class represents an analyzed expression in the program.
The main scalar evolution driver.
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:696
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
static StackOffset getScalable(int64_t Scalable)
Definition: TypeSize.h:43
static StackOffset getFixed(int64_t Fixed)
Definition: TypeSize.h:42
An instruction for storing to memory.
Definition: Instructions.h:318
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TypeSize getElementOffset(unsigned Idx) const
Definition: DataLayout.h:651
Class to represent struct types.
Definition: DerivedTypes.h:216
Multiway switch.
Provides information about what library functions are available for the current target.
Base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
const DataLayout & getDataLayout() const
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicCpySize) const
bool isLegalToVectorizeStore(StoreInst *SI) const
bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const
bool shouldTreatInstructionLikeSelect(const Instruction *I)
bool isLegalToVectorizeLoad(LoadInst *LI) const
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
std::optional< unsigned > getVScaleForTuning() const
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
bool isLegalICmpImmediate(int64_t Imm) const
unsigned getRegUsageForType(Type *Ty) const
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) const
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
void getPeelingPreferences(Loop *, ScalarEvolution &, TTI::PeelingPreferences &) const
bool isAlwaysUniform(const Value *V) const
bool isProfitableToHoist(Instruction *I) const
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
bool isLSRCostLess(const TTI::LSRCost &C1, const TTI::LSRCost &C2) const
bool isExpensiveToSpeculativelyExecute(const Instruction *I)
bool isTruncateFree(Type *Ty1, Type *Ty2) const
bool isStridedAccess(const SCEV *Ptr) const
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
InstructionCost getArithmeticReductionCost(unsigned, VectorType *, std::optional< FastMathFlags > FMF, TTI::TargetCostKind) const
InstructionCost getFPOpCost(Type *Ty) const
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
InstructionCost getMemcpyCost(const Instruction *I) const
unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
std::optional< unsigned > getMaxVScale() const
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const
bool isProfitableLSRChainElement(Instruction *I) const
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt, const Instruction *CxtI=nullptr) const
InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
bool preferToKeepConstantsAttached(const Instruction &Inst, const Function &Fn) const
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
InstructionCost getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
bool isNoopAddrSpaceCast(unsigned, unsigned) const
unsigned getStoreMinimumVF(unsigned VF, Type *, Type *) const
InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, TTI::TargetCostKind CostKind, unsigned Index) const
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg)
TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
void getUnrollingPreferences(Loop *, ScalarEvolution &, TTI::UnrollingPreferences &, OptimizationRemarkEmitter *) const
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr, int64_t ScalableOffset=0) const
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicElementSize) const
std::optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const
unsigned getAssumedAddrSpace(const Value *V) const
bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const
bool isLegalNTStore(Type *DataType, Align Alignment) const
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
unsigned adjustInliningThreshold(const CallBase *CB) const
BranchProbability getPredictableBranchThreshold() const
std::optional< unsigned > getMinPageSize() const
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind) const
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, unsigned *Fast) const
const SCEVConstant * getConstantStrideStep(ScalarEvolution *SE, const SCEV *Ptr) const
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
bool shouldPrefetchAddressSpace(unsigned AS) const
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
unsigned getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
bool isSourceOfDivergence(const Value *V) const
bool enableAggressiveInterleaving(bool LoopHasReductions) const
unsigned getMaxInterleaveFactor(ElementCount VF) const
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I) const
std::optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr) const
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
bool forceScalarizeMaskedGather(VectorType *DataType, Align Alignment) const
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
bool hasDivRemOp(Type *DataType, bool IsSigned) const
InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *, const SCEV *) const
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I) const
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const
bool isLoweredToCall(const Function *F) const
bool hasBranchDivergence(const Function *F=nullptr) const
TargetTransformInfoImplBase(const DataLayout &DL)
bool isLegalMaskedVectorHistogram(Type *AddrType, Type *DataType) const
const char * getRegisterClassName(unsigned ClassID) const
bool isElementTypeLegalForScalableVector(Type *Ty) const
bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind) const
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
TailFoldingStyle getPreferredTailFoldingStyle(bool IVUpdateMayOverflow=true) const
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *, FastMathFlags, TTI::TargetCostKind) const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1) const
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo, const Instruction *I) const
bool useColdCCForColdCall(Function &F) const
bool shouldExpandReduction(const IntrinsicInst *II) const
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
unsigned getNumberOfRegisters(unsigned ClassID) const
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType, TTI::TargetCostKind CostKind) const
bool isLegalNTLoad(Type *DataType, Align Alignment) const
std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
bool forceScalarizeMaskedScatter(VectorType *DataType, Align Alignment) const
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
bool isLegalAddScalableImmediate(int64_t Imm) const
bool isLegalMaskedCompressStore(Type *DataType, Align Alignment) const
InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const
TargetTransformInfoImplBase(const TargetTransformInfoImplBase &Arg)=default
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
bool shouldBuildLookupTablesForConstant(Constant *C) const
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
bool supportsTailCallFor(const CallBase *CB) const
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType, TTI::TargetCostKind CostKind)
InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const TTI::PointersChainInfo &Info, Type *AccessTy, TTI::TargetCostKind CostKind)
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
bool isExpensiveToSpeculativelyExecute(const Instruction *I)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
static OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
TargetCostKind
The kind of cost model.
@ TCK_RecipThroughput
Reciprocal throughput.
@ TCK_CodeSize
Instruction code size.
@ TCK_SizeAndLatency
The weighted sum of size and latency.
@ TCK_Latency
The latency of instruction.
PopcntSupportKind
Flags indicating the kind of support for population count.
@ TCC_Expensive
The cost of a 'div' instruction on x86.
@ TCC_Free
Expected to fold away in lowering.
@ TCC_Basic
The cost of a typical 'add' instruction.
MemIndexedMode
The type of load/store indexing.
ShuffleKind
The various kinds of shuffle patterns for vector queries.
@ SK_InsertSubvector
InsertSubvector. Index indicates start offset.
@ SK_Select
Selects elements from the corresponding lane of either source operand.
@ SK_PermuteSingleSrc
Shuffle elements of single source vector with any shuffle mask.
@ SK_Transpose
Transpose two vectors.
@ SK_Splice
Concatenates elements from the first input vector with elements of the second input vector.
@ SK_Broadcast
Broadcast element 0 to all other elements.
@ SK_PermuteTwoSrc
Merge elements from two source vectors into one with any shuffle mask.
@ SK_Reverse
Reverse the order of the vector.
@ SK_ExtractSubvector
ExtractSubvector Index indicates start offset.
CastContextHint
Represents a hint about the context in which a cast is used.
CacheLevel
The possible cache levels.
This class represents a truncation of integer types.
static constexpr TypeSize getFixed(ScalarTy ExactSize)
Definition: TypeSize.h:342
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:265
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
static IntegerType * getInt8Ty(LLVMContext &C)
bool isFloatingPointTy() const
Return true if this is one of the floating-point types.
Definition: Type.h:185
bool isScalableTy() const
Return true if this is a type whose size is a known multiple of vscale.
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:348
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
constexpr ScalarTy getFixedValue() const
Definition: TypeSize.h:199
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:171
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
auto m_LogicalOr()
Matches L || R where L and R are arbitrary values.
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:92
auto m_LogicalAnd()
Matches L && R where L and R are arbitrary values.
match_combine_or< LTy, RTy > m_CombineOr(const LTy &L, const RTy &R)
Combine two pattern matchers matching L || R.
Definition: PatternMatch.h:239
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Length
Definition: DWP.cpp:456
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are are tuples (A,...
Definition: STLExtras.h:2400
AddressSpace
Definition: NVPTXBaseInfo.h:21
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1729
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:275
constexpr int PoisonMaskElem
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:191
gep_type_iterator gep_type_begin(const User *GEP)
InstructionCost Cost
@ DataWithoutLaneMask
Same as Data, but avoids using the get.active.lane.mask intrinsic to calculate the mask and instead i...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Attributes of a target dependent hardware loop.
Information about a load/store intrinsic defined by the target.
Returns options for expansion of memcmp. IsZeroCmp is.
Describe known properties for a set of pointers.
Flags describing the kind of vector reduction.
Parameters that control the generic loop unrolling transformation.