LLVM  14.0.0git
TargetTransformInfoImpl.h
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1 //===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file provides helpers for the implementation of
10 /// a TargetTransformInfo-conforming class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
15 #define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
16 
20 #include "llvm/IR/DataLayout.h"
21 #include "llvm/IR/Function.h"
23 #include "llvm/IR/IntrinsicInst.h"
24 #include "llvm/IR/Operator.h"
25 #include "llvm/IR/PatternMatch.h"
26 #include "llvm/IR/Type.h"
27 #include <utility>
28 
29 using namespace llvm::PatternMatch;
30 
31 namespace llvm {
32 
33 /// Base class for use as a mix-in that aids implementing
34 /// a TargetTransformInfo-compatible class.
36 protected:
38 
39  const DataLayout &DL;
40 
42 
43 public:
44  // Provide value semantics. MSVC requires that we spell all of these out.
46  : DL(Arg.DL) {}
48 
49  const DataLayout &getDataLayout() const { return DL; }
50 
51  InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr,
54  // In the basic model, we just assume that all-constant GEPs will be folded
55  // into their uses via addressing modes.
56  for (unsigned Idx = 0, Size = Operands.size(); Idx != Size; ++Idx)
57  if (!isa<Constant>(Operands[Idx]))
58  return TTI::TCC_Basic;
59 
60  return TTI::TCC_Free;
61  }
62 
64  unsigned &JTSize,
65  ProfileSummaryInfo *PSI,
66  BlockFrequencyInfo *BFI) const {
67  (void)PSI;
68  (void)BFI;
69  JTSize = 0;
70  return SI.getNumCases();
71  }
72 
73  unsigned getInliningThresholdMultiplier() const { return 1; }
74  unsigned adjustInliningThreshold(const CallBase *CB) const { return 0; }
75 
76  int getInlinerVectorBonusPercent() const { return 150; }
77 
79  return TTI::TCC_Expensive;
80  }
81 
82  // Although this default value is arbitrary, it is not random. It is assumed
83  // that a condition that evaluates the same way by a higher percentage than
84  // this is best represented as control flow. Therefore, the default value N
85  // should be set such that the win from N% correct executions is greater than
86  // the loss from (100 - N)% mispredicted executions for the majority of
87  // intended targets.
89  return BranchProbability(99, 100);
90  }
91 
92  bool hasBranchDivergence() const { return false; }
93 
94  bool useGPUDivergenceAnalysis() const { return false; }
95 
96  bool isSourceOfDivergence(const Value *V) const { return false; }
97 
98  bool isAlwaysUniform(const Value *V) const { return false; }
99 
100  unsigned getFlatAddressSpace() const { return -1; }
101 
103  Intrinsic::ID IID) const {
104  return false;
105  }
106 
107  bool isNoopAddrSpaceCast(unsigned, unsigned) const { return false; }
109  return AS == 0;
110  };
111 
112  unsigned getAssumedAddrSpace(const Value *V) const { return -1; }
113 
114  std::pair<const Value *, unsigned>
115  getPredicatedAddrSpace(const Value *V) const {
116  return std::make_pair(nullptr, -1);
117  }
118 
120  Value *NewV) const {
121  return nullptr;
122  }
123 
124  bool isLoweredToCall(const Function *F) const {
125  assert(F && "A concrete function must be provided to this routine.");
126 
127  // FIXME: These should almost certainly not be handled here, and instead
128  // handled with the help of TLI or the target itself. This was largely
129  // ported from existing analysis heuristics here so that such refactorings
130  // can take place in the future.
131 
132  if (F->isIntrinsic())
133  return false;
134 
135  if (F->hasLocalLinkage() || !F->hasName())
136  return true;
137 
138  StringRef Name = F->getName();
139 
140  // These will all likely lower to a single selection DAG node.
141  if (Name == "copysign" || Name == "copysignf" || Name == "copysignl" ||
142  Name == "fabs" || Name == "fabsf" || Name == "fabsl" || Name == "sin" ||
143  Name == "fmin" || Name == "fminf" || Name == "fminl" ||
144  Name == "fmax" || Name == "fmaxf" || Name == "fmaxl" ||
145  Name == "sinf" || Name == "sinl" || Name == "cos" || Name == "cosf" ||
146  Name == "cosl" || Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl")
147  return false;
148 
149  // These are all likely to be optimized into something smaller.
150  if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" ||
151  Name == "exp2l" || Name == "exp2f" || Name == "floor" ||
152  Name == "floorf" || Name == "ceil" || Name == "round" ||
153  Name == "ffs" || Name == "ffsl" || Name == "abs" || Name == "labs" ||
154  Name == "llabs")
155  return false;
156 
157  return true;
158  }
159 
161  AssumptionCache &AC, TargetLibraryInfo *LibInfo,
162  HardwareLoopInfo &HWLoopInfo) const {
163  return false;
164  }
165 
168  DominatorTree *DT,
169  const LoopAccessInfo *LAI) const {
170  return false;
171  }
172 
173  bool emitGetActiveLaneMask() const {
174  return false;
175  }
176 
178  IntrinsicInst &II) const {
179  return None;
180  }
181 
184  APInt DemandedMask, KnownBits &Known,
185  bool &KnownBitsComputed) const {
186  return None;
187  }
188 
190  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
191  APInt &UndefElts2, APInt &UndefElts3,
192  std::function<void(Instruction *, unsigned, APInt, APInt &)>
193  SimplifyAndSetOp) const {
194  return None;
195  }
196 
199  OptimizationRemarkEmitter *) const {}
200 
202  TTI::PeelingPreferences &) const {}
203 
204  bool isLegalAddImmediate(int64_t Imm) const { return false; }
205 
206  bool isLegalICmpImmediate(int64_t Imm) const { return false; }
207 
208  bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
209  bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
210  Instruction *I = nullptr) const {
211  // Guess that only reg and reg+reg addressing is allowed. This heuristic is
212  // taken from the implementation of LSR.
213  return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
214  }
215 
217  return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
218  C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
219  std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
220  C2.ScaleCost, C2.ImmCost, C2.SetupCost);
221  }
222 
223  bool isNumRegsMajorCostOfLSR() const { return true; }
224 
225  bool isProfitableLSRChainElement(Instruction *I) const { return false; }
226 
227  bool canMacroFuseCmp() const { return false; }
228 
231  TargetLibraryInfo *LibInfo) const {
232  return false;
233  }
234 
237  return TTI::AMK_None;
238  }
239 
240  bool isLegalMaskedStore(Type *DataType, Align Alignment) const {
241  return false;
242  }
243 
244  bool isLegalMaskedLoad(Type *DataType, Align Alignment) const {
245  return false;
246  }
247 
248  bool isLegalNTStore(Type *DataType, Align Alignment) const {
249  // By default, assume nontemporal memory stores are available for stores
250  // that are aligned and have a size that is a power of 2.
251  unsigned DataSize = DL.getTypeStoreSize(DataType);
252  return Alignment >= DataSize && isPowerOf2_32(DataSize);
253  }
254 
255  bool isLegalNTLoad(Type *DataType, Align Alignment) const {
256  // By default, assume nontemporal memory loads are available for loads that
257  // are aligned and have a size that is a power of 2.
258  unsigned DataSize = DL.getTypeStoreSize(DataType);
259  return Alignment >= DataSize && isPowerOf2_32(DataSize);
260  }
261 
262  bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
263  return false;
264  }
265 
266  bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
267  return false;
268  }
269 
270  bool isLegalMaskedCompressStore(Type *DataType) const { return false; }
271 
272  bool isLegalMaskedExpandLoad(Type *DataType) const { return false; }
273 
274  bool enableOrderedReductions() const { return false; }
275 
276  bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; }
277 
278  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const {
279  return false;
280  }
281 
282  bool prefersVectorizedAddressing() const { return true; }
283 
285  int64_t BaseOffset, bool HasBaseReg,
286  int64_t Scale,
287  unsigned AddrSpace) const {
288  // Guess that all legal addressing mode are free.
289  if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
290  AddrSpace))
291  return 0;
292  return -1;
293  }
294 
295  bool LSRWithInstrQueries() const { return false; }
296 
297  bool isTruncateFree(Type *Ty1, Type *Ty2) const { return false; }
298 
299  bool isProfitableToHoist(Instruction *I) const { return true; }
300 
301  bool useAA() const { return false; }
302 
303  bool isTypeLegal(Type *Ty) const { return false; }
304 
305  InstructionCost getRegUsageForType(Type *Ty) const { return 1; }
306 
307  bool shouldBuildLookupTables() const { return true; }
308 
309  bool shouldBuildLookupTablesForConstant(Constant *C) const { return true; }
310 
311  bool shouldBuildRelLookupTables() const { return false; }
312 
313  bool useColdCCForColdCall(Function &F) const { return false; }
314 
316  const APInt &DemandedElts,
317  bool Insert, bool Extract) const {
318  return 0;
319  }
320 
322  ArrayRef<Type *> Tys) const {
323  return 0;
324  }
325 
326  bool supportsEfficientVectorElementLoadStore() const { return false; }
327 
328  bool enableAggressiveInterleaving(bool LoopHasReductions) const {
329  return false;
330  }
331 
333  bool IsZeroCmp) const {
334  return {};
335  }
336 
337  bool enableInterleavedAccessVectorization() const { return false; }
338 
339  bool enableMaskedInterleavedAccessVectorization() const { return false; }
340 
341  bool isFPVectorizationPotentiallyUnsafe() const { return false; }
342 
344  unsigned AddressSpace, Align Alignment,
345  bool *Fast) const {
346  return false;
347  }
348 
349  TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const {
350  return TTI::PSK_Software;
351  }
352 
353  bool haveFastSqrt(Type *Ty) const { return false; }
354 
355  bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; }
356 
359  }
360 
361  InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
362  const APInt &Imm, Type *Ty) const {
363  return 0;
364  }
365 
368  return TTI::TCC_Basic;
369  }
370 
371  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
372  const APInt &Imm, Type *Ty,
374  Instruction *Inst = nullptr) const {
375  return TTI::TCC_Free;
376  }
377 
379  const APInt &Imm, Type *Ty,
381  return TTI::TCC_Free;
382  }
383 
384  unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; }
385 
386  unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
387  return Vector ? 1 : 0;
388  };
389 
390  const char *getRegisterClassName(unsigned ClassID) const {
391  switch (ClassID) {
392  default:
393  return "Generic::Unknown Register Class";
394  case 0:
395  return "Generic::ScalarRC";
396  case 1:
397  return "Generic::VectorRC";
398  }
399  }
400 
402  return TypeSize::getFixed(32);
403  }
404 
405  unsigned getMinVectorRegisterBitWidth() const { return 128; }
406 
409 
410  bool shouldMaximizeVectorBandwidth() const { return false; }
411 
412  ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const {
413  return ElementCount::get(0, IsScalable);
414  }
415 
416  unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const { return 0; }
417 
419  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
420  AllowPromotionWithoutCommonHeader = false;
421  return false;
422  }
423 
424  unsigned getCacheLineSize() const { return 0; }
425 
428  switch (Level) {
432  return llvm::Optional<unsigned>();
433  }
434  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
435  }
436 
439  switch (Level) {
443  return llvm::Optional<unsigned>();
444  }
445 
446  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
447  }
448 
449  unsigned getPrefetchDistance() const { return 0; }
450  unsigned getMinPrefetchStride(unsigned NumMemAccesses,
451  unsigned NumStridedMemAccesses,
452  unsigned NumPrefetches, bool HasCall) const {
453  return 1;
454  }
455  unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; }
456  bool enableWritePrefetching() const { return false; }
457 
458  unsigned getMaxInterleaveFactor(unsigned VF) const { return 1; }
459 
461  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
462  TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info,
463  TTI::OperandValueProperties Opd1PropInfo,
465  const Instruction *CxtI = nullptr) const {
466  // FIXME: A number of transformation tests seem to require these values
467  // which seems a little odd for how arbitary there are.
468  switch (Opcode) {
469  default:
470  break;
471  case Instruction::FDiv:
472  case Instruction::FRem:
473  case Instruction::SDiv:
474  case Instruction::SRem:
475  case Instruction::UDiv:
476  case Instruction::URem:
477  // FIXME: Unlikely to be true for CodeSize.
478  return TTI::TCC_Expensive;
479  }
480  return 1;
481  }
482 
484  ArrayRef<int> Mask, int Index,
485  VectorType *SubTp) const {
486  return 1;
487  }
488 
489  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
492  const Instruction *I) const {
493  switch (Opcode) {
494  default:
495  break;
496  case Instruction::IntToPtr: {
497  unsigned SrcSize = Src->getScalarSizeInBits();
498  if (DL.isLegalInteger(SrcSize) &&
499  SrcSize <= DL.getPointerTypeSizeInBits(Dst))
500  return 0;
501  break;
502  }
503  case Instruction::PtrToInt: {
504  unsigned DstSize = Dst->getScalarSizeInBits();
505  if (DL.isLegalInteger(DstSize) &&
506  DstSize >= DL.getPointerTypeSizeInBits(Src))
507  return 0;
508  break;
509  }
510  case Instruction::BitCast:
511  if (Dst == Src || (Dst->isPointerTy() && Src->isPointerTy()))
512  // Identity and pointer-to-pointer casts are free.
513  return 0;
514  break;
515  case Instruction::Trunc: {
516  // trunc to a native type is free (assuming the target has compare and
517  // shift-right of the same width).
518  TypeSize DstSize = DL.getTypeSizeInBits(Dst);
519  if (!DstSize.isScalable() && DL.isLegalInteger(DstSize.getFixedSize()))
520  return 0;
521  break;
522  }
523  }
524  return 1;
525  }
526 
528  VectorType *VecTy,
529  unsigned Index) const {
530  return 1;
531  }
532 
534  const Instruction *I = nullptr) const {
535  // A phi would be free, unless we're costing the throughput because it
536  // will require a register.
537  if (Opcode == Instruction::PHI && CostKind != TTI::TCK_RecipThroughput)
538  return 0;
539  return 1;
540  }
541 
542  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
543  CmpInst::Predicate VecPred,
545  const Instruction *I) const {
546  return 1;
547  }
548 
549  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
550  unsigned Index) const {
551  return 1;
552  }
553 
554  unsigned getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF,
555  const APInt &DemandedDstElts,
557  return 1;
558  }
559 
560  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
561  unsigned AddressSpace,
563  const Instruction *I) const {
564  return 1;
565  }
566 
568  Align Alignment, unsigned AddressSpace,
570  return 1;
571  }
572 
573  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
574  const Value *Ptr, bool VariableMask,
575  Align Alignment,
577  const Instruction *I = nullptr) const {
578  return 1;
579  }
580 
582  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
583  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
584  bool UseMaskForCond, bool UseMaskForGaps) const {
585  return 1;
586  }
587 
590  switch (ICA.getID()) {
591  default:
592  break;
593  case Intrinsic::annotation:
594  case Intrinsic::assume:
595  case Intrinsic::sideeffect:
596  case Intrinsic::pseudoprobe:
597  case Intrinsic::arithmetic_fence:
598  case Intrinsic::dbg_declare:
599  case Intrinsic::dbg_value:
600  case Intrinsic::dbg_label:
601  case Intrinsic::invariant_start:
602  case Intrinsic::invariant_end:
603  case Intrinsic::launder_invariant_group:
604  case Intrinsic::strip_invariant_group:
605  case Intrinsic::is_constant:
606  case Intrinsic::lifetime_start:
607  case Intrinsic::lifetime_end:
608  case Intrinsic::experimental_noalias_scope_decl:
609  case Intrinsic::objectsize:
610  case Intrinsic::ptr_annotation:
611  case Intrinsic::var_annotation:
612  case Intrinsic::experimental_gc_result:
613  case Intrinsic::experimental_gc_relocate:
614  case Intrinsic::coro_alloc:
615  case Intrinsic::coro_begin:
616  case Intrinsic::coro_free:
617  case Intrinsic::coro_end:
618  case Intrinsic::coro_frame:
619  case Intrinsic::coro_size:
620  case Intrinsic::coro_suspend:
621  case Intrinsic::coro_param:
622  case Intrinsic::coro_subfn_addr:
623  // These intrinsics don't actually represent code after lowering.
624  return 0;
625  }
626  return 1;
627  }
628 
630  ArrayRef<Type *> Tys,
632  return 1;
633  }
634 
635  // Assume that we have a register of the right size for the type.
636  unsigned getNumberOfParts(Type *Tp) const { return 1; }
637 
639  const SCEV *) const {
640  return 0;
641  }
642 
645  TTI::TargetCostKind) const {
646  return 1;
647  }
648 
650  TTI::TargetCostKind) const {
651  return 1;
652  }
653 
655  getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned, Type *ResTy,
656  VectorType *Ty,
658  return 1;
659  }
660 
662  return 0;
663  }
664 
666  return false;
667  }
668 
670  // Note for overrides: You must ensure for all element unordered-atomic
671  // memory intrinsics that all power-of-2 element sizes up to, and
672  // including, the return value of this method have a corresponding
673  // runtime lib call. These runtime lib call definitions can be found
674  // in RuntimeLibcalls.h
675  return 0;
676  }
677 
679  Type *ExpectedType) const {
680  return nullptr;
681  }
682 
684  unsigned SrcAddrSpace, unsigned DestAddrSpace,
685  unsigned SrcAlign, unsigned DestAlign) const {
686  return Type::getInt8Ty(Context);
687  }
688 
691  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
692  unsigned SrcAlign, unsigned DestAlign) const {
693  for (unsigned i = 0; i != RemainingBytes; ++i)
694  OpsOut.push_back(Type::getInt8Ty(Context));
695  }
696 
697  bool areInlineCompatible(const Function *Caller,
698  const Function *Callee) const {
699  return (Caller->getFnAttribute("target-cpu") ==
700  Callee->getFnAttribute("target-cpu")) &&
701  (Caller->getFnAttribute("target-features") ==
702  Callee->getFnAttribute("target-features"));
703  }
704 
706  const Function *Callee,
708  return (Caller->getFnAttribute("target-cpu") ==
709  Callee->getFnAttribute("target-cpu")) &&
710  (Caller->getFnAttribute("target-features") ==
711  Callee->getFnAttribute("target-features"));
712  }
713 
715  const DataLayout &DL) const {
716  return false;
717  }
718 
720  const DataLayout &DL) const {
721  return false;
722  }
723 
724  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; }
725 
726  bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; }
727 
728  bool isLegalToVectorizeStore(StoreInst *SI) const { return true; }
729 
730  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
731  unsigned AddrSpace) const {
732  return true;
733  }
734 
735  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
736  unsigned AddrSpace) const {
737  return true;
738  }
739 
741  ElementCount VF) const {
742  return true;
743  }
744 
745  bool isElementTypeLegalForScalableVector(Type *Ty) const { return true; }
746 
747  unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
748  unsigned ChainSizeInBytes,
749  VectorType *VecTy) const {
750  return VF;
751  }
752 
753  unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
754  unsigned ChainSizeInBytes,
755  VectorType *VecTy) const {
756  return VF;
757  }
758 
759  bool preferInLoopReduction(unsigned Opcode, Type *Ty,
760  TTI::ReductionFlags Flags) const {
761  return false;
762  }
763 
764  bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
765  TTI::ReductionFlags Flags) const {
766  return false;
767  }
768 
769  bool shouldExpandReduction(const IntrinsicInst *II) const { return true; }
770 
771  unsigned getGISelRematGlobalCost() const { return 1; }
772 
773  bool supportsScalableVectors() const { return false; }
774 
775  bool hasActiveVectorLength() const { return false; }
776 
780  /* EVLParamStrategy */ TargetTransformInfo::VPLegalization::Discard,
781  /* OperatorStrategy */ TargetTransformInfo::VPLegalization::Convert);
782  }
783 
784 protected:
785  // Obtain the minimum required size to hold the value (without the sign)
786  // In case of a vector it returns the min required size for one element.
787  unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const {
788  if (isa<ConstantDataVector>(Val) || isa<ConstantVector>(Val)) {
789  const auto *VectorValue = cast<Constant>(Val);
790 
791  // In case of a vector need to pick the max between the min
792  // required size for each element
793  auto *VT = cast<FixedVectorType>(Val->getType());
794 
795  // Assume unsigned elements
796  isSigned = false;
797 
798  // The max required size is the size of the vector element type
799  unsigned MaxRequiredSize =
800  VT->getElementType()->getPrimitiveSizeInBits().getFixedSize();
801 
802  unsigned MinRequiredSize = 0;
803  for (unsigned i = 0, e = VT->getNumElements(); i < e; ++i) {
804  if (auto *IntElement =
805  dyn_cast<ConstantInt>(VectorValue->getAggregateElement(i))) {
806  bool signedElement = IntElement->getValue().isNegative();
807  // Get the element min required size.
808  unsigned ElementMinRequiredSize =
809  IntElement->getValue().getMinSignedBits() - 1;
810  // In case one element is signed then all the vector is signed.
811  isSigned |= signedElement;
812  // Save the max required bit size between all the elements.
813  MinRequiredSize = std::max(MinRequiredSize, ElementMinRequiredSize);
814  } else {
815  // not an int constant element
816  return MaxRequiredSize;
817  }
818  }
819  return MinRequiredSize;
820  }
821 
822  if (const auto *CI = dyn_cast<ConstantInt>(Val)) {
823  isSigned = CI->getValue().isNegative();
824  return CI->getValue().getMinSignedBits() - 1;
825  }
826 
827  if (const auto *Cast = dyn_cast<SExtInst>(Val)) {
828  isSigned = true;
829  return Cast->getSrcTy()->getScalarSizeInBits() - 1;
830  }
831 
832  if (const auto *Cast = dyn_cast<ZExtInst>(Val)) {
833  isSigned = false;
834  return Cast->getSrcTy()->getScalarSizeInBits();
835  }
836 
837  isSigned = false;
838  return Val->getType()->getScalarSizeInBits();
839  }
840 
841  bool isStridedAccess(const SCEV *Ptr) const {
842  return Ptr && isa<SCEVAddRecExpr>(Ptr);
843  }
844 
846  const SCEV *Ptr) const {
847  if (!isStridedAccess(Ptr))
848  return nullptr;
849  const SCEVAddRecExpr *AddRec = cast<SCEVAddRecExpr>(Ptr);
850  return dyn_cast<SCEVConstant>(AddRec->getStepRecurrence(*SE));
851  }
852 
854  int64_t MergeDistance) const {
855  const SCEVConstant *Step = getConstantStrideStep(SE, Ptr);
856  if (!Step)
857  return false;
858  APInt StrideVal = Step->getAPInt();
859  if (StrideVal.getBitWidth() > 64)
860  return false;
861  // FIXME: Need to take absolute value for negative stride case.
862  return StrideVal.getSExtValue() < MergeDistance;
863  }
864 };
865 
866 /// CRTP base class for use as a mix-in that aids implementing
867 /// a TargetTransformInfo-compatible class.
868 template <typename T>
870 private:
872 
873 protected:
875 
876 public:
877  using BaseT::getGEPCost;
878 
879  InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr,
882  assert(PointeeType && Ptr && "can't get GEPCost of nullptr");
883  assert(cast<PointerType>(Ptr->getType()->getScalarType())
884  ->isOpaqueOrPointeeTypeMatches(PointeeType) &&
885  "explicit pointee type doesn't match operand's pointee type");
886  auto *BaseGV = dyn_cast<GlobalValue>(Ptr->stripPointerCasts());
887  bool HasBaseReg = (BaseGV == nullptr);
888 
889  auto PtrSizeBits = DL.getPointerTypeSizeInBits(Ptr->getType());
890  APInt BaseOffset(PtrSizeBits, 0);
891  int64_t Scale = 0;
892 
893  auto GTI = gep_type_begin(PointeeType, Operands);
894  Type *TargetType = nullptr;
895 
896  // Handle the case where the GEP instruction has a single operand,
897  // the basis, therefore TargetType is a nullptr.
898  if (Operands.empty())
899  return !BaseGV ? TTI::TCC_Free : TTI::TCC_Basic;
900 
901  for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
902  TargetType = GTI.getIndexedType();
903  // We assume that the cost of Scalar GEP with constant index and the
904  // cost of Vector GEP with splat constant index are the same.
905  const ConstantInt *ConstIdx = dyn_cast<ConstantInt>(*I);
906  if (!ConstIdx)
907  if (auto Splat = getSplatValue(*I))
908  ConstIdx = dyn_cast<ConstantInt>(Splat);
909  if (StructType *STy = GTI.getStructTypeOrNull()) {
910  // For structures the index is always splat or scalar constant
911  assert(ConstIdx && "Unexpected GEP index");
912  uint64_t Field = ConstIdx->getZExtValue();
913  BaseOffset += DL.getStructLayout(STy)->getElementOffset(Field);
914  } else {
915  // If this operand is a scalable type, bail out early.
916  // TODO: handle scalable vectors
917  if (isa<ScalableVectorType>(TargetType))
918  return TTI::TCC_Basic;
919  int64_t ElementSize =
920  DL.getTypeAllocSize(GTI.getIndexedType()).getFixedSize();
921  if (ConstIdx) {
922  BaseOffset +=
923  ConstIdx->getValue().sextOrTrunc(PtrSizeBits) * ElementSize;
924  } else {
925  // Needs scale register.
926  if (Scale != 0)
927  // No addressing mode takes two scale registers.
928  return TTI::TCC_Basic;
929  Scale = ElementSize;
930  }
931  }
932  }
933 
934  if (static_cast<T *>(this)->isLegalAddressingMode(
935  TargetType, const_cast<GlobalValue *>(BaseGV),
936  BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale,
937  Ptr->getType()->getPointerAddressSpace()))
938  return TTI::TCC_Free;
939  return TTI::TCC_Basic;
940  }
941 
944  auto *TargetTTI = static_cast<T *>(this);
945  // Handle non-intrinsic calls, invokes, and callbr.
946  // FIXME: Unlikely to be true for anything but CodeSize.
947  auto *CB = dyn_cast<CallBase>(U);
948  if (CB && !isa<IntrinsicInst>(U)) {
949  if (const Function *F = CB->getCalledFunction()) {
950  if (!TargetTTI->isLoweredToCall(F))
951  return TTI::TCC_Basic; // Give a basic cost if it will be lowered
952 
953  return TTI::TCC_Basic * (F->getFunctionType()->getNumParams() + 1);
954  }
955  // For indirect or other calls, scale cost by number of arguments.
956  return TTI::TCC_Basic * (CB->arg_size() + 1);
957  }
958 
959  Type *Ty = U->getType();
960  Type *OpTy =
961  U->getNumOperands() == 1 ? U->getOperand(0)->getType() : nullptr;
962  unsigned Opcode = Operator::getOpcode(U);
963  auto *I = dyn_cast<Instruction>(U);
964  switch (Opcode) {
965  default:
966  break;
967  case Instruction::Call: {
968  assert(isa<IntrinsicInst>(U) && "Unexpected non-intrinsic call");
969  auto *Intrinsic = cast<IntrinsicInst>(U);
970  IntrinsicCostAttributes CostAttrs(Intrinsic->getIntrinsicID(), *CB);
971  return TargetTTI->getIntrinsicInstrCost(CostAttrs, CostKind);
972  }
973  case Instruction::Br:
974  case Instruction::Ret:
975  case Instruction::PHI:
976  case Instruction::Switch:
977  return TargetTTI->getCFInstrCost(Opcode, CostKind, I);
978  case Instruction::ExtractValue:
979  case Instruction::Freeze:
980  return TTI::TCC_Free;
981  case Instruction::Alloca:
982  if (cast<AllocaInst>(U)->isStaticAlloca())
983  return TTI::TCC_Free;
984  break;
985  case Instruction::GetElementPtr: {
986  const auto *GEP = cast<GEPOperator>(U);
987  return TargetTTI->getGEPCost(GEP->getSourceElementType(),
988  GEP->getPointerOperand(),
989  Operands.drop_front(), CostKind);
990  }
991  case Instruction::Add:
992  case Instruction::FAdd:
993  case Instruction::Sub:
994  case Instruction::FSub:
995  case Instruction::Mul:
996  case Instruction::FMul:
997  case Instruction::UDiv:
998  case Instruction::SDiv:
999  case Instruction::FDiv:
1000  case Instruction::URem:
1001  case Instruction::SRem:
1002  case Instruction::FRem:
1003  case Instruction::Shl:
1004  case Instruction::LShr:
1005  case Instruction::AShr:
1006  case Instruction::And:
1007  case Instruction::Or:
1008  case Instruction::Xor:
1009  case Instruction::FNeg: {
1012  TTI::OperandValueKind Op1VK =
1013  TTI::getOperandInfo(U->getOperand(0), Op1VP);
1014  TTI::OperandValueKind Op2VK = Opcode != Instruction::FNeg ?
1017  return TargetTTI->getArithmeticInstrCost(Opcode, Ty, CostKind,
1018  Op1VK, Op2VK,
1019  Op1VP, Op2VP, Operands, I);
1020  }
1021  case Instruction::IntToPtr:
1022  case Instruction::PtrToInt:
1023  case Instruction::SIToFP:
1024  case Instruction::UIToFP:
1025  case Instruction::FPToUI:
1026  case Instruction::FPToSI:
1027  case Instruction::Trunc:
1028  case Instruction::FPTrunc:
1029  case Instruction::BitCast:
1030  case Instruction::FPExt:
1031  case Instruction::SExt:
1032  case Instruction::ZExt:
1033  case Instruction::AddrSpaceCast:
1034  return TargetTTI->getCastInstrCost(
1035  Opcode, Ty, OpTy, TTI::getCastContextHint(I), CostKind, I);
1036  case Instruction::Store: {
1037  auto *SI = cast<StoreInst>(U);
1038  Type *ValTy = U->getOperand(0)->getType();
1039  return TargetTTI->getMemoryOpCost(Opcode, ValTy, SI->getAlign(),
1040  SI->getPointerAddressSpace(),
1041  CostKind, I);
1042  }
1043  case Instruction::Load: {
1044  auto *LI = cast<LoadInst>(U);
1045  return TargetTTI->getMemoryOpCost(Opcode, U->getType(), LI->getAlign(),
1046  LI->getPointerAddressSpace(),
1047  CostKind, I);
1048  }
1049  case Instruction::Select: {
1050  const Value *Op0, *Op1;
1051  if (match(U, m_LogicalAnd(m_Value(Op0), m_Value(Op1))) ||
1052  match(U, m_LogicalOr(m_Value(Op0), m_Value(Op1)))) {
1053  // select x, y, false --> x & y
1054  // select x, true, y --> x | y
1057  TTI::OperandValueKind Op1VK = TTI::getOperandInfo(Op0, Op1VP);
1058  TTI::OperandValueKind Op2VK = TTI::getOperandInfo(Op1, Op2VP);
1059  assert(Op0->getType()->getScalarSizeInBits() == 1 &&
1060  Op1->getType()->getScalarSizeInBits() == 1);
1061 
1063  return TargetTTI->getArithmeticInstrCost(
1064  match(U, m_LogicalOr()) ? Instruction::Or : Instruction::And, Ty,
1065  CostKind, Op1VK, Op2VK, Op1VP, Op2VP, Operands, I);
1066  }
1067  Type *CondTy = U->getOperand(0)->getType();
1068  return TargetTTI->getCmpSelInstrCost(Opcode, U->getType(), CondTy,
1070  CostKind, I);
1071  }
1072  case Instruction::ICmp:
1073  case Instruction::FCmp: {
1074  Type *ValTy = U->getOperand(0)->getType();
1075  // TODO: Also handle ICmp/FCmp constant expressions.
1076  return TargetTTI->getCmpSelInstrCost(Opcode, ValTy, U->getType(),
1077  I ? cast<CmpInst>(I)->getPredicate()
1079  CostKind, I);
1080  }
1081  case Instruction::InsertElement: {
1082  auto *IE = dyn_cast<InsertElementInst>(U);
1083  if (!IE)
1084  return TTI::TCC_Basic; // FIXME
1085  unsigned Idx = -1;
1086  if (auto *CI = dyn_cast<ConstantInt>(IE->getOperand(2)))
1087  if (CI->getValue().getActiveBits() <= 32)
1088  Idx = CI->getZExtValue();
1089  return TargetTTI->getVectorInstrCost(Opcode, Ty, Idx);
1090  }
1091  case Instruction::ShuffleVector: {
1092  auto *Shuffle = dyn_cast<ShuffleVectorInst>(U);
1093  if (!Shuffle)
1094  return TTI::TCC_Basic; // FIXME
1095 
1096  auto *VecTy = cast<VectorType>(U->getType());
1097  auto *VecSrcTy = cast<VectorType>(U->getOperand(0)->getType());
1098  int NumSubElts, SubIndex;
1099 
1100  if (Shuffle->changesLength()) {
1101  // Treat a 'subvector widening' as a free shuffle.
1102  if (Shuffle->increasesLength() && Shuffle->isIdentityWithPadding())
1103  return 0;
1104 
1105  if (Shuffle->isExtractSubvectorMask(SubIndex))
1106  return TargetTTI->getShuffleCost(TTI::SK_ExtractSubvector, VecSrcTy,
1107  Shuffle->getShuffleMask(), SubIndex,
1108  VecTy);
1109 
1110  if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1111  return TargetTTI->getShuffleCost(
1112  TTI::SK_InsertSubvector, VecTy, Shuffle->getShuffleMask(),
1113  SubIndex,
1114  FixedVectorType::get(VecTy->getScalarType(), NumSubElts));
1115 
1116  int ReplicationFactor, VF;
1117  if (Shuffle->isReplicationMask(ReplicationFactor, VF)) {
1118  APInt DemandedDstElts =
1119  APInt::getNullValue(Shuffle->getShuffleMask().size());
1120  for (auto I : enumerate(Shuffle->getShuffleMask())) {
1121  if (I.value() != UndefMaskElem)
1122  DemandedDstElts.setBit(I.index());
1123  }
1124  return TargetTTI->getReplicationShuffleCost(
1125  VecSrcTy->getElementType(), ReplicationFactor, VF,
1126  DemandedDstElts, CostKind);
1127  }
1128 
1129  return CostKind == TTI::TCK_RecipThroughput ? -1 : 1;
1130  }
1131 
1132  if (Shuffle->isIdentity())
1133  return 0;
1134 
1135  if (Shuffle->isReverse())
1136  return TargetTTI->getShuffleCost(TTI::SK_Reverse, VecTy,
1137  Shuffle->getShuffleMask(), 0, nullptr);
1138 
1139  if (Shuffle->isSelect())
1140  return TargetTTI->getShuffleCost(TTI::SK_Select, VecTy,
1141  Shuffle->getShuffleMask(), 0, nullptr);
1142 
1143  if (Shuffle->isTranspose())
1144  return TargetTTI->getShuffleCost(TTI::SK_Transpose, VecTy,
1145  Shuffle->getShuffleMask(), 0, nullptr);
1146 
1147  if (Shuffle->isZeroEltSplat())
1148  return TargetTTI->getShuffleCost(TTI::SK_Broadcast, VecTy,
1149  Shuffle->getShuffleMask(), 0, nullptr);
1150 
1151  if (Shuffle->isSingleSource())
1152  return TargetTTI->getShuffleCost(TTI::SK_PermuteSingleSrc, VecTy,
1153  Shuffle->getShuffleMask(), 0, nullptr);
1154 
1155  if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1156  return TargetTTI->getShuffleCost(
1157  TTI::SK_InsertSubvector, VecTy, Shuffle->getShuffleMask(), SubIndex,
1158  FixedVectorType::get(VecTy->getScalarType(), NumSubElts));
1159 
1160  return TargetTTI->getShuffleCost(TTI::SK_PermuteTwoSrc, VecTy,
1161  Shuffle->getShuffleMask(), 0, nullptr);
1162  }
1163  case Instruction::ExtractElement: {
1164  auto *EEI = dyn_cast<ExtractElementInst>(U);
1165  if (!EEI)
1166  return TTI::TCC_Basic; // FIXME
1167  unsigned Idx = -1;
1168  if (auto *CI = dyn_cast<ConstantInt>(EEI->getOperand(1)))
1169  if (CI->getValue().getActiveBits() <= 32)
1170  Idx = CI->getZExtValue();
1171  Type *DstTy = U->getOperand(0)->getType();
1172  return TargetTTI->getVectorInstrCost(Opcode, DstTy, Idx);
1173  }
1174  }
1175  // By default, just classify everything as 'basic'.
1176  return TTI::TCC_Basic;
1177  }
1178 
1180  SmallVector<const Value *, 4> Operands(I->operand_values());
1181  if (getUserCost(I, Operands, TTI::TCK_Latency) == TTI::TCC_Free)
1182  return 0;
1183 
1184  if (isa<LoadInst>(I))
1185  return 4;
1186 
1187  Type *DstTy = I->getType();
1188 
1189  // Usually an intrinsic is a simple instruction.
1190  // A real function call is much slower.
1191  if (auto *CI = dyn_cast<CallInst>(I)) {
1192  const Function *F = CI->getCalledFunction();
1193  if (!F || static_cast<T *>(this)->isLoweredToCall(F))
1194  return 40;
1195  // Some intrinsics return a value and a flag, we use the value type
1196  // to decide its latency.
1197  if (StructType *StructTy = dyn_cast<StructType>(DstTy))
1198  DstTy = StructTy->getElementType(0);
1199  // Fall through to simple instructions.
1200  }
1201 
1202  if (VectorType *VectorTy = dyn_cast<VectorType>(DstTy))
1203  DstTy = VectorTy->getElementType();
1204  if (DstTy->isFloatingPointTy())
1205  return 3;
1206 
1207  return 1;
1208  }
1209 };
1210 } // namespace llvm
1211 
1212 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::CacheLevel::L1D
@ L1D
llvm::orc::BaseT
RTTIExtends< ObjectLinkingLayer, ObjectLayer > BaseT
Definition: ObjectLinkingLayer.cpp:617
llvm::TargetTransformInfoImplBase::canHaveNonUndefGlobalInitializerInAddressSpace
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Definition: TargetTransformInfoImpl.h:108
llvm::TargetTransformInfoImplBase::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfoImpl.h:424
llvm::TargetTransformInfo::SK_Select
@ SK_Select
Selects elements from the corresponding lane of either source operand.
Definition: TargetTransformInfo.h:866
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:212
llvm::TargetTransformInfoImplBase::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Definition: TargetTransformInfoImpl.h:160
llvm::TargetTransformInfo::LSRCost::NumRegs
unsigned NumRegs
Definition: TargetTransformInfo.h:422
llvm::TargetTransformInfo::TCC_Expensive
@ TCC_Expensive
The cost of a 'div' instruction on x86.
Definition: TargetTransformInfo.h:265
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1355
llvm::TargetTransformInfoImplBase::useAA
bool useAA() const
Definition: TargetTransformInfoImpl.h:301
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetTransformInfoImplBase::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI) const
Definition: TargetTransformInfoImpl.h:166
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1303
llvm::TargetTransformInfo::TCK_Latency
@ TCK_Latency
The latency of instruction.
Definition: TargetTransformInfo.h:214
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:721
llvm::TargetTransformInfoImplBase::enableOrderedReductions
bool enableOrderedReductions() const
Definition: TargetTransformInfoImpl.h:274
llvm::TargetTransformInfoImplBase::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfoImpl.h:112
llvm::TargetTransformInfoImplBase::isStridedAccess
bool isStridedAccess(const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:841
IntrinsicInst.h
llvm::ElementCount
Definition: TypeSize.h:385
llvm::TargetTransformInfoImplBase::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfoImpl.h:407
llvm::TypeSize::getFixedSize
ScalarTy getFixedSize() const
Definition: TypeSize.h:425
T
llvm::Function
Definition: Function.h:62
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::TargetTransformInfoImplBase::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:206
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:596
llvm::TargetTransformInfoImplCRTPBase::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:942
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
GetElementPtrTypeIterator.h
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:308
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:133
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::enumerate
detail::enumerator< R > enumerate(R &&TheRange)
Given an input range, returns a new range whose values are are pair (A,B) such that A is the 0-based ...
Definition: STLExtras.h:2006
llvm::TargetTransformInfoImplBase::isLSRCostLess
bool isLSRCostLess(TTI::LSRCost &C1, TTI::LSRCost &C2) const
Definition: TargetTransformInfoImpl.h:216
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1474
llvm::TargetTransformInfoImplBase::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Definition: TargetTransformInfoImpl.h:272
llvm::TargetTransformInfoImplBase::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *, const SCEV *) const
Definition: TargetTransformInfoImpl.h:638
llvm::TargetTransformInfoImplBase::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Definition: TargetTransformInfoImpl.h:100
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:366
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:169
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:734
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:460
llvm::TargetTransformInfoImplBase::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfoImpl.h:405
llvm::TargetTransformInfoImplBase::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfoImpl.h:76
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:151
llvm::TargetTransformInfoImplBase::TTI
TargetTransformInfo TTI
Definition: TargetTransformInfoImpl.h:37
llvm::TargetTransformInfoImplBase::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:284
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1398
llvm::TargetTransformInfo::LSRCost::NumIVMuls
unsigned NumIVMuls
Definition: TargetTransformInfo.h:424
llvm::TargetTransformInfoImplBase::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:390
llvm::TargetTransformInfoImplBase::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:724
llvm::TargetTransformInfoImplBase::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Definition: TargetTransformInfoImpl.h:349
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1410
llvm::TargetTransformInfo::VPLegalization::Convert
@ Convert
Definition: TargetTransformInfo.h:1405
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:539
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfoImpl.h:728
llvm::TargetTransformInfoImplBase::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Definition: TargetTransformInfoImpl.h:299
llvm::Optional
Definition: APInt.h:33
Operator.h
llvm::TargetTransformInfoImplBase::areFunctionArgsABICompatible
bool areFunctionArgsABICompatible(const Function *Caller, const Function *Callee, SmallPtrSetImpl< Argument * > &Args) const
Definition: TargetTransformInfoImpl.h:705
llvm::TargetTransformInfoImplBase::hasActiveVectorLength
bool hasActiveVectorLength() const
Definition: TargetTransformInfoImpl.h:775
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::TargetTransformInfoImplBase::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Definition: TargetTransformInfoImpl.h:94
llvm::TargetTransformInfoImplBase::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:366
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:41
llvm::TargetTransformInfoImplCRTPBase::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:879
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::gep_type_begin
gep_type_iterator gep_type_begin(const User *GEP)
Definition: GetElementPtrTypeIterator.h:139
llvm::TargetTransformInfoImplBase::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *, VectorType *, bool, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:649
llvm::Type::isFloatingPointTy
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:162
llvm::TargetTransformInfoImplBase::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:266
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetTransformInfo::SK_PermuteSingleSrc
@ SK_PermuteSingleSrc
Shuffle elements of single source vector with any shuffle mask.
Definition: TargetTransformInfo.h:874
llvm::TargetTransformInfoImplBase::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Definition: TargetTransformInfoImpl.h:353
llvm::Type::getInt8Ty
static IntegerType * getInt8Ty(LLVMContext &C)
Definition: Type.cpp:239
llvm::TargetTransformInfoImplBase::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:337
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:298
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:955
llvm::TargetTransformInfoImplBase::getConstantStrideStep
const SCEVConstant * getConstantStrideStep(ScalarEvolution *SE, const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:845
llvm::TargetTransformInfoImplBase::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Definition: TargetTransformInfoImpl.h:102
llvm::TargetTransformInfo::SK_Broadcast
@ SK_Broadcast
Broadcast element 0 to all other elements.
Definition: TargetTransformInfo.h:864
F
#define F(x, y, z)
Definition: MD5.cpp:56
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
llvm::TargetTransformInfo::LSRCost::AddRecCost
unsigned AddRecCost
Definition: TargetTransformInfo.h:423
llvm::TargetTransformInfoImplBase::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Definition: TargetTransformInfoImpl.h:297
llvm::UndefMaskElem
constexpr int UndefMaskElem
Definition: Instructions.h:2009
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:49
llvm::TargetTransformInfoImplBase::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfoImpl.h:697
llvm::TargetTransformInfoImplBase::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfoImpl.h:412
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::TargetTransformInfo::LSRCost::SetupCost
unsigned SetupCost
Definition: TargetTransformInfo.h:427
llvm::TargetTransformInfoImplBase::getExtendedAddReductionCost
InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:655
llvm::TargetTransformInfoImplBase::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Definition: TargetTransformInfoImpl.h:223
llvm::TargetTransformInfoImplBase::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: TargetTransformInfoImpl.h:740
llvm::TargetTransformInfoImplBase::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
Definition: TargetTransformInfoImpl.h:88
llvm::TargetTransformInfoImplBase::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, bool *Fast) const
Definition: TargetTransformInfoImpl.h:343
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::TargetTransformInfoImplBase::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Definition: TargetTransformInfoImpl.h:276
llvm::TargetTransformInfo::SK_PermuteTwoSrc
@ SK_PermuteTwoSrc
Merge elements from two source vectors into one with any shuffle mask.
Definition: TargetTransformInfo.h:872
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::LinearPolySize< ElementCount >::get
static ElementCount get(ScalarTy MinVal, bool Scalable)
Definition: TypeSize.h:289
llvm::TargetTransformInfoImplBase::getReplicationShuffleCost
unsigned getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:554
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:746
llvm::TargetTransformInfoImplBase::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfoImpl.h:458
llvm::APInt::setBit
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
Definition: APInt.h:1279
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg)
Definition: TargetTransformInfoImpl.h:47
llvm::TargetTransformInfoImplBase
Base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:35
llvm::TargetTransformInfoImplBase::getCacheAssociativity
llvm::Optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:438
llvm::PatternMatch::match
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
llvm::TargetTransformInfoImplBase::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfoImpl.h:449
llvm::TargetTransformInfoImplBase::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:384
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:890
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:863
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1069
llvm::TargetTransformInfoImplBase::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:240
llvm::User
Definition: User.h:44
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetTransformInfoImplBase::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Definition: TargetTransformInfoImpl.h:309
llvm::TargetTransformInfoImplBase::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const
Definition: TargetTransformInfoImpl.h:549
llvm::TargetTransformInfoImplBase::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfoImpl.h:683
llvm::TargetTransformInfoImplBase::hasBranchDivergence
bool hasBranchDivergence() const
Definition: TargetTransformInfoImpl.h:92
llvm::TargetTransformInfoImplBase::isIndexedStoreLegal
bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:719
llvm::TargetTransformInfoImplBase::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Definition: TargetTransformInfoImpl.h:307
llvm::Instruction
Definition: Instruction.h:45
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:191
llvm::TargetTransformInfoImplBase::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfoImpl.h:636
llvm::TargetTransformInfoImplBase::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
Definition: TargetTransformInfoImpl.h:371
llvm::Operator::getOpcode
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
Definition: Operator.h:41
llvm::TargetTransformInfoImplBase::isTypeLegal
bool isTypeLegal(Type *Ty) const
Definition: TargetTransformInfoImpl.h:303
llvm::TargetTransformInfoImplBase::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:208
llvm::TargetTransformInfoImplBase::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:533
llvm::TargetTransformInfoImplBase::getRegUsageForType
InstructionCost getRegUsageForType(Type *Ty) const
Definition: TargetTransformInfoImpl.h:305
llvm::TargetTransformInfoImplBase::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfoImpl.h:678
llvm::TargetTransformInfoImplCRTPBase
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:869
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetTransformInfoImplBase::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:278
llvm::TargetTransformInfoImplBase::getPredicatedAddrSpace
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
Definition: TargetTransformInfoImpl.h:115
PatternMatch.h
llvm::TargetTransformInfoImplBase::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:661
llvm::TargetTransformInfoImplBase::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfoImpl.h:456
llvm::FixedVectorType::get
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
Definition: Type.cpp:686
llvm::TargetTransformInfoImplBase::enableMemCmpExpansion
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfoImpl.h:332
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:153
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::TargetTransformInfoImplBase::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Definition: TargetTransformInfoImpl.h:96
llvm::TargetTransformInfoImplBase::getVPLegalizationStrategy
TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: TargetTransformInfoImpl.h:778
llvm::TargetTransformInfoImplBase::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:567
llvm::None
const NoneType None
Definition: None.h:23
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
Type.h
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:119
llvm::TargetTransformInfoImplBase::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:573
llvm::TargetTransformInfo::PSK_Software
@ PSK_Software
Definition: TargetTransformInfo.h:596
llvm::TargetTransformInfoImplBase::getCacheSize
llvm::Optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:427
llvm::TargetTransformInfoImplBase::emitGetActiveLaneMask
bool emitGetActiveLaneMask() const
Definition: TargetTransformInfoImpl.h:173
llvm::TargetTransformInfoImplBase::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfoImpl.h:225
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::ARM_PROC::IE
@ IE
Definition: ARMBaseInfo.h:27
llvm::TargetTransformInfoImplBase::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: TargetTransformInfoImpl.h:189
llvm::TargetTransformInfoImplBase::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:764
llvm::TargetTransformInfoImplBase::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfoImpl.h:773
llvm::TargetTransformInfoImplBase::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:339
llvm::TargetTransformInfo::SK_Reverse
@ SK_Reverse
Reverse the order of the vector.
Definition: TargetTransformInfo.h:865
llvm::TargetTransformInfoImplCRTPBase::TargetTransformInfoImplCRTPBase
TargetTransformInfoImplCRTPBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:874
llvm::TargetTransformInfoImplBase::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:629
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
VectorUtils.h
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:77
llvm::TargetTransformInfoImplBase::canMacroFuseCmp
bool canMacroFuseCmp() const
Definition: TargetTransformInfoImpl.h:227
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:304
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::TargetTransformInfo::SK_InsertSubvector
@ SK_InsertSubvector
InsertSubvector. Index indicates start offset.
Definition: TargetTransformInfo.h:870
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfoImplBase::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfoImpl.h:63
llvm::TargetTransformInfoImplBase::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:248
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::TargetTransformInfoImplBase::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth() const
Definition: TargetTransformInfoImpl.h:410
uint64_t
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:418
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:735
llvm::PatternMatch::m_LogicalOr
LogicalOp_match< LHS, RHS, Instruction::Or > m_LogicalOr(const LHS &L, const RHS &R)
Matches L || R either in the form of L | R or L ? true : R.
Definition: PatternMatch.h:2526
llvm::TargetTransformInfoImplBase::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned, VectorType *, Optional< FastMathFlags > FMF, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:643
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::TargetTransformInfoImplBase::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Definition: TargetTransformInfoImpl.h:183
llvm::TargetTransformInfoImplBase::getPreferredAddressingMode
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Definition: TargetTransformInfoImpl.h:236
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:432
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfoImplBase::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:489
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:890
llvm::LoopAccessInfo
Drive the analysis of memory accesses in the loop.
Definition: LoopAccessAnalysis.h:515
llvm::SCEVConstant
This class represents a constant integer value.
Definition: ScalarEvolutionExpressions.h:47
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetTransformInfo::VPLegalization::Discard
@ Discard
Definition: TargetTransformInfo.h:1403
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::TargetTransformInfoImplBase::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfoImpl.h:418
llvm::TargetTransformInfoImplBase::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Definition: TargetTransformInfoImpl.h:124
llvm::CmpInst::BAD_ICMP_PREDICATE
@ BAD_ICMP_PREDICATE
Definition: InstrTypes.h:754
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::TargetTransformInfo::LSRCost::ScaleCost
unsigned ScaleCost
Definition: TargetTransformInfo.h:428
llvm::TargetTransformInfoImplBase::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:321
llvm::TargetTransformInfoImplBase::getInterleavedMemoryOpCost
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) const
Definition: TargetTransformInfoImpl.h:581
llvm::TargetTransformInfoImplBase::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfoImpl.h:665
llvm::TargetTransformInfoImplBase::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Definition: TargetTransformInfoImpl.h:328
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:882
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::PatternMatch::m_Value
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:76
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfoImplBase::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned, unsigned) const
Definition: TargetTransformInfoImpl.h:107
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:765
llvm::TargetTransformInfoImplBase::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:255
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:263
llvm::TargetTransformInfoImplBase::isElementTypeLegalForScalableVector
bool isElementTypeLegalForScalableVector(Type *Ty) const
Definition: TargetTransformInfoImpl.h:745
llvm::TargetTransformInfoImplBase::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfoImpl.h:769
llvm::TargetTransformInfoImplBase::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfoImpl.h:73
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1083
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
DataLayout.h
llvm::StructType
Class to represent struct types.
Definition: DerivedTypes.h:213
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:42
llvm::TargetTransformInfoImplBase::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfoImpl.h:771
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::TargetTransformInfoImplCRTPBase::getInstructionLatency
InstructionCost getInstructionLatency(const Instruction *I)
Definition: TargetTransformInfoImpl.h:1179
llvm::TargetTransformInfoImplBase::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Definition: TargetTransformInfoImpl.h:295
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::TargetTransformInfoImplBase::getVScaleForTuning
Optional< unsigned > getVScaleForTuning() const
Definition: TargetTransformInfoImpl.h:408
llvm::TargetTransformInfoImplBase::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Definition: TargetTransformInfoImpl.h:315
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetTransformInfoImplBase::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
Definition: TargetTransformInfoImpl.h:326
llvm::TargetTransformInfoImplBase::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Definition: TargetTransformInfoImpl.h:355
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::TargetTransformInfoImplBase::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:542
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:643
llvm::TargetTransformInfoImplBase::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:244
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:431
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:883
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:286
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:175
llvm::TargetTransformInfo::SK_Transpose
@ SK_Transpose
Transpose two vectors.
Definition: TargetTransformInfo.h:869
llvm::TargetTransformInfoImplBase::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfoImpl.h:689
llvm::Value::stripPointerCasts
const Value * stripPointerCasts() const
Strip off pointer casts, all-zero GEPs and address space casts.
Definition: Value.cpp:685
llvm::TargetTransformInfo::CacheLevel::L2D
@ L2D
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:142
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:206
llvm::TargetTransformInfoImplBase::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr) const
Definition: TargetTransformInfoImpl.h:460
llvm::APInt::getNullValue
static APInt getNullValue(unsigned numBits)
NOTE: This is soft-deprecated. Please use getZero() instead.
Definition: APInt.h:180
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:162
llvm::TargetTransformInfoImplBase::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:759
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::KnownBits
Definition: KnownBits.h:23
llvm::TargetTransformInfoImplBase::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef< int > Mask, int Index, VectorType *SubTp) const
Definition: TargetTransformInfoImpl.h:483
llvm::TargetTransformInfo::LSRCost::NumBaseAdds
unsigned NumBaseAdds
Definition: TargetTransformInfo.h:425
llvm::TargetTransformInfoImplBase::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfoImpl.h:669
llvm::TargetTransformInfoImplBase::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfoImpl.h:455
llvm::TargetTransformInfoImplBase::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:378
llvm::TargetTransformInfoImplBase::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfoImpl.h:78
llvm::TargetTransformInfoImplBase::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Definition: TargetTransformInfoImpl.h:119
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:390
VPLegalization
TargetTransformInfo::VPLegalization VPLegalization
Definition: ExpandVectorPredication.cpp:36
llvm::APInt::sextOrTrunc
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:978
llvm::TargetTransformInfoImplBase::minRequiredElementSize
unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const
Definition: TargetTransformInfoImpl.h:787
llvm::TypeSize
Definition: TypeSize.h:416
llvm::SCEVAddRecExpr
This node represents a polynomial recurrence on the trip count of the specified loop.
Definition: ScalarEvolutionExpressions.h:352
Function.h
llvm::TargetTransformInfoImplBase::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:747
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::TargetTransformInfoImplBase::isIndexedLoadLegal
bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:714
llvm::TargetTransformInfoImplBase::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Definition: TargetTransformInfoImpl.h:450
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:221
llvm::User::operand_values
iterator_range< value_op_iterator > operand_values()
Definition: User.h:266
llvm::TargetTransformInfo::LSRCost::ImmCost
unsigned ImmCost
Definition: TargetTransformInfo.h:426
llvm::TargetTransformInfoImplBase::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:204
llvm::TargetTransformInfoImplBase::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:560
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:183
llvm::TargetTransformInfoImplBase::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfoImpl.h:386
llvm::TargetTransformInfoImplBase::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: TargetTransformInfoImpl.h:401
llvm::TargetTransformInfoImplBase::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Definition: TargetTransformInfoImpl.h:229
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfoImplBase::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: TargetTransformInfoImpl.h:177
llvm::SCEVConstant::getAPInt
const APInt & getAPInt() const
Definition: ScalarEvolutionExpressions.h:57
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:96
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::TargetTransformInfoImplBase::getUnrollingPreferences
void getUnrollingPreferences(Loop *, ScalarEvolution &, TTI::UnrollingPreferences &, OptimizationRemarkEmitter *) const
Definition: TargetTransformInfoImpl.h:197
llvm::TargetTransformInfoImplBase::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
Definition: TargetTransformInfoImpl.h:527
llvm::TargetTransformInfoImplBase::isConstantStridedAccessLessThan
bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
Definition: TargetTransformInfoImpl.h:853
llvm::TargetTransformInfoImplBase::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Definition: TargetTransformInfoImpl.h:341
ScalarEvolutionExpressions.h
llvm::TargetTransformInfoImplBase::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfoImpl.h:98
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:73
llvm::TargetTransformInfoImplBase::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Definition: TargetTransformInfoImpl.h:270
llvm::User::getNumOperands
unsigned getNumOperands() const
Definition: User.h:191
llvm::IntrinsicCostAttributes::getID
Intrinsic::ID getID() const
Definition: TargetTransformInfo.h:149
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:911
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfoImpl.h:726
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
TargetTransformInfo.h
llvm::PatternMatch
Definition: PatternMatch.h:47
llvm::SmallVectorImpl< int >
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:71
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1176
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
llvm::TargetTransformInfoImplBase::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:753
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:730
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:172
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(const TargetTransformInfoImplBase &Arg)
Definition: TargetTransformInfoImpl.h:45
llvm::TargetTransformInfoImplBase::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:262
llvm::TargetTransformInfo::getOperandInfo
static OperandValueKind getOperandInfo(const Value *V, OperandValueProperties &OpProps)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:674
llvm::TargetTransformInfo::TCC_Basic
@ TCC_Basic
The cost of a typical 'add' instruction.
Definition: TargetTransformInfo.h:264
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3245
llvm::OptimizedStructLayoutField
A field in a structure.
Definition: OptimizedStructLayout.h:45
llvm::TargetTransformInfoImplBase::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Definition: TargetTransformInfoImpl.h:311
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::TargetTransformInfoImplBase::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfoImpl.h:74
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3101
llvm::TargetTransformInfoImplBase::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:588
llvm::TargetTransformInfoImplBase::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Definition: TargetTransformInfoImpl.h:282
llvm::TargetTransformInfoImplBase::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Definition: TargetTransformInfoImpl.h:313
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:213
llvm::TargetTransformInfoImplBase::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
Definition: TargetTransformInfoImpl.h:361
llvm::TargetTransformInfo::AMK_None
@ AMK_None
Definition: TargetTransformInfo.h:646
llvm::TargetTransformInfo::SK_ExtractSubvector
@ SK_ExtractSubvector
ExtractSubvector Index indicates start offset.
Definition: TargetTransformInfo.h:871
llvm::PatternMatch::m_LogicalAnd
LogicalOp_match< LHS, RHS, Instruction::And > m_LogicalAnd(const LHS &L, const RHS &R)
Matches L && R either in the form of L & R or L ? R : false.
Definition: PatternMatch.h:2508
llvm::TargetTransformInfoImplBase::getPeelingPreferences
void getPeelingPreferences(Loop *, ScalarEvolution &, TTI::PeelingPreferences &) const
Definition: TargetTransformInfoImpl.h:201
llvm::SCEVAddRecExpr::getStepRecurrence
const SCEV * getStepRecurrence(ScalarEvolution &SE) const
Constructs and returns the recurrence indicating how much this expression steps by.
Definition: ScalarEvolutionExpressions.h:370
llvm::TargetTransformInfoImplBase::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfoImpl.h:416
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::TargetTransformInfoImplBase::getFPOpCost
InstructionCost getFPOpCost(Type *Ty) const
Definition: TargetTransformInfoImpl.h:357