LLVM  14.0.0git
TargetTransformInfoImpl.h
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1 //===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file provides helpers for the implementation of
10 /// a TargetTransformInfo-conforming class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
15 #define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
16 
20 #include "llvm/IR/DataLayout.h"
21 #include "llvm/IR/Function.h"
23 #include "llvm/IR/IntrinsicInst.h"
24 #include "llvm/IR/Operator.h"
25 #include "llvm/IR/PatternMatch.h"
26 #include "llvm/IR/Type.h"
27 
28 using namespace llvm::PatternMatch;
29 
30 namespace llvm {
31 
32 /// Base class for use as a mix-in that aids implementing
33 /// a TargetTransformInfo-compatible class.
35 protected:
37 
38  const DataLayout &DL;
39 
41 
42 public:
43  // Provide value semantics. MSVC requires that we spell all of these out.
45  : DL(Arg.DL) {}
47 
48  const DataLayout &getDataLayout() const { return DL; }
49 
51  getGEPCost(Type *PointeeType, const Value *Ptr,
54  // In the basic model, we just assume that all-constant GEPs will be folded
55  // into their uses via addressing modes.
56  for (unsigned Idx = 0, Size = Operands.size(); Idx != Size; ++Idx)
57  if (!isa<Constant>(Operands[Idx]))
58  return TTI::TCC_Basic;
59 
60  return TTI::TCC_Free;
61  }
62 
64  unsigned &JTSize,
65  ProfileSummaryInfo *PSI,
66  BlockFrequencyInfo *BFI) const {
67  (void)PSI;
68  (void)BFI;
69  JTSize = 0;
70  return SI.getNumCases();
71  }
72 
73  unsigned getInliningThresholdMultiplier() const { return 1; }
74  unsigned adjustInliningThreshold(const CallBase *CB) const { return 0; }
75 
76  int getInlinerVectorBonusPercent() const { return 150; }
77 
79  return TTI::TCC_Expensive;
80  }
81 
82  // Although this default value is arbitrary, it is not random. It is assumed
83  // that a condition that evaluates the same way by a higher percentage than
84  // this is best represented as control flow. Therefore, the default value N
85  // should be set such that the win from N% correct executions is greater than
86  // the loss from (100 - N)% mispredicted executions for the majority of
87  // intended targets.
89  return BranchProbability(99, 100);
90  }
91 
92  bool hasBranchDivergence() const { return false; }
93 
94  bool useGPUDivergenceAnalysis() const { return false; }
95 
96  bool isSourceOfDivergence(const Value *V) const { return false; }
97 
98  bool isAlwaysUniform(const Value *V) const { return false; }
99 
100  unsigned getFlatAddressSpace() const { return -1; }
101 
103  Intrinsic::ID IID) const {
104  return false;
105  }
106 
107  bool isNoopAddrSpaceCast(unsigned, unsigned) const { return false; }
109  return AS == 0;
110  };
111 
112  unsigned getAssumedAddrSpace(const Value *V) const { return -1; }
113 
115  Value *NewV) const {
116  return nullptr;
117  }
118 
119  bool isLoweredToCall(const Function *F) const {
120  assert(F && "A concrete function must be provided to this routine.");
121 
122  // FIXME: These should almost certainly not be handled here, and instead
123  // handled with the help of TLI or the target itself. This was largely
124  // ported from existing analysis heuristics here so that such refactorings
125  // can take place in the future.
126 
127  if (F->isIntrinsic())
128  return false;
129 
130  if (F->hasLocalLinkage() || !F->hasName())
131  return true;
132 
133  StringRef Name = F->getName();
134 
135  // These will all likely lower to a single selection DAG node.
136  if (Name == "copysign" || Name == "copysignf" || Name == "copysignl" ||
137  Name == "fabs" || Name == "fabsf" || Name == "fabsl" || Name == "sin" ||
138  Name == "fmin" || Name == "fminf" || Name == "fminl" ||
139  Name == "fmax" || Name == "fmaxf" || Name == "fmaxl" ||
140  Name == "sinf" || Name == "sinl" || Name == "cos" || Name == "cosf" ||
141  Name == "cosl" || Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl")
142  return false;
143 
144  // These are all likely to be optimized into something smaller.
145  if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" ||
146  Name == "exp2l" || Name == "exp2f" || Name == "floor" ||
147  Name == "floorf" || Name == "ceil" || Name == "round" ||
148  Name == "ffs" || Name == "ffsl" || Name == "abs" || Name == "labs" ||
149  Name == "llabs")
150  return false;
151 
152  return true;
153  }
154 
156  AssumptionCache &AC, TargetLibraryInfo *LibInfo,
157  HardwareLoopInfo &HWLoopInfo) const {
158  return false;
159  }
160 
163  DominatorTree *DT,
164  const LoopAccessInfo *LAI) const {
165  return false;
166  }
167 
168  bool emitGetActiveLaneMask() const {
169  return false;
170  }
171 
173  IntrinsicInst &II) const {
174  return None;
175  }
176 
179  APInt DemandedMask, KnownBits &Known,
180  bool &KnownBitsComputed) const {
181  return None;
182  }
183 
185  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
186  APInt &UndefElts2, APInt &UndefElts3,
187  std::function<void(Instruction *, unsigned, APInt, APInt &)>
188  SimplifyAndSetOp) const {
189  return None;
190  }
191 
194  OptimizationRemarkEmitter *) const {}
195 
197  TTI::PeelingPreferences &) const {}
198 
199  bool isLegalAddImmediate(int64_t Imm) const { return false; }
200 
201  bool isLegalICmpImmediate(int64_t Imm) const { return false; }
202 
203  bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
204  bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
205  Instruction *I = nullptr) const {
206  // Guess that only reg and reg+reg addressing is allowed. This heuristic is
207  // taken from the implementation of LSR.
208  return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
209  }
210 
212  return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
213  C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
214  std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
215  C2.ScaleCost, C2.ImmCost, C2.SetupCost);
216  }
217 
218  bool isNumRegsMajorCostOfLSR() const { return true; }
219 
220  bool isProfitableLSRChainElement(Instruction *I) const { return false; }
221 
222  bool canMacroFuseCmp() const { return false; }
223 
226  TargetLibraryInfo *LibInfo) const {
227  return false;
228  }
229 
232  return TTI::AMK_None;
233  }
234 
235  bool isLegalMaskedStore(Type *DataType, Align Alignment) const {
236  return false;
237  }
238 
239  bool isLegalMaskedLoad(Type *DataType, Align Alignment) const {
240  return false;
241  }
242 
243  bool isLegalNTStore(Type *DataType, Align Alignment) const {
244  // By default, assume nontemporal memory stores are available for stores
245  // that are aligned and have a size that is a power of 2.
246  unsigned DataSize = DL.getTypeStoreSize(DataType);
247  return Alignment >= DataSize && isPowerOf2_32(DataSize);
248  }
249 
250  bool isLegalNTLoad(Type *DataType, Align Alignment) const {
251  // By default, assume nontemporal memory loads are available for loads that
252  // are aligned and have a size that is a power of 2.
253  unsigned DataSize = DL.getTypeStoreSize(DataType);
254  return Alignment >= DataSize && isPowerOf2_32(DataSize);
255  }
256 
257  bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
258  return false;
259  }
260 
261  bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
262  return false;
263  }
264 
265  bool isLegalMaskedCompressStore(Type *DataType) const { return false; }
266 
267  bool isLegalMaskedExpandLoad(Type *DataType) const { return false; }
268 
269  bool enableOrderedReductions() const { return false; }
270 
271  bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; }
272 
273  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const {
274  return false;
275  }
276 
277  bool prefersVectorizedAddressing() const { return true; }
278 
280  int64_t BaseOffset, bool HasBaseReg,
281  int64_t Scale,
282  unsigned AddrSpace) const {
283  // Guess that all legal addressing mode are free.
284  if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
285  AddrSpace))
286  return 0;
287  return -1;
288  }
289 
290  bool LSRWithInstrQueries() const { return false; }
291 
292  bool isTruncateFree(Type *Ty1, Type *Ty2) const { return false; }
293 
294  bool isProfitableToHoist(Instruction *I) const { return true; }
295 
296  bool useAA() const { return false; }
297 
298  bool isTypeLegal(Type *Ty) const { return false; }
299 
300  InstructionCost getRegUsageForType(Type *Ty) const { return 1; }
301 
302  bool shouldBuildLookupTables() const { return true; }
303 
304  bool shouldBuildLookupTablesForConstant(Constant *C) const { return true; }
305 
306  bool shouldBuildRelLookupTables() const { return false; }
307 
308  bool useColdCCForColdCall(Function &F) const { return false; }
309 
311  const APInt &DemandedElts,
312  bool Insert, bool Extract) const {
313  return 0;
314  }
315 
317  ArrayRef<Type *> Tys) const {
318  return 0;
319  }
320 
321  bool supportsEfficientVectorElementLoadStore() const { return false; }
322 
323  bool enableAggressiveInterleaving(bool LoopHasReductions) const {
324  return false;
325  }
326 
328  bool IsZeroCmp) const {
329  return {};
330  }
331 
332  bool enableInterleavedAccessVectorization() const { return false; }
333 
334  bool enableMaskedInterleavedAccessVectorization() const { return false; }
335 
336  bool isFPVectorizationPotentiallyUnsafe() const { return false; }
337 
339  unsigned AddressSpace, Align Alignment,
340  bool *Fast) const {
341  return false;
342  }
343 
344  TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const {
345  return TTI::PSK_Software;
346  }
347 
348  bool haveFastSqrt(Type *Ty) const { return false; }
349 
350  bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; }
351 
354  }
355 
356  InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
357  const APInt &Imm, Type *Ty) const {
358  return 0;
359  }
360 
363  return TTI::TCC_Basic;
364  }
365 
366  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
367  const APInt &Imm, Type *Ty,
369  Instruction *Inst = nullptr) const {
370  return TTI::TCC_Free;
371  }
372 
374  const APInt &Imm, Type *Ty,
376  return TTI::TCC_Free;
377  }
378 
379  unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; }
380 
381  unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
382  return Vector ? 1 : 0;
383  };
384 
385  const char *getRegisterClassName(unsigned ClassID) const {
386  switch (ClassID) {
387  default:
388  return "Generic::Unknown Register Class";
389  case 0:
390  return "Generic::ScalarRC";
391  case 1:
392  return "Generic::VectorRC";
393  }
394  }
395 
397  return TypeSize::getFixed(32);
398  }
399 
400  unsigned getMinVectorRegisterBitWidth() const { return 128; }
401 
403 
404  bool shouldMaximizeVectorBandwidth() const { return false; }
405 
406  ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const {
407  return ElementCount::get(0, IsScalable);
408  }
409 
410  unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const { return 0; }
411 
413  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
414  AllowPromotionWithoutCommonHeader = false;
415  return false;
416  }
417 
418  unsigned getCacheLineSize() const { return 0; }
419 
422  switch (Level) {
426  return llvm::Optional<unsigned>();
427  }
428  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
429  }
430 
433  switch (Level) {
437  return llvm::Optional<unsigned>();
438  }
439 
440  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
441  }
442 
443  unsigned getPrefetchDistance() const { return 0; }
444  unsigned getMinPrefetchStride(unsigned NumMemAccesses,
445  unsigned NumStridedMemAccesses,
446  unsigned NumPrefetches, bool HasCall) const {
447  return 1;
448  }
449  unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; }
450  bool enableWritePrefetching() const { return false; }
451 
452  unsigned getMaxInterleaveFactor(unsigned VF) const { return 1; }
453 
455  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
456  TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info,
457  TTI::OperandValueProperties Opd1PropInfo,
459  const Instruction *CxtI = nullptr) const {
460  // FIXME: A number of transformation tests seem to require these values
461  // which seems a little odd for how arbitary there are.
462  switch (Opcode) {
463  default:
464  break;
465  case Instruction::FDiv:
466  case Instruction::FRem:
467  case Instruction::SDiv:
468  case Instruction::SRem:
469  case Instruction::UDiv:
470  case Instruction::URem:
471  // FIXME: Unlikely to be true for CodeSize.
472  return TTI::TCC_Expensive;
473  }
474  return 1;
475  }
476 
478  ArrayRef<int> Mask, int Index,
479  VectorType *SubTp) const {
480  return 1;
481  }
482 
483  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
486  const Instruction *I) const {
487  switch (Opcode) {
488  default:
489  break;
490  case Instruction::IntToPtr: {
491  unsigned SrcSize = Src->getScalarSizeInBits();
492  if (DL.isLegalInteger(SrcSize) &&
493  SrcSize <= DL.getPointerTypeSizeInBits(Dst))
494  return 0;
495  break;
496  }
497  case Instruction::PtrToInt: {
498  unsigned DstSize = Dst->getScalarSizeInBits();
499  if (DL.isLegalInteger(DstSize) &&
500  DstSize >= DL.getPointerTypeSizeInBits(Src))
501  return 0;
502  break;
503  }
504  case Instruction::BitCast:
505  if (Dst == Src || (Dst->isPointerTy() && Src->isPointerTy()))
506  // Identity and pointer-to-pointer casts are free.
507  return 0;
508  break;
509  case Instruction::Trunc: {
510  // trunc to a native type is free (assuming the target has compare and
511  // shift-right of the same width).
512  TypeSize DstSize = DL.getTypeSizeInBits(Dst);
513  if (!DstSize.isScalable() && DL.isLegalInteger(DstSize.getFixedSize()))
514  return 0;
515  break;
516  }
517  }
518  return 1;
519  }
520 
522  VectorType *VecTy,
523  unsigned Index) const {
524  return 1;
525  }
526 
528  const Instruction *I = nullptr) const {
529  // A phi would be free, unless we're costing the throughput because it
530  // will require a register.
531  if (Opcode == Instruction::PHI && CostKind != TTI::TCK_RecipThroughput)
532  return 0;
533  return 1;
534  }
535 
536  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
537  CmpInst::Predicate VecPred,
539  const Instruction *I) const {
540  return 1;
541  }
542 
543  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
544  unsigned Index) const {
545  return 1;
546  }
547 
548  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
549  unsigned AddressSpace,
551  const Instruction *I) const {
552  return 1;
553  }
554 
556  Align Alignment, unsigned AddressSpace,
558  return 1;
559  }
560 
561  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
562  const Value *Ptr, bool VariableMask,
563  Align Alignment,
565  const Instruction *I = nullptr) const {
566  return 1;
567  }
568 
570  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
571  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
572  bool UseMaskForCond, bool UseMaskForGaps) const {
573  return 1;
574  }
575 
578  switch (ICA.getID()) {
579  default:
580  break;
581  case Intrinsic::annotation:
582  case Intrinsic::assume:
583  case Intrinsic::sideeffect:
584  case Intrinsic::pseudoprobe:
585  case Intrinsic::arithmetic_fence:
586  case Intrinsic::dbg_declare:
587  case Intrinsic::dbg_value:
588  case Intrinsic::dbg_label:
589  case Intrinsic::invariant_start:
590  case Intrinsic::invariant_end:
591  case Intrinsic::launder_invariant_group:
592  case Intrinsic::strip_invariant_group:
593  case Intrinsic::is_constant:
594  case Intrinsic::lifetime_start:
595  case Intrinsic::lifetime_end:
596  case Intrinsic::experimental_noalias_scope_decl:
597  case Intrinsic::objectsize:
598  case Intrinsic::ptr_annotation:
599  case Intrinsic::var_annotation:
600  case Intrinsic::experimental_gc_result:
601  case Intrinsic::experimental_gc_relocate:
602  case Intrinsic::coro_alloc:
603  case Intrinsic::coro_begin:
604  case Intrinsic::coro_free:
605  case Intrinsic::coro_end:
606  case Intrinsic::coro_frame:
607  case Intrinsic::coro_size:
608  case Intrinsic::coro_suspend:
609  case Intrinsic::coro_param:
610  case Intrinsic::coro_subfn_addr:
611  // These intrinsics don't actually represent code after lowering.
612  return 0;
613  }
614  return 1;
615  }
616 
618  ArrayRef<Type *> Tys,
620  return 1;
621  }
622 
623  unsigned getNumberOfParts(Type *Tp) const { return 0; }
624 
626  const SCEV *) const {
627  return 0;
628  }
629 
632  TTI::TargetCostKind) const {
633  return 1;
634  }
635 
637  TTI::TargetCostKind) const {
638  return 1;
639  }
640 
642  bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty,
644  return 1;
645  }
646 
648  return 0;
649  }
650 
652  return false;
653  }
654 
656  // Note for overrides: You must ensure for all element unordered-atomic
657  // memory intrinsics that all power-of-2 element sizes up to, and
658  // including, the return value of this method have a corresponding
659  // runtime lib call. These runtime lib call definitions can be found
660  // in RuntimeLibcalls.h
661  return 0;
662  }
663 
665  Type *ExpectedType) const {
666  return nullptr;
667  }
668 
670  unsigned SrcAddrSpace, unsigned DestAddrSpace,
671  unsigned SrcAlign, unsigned DestAlign) const {
672  return Type::getInt8Ty(Context);
673  }
674 
677  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
678  unsigned SrcAlign, unsigned DestAlign) const {
679  for (unsigned i = 0; i != RemainingBytes; ++i)
680  OpsOut.push_back(Type::getInt8Ty(Context));
681  }
682 
683  bool areInlineCompatible(const Function *Caller,
684  const Function *Callee) const {
685  return (Caller->getFnAttribute("target-cpu") ==
686  Callee->getFnAttribute("target-cpu")) &&
687  (Caller->getFnAttribute("target-features") ==
688  Callee->getFnAttribute("target-features"));
689  }
690 
692  const Function *Callee,
694  return (Caller->getFnAttribute("target-cpu") ==
695  Callee->getFnAttribute("target-cpu")) &&
696  (Caller->getFnAttribute("target-features") ==
697  Callee->getFnAttribute("target-features"));
698  }
699 
701  const DataLayout &DL) const {
702  return false;
703  }
704 
706  const DataLayout &DL) const {
707  return false;
708  }
709 
710  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; }
711 
712  bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; }
713 
714  bool isLegalToVectorizeStore(StoreInst *SI) const { return true; }
715 
716  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
717  unsigned AddrSpace) const {
718  return true;
719  }
720 
721  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
722  unsigned AddrSpace) const {
723  return true;
724  }
725 
727  ElementCount VF) const {
728  return true;
729  }
730 
731  bool isElementTypeLegalForScalableVector(Type *Ty) const { return true; }
732 
733  unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
734  unsigned ChainSizeInBytes,
735  VectorType *VecTy) const {
736  return VF;
737  }
738 
739  unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
740  unsigned ChainSizeInBytes,
741  VectorType *VecTy) const {
742  return VF;
743  }
744 
745  bool preferInLoopReduction(unsigned Opcode, Type *Ty,
746  TTI::ReductionFlags Flags) const {
747  return false;
748  }
749 
750  bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
751  TTI::ReductionFlags Flags) const {
752  return false;
753  }
754 
755  bool shouldExpandReduction(const IntrinsicInst *II) const { return true; }
756 
757  unsigned getGISelRematGlobalCost() const { return 1; }
758 
759  bool supportsScalableVectors() const { return false; }
760 
761  bool hasActiveVectorLength() const { return false; }
762 
766  /* EVLParamStrategy */ TargetTransformInfo::VPLegalization::Discard,
767  /* OperatorStrategy */ TargetTransformInfo::VPLegalization::Convert);
768  }
769 
770 protected:
771  // Obtain the minimum required size to hold the value (without the sign)
772  // In case of a vector it returns the min required size for one element.
773  unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const {
774  if (isa<ConstantDataVector>(Val) || isa<ConstantVector>(Val)) {
775  const auto *VectorValue = cast<Constant>(Val);
776 
777  // In case of a vector need to pick the max between the min
778  // required size for each element
779  auto *VT = cast<FixedVectorType>(Val->getType());
780 
781  // Assume unsigned elements
782  isSigned = false;
783 
784  // The max required size is the size of the vector element type
785  unsigned MaxRequiredSize =
786  VT->getElementType()->getPrimitiveSizeInBits().getFixedSize();
787 
788  unsigned MinRequiredSize = 0;
789  for (unsigned i = 0, e = VT->getNumElements(); i < e; ++i) {
790  if (auto *IntElement =
791  dyn_cast<ConstantInt>(VectorValue->getAggregateElement(i))) {
792  bool signedElement = IntElement->getValue().isNegative();
793  // Get the element min required size.
794  unsigned ElementMinRequiredSize =
795  IntElement->getValue().getMinSignedBits() - 1;
796  // In case one element is signed then all the vector is signed.
797  isSigned |= signedElement;
798  // Save the max required bit size between all the elements.
799  MinRequiredSize = std::max(MinRequiredSize, ElementMinRequiredSize);
800  } else {
801  // not an int constant element
802  return MaxRequiredSize;
803  }
804  }
805  return MinRequiredSize;
806  }
807 
808  if (const auto *CI = dyn_cast<ConstantInt>(Val)) {
809  isSigned = CI->getValue().isNegative();
810  return CI->getValue().getMinSignedBits() - 1;
811  }
812 
813  if (const auto *Cast = dyn_cast<SExtInst>(Val)) {
814  isSigned = true;
815  return Cast->getSrcTy()->getScalarSizeInBits() - 1;
816  }
817 
818  if (const auto *Cast = dyn_cast<ZExtInst>(Val)) {
819  isSigned = false;
820  return Cast->getSrcTy()->getScalarSizeInBits();
821  }
822 
823  isSigned = false;
824  return Val->getType()->getScalarSizeInBits();
825  }
826 
827  bool isStridedAccess(const SCEV *Ptr) const {
828  return Ptr && isa<SCEVAddRecExpr>(Ptr);
829  }
830 
832  const SCEV *Ptr) const {
833  if (!isStridedAccess(Ptr))
834  return nullptr;
835  const SCEVAddRecExpr *AddRec = cast<SCEVAddRecExpr>(Ptr);
836  return dyn_cast<SCEVConstant>(AddRec->getStepRecurrence(*SE));
837  }
838 
840  int64_t MergeDistance) const {
841  const SCEVConstant *Step = getConstantStrideStep(SE, Ptr);
842  if (!Step)
843  return false;
844  APInt StrideVal = Step->getAPInt();
845  if (StrideVal.getBitWidth() > 64)
846  return false;
847  // FIXME: Need to take absolute value for negative stride case.
848  return StrideVal.getSExtValue() < MergeDistance;
849  }
850 };
851 
852 /// CRTP base class for use as a mix-in that aids implementing
853 /// a TargetTransformInfo-compatible class.
854 template <typename T>
856 private:
858 
859 protected:
861 
862 public:
863  using BaseT::getGEPCost;
864 
866  getGEPCost(Type *PointeeType, const Value *Ptr,
869  assert(PointeeType && Ptr && "can't get GEPCost of nullptr");
870  assert(cast<PointerType>(Ptr->getType()->getScalarType())
871  ->isOpaqueOrPointeeTypeMatches(PointeeType) &&
872  "explicit pointee type doesn't match operand's pointee type");
873  auto *BaseGV = dyn_cast<GlobalValue>(Ptr->stripPointerCasts());
874  bool HasBaseReg = (BaseGV == nullptr);
875 
876  auto PtrSizeBits = DL.getPointerTypeSizeInBits(Ptr->getType());
877  APInt BaseOffset(PtrSizeBits, 0);
878  int64_t Scale = 0;
879 
880  auto GTI = gep_type_begin(PointeeType, Operands);
881  Type *TargetType = nullptr;
882 
883  // Handle the case where the GEP instruction has a single operand,
884  // the basis, therefore TargetType is a nullptr.
885  if (Operands.empty())
886  return !BaseGV ? TTI::TCC_Free : TTI::TCC_Basic;
887 
888  for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
889  TargetType = GTI.getIndexedType();
890  // We assume that the cost of Scalar GEP with constant index and the
891  // cost of Vector GEP with splat constant index are the same.
892  const ConstantInt *ConstIdx = dyn_cast<ConstantInt>(*I);
893  if (!ConstIdx)
894  if (auto Splat = getSplatValue(*I))
895  ConstIdx = dyn_cast<ConstantInt>(Splat);
896  if (StructType *STy = GTI.getStructTypeOrNull()) {
897  // For structures the index is always splat or scalar constant
898  assert(ConstIdx && "Unexpected GEP index");
899  uint64_t Field = ConstIdx->getZExtValue();
900  BaseOffset += DL.getStructLayout(STy)->getElementOffset(Field);
901  } else {
902  // If this operand is a scalable type, bail out early.
903  // TODO: handle scalable vectors
904  if (isa<ScalableVectorType>(TargetType))
905  return TTI::TCC_Basic;
906  int64_t ElementSize =
907  DL.getTypeAllocSize(GTI.getIndexedType()).getFixedSize();
908  if (ConstIdx) {
909  BaseOffset +=
910  ConstIdx->getValue().sextOrTrunc(PtrSizeBits) * ElementSize;
911  } else {
912  // Needs scale register.
913  if (Scale != 0)
914  // No addressing mode takes two scale registers.
915  return TTI::TCC_Basic;
916  Scale = ElementSize;
917  }
918  }
919  }
920 
921  if (static_cast<T *>(this)->isLegalAddressingMode(
922  TargetType, const_cast<GlobalValue *>(BaseGV),
923  BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale,
924  Ptr->getType()->getPointerAddressSpace()))
925  return TTI::TCC_Free;
926  return TTI::TCC_Basic;
927  }
928 
931  auto *TargetTTI = static_cast<T *>(this);
932  // Handle non-intrinsic calls, invokes, and callbr.
933  // FIXME: Unlikely to be true for anything but CodeSize.
934  auto *CB = dyn_cast<CallBase>(U);
935  if (CB && !isa<IntrinsicInst>(U)) {
936  if (const Function *F = CB->getCalledFunction()) {
937  if (!TargetTTI->isLoweredToCall(F))
938  return TTI::TCC_Basic; // Give a basic cost if it will be lowered
939 
940  return TTI::TCC_Basic * (F->getFunctionType()->getNumParams() + 1);
941  }
942  // For indirect or other calls, scale cost by number of arguments.
943  return TTI::TCC_Basic * (CB->arg_size() + 1);
944  }
945 
946  Type *Ty = U->getType();
947  Type *OpTy =
948  U->getNumOperands() == 1 ? U->getOperand(0)->getType() : nullptr;
949  unsigned Opcode = Operator::getOpcode(U);
950  auto *I = dyn_cast<Instruction>(U);
951  switch (Opcode) {
952  default:
953  break;
954  case Instruction::Call: {
955  assert(isa<IntrinsicInst>(U) && "Unexpected non-intrinsic call");
956  auto *Intrinsic = cast<IntrinsicInst>(U);
957  IntrinsicCostAttributes CostAttrs(Intrinsic->getIntrinsicID(), *CB);
958  return TargetTTI->getIntrinsicInstrCost(CostAttrs, CostKind);
959  }
960  case Instruction::Br:
961  case Instruction::Ret:
962  case Instruction::PHI:
963  case Instruction::Switch:
964  return TargetTTI->getCFInstrCost(Opcode, CostKind, I);
965  case Instruction::ExtractValue:
966  case Instruction::Freeze:
967  return TTI::TCC_Free;
968  case Instruction::Alloca:
969  if (cast<AllocaInst>(U)->isStaticAlloca())
970  return TTI::TCC_Free;
971  break;
972  case Instruction::GetElementPtr: {
973  const GEPOperator *GEP = cast<GEPOperator>(U);
974  return TargetTTI->getGEPCost(GEP->getSourceElementType(),
975  GEP->getPointerOperand(),
976  Operands.drop_front());
977  }
978  case Instruction::Add:
979  case Instruction::FAdd:
980  case Instruction::Sub:
981  case Instruction::FSub:
982  case Instruction::Mul:
983  case Instruction::FMul:
984  case Instruction::UDiv:
985  case Instruction::SDiv:
986  case Instruction::FDiv:
987  case Instruction::URem:
988  case Instruction::SRem:
989  case Instruction::FRem:
990  case Instruction::Shl:
991  case Instruction::LShr:
992  case Instruction::AShr:
993  case Instruction::And:
994  case Instruction::Or:
995  case Instruction::Xor:
996  case Instruction::FNeg: {
999  TTI::OperandValueKind Op1VK =
1000  TTI::getOperandInfo(U->getOperand(0), Op1VP);
1001  TTI::OperandValueKind Op2VK = Opcode != Instruction::FNeg ?
1004  return TargetTTI->getArithmeticInstrCost(Opcode, Ty, CostKind,
1005  Op1VK, Op2VK,
1006  Op1VP, Op2VP, Operands, I);
1007  }
1008  case Instruction::IntToPtr:
1009  case Instruction::PtrToInt:
1010  case Instruction::SIToFP:
1011  case Instruction::UIToFP:
1012  case Instruction::FPToUI:
1013  case Instruction::FPToSI:
1014  case Instruction::Trunc:
1015  case Instruction::FPTrunc:
1016  case Instruction::BitCast:
1017  case Instruction::FPExt:
1018  case Instruction::SExt:
1019  case Instruction::ZExt:
1020  case Instruction::AddrSpaceCast:
1021  return TargetTTI->getCastInstrCost(
1022  Opcode, Ty, OpTy, TTI::getCastContextHint(I), CostKind, I);
1023  case Instruction::Store: {
1024  auto *SI = cast<StoreInst>(U);
1025  Type *ValTy = U->getOperand(0)->getType();
1026  return TargetTTI->getMemoryOpCost(Opcode, ValTy, SI->getAlign(),
1027  SI->getPointerAddressSpace(),
1028  CostKind, I);
1029  }
1030  case Instruction::Load: {
1031  auto *LI = cast<LoadInst>(U);
1032  return TargetTTI->getMemoryOpCost(Opcode, U->getType(), LI->getAlign(),
1033  LI->getPointerAddressSpace(),
1034  CostKind, I);
1035  }
1036  case Instruction::Select: {
1037  const Value *Op0, *Op1;
1038  if (match(U, m_LogicalAnd(m_Value(Op0), m_Value(Op1))) ||
1039  match(U, m_LogicalOr(m_Value(Op0), m_Value(Op1)))) {
1040  // select x, y, false --> x & y
1041  // select x, true, y --> x | y
1044  TTI::OperandValueKind Op1VK = TTI::getOperandInfo(Op0, Op1VP);
1045  TTI::OperandValueKind Op2VK = TTI::getOperandInfo(Op1, Op2VP);
1046  assert(Op0->getType()->getScalarSizeInBits() == 1 &&
1047  Op1->getType()->getScalarSizeInBits() == 1);
1048 
1050  return TargetTTI->getArithmeticInstrCost(
1051  match(U, m_LogicalOr()) ? Instruction::Or : Instruction::And, Ty,
1052  CostKind, Op1VK, Op2VK, Op1VP, Op2VP, Operands, I);
1053  }
1054  Type *CondTy = U->getOperand(0)->getType();
1055  return TargetTTI->getCmpSelInstrCost(Opcode, U->getType(), CondTy,
1057  CostKind, I);
1058  }
1059  case Instruction::ICmp:
1060  case Instruction::FCmp: {
1061  Type *ValTy = U->getOperand(0)->getType();
1062  // TODO: Also handle ICmp/FCmp constant expressions.
1063  return TargetTTI->getCmpSelInstrCost(Opcode, ValTy, U->getType(),
1064  I ? cast<CmpInst>(I)->getPredicate()
1066  CostKind, I);
1067  }
1068  case Instruction::InsertElement: {
1069  auto *IE = dyn_cast<InsertElementInst>(U);
1070  if (!IE)
1071  return TTI::TCC_Basic; // FIXME
1072  auto *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1073  unsigned Idx = CI ? CI->getZExtValue() : -1;
1074  return TargetTTI->getVectorInstrCost(Opcode, Ty, Idx);
1075  }
1076  case Instruction::ShuffleVector: {
1077  auto *Shuffle = dyn_cast<ShuffleVectorInst>(U);
1078  if (!Shuffle)
1079  return TTI::TCC_Basic; // FIXME
1080 
1081  auto *VecTy = cast<VectorType>(U->getType());
1082  auto *VecSrcTy = cast<VectorType>(U->getOperand(0)->getType());
1083  int NumSubElts, SubIndex;
1084 
1085  if (Shuffle->changesLength()) {
1086  // Treat a 'subvector widening' as a free shuffle.
1087  if (Shuffle->increasesLength() && Shuffle->isIdentityWithPadding())
1088  return 0;
1089 
1090  if (Shuffle->isExtractSubvectorMask(SubIndex))
1091  return TargetTTI->getShuffleCost(TTI::SK_ExtractSubvector, VecSrcTy,
1092  Shuffle->getShuffleMask(), SubIndex,
1093  VecTy);
1094 
1095  if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1096  return TargetTTI->getShuffleCost(
1097  TTI::SK_InsertSubvector, VecTy, Shuffle->getShuffleMask(),
1098  SubIndex,
1099  FixedVectorType::get(VecTy->getScalarType(), NumSubElts));
1100 
1101  return CostKind == TTI::TCK_RecipThroughput ? -1 : 1;
1102  }
1103 
1104  if (Shuffle->isIdentity())
1105  return 0;
1106 
1107  if (Shuffle->isReverse())
1108  return TargetTTI->getShuffleCost(TTI::SK_Reverse, VecTy,
1109  Shuffle->getShuffleMask(), 0, nullptr);
1110 
1111  if (Shuffle->isSelect())
1112  return TargetTTI->getShuffleCost(TTI::SK_Select, VecTy,
1113  Shuffle->getShuffleMask(), 0, nullptr);
1114 
1115  if (Shuffle->isTranspose())
1116  return TargetTTI->getShuffleCost(TTI::SK_Transpose, VecTy,
1117  Shuffle->getShuffleMask(), 0, nullptr);
1118 
1119  if (Shuffle->isZeroEltSplat())
1120  return TargetTTI->getShuffleCost(TTI::SK_Broadcast, VecTy,
1121  Shuffle->getShuffleMask(), 0, nullptr);
1122 
1123  if (Shuffle->isSingleSource())
1124  return TargetTTI->getShuffleCost(TTI::SK_PermuteSingleSrc, VecTy,
1125  Shuffle->getShuffleMask(), 0, nullptr);
1126 
1127  if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1128  return TargetTTI->getShuffleCost(
1129  TTI::SK_InsertSubvector, VecTy, Shuffle->getShuffleMask(), SubIndex,
1130  FixedVectorType::get(VecTy->getScalarType(), NumSubElts));
1131 
1132  return TargetTTI->getShuffleCost(TTI::SK_PermuteTwoSrc, VecTy,
1133  Shuffle->getShuffleMask(), 0, nullptr);
1134  }
1135  case Instruction::ExtractElement: {
1136  unsigned Idx = -1;
1137  auto *EEI = dyn_cast<ExtractElementInst>(U);
1138  if (!EEI)
1139  return TTI::TCC_Basic; // FIXME
1140 
1141  auto *CI = dyn_cast<ConstantInt>(EEI->getOperand(1));
1142  if (CI)
1143  Idx = CI->getZExtValue();
1144 
1145  return TargetTTI->getVectorInstrCost(Opcode, U->getOperand(0)->getType(),
1146  Idx);
1147  }
1148  }
1149  // By default, just classify everything as 'basic'.
1150  return TTI::TCC_Basic;
1151  }
1152 
1154  SmallVector<const Value *, 4> Operands(I->operand_values());
1155  if (getUserCost(I, Operands, TTI::TCK_Latency) == TTI::TCC_Free)
1156  return 0;
1157 
1158  if (isa<LoadInst>(I))
1159  return 4;
1160 
1161  Type *DstTy = I->getType();
1162 
1163  // Usually an intrinsic is a simple instruction.
1164  // A real function call is much slower.
1165  if (auto *CI = dyn_cast<CallInst>(I)) {
1166  const Function *F = CI->getCalledFunction();
1167  if (!F || static_cast<T *>(this)->isLoweredToCall(F))
1168  return 40;
1169  // Some intrinsics return a value and a flag, we use the value type
1170  // to decide its latency.
1171  if (StructType *StructTy = dyn_cast<StructType>(DstTy))
1172  DstTy = StructTy->getElementType(0);
1173  // Fall through to simple instructions.
1174  }
1175 
1176  if (VectorType *VectorTy = dyn_cast<VectorType>(DstTy))
1177  DstTy = VectorTy->getElementType();
1178  if (DstTy->isFloatingPointTy())
1179  return 3;
1180 
1181  return 1;
1182  }
1183 };
1184 } // namespace llvm
1185 
1186 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::CacheLevel::L1D
@ L1D
llvm::orc::BaseT
RTTIExtends< ObjectLinkingLayer, ObjectLayer > BaseT
Definition: ObjectLinkingLayer.cpp:615
llvm::TargetTransformInfoImplBase::canHaveNonUndefGlobalInitializerInAddressSpace
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Definition: TargetTransformInfoImpl.h:108
llvm::TargetTransformInfoImplBase::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfoImpl.h:418
llvm::TargetTransformInfo::SK_Select
@ SK_Select
Selects elements from the corresponding lane of either source operand.
Definition: TargetTransformInfo.h:862
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm::TargetTransformInfoImplBase::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Definition: TargetTransformInfoImpl.h:155
llvm::TargetTransformInfo::LSRCost::NumRegs
unsigned NumRegs
Definition: TargetTransformInfo.h:418
llvm::TargetTransformInfo::TCC_Expensive
@ TCC_Expensive
The cost of a 'div' instruction on x86.
Definition: TargetTransformInfo.h:264
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1338
llvm::TargetTransformInfoImplBase::useAA
bool useAA() const
Definition: TargetTransformInfoImpl.h:296
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::TargetTransformInfoImplBase::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI) const
Definition: TargetTransformInfoImpl.h:161
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1286
llvm::TargetTransformInfo::TCK_Latency
@ TCK_Latency
The latency of instruction.
Definition: TargetTransformInfo.h:213
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
llvm::TargetTransformInfoImplBase::enableOrderedReductions
bool enableOrderedReductions() const
Definition: TargetTransformInfoImpl.h:269
llvm::TargetTransformInfoImplBase::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfoImpl.h:112
llvm::TargetTransformInfoImplBase::isStridedAccess
bool isStridedAccess(const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:827
IntrinsicInst.h
llvm::ElementCount
Definition: TypeSize.h:386
llvm::TargetTransformInfoImplBase::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfoImpl.h:402
llvm::TypeSize::getFixedSize
ScalarTy getFixedSize() const
Definition: TypeSize.h:426
llvm::Function
Definition: Function.h:61
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::TargetTransformInfoImplBase::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:201
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:592
llvm::TargetTransformInfoImplCRTPBase::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:929
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
GetElementPtrTypeIterator.h
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:319
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:133
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::TargetTransformInfoImplBase::getExtendedAddReductionCost
InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfoImpl.h:641
llvm::TargetTransformInfoImplBase::isLSRCostLess
bool isLSRCostLess(TTI::LSRCost &C1, TTI::LSRCost &C2) const
Definition: TargetTransformInfoImpl.h:211
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1467
llvm::TargetTransformInfoImplBase::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Definition: TargetTransformInfoImpl.h:267
llvm::TargetTransformInfoImplBase::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *, const SCEV *) const
Definition: TargetTransformInfoImpl.h:625
llvm::TargetTransformInfoImplBase::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Definition: TargetTransformInfoImpl.h:100
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:366
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:734
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:461
llvm::TargetTransformInfoImplBase::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfoImpl.h:400
llvm::TargetTransformInfoImplBase::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfoImpl.h:76
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:151
llvm::TargetTransformInfoImplBase::TTI
TargetTransformInfo TTI
Definition: TargetTransformInfoImpl.h:36
llvm::TargetTransformInfoImplBase::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:279
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1381
llvm::TargetTransformInfo::LSRCost::NumIVMuls
unsigned NumIVMuls
Definition: TargetTransformInfo.h:420
llvm::TargetTransformInfoImplBase::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:385
llvm::TargetTransformInfoImplBase::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:710
llvm::TargetTransformInfoImplBase::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Definition: TargetTransformInfoImpl.h:344
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1403
llvm::TargetTransformInfo::VPLegalization::Convert
@ Convert
Definition: TargetTransformInfo.h:1388
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:535
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfoImpl.h:714
llvm::TargetTransformInfoImplBase::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Definition: TargetTransformInfoImpl.h:294
llvm::Optional
Definition: APInt.h:33
T
#define T
Definition: Mips16ISelLowering.cpp:341
Operator.h
llvm::TargetTransformInfoImplBase::areFunctionArgsABICompatible
bool areFunctionArgsABICompatible(const Function *Caller, const Function *Callee, SmallPtrSetImpl< Argument * > &Args) const
Definition: TargetTransformInfoImpl.h:691
llvm::TargetTransformInfoImplBase::hasActiveVectorLength
bool hasActiveVectorLength() const
Definition: TargetTransformInfoImpl.h:761
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::TargetTransformInfoImplBase::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Definition: TargetTransformInfoImpl.h:94
llvm::TargetTransformInfoImplBase::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:361
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:40
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::gep_type_begin
gep_type_iterator gep_type_begin(const User *GEP)
Definition: GetElementPtrTypeIterator.h:139
llvm::TargetTransformInfoImplBase::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *, VectorType *, bool, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:636
llvm::Type::isFloatingPointTy
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:162
llvm::TargetTransformInfoImplBase::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:261
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetTransformInfo::SK_PermuteSingleSrc
@ SK_PermuteSingleSrc
Shuffle elements of single source vector with any shuffle mask.
Definition: TargetTransformInfo.h:870
llvm::TargetTransformInfoImplBase::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Definition: TargetTransformInfoImpl.h:348
llvm::Type::getInt8Ty
static IntegerType * getInt8Ty(LLVMContext &C)
Definition: Type.cpp:201
llvm::TargetTransformInfoImplBase::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:332
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:299
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:948
llvm::TargetTransformInfoImplBase::getConstantStrideStep
const SCEVConstant * getConstantStrideStep(ScalarEvolution *SE, const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:831
llvm::TargetTransformInfoImplCRTPBase::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency)
Definition: TargetTransformInfoImpl.h:866
llvm::TargetTransformInfoImplBase::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Definition: TargetTransformInfoImpl.h:102
llvm::TargetTransformInfo::SK_Broadcast
@ SK_Broadcast
Broadcast element 0 to all other elements.
Definition: TargetTransformInfo.h:860
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::TargetTransformInfo::LSRCost::AddRecCost
unsigned AddRecCost
Definition: TargetTransformInfo.h:419
llvm::TargetTransformInfoImplBase::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Definition: TargetTransformInfoImpl.h:292
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:48
llvm::TargetTransformInfoImplBase::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfoImpl.h:683
llvm::TargetTransformInfoImplBase::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfoImpl.h:406
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::TargetTransformInfo::LSRCost::SetupCost
unsigned SetupCost
Definition: TargetTransformInfo.h:423
llvm::TargetTransformInfoImplBase::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Definition: TargetTransformInfoImpl.h:218
llvm::TargetTransformInfoImplBase::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: TargetTransformInfoImpl.h:726
llvm::TargetTransformInfoImplBase::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
Definition: TargetTransformInfoImpl.h:88
llvm::TargetTransformInfoImplBase::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, bool *Fast) const
Definition: TargetTransformInfoImpl.h:338
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::TargetTransformInfoImplBase::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Definition: TargetTransformInfoImpl.h:271
llvm::TargetTransformInfo::SK_PermuteTwoSrc
@ SK_PermuteTwoSrc
Merge elements from two source vectors into one with any shuffle mask.
Definition: TargetTransformInfo.h:868
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::LinearPolySize< ElementCount >::get
static ElementCount get(ScalarTy MinVal, bool Scalable)
Definition: TypeSize.h:290
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:737
llvm::TargetTransformInfoImplBase::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfoImpl.h:452
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg)
Definition: TargetTransformInfoImpl.h:46
llvm::TargetTransformInfoImplBase
Base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:34
llvm::TargetTransformInfoImplBase::getCacheAssociativity
llvm::Optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:432
llvm::PatternMatch::match
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
llvm::TargetTransformInfoImplBase::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfoImpl.h:443
llvm::TargetTransformInfoImplBase::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:379
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:886
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:859
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1062
llvm::TargetTransformInfoImplBase::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:235
llvm::User
Definition: User.h:44
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetTransformInfoImplBase::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Definition: TargetTransformInfoImpl.h:304
llvm::TargetTransformInfoImplBase::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const
Definition: TargetTransformInfoImpl.h:543
llvm::TargetTransformInfoImplBase::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfoImpl.h:669
llvm::TargetTransformInfoImplBase::hasBranchDivergence
bool hasBranchDivergence() const
Definition: TargetTransformInfoImpl.h:92
llvm::TargetTransformInfoImplBase::isIndexedStoreLegal
bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:705
llvm::TargetTransformInfoImplBase::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Definition: TargetTransformInfoImpl.h:302
llvm::Instruction
Definition: Instruction.h:45
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:153
llvm::TargetTransformInfoImplBase::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfoImpl.h:623
llvm::TargetTransformInfoImplBase::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
Definition: TargetTransformInfoImpl.h:366
llvm::Operator::getOpcode
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
Definition: Operator.h:41
llvm::TargetTransformInfoImplBase::isTypeLegal
bool isTypeLegal(Type *Ty) const
Definition: TargetTransformInfoImpl.h:298
llvm::TargetTransformInfoImplBase::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:203
llvm::TargetTransformInfoImplBase::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:527
llvm::TargetTransformInfoImplBase::getRegUsageForType
InstructionCost getRegUsageForType(Type *Ty) const
Definition: TargetTransformInfoImpl.h:300
llvm::TargetTransformInfoImplBase::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfoImpl.h:664
llvm::TargetTransformInfoImplCRTPBase
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:855
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetTransformInfoImplBase::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:273
PatternMatch.h
llvm::TargetTransformInfoImplBase::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:647
llvm::TargetTransformInfoImplBase::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfoImpl.h:450
llvm::FixedVectorType::get
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
Definition: Type.cpp:648
llvm::TargetTransformInfoImplBase::enableMemCmpExpansion
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfoImpl.h:327
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:153
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::TargetTransformInfoImplBase::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Definition: TargetTransformInfoImpl.h:96
llvm::TargetTransformInfoImplBase::getVPLegalizationStrategy
TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: TargetTransformInfoImpl.h:764
llvm::TargetTransformInfoImplBase::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:555
llvm::None
const NoneType None
Definition: None.h:23
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:284
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
Type.h
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:118
llvm::TargetTransformInfoImplBase::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:561
llvm::TargetTransformInfo::PSK_Software
@ PSK_Software
Definition: TargetTransformInfo.h:592
llvm::TargetTransformInfoImplBase::getCacheSize
llvm::Optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:421
llvm::TargetTransformInfoImplBase::emitGetActiveLaneMask
bool emitGetActiveLaneMask() const
Definition: TargetTransformInfoImpl.h:168
llvm::TargetTransformInfoImplBase::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfoImpl.h:220
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::ARM_PROC::IE
@ IE
Definition: ARMBaseInfo.h:27
llvm::TargetTransformInfoImplBase::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: TargetTransformInfoImpl.h:184
llvm::TargetTransformInfoImplBase::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:750
llvm::TargetTransformInfoImplBase::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfoImpl.h:759
llvm::TargetTransformInfoImplBase::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:334
llvm::TargetTransformInfo::SK_Reverse
@ SK_Reverse
Reverse the order of the vector.
Definition: TargetTransformInfo.h:861
llvm::TargetTransformInfoImplCRTPBase::TargetTransformInfoImplCRTPBase
TargetTransformInfoImplCRTPBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:860
llvm::TargetTransformInfoImplBase::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:617
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
VectorUtils.h
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:78
llvm::TargetTransformInfoImplBase::canMacroFuseCmp
bool canMacroFuseCmp() const
Definition: TargetTransformInfoImpl.h:222
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:304
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::TargetTransformInfo::SK_InsertSubvector
@ SK_InsertSubvector
InsertSubvector. Index indicates start offset.
Definition: TargetTransformInfo.h:866
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfoImplBase::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfoImpl.h:63
llvm::TargetTransformInfoImplBase::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:243
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::TargetTransformInfoImplBase::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth() const
Definition: TargetTransformInfoImpl.h:404
uint64_t
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:414
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:721
llvm::PatternMatch::m_LogicalOr
LogicalOp_match< LHS, RHS, Instruction::Or > m_LogicalOr(const LHS &L, const RHS &R)
Matches L || R either in the form of L | R or L ? true : R.
Definition: PatternMatch.h:2510
llvm::TargetTransformInfoImplBase::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned, VectorType *, Optional< FastMathFlags > FMF, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:630
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::TargetTransformInfoImplBase::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Definition: TargetTransformInfoImpl.h:178
llvm::TargetTransformInfoImplBase::getPreferredAddressingMode
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Definition: TargetTransformInfoImpl.h:231
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:428
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfoImplBase::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:483
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:886
llvm::LoopAccessInfo
Drive the analysis of memory accesses in the loop.
Definition: LoopAccessAnalysis.h:515
llvm::SCEVConstant
This class represents a constant integer value.
Definition: ScalarEvolutionExpressions.h:47
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetTransformInfo::VPLegalization::Discard
@ Discard
Definition: TargetTransformInfo.h:1386
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::TargetTransformInfoImplBase::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfoImpl.h:412
llvm::TargetTransformInfoImplBase::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Definition: TargetTransformInfoImpl.h:119
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::CmpInst::BAD_ICMP_PREDICATE
@ BAD_ICMP_PREDICATE
Definition: InstrTypes.h:753
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::TargetTransformInfo::LSRCost::ScaleCost
unsigned ScaleCost
Definition: TargetTransformInfo.h:424
llvm::TargetTransformInfoImplBase::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:316
llvm::TargetTransformInfoImplBase::getInterleavedMemoryOpCost
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) const
Definition: TargetTransformInfoImpl.h:569
llvm::TargetTransformInfoImplBase::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfoImpl.h:651
llvm::TargetTransformInfoImplBase::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Definition: TargetTransformInfoImpl.h:323
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:878
llvm::GEPOperator
Definition: Operator.h:458
llvm::PatternMatch::m_Value
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:76
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfoImplBase::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned, unsigned) const
Definition: TargetTransformInfoImpl.h:107
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:761
llvm::TargetTransformInfoImplBase::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:250
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:262
llvm::TargetTransformInfoImplBase::isElementTypeLegalForScalableVector
bool isElementTypeLegalForScalableVector(Type *Ty) const
Definition: TargetTransformInfoImpl.h:731
llvm::TargetTransformInfoImplBase::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfoImpl.h:755
llvm::TargetTransformInfoImplBase::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfoImpl.h:73
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1083
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
DataLayout.h
llvm::StructType
Class to represent struct types.
Definition: DerivedTypes.h:213
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:41
llvm::TargetTransformInfo::TCK_SizeAndLatency
@ TCK_SizeAndLatency
The weighted sum of size and latency.
Definition: TargetTransformInfo.h:215
llvm::TargetTransformInfoImplBase::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfoImpl.h:757
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::TargetTransformInfoImplCRTPBase::getInstructionLatency
InstructionCost getInstructionLatency(const Instruction *I)
Definition: TargetTransformInfoImpl.h:1153
llvm::TargetTransformInfoImplBase::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Definition: TargetTransformInfoImpl.h:290
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::TargetTransformInfoImplBase::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Definition: TargetTransformInfoImpl.h:310
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetTransformInfoImplBase::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
Definition: TargetTransformInfoImpl.h:321
llvm::TargetTransformInfoImplBase::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Definition: TargetTransformInfoImpl.h:350
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::TargetTransformInfoImplBase::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:536
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:639
llvm::TargetTransformInfoImplBase::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:239
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:421
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:879
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:175
llvm::TargetTransformInfo::SK_Transpose
@ SK_Transpose
Transpose two vectors.
Definition: TargetTransformInfo.h:865
llvm::TargetTransformInfoImplBase::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfoImpl.h:675
llvm::Value::stripPointerCasts
const Value * stripPointerCasts() const
Strip off pointer casts, all-zero GEPs and address space casts.
Definition: Value.cpp:675
llvm::TargetTransformInfo::CacheLevel::L2D
@ L2D
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:142
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:206
llvm::TargetTransformInfoImplBase::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr) const
Definition: TargetTransformInfoImpl.h:454
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:162
llvm::TargetTransformInfoImplBase::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:745
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::KnownBits
Definition: KnownBits.h:23
llvm::TargetTransformInfoImplBase::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef< int > Mask, int Index, VectorType *SubTp) const
Definition: TargetTransformInfoImpl.h:477
llvm::TargetTransformInfo::LSRCost::NumBaseAdds
unsigned NumBaseAdds
Definition: TargetTransformInfo.h:421
llvm::TargetTransformInfoImplBase::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfoImpl.h:655
llvm::TargetTransformInfoImplBase::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfoImpl.h:449
llvm::TargetTransformInfoImplBase::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:373
llvm::TargetTransformInfoImplBase::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfoImpl.h:78
llvm::TargetTransformInfoImplBase::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Definition: TargetTransformInfoImpl.h:114
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:390
VPLegalization
TargetTransformInfo::VPLegalization VPLegalization
Definition: ExpandVectorPredication.cpp:36
llvm::APInt::sextOrTrunc
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:976
llvm::TargetTransformInfoImplBase::minRequiredElementSize
unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const
Definition: TargetTransformInfoImpl.h:773
llvm::TypeSize
Definition: TypeSize.h:417
llvm::SCEVAddRecExpr
This node represents a polynomial recurrence on the trip count of the specified loop.
Definition: ScalarEvolutionExpressions.h:352
Function.h
llvm::TargetTransformInfoImplBase::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:733
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::TargetTransformInfoImplBase::isIndexedLoadLegal
bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:700
llvm::TargetTransformInfoImplBase::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Definition: TargetTransformInfoImpl.h:444
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:219
llvm::User::operand_values
iterator_range< value_op_iterator > operand_values()
Definition: User.h:266
llvm::TargetTransformInfo::LSRCost::ImmCost
unsigned ImmCost
Definition: TargetTransformInfo.h:422
llvm::TargetTransformInfoImplBase::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:199
llvm::TargetTransformInfoImplBase::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:548
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:183
llvm::TargetTransformInfoImplBase::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfoImpl.h:381
llvm::TargetTransformInfoImplBase::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: TargetTransformInfoImpl.h:396
llvm::TargetTransformInfoImplBase::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Definition: TargetTransformInfoImpl.h:224
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfoImplBase::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: TargetTransformInfoImpl.h:172
llvm::SCEVConstant::getAPInt
const APInt & getAPInt() const
Definition: ScalarEvolutionExpressions.h:57
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:95
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::TargetTransformInfoImplBase::getUnrollingPreferences
void getUnrollingPreferences(Loop *, ScalarEvolution &, TTI::UnrollingPreferences &, OptimizationRemarkEmitter *) const
Definition: TargetTransformInfoImpl.h:192
llvm::TargetTransformInfoImplBase::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
Definition: TargetTransformInfoImpl.h:521
llvm::TargetTransformInfoImplBase::isConstantStridedAccessLessThan
bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
Definition: TargetTransformInfoImpl.h:839
llvm::TargetTransformInfoImplBase::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Definition: TargetTransformInfoImpl.h:336
ScalarEvolutionExpressions.h
llvm::TargetTransformInfoImplBase::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfoImpl.h:98
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:67
llvm::TargetTransformInfoImplBase::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Definition: TargetTransformInfoImpl.h:265
llvm::User::getNumOperands
unsigned getNumOperands() const
Definition: User.h:191
llvm::IntrinsicCostAttributes::getID
Intrinsic::ID getID() const
Definition: TargetTransformInfo.h:148
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:907
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfoImpl.h:712
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
TargetTransformInfo.h
llvm::PatternMatch
Definition: PatternMatch.h:47
llvm::SmallVectorImpl< int >
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:70
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1161
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
llvm::TargetTransformInfoImplBase::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:739
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:716
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:172
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(const TargetTransformInfoImplBase &Arg)
Definition: TargetTransformInfoImpl.h:44
llvm::TargetTransformInfoImplBase::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:257
llvm::TargetTransformInfo::getOperandInfo
static OperandValueKind getOperandInfo(const Value *V, OperandValueProperties &OpProps)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:665
llvm::TargetTransformInfo::TCC_Basic
@ TCC_Basic
The cost of a typical 'add' instruction.
Definition: TargetTransformInfo.h:263
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3204
llvm::OptimizedStructLayoutField
A field in a structure.
Definition: OptimizedStructLayout.h:45
llvm::TargetTransformInfoImplBase::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Definition: TargetTransformInfoImpl.h:306
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::TargetTransformInfoImplBase::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfoImpl.h:74
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3060
llvm::TargetTransformInfoImplBase::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:576
llvm::TargetTransformInfoImplBase::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Definition: TargetTransformInfoImpl.h:277
llvm::TargetTransformInfoImplBase::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Definition: TargetTransformInfoImpl.h:308
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:212
llvm::TargetTransformInfoImplBase::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
Definition: TargetTransformInfoImpl.h:356
llvm::TargetTransformInfo::AMK_None
@ AMK_None
Definition: TargetTransformInfo.h:642
llvm::TargetTransformInfo::SK_ExtractSubvector
@ SK_ExtractSubvector
ExtractSubvector Index indicates start offset.
Definition: TargetTransformInfo.h:867
llvm::PatternMatch::m_LogicalAnd
LogicalOp_match< LHS, RHS, Instruction::And > m_LogicalAnd(const LHS &L, const RHS &R)
Matches L && R either in the form of L & R or L ? R : false.
Definition: PatternMatch.h:2499
llvm::TargetTransformInfoImplBase::getPeelingPreferences
void getPeelingPreferences(Loop *, ScalarEvolution &, TTI::PeelingPreferences &) const
Definition: TargetTransformInfoImpl.h:196
llvm::SCEVAddRecExpr::getStepRecurrence
const SCEV * getStepRecurrence(ScalarEvolution &SE) const
Constructs and returns the recurrence indicating how much this expression steps by.
Definition: ScalarEvolutionExpressions.h:370
llvm::TargetTransformInfoImplBase::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfoImpl.h:410
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::TargetTransformInfoImplBase::getFPOpCost
InstructionCost getFPOpCost(Type *Ty) const
Definition: TargetTransformInfoImpl.h:352