LLVM  13.0.0git
TargetTransformInfoImpl.h
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1 //===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file provides helpers for the implementation of
10 /// a TargetTransformInfo-conforming class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
15 #define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
16 
20 #include "llvm/IR/DataLayout.h"
21 #include "llvm/IR/Function.h"
23 #include "llvm/IR/IntrinsicInst.h"
24 #include "llvm/IR/Operator.h"
25 #include "llvm/IR/PatternMatch.h"
26 #include "llvm/IR/Type.h"
27 
28 using namespace llvm::PatternMatch;
29 
30 namespace llvm {
31 
32 /// Base class for use as a mix-in that aids implementing
33 /// a TargetTransformInfo-compatible class.
35 protected:
37 
38  const DataLayout &DL;
39 
41 
42 public:
43  // Provide value semantics. MSVC requires that we spell all of these out.
45  : DL(Arg.DL) {}
47 
48  const DataLayout &getDataLayout() const { return DL; }
49 
51  getGEPCost(Type *PointeeType, const Value *Ptr,
54  // In the basic model, we just assume that all-constant GEPs will be folded
55  // into their uses via addressing modes.
56  for (unsigned Idx = 0, Size = Operands.size(); Idx != Size; ++Idx)
57  if (!isa<Constant>(Operands[Idx]))
58  return TTI::TCC_Basic;
59 
60  return TTI::TCC_Free;
61  }
62 
64  unsigned &JTSize,
65  ProfileSummaryInfo *PSI,
66  BlockFrequencyInfo *BFI) const {
67  (void)PSI;
68  (void)BFI;
69  JTSize = 0;
70  return SI.getNumCases();
71  }
72 
73  unsigned getInliningThresholdMultiplier() const { return 1; }
74  unsigned adjustInliningThreshold(const CallBase *CB) const { return 0; }
75 
76  int getInlinerVectorBonusPercent() const { return 150; }
77 
79  return TTI::TCC_Expensive;
80  }
81 
82  // Although this default value is arbitrary, it is not random. It is assumed
83  // that a condition that evaluates the same way by a higher percentage than
84  // this is best represented as control flow. Therefore, the default value N
85  // should be set such that the win from N% correct executions is greater than
86  // the loss from (100 - N)% mispredicted executions for the majority of
87  // intended targets.
89  return BranchProbability(99, 100);
90  }
91 
92  bool hasBranchDivergence() const { return false; }
93 
94  bool useGPUDivergenceAnalysis() const { return false; }
95 
96  bool isSourceOfDivergence(const Value *V) const { return false; }
97 
98  bool isAlwaysUniform(const Value *V) const { return false; }
99 
100  unsigned getFlatAddressSpace() const { return -1; }
101 
103  Intrinsic::ID IID) const {
104  return false;
105  }
106 
107  bool isNoopAddrSpaceCast(unsigned, unsigned) const { return false; }
108 
109  unsigned getAssumedAddrSpace(const Value *V) const { return -1; }
110 
112  Value *NewV) const {
113  return nullptr;
114  }
115 
116  bool isLoweredToCall(const Function *F) const {
117  assert(F && "A concrete function must be provided to this routine.");
118 
119  // FIXME: These should almost certainly not be handled here, and instead
120  // handled with the help of TLI or the target itself. This was largely
121  // ported from existing analysis heuristics here so that such refactorings
122  // can take place in the future.
123 
124  if (F->isIntrinsic())
125  return false;
126 
127  if (F->hasLocalLinkage() || !F->hasName())
128  return true;
129 
130  StringRef Name = F->getName();
131 
132  // These will all likely lower to a single selection DAG node.
133  if (Name == "copysign" || Name == "copysignf" || Name == "copysignl" ||
134  Name == "fabs" || Name == "fabsf" || Name == "fabsl" || Name == "sin" ||
135  Name == "fmin" || Name == "fminf" || Name == "fminl" ||
136  Name == "fmax" || Name == "fmaxf" || Name == "fmaxl" ||
137  Name == "sinf" || Name == "sinl" || Name == "cos" || Name == "cosf" ||
138  Name == "cosl" || Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl")
139  return false;
140 
141  // These are all likely to be optimized into something smaller.
142  if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" ||
143  Name == "exp2l" || Name == "exp2f" || Name == "floor" ||
144  Name == "floorf" || Name == "ceil" || Name == "round" ||
145  Name == "ffs" || Name == "ffsl" || Name == "abs" || Name == "labs" ||
146  Name == "llabs")
147  return false;
148 
149  return true;
150  }
151 
153  AssumptionCache &AC, TargetLibraryInfo *LibInfo,
154  HardwareLoopInfo &HWLoopInfo) const {
155  return false;
156  }
157 
160  DominatorTree *DT,
161  const LoopAccessInfo *LAI) const {
162  return false;
163  }
164 
165  bool emitGetActiveLaneMask() const {
166  return false;
167  }
168 
170  IntrinsicInst &II) const {
171  return None;
172  }
173 
176  APInt DemandedMask, KnownBits &Known,
177  bool &KnownBitsComputed) const {
178  return None;
179  }
180 
182  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
183  APInt &UndefElts2, APInt &UndefElts3,
184  std::function<void(Instruction *, unsigned, APInt, APInt &)>
185  SimplifyAndSetOp) const {
186  return None;
187  }
188 
190  TTI::UnrollingPreferences &) const {}
191 
193  TTI::PeelingPreferences &) const {}
194 
195  bool isLegalAddImmediate(int64_t Imm) const { return false; }
196 
197  bool isLegalICmpImmediate(int64_t Imm) const { return false; }
198 
199  bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
200  bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
201  Instruction *I = nullptr) const {
202  // Guess that only reg and reg+reg addressing is allowed. This heuristic is
203  // taken from the implementation of LSR.
204  return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
205  }
206 
208  return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
209  C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
210  std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
211  C2.ScaleCost, C2.ImmCost, C2.SetupCost);
212  }
213 
214  bool isNumRegsMajorCostOfLSR() const { return true; }
215 
216  bool isProfitableLSRChainElement(Instruction *I) const { return false; }
217 
218  bool canMacroFuseCmp() const { return false; }
219 
222  TargetLibraryInfo *LibInfo) const {
223  return false;
224  }
225 
228  return TTI::AMK_None;
229  }
230 
231  bool isLegalMaskedStore(Type *DataType, Align Alignment) const {
232  return false;
233  }
234 
235  bool isLegalMaskedLoad(Type *DataType, Align Alignment) const {
236  return false;
237  }
238 
239  bool isLegalNTStore(Type *DataType, Align Alignment) const {
240  // By default, assume nontemporal memory stores are available for stores
241  // that are aligned and have a size that is a power of 2.
242  unsigned DataSize = DL.getTypeStoreSize(DataType);
243  return Alignment >= DataSize && isPowerOf2_32(DataSize);
244  }
245 
246  bool isLegalNTLoad(Type *DataType, Align Alignment) const {
247  // By default, assume nontemporal memory loads are available for loads that
248  // are aligned and have a size that is a power of 2.
249  unsigned DataSize = DL.getTypeStoreSize(DataType);
250  return Alignment >= DataSize && isPowerOf2_32(DataSize);
251  }
252 
253  bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
254  return false;
255  }
256 
257  bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
258  return false;
259  }
260 
261  bool isLegalMaskedCompressStore(Type *DataType) const { return false; }
262 
263  bool isLegalMaskedExpandLoad(Type *DataType) const { return false; }
264 
265  bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; }
266 
267  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const {
268  return false;
269  }
270 
271  bool prefersVectorizedAddressing() const { return true; }
272 
274  int64_t BaseOffset, bool HasBaseReg,
275  int64_t Scale,
276  unsigned AddrSpace) const {
277  // Guess that all legal addressing mode are free.
278  if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
279  AddrSpace))
280  return 0;
281  return -1;
282  }
283 
284  bool LSRWithInstrQueries() const { return false; }
285 
286  bool isTruncateFree(Type *Ty1, Type *Ty2) const { return false; }
287 
288  bool isProfitableToHoist(Instruction *I) const { return true; }
289 
290  bool useAA() const { return false; }
291 
292  bool isTypeLegal(Type *Ty) const { return false; }
293 
294  InstructionCost getRegUsageForType(Type *Ty) const { return 1; }
295 
296  bool shouldBuildLookupTables() const { return true; }
297 
298  bool shouldBuildLookupTablesForConstant(Constant *C) const { return true; }
299 
300  bool shouldBuildRelLookupTables() const { return false; }
301 
302  bool useColdCCForColdCall(Function &F) const { return false; }
303 
305  const APInt &DemandedElts,
306  bool Insert, bool Extract) const {
307  return 0;
308  }
309 
311  ArrayRef<Type *> Tys) const {
312  return 0;
313  }
314 
315  bool supportsEfficientVectorElementLoadStore() const { return false; }
316 
317  bool enableAggressiveInterleaving(bool LoopHasReductions) const {
318  return false;
319  }
320 
322  bool IsZeroCmp) const {
323  return {};
324  }
325 
326  bool enableInterleavedAccessVectorization() const { return false; }
327 
328  bool enableMaskedInterleavedAccessVectorization() const { return false; }
329 
330  bool isFPVectorizationPotentiallyUnsafe() const { return false; }
331 
333  unsigned AddressSpace, Align Alignment,
334  bool *Fast) const {
335  return false;
336  }
337 
338  TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const {
339  return TTI::PSK_Software;
340  }
341 
342  bool haveFastSqrt(Type *Ty) const { return false; }
343 
344  bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; }
345 
348  }
349 
350  InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
351  const APInt &Imm, Type *Ty) const {
352  return 0;
353  }
354 
357  return TTI::TCC_Basic;
358  }
359 
360  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
361  const APInt &Imm, Type *Ty,
363  Instruction *Inst = nullptr) const {
364  return TTI::TCC_Free;
365  }
366 
368  const APInt &Imm, Type *Ty,
370  return TTI::TCC_Free;
371  }
372 
373  unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; }
374 
375  unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
376  return Vector ? 1 : 0;
377  };
378 
379  const char *getRegisterClassName(unsigned ClassID) const {
380  switch (ClassID) {
381  default:
382  return "Generic::Unknown Register Class";
383  case 0:
384  return "Generic::ScalarRC";
385  case 1:
386  return "Generic::VectorRC";
387  }
388  }
389 
391  return TypeSize::getFixed(32);
392  }
393 
394  unsigned getMinVectorRegisterBitWidth() const { return 128; }
395 
397 
398  bool shouldMaximizeVectorBandwidth() const { return false; }
399 
400  ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const {
401  return ElementCount::get(0, IsScalable);
402  }
403 
404  unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const { return 0; }
405 
407  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
408  AllowPromotionWithoutCommonHeader = false;
409  return false;
410  }
411 
412  unsigned getCacheLineSize() const { return 0; }
413 
416  switch (Level) {
420  return llvm::Optional<unsigned>();
421  }
422  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
423  }
424 
427  switch (Level) {
431  return llvm::Optional<unsigned>();
432  }
433 
434  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
435  }
436 
437  unsigned getPrefetchDistance() const { return 0; }
438  unsigned getMinPrefetchStride(unsigned NumMemAccesses,
439  unsigned NumStridedMemAccesses,
440  unsigned NumPrefetches, bool HasCall) const {
441  return 1;
442  }
443  unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; }
444  bool enableWritePrefetching() const { return false; }
445 
446  unsigned getMaxInterleaveFactor(unsigned VF) const { return 1; }
447 
449  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
450  TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info,
451  TTI::OperandValueProperties Opd1PropInfo,
453  const Instruction *CxtI = nullptr) const {
454  // FIXME: A number of transformation tests seem to require these values
455  // which seems a little odd for how arbitary there are.
456  switch (Opcode) {
457  default:
458  break;
459  case Instruction::FDiv:
460  case Instruction::FRem:
461  case Instruction::SDiv:
462  case Instruction::SRem:
463  case Instruction::UDiv:
464  case Instruction::URem:
465  // FIXME: Unlikely to be true for CodeSize.
466  return TTI::TCC_Expensive;
467  }
468  return 1;
469  }
470 
472  ArrayRef<int> Mask, int Index,
473  VectorType *SubTp) const {
474  return 1;
475  }
476 
477  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
480  const Instruction *I) const {
481  switch (Opcode) {
482  default:
483  break;
484  case Instruction::IntToPtr: {
485  unsigned SrcSize = Src->getScalarSizeInBits();
486  if (DL.isLegalInteger(SrcSize) &&
487  SrcSize <= DL.getPointerTypeSizeInBits(Dst))
488  return 0;
489  break;
490  }
491  case Instruction::PtrToInt: {
492  unsigned DstSize = Dst->getScalarSizeInBits();
493  if (DL.isLegalInteger(DstSize) &&
494  DstSize >= DL.getPointerTypeSizeInBits(Src))
495  return 0;
496  break;
497  }
498  case Instruction::BitCast:
499  if (Dst == Src || (Dst->isPointerTy() && Src->isPointerTy()))
500  // Identity and pointer-to-pointer casts are free.
501  return 0;
502  break;
503  case Instruction::Trunc: {
504  // trunc to a native type is free (assuming the target has compare and
505  // shift-right of the same width).
506  TypeSize DstSize = DL.getTypeSizeInBits(Dst);
507  if (!DstSize.isScalable() && DL.isLegalInteger(DstSize.getFixedSize()))
508  return 0;
509  break;
510  }
511  }
512  return 1;
513  }
514 
516  VectorType *VecTy,
517  unsigned Index) const {
518  return 1;
519  }
520 
522  const Instruction *I = nullptr) const {
523  // A phi would be free, unless we're costing the throughput because it
524  // will require a register.
525  if (Opcode == Instruction::PHI && CostKind != TTI::TCK_RecipThroughput)
526  return 0;
527  return 1;
528  }
529 
530  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
531  CmpInst::Predicate VecPred,
533  const Instruction *I) const {
534  return 1;
535  }
536 
537  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
538  unsigned Index) const {
539  return 1;
540  }
541 
542  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
543  unsigned AddressSpace,
545  const Instruction *I) const {
546  return 1;
547  }
548 
550  Align Alignment, unsigned AddressSpace,
552  return 1;
553  }
554 
555  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
556  const Value *Ptr, bool VariableMask,
557  Align Alignment,
559  const Instruction *I = nullptr) const {
560  return 1;
561  }
562 
564  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
565  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
566  bool UseMaskForCond, bool UseMaskForGaps) const {
567  return 1;
568  }
569 
572  switch (ICA.getID()) {
573  default:
574  break;
575  case Intrinsic::annotation:
576  case Intrinsic::assume:
577  case Intrinsic::sideeffect:
578  case Intrinsic::pseudoprobe:
579  case Intrinsic::dbg_declare:
580  case Intrinsic::dbg_value:
581  case Intrinsic::dbg_label:
582  case Intrinsic::invariant_start:
583  case Intrinsic::invariant_end:
584  case Intrinsic::launder_invariant_group:
585  case Intrinsic::strip_invariant_group:
586  case Intrinsic::is_constant:
587  case Intrinsic::lifetime_start:
588  case Intrinsic::lifetime_end:
589  case Intrinsic::experimental_noalias_scope_decl:
590  case Intrinsic::objectsize:
591  case Intrinsic::ptr_annotation:
592  case Intrinsic::var_annotation:
593  case Intrinsic::experimental_gc_result:
594  case Intrinsic::experimental_gc_relocate:
595  case Intrinsic::coro_alloc:
596  case Intrinsic::coro_begin:
597  case Intrinsic::coro_free:
598  case Intrinsic::coro_end:
599  case Intrinsic::coro_frame:
600  case Intrinsic::coro_size:
601  case Intrinsic::coro_suspend:
602  case Intrinsic::coro_param:
603  case Intrinsic::coro_subfn_addr:
604  // These intrinsics don't actually represent code after lowering.
605  return 0;
606  }
607  return 1;
608  }
609 
611  ArrayRef<Type *> Tys,
613  return 1;
614  }
615 
616  unsigned getNumberOfParts(Type *Tp) const { return 0; }
617 
619  const SCEV *) const {
620  return 0;
621  }
622 
624  TTI::TargetCostKind) const {
625  return 1;
626  }
627 
629  TTI::TargetCostKind) const {
630  return 1;
631  }
632 
634  bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty,
636  return 1;
637  }
638 
640  return 0;
641  }
642 
644  return false;
645  }
646 
648  // Note for overrides: You must ensure for all element unordered-atomic
649  // memory intrinsics that all power-of-2 element sizes up to, and
650  // including, the return value of this method have a corresponding
651  // runtime lib call. These runtime lib call definitions can be found
652  // in RuntimeLibcalls.h
653  return 0;
654  }
655 
657  Type *ExpectedType) const {
658  return nullptr;
659  }
660 
662  unsigned SrcAddrSpace, unsigned DestAddrSpace,
663  unsigned SrcAlign, unsigned DestAlign) const {
664  return Type::getInt8Ty(Context);
665  }
666 
669  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
670  unsigned SrcAlign, unsigned DestAlign) const {
671  for (unsigned i = 0; i != RemainingBytes; ++i)
672  OpsOut.push_back(Type::getInt8Ty(Context));
673  }
674 
675  bool areInlineCompatible(const Function *Caller,
676  const Function *Callee) const {
677  return (Caller->getFnAttribute("target-cpu") ==
678  Callee->getFnAttribute("target-cpu")) &&
679  (Caller->getFnAttribute("target-features") ==
680  Callee->getFnAttribute("target-features"));
681  }
682 
684  const Function *Callee,
686  return (Caller->getFnAttribute("target-cpu") ==
687  Callee->getFnAttribute("target-cpu")) &&
688  (Caller->getFnAttribute("target-features") ==
689  Callee->getFnAttribute("target-features"));
690  }
691 
693  const DataLayout &DL) const {
694  return false;
695  }
696 
698  const DataLayout &DL) const {
699  return false;
700  }
701 
702  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; }
703 
704  bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; }
705 
706  bool isLegalToVectorizeStore(StoreInst *SI) const { return true; }
707 
708  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
709  unsigned AddrSpace) const {
710  return true;
711  }
712 
713  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
714  unsigned AddrSpace) const {
715  return true;
716  }
717 
719  ElementCount VF) const {
720  return true;
721  }
722 
723  unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
724  unsigned ChainSizeInBytes,
725  VectorType *VecTy) const {
726  return VF;
727  }
728 
729  unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
730  unsigned ChainSizeInBytes,
731  VectorType *VecTy) const {
732  return VF;
733  }
734 
735  bool preferInLoopReduction(unsigned Opcode, Type *Ty,
736  TTI::ReductionFlags Flags) const {
737  return false;
738  }
739 
740  bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
741  TTI::ReductionFlags Flags) const {
742  return false;
743  }
744 
745  bool shouldExpandReduction(const IntrinsicInst *II) const { return true; }
746 
747  unsigned getGISelRematGlobalCost() const { return 1; }
748 
749  bool supportsScalableVectors() const { return false; }
750 
751  bool hasActiveVectorLength() const { return false; }
752 
756  /* EVLParamStrategy */ TargetTransformInfo::VPLegalization::Discard,
757  /* OperatorStrategy */ TargetTransformInfo::VPLegalization::Convert);
758  }
759 
760 protected:
761  // Obtain the minimum required size to hold the value (without the sign)
762  // In case of a vector it returns the min required size for one element.
763  unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const {
764  if (isa<ConstantDataVector>(Val) || isa<ConstantVector>(Val)) {
765  const auto *VectorValue = cast<Constant>(Val);
766 
767  // In case of a vector need to pick the max between the min
768  // required size for each element
769  auto *VT = cast<FixedVectorType>(Val->getType());
770 
771  // Assume unsigned elements
772  isSigned = false;
773 
774  // The max required size is the size of the vector element type
775  unsigned MaxRequiredSize =
776  VT->getElementType()->getPrimitiveSizeInBits().getFixedSize();
777 
778  unsigned MinRequiredSize = 0;
779  for (unsigned i = 0, e = VT->getNumElements(); i < e; ++i) {
780  if (auto *IntElement =
781  dyn_cast<ConstantInt>(VectorValue->getAggregateElement(i))) {
782  bool signedElement = IntElement->getValue().isNegative();
783  // Get the element min required size.
784  unsigned ElementMinRequiredSize =
785  IntElement->getValue().getMinSignedBits() - 1;
786  // In case one element is signed then all the vector is signed.
787  isSigned |= signedElement;
788  // Save the max required bit size between all the elements.
789  MinRequiredSize = std::max(MinRequiredSize, ElementMinRequiredSize);
790  } else {
791  // not an int constant element
792  return MaxRequiredSize;
793  }
794  }
795  return MinRequiredSize;
796  }
797 
798  if (const auto *CI = dyn_cast<ConstantInt>(Val)) {
799  isSigned = CI->getValue().isNegative();
800  return CI->getValue().getMinSignedBits() - 1;
801  }
802 
803  if (const auto *Cast = dyn_cast<SExtInst>(Val)) {
804  isSigned = true;
805  return Cast->getSrcTy()->getScalarSizeInBits() - 1;
806  }
807 
808  if (const auto *Cast = dyn_cast<ZExtInst>(Val)) {
809  isSigned = false;
810  return Cast->getSrcTy()->getScalarSizeInBits();
811  }
812 
813  isSigned = false;
814  return Val->getType()->getScalarSizeInBits();
815  }
816 
817  bool isStridedAccess(const SCEV *Ptr) const {
818  return Ptr && isa<SCEVAddRecExpr>(Ptr);
819  }
820 
822  const SCEV *Ptr) const {
823  if (!isStridedAccess(Ptr))
824  return nullptr;
825  const SCEVAddRecExpr *AddRec = cast<SCEVAddRecExpr>(Ptr);
826  return dyn_cast<SCEVConstant>(AddRec->getStepRecurrence(*SE));
827  }
828 
830  int64_t MergeDistance) const {
831  const SCEVConstant *Step = getConstantStrideStep(SE, Ptr);
832  if (!Step)
833  return false;
834  APInt StrideVal = Step->getAPInt();
835  if (StrideVal.getBitWidth() > 64)
836  return false;
837  // FIXME: Need to take absolute value for negative stride case.
838  return StrideVal.getSExtValue() < MergeDistance;
839  }
840 };
841 
842 /// CRTP base class for use as a mix-in that aids implementing
843 /// a TargetTransformInfo-compatible class.
844 template <typename T>
846 private:
848 
849 protected:
851 
852 public:
853  using BaseT::getGEPCost;
854 
856  getGEPCost(Type *PointeeType, const Value *Ptr,
859  assert(PointeeType && Ptr && "can't get GEPCost of nullptr");
860  // TODO: will remove this when pointers have an opaque type.
862  PointeeType &&
863  "explicit pointee type doesn't match operand's pointee type");
864  auto *BaseGV = dyn_cast<GlobalValue>(Ptr->stripPointerCasts());
865  bool HasBaseReg = (BaseGV == nullptr);
866 
867  auto PtrSizeBits = DL.getPointerTypeSizeInBits(Ptr->getType());
868  APInt BaseOffset(PtrSizeBits, 0);
869  int64_t Scale = 0;
870 
871  auto GTI = gep_type_begin(PointeeType, Operands);
872  Type *TargetType = nullptr;
873 
874  // Handle the case where the GEP instruction has a single operand,
875  // the basis, therefore TargetType is a nullptr.
876  if (Operands.empty())
877  return !BaseGV ? TTI::TCC_Free : TTI::TCC_Basic;
878 
879  for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
880  TargetType = GTI.getIndexedType();
881  // We assume that the cost of Scalar GEP with constant index and the
882  // cost of Vector GEP with splat constant index are the same.
883  const ConstantInt *ConstIdx = dyn_cast<ConstantInt>(*I);
884  if (!ConstIdx)
885  if (auto Splat = getSplatValue(*I))
886  ConstIdx = dyn_cast<ConstantInt>(Splat);
887  if (StructType *STy = GTI.getStructTypeOrNull()) {
888  // For structures the index is always splat or scalar constant
889  assert(ConstIdx && "Unexpected GEP index");
890  uint64_t Field = ConstIdx->getZExtValue();
891  BaseOffset += DL.getStructLayout(STy)->getElementOffset(Field);
892  } else {
893  // If this operand is a scalable type, bail out early.
894  // TODO: handle scalable vectors
895  if (isa<ScalableVectorType>(TargetType))
896  return TTI::TCC_Basic;
897  int64_t ElementSize =
898  DL.getTypeAllocSize(GTI.getIndexedType()).getFixedSize();
899  if (ConstIdx) {
900  BaseOffset +=
901  ConstIdx->getValue().sextOrTrunc(PtrSizeBits) * ElementSize;
902  } else {
903  // Needs scale register.
904  if (Scale != 0)
905  // No addressing mode takes two scale registers.
906  return TTI::TCC_Basic;
907  Scale = ElementSize;
908  }
909  }
910  }
911 
912  if (static_cast<T *>(this)->isLegalAddressingMode(
913  TargetType, const_cast<GlobalValue *>(BaseGV),
914  BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale,
915  Ptr->getType()->getPointerAddressSpace()))
916  return TTI::TCC_Free;
917  return TTI::TCC_Basic;
918  }
919 
922  auto *TargetTTI = static_cast<T *>(this);
923  // Handle non-intrinsic calls, invokes, and callbr.
924  // FIXME: Unlikely to be true for anything but CodeSize.
925  auto *CB = dyn_cast<CallBase>(U);
926  if (CB && !isa<IntrinsicInst>(U)) {
927  if (const Function *F = CB->getCalledFunction()) {
928  if (!TargetTTI->isLoweredToCall(F))
929  return TTI::TCC_Basic; // Give a basic cost if it will be lowered
930 
931  return TTI::TCC_Basic * (F->getFunctionType()->getNumParams() + 1);
932  }
933  // For indirect or other calls, scale cost by number of arguments.
934  return TTI::TCC_Basic * (CB->arg_size() + 1);
935  }
936 
937  Type *Ty = U->getType();
938  Type *OpTy =
939  U->getNumOperands() == 1 ? U->getOperand(0)->getType() : nullptr;
940  unsigned Opcode = Operator::getOpcode(U);
941  auto *I = dyn_cast<Instruction>(U);
942  switch (Opcode) {
943  default:
944  break;
945  case Instruction::Call: {
946  assert(isa<IntrinsicInst>(U) && "Unexpected non-intrinsic call");
947  auto *Intrinsic = cast<IntrinsicInst>(U);
948  IntrinsicCostAttributes CostAttrs(Intrinsic->getIntrinsicID(), *CB);
949  return TargetTTI->getIntrinsicInstrCost(CostAttrs, CostKind);
950  }
951  case Instruction::Br:
952  case Instruction::Ret:
953  case Instruction::PHI:
954  case Instruction::Switch:
955  return TargetTTI->getCFInstrCost(Opcode, CostKind, I);
956  case Instruction::ExtractValue:
957  case Instruction::Freeze:
958  return TTI::TCC_Free;
959  case Instruction::Alloca:
960  if (cast<AllocaInst>(U)->isStaticAlloca())
961  return TTI::TCC_Free;
962  break;
963  case Instruction::GetElementPtr: {
964  const GEPOperator *GEP = cast<GEPOperator>(U);
965  return TargetTTI->getGEPCost(GEP->getSourceElementType(),
966  GEP->getPointerOperand(),
967  Operands.drop_front());
968  }
969  case Instruction::Add:
970  case Instruction::FAdd:
971  case Instruction::Sub:
972  case Instruction::FSub:
973  case Instruction::Mul:
974  case Instruction::FMul:
975  case Instruction::UDiv:
976  case Instruction::SDiv:
977  case Instruction::FDiv:
978  case Instruction::URem:
979  case Instruction::SRem:
980  case Instruction::FRem:
981  case Instruction::Shl:
982  case Instruction::LShr:
983  case Instruction::AShr:
984  case Instruction::And:
985  case Instruction::Or:
986  case Instruction::Xor:
987  case Instruction::FNeg: {
990  TTI::OperandValueKind Op1VK =
991  TTI::getOperandInfo(U->getOperand(0), Op1VP);
992  TTI::OperandValueKind Op2VK = Opcode != Instruction::FNeg ?
995  return TargetTTI->getArithmeticInstrCost(Opcode, Ty, CostKind,
996  Op1VK, Op2VK,
997  Op1VP, Op2VP, Operands, I);
998  }
999  case Instruction::IntToPtr:
1000  case Instruction::PtrToInt:
1001  case Instruction::SIToFP:
1002  case Instruction::UIToFP:
1003  case Instruction::FPToUI:
1004  case Instruction::FPToSI:
1005  case Instruction::Trunc:
1006  case Instruction::FPTrunc:
1007  case Instruction::BitCast:
1008  case Instruction::FPExt:
1009  case Instruction::SExt:
1010  case Instruction::ZExt:
1011  case Instruction::AddrSpaceCast:
1012  return TargetTTI->getCastInstrCost(
1013  Opcode, Ty, OpTy, TTI::getCastContextHint(I), CostKind, I);
1014  case Instruction::Store: {
1015  auto *SI = cast<StoreInst>(U);
1016  Type *ValTy = U->getOperand(0)->getType();
1017  return TargetTTI->getMemoryOpCost(Opcode, ValTy, SI->getAlign(),
1018  SI->getPointerAddressSpace(),
1019  CostKind, I);
1020  }
1021  case Instruction::Load: {
1022  auto *LI = cast<LoadInst>(U);
1023  return TargetTTI->getMemoryOpCost(Opcode, U->getType(), LI->getAlign(),
1024  LI->getPointerAddressSpace(),
1025  CostKind, I);
1026  }
1027  case Instruction::Select: {
1028  const Value *Op0, *Op1;
1029  if (match(U, m_LogicalAnd(m_Value(Op0), m_Value(Op1))) ||
1030  match(U, m_LogicalOr(m_Value(Op0), m_Value(Op1)))) {
1031  // select x, y, false --> x & y
1032  // select x, true, y --> x | y
1035  TTI::OperandValueKind Op1VK = TTI::getOperandInfo(Op0, Op1VP);
1036  TTI::OperandValueKind Op2VK = TTI::getOperandInfo(Op1, Op2VP);
1037  assert(Op0->getType()->getScalarSizeInBits() == 1 &&
1038  Op1->getType()->getScalarSizeInBits() == 1);
1039 
1041  return TargetTTI->getArithmeticInstrCost(
1042  match(U, m_LogicalOr()) ? Instruction::Or : Instruction::And, Ty,
1043  CostKind, Op1VK, Op2VK, Op1VP, Op2VP, Operands, I);
1044  }
1045  Type *CondTy = U->getOperand(0)->getType();
1046  return TargetTTI->getCmpSelInstrCost(Opcode, U->getType(), CondTy,
1048  CostKind, I);
1049  }
1050  case Instruction::ICmp:
1051  case Instruction::FCmp: {
1052  Type *ValTy = U->getOperand(0)->getType();
1053  // TODO: Also handle ICmp/FCmp constant expressions.
1054  return TargetTTI->getCmpSelInstrCost(Opcode, ValTy, U->getType(),
1055  I ? cast<CmpInst>(I)->getPredicate()
1057  CostKind, I);
1058  }
1059  case Instruction::InsertElement: {
1060  auto *IE = dyn_cast<InsertElementInst>(U);
1061  if (!IE)
1062  return TTI::TCC_Basic; // FIXME
1063  auto *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1064  unsigned Idx = CI ? CI->getZExtValue() : -1;
1065  return TargetTTI->getVectorInstrCost(Opcode, Ty, Idx);
1066  }
1067  case Instruction::ShuffleVector: {
1068  auto *Shuffle = dyn_cast<ShuffleVectorInst>(U);
1069  if (!Shuffle)
1070  return TTI::TCC_Basic; // FIXME
1071  auto *VecTy = cast<VectorType>(U->getType());
1072  auto *VecSrcTy = cast<VectorType>(U->getOperand(0)->getType());
1073 
1074  // TODO: Identify and add costs for insert subvector, etc.
1075  int SubIndex;
1076  if (Shuffle->isExtractSubvectorMask(SubIndex))
1077  return TargetTTI->getShuffleCost(TTI::SK_ExtractSubvector, VecSrcTy,
1078  Shuffle->getShuffleMask(), SubIndex,
1079  VecTy);
1080  else if (Shuffle->changesLength())
1081  return CostKind == TTI::TCK_RecipThroughput ? -1 : 1;
1082  else if (Shuffle->isIdentity())
1083  return 0;
1084  else if (Shuffle->isReverse())
1085  return TargetTTI->getShuffleCost(TTI::SK_Reverse, VecTy,
1086  Shuffle->getShuffleMask(), 0, nullptr);
1087  else if (Shuffle->isSelect())
1088  return TargetTTI->getShuffleCost(TTI::SK_Select, VecTy,
1089  Shuffle->getShuffleMask(), 0, nullptr);
1090  else if (Shuffle->isTranspose())
1091  return TargetTTI->getShuffleCost(TTI::SK_Transpose, VecTy,
1092  Shuffle->getShuffleMask(), 0, nullptr);
1093  else if (Shuffle->isZeroEltSplat())
1094  return TargetTTI->getShuffleCost(TTI::SK_Broadcast, VecTy,
1095  Shuffle->getShuffleMask(), 0, nullptr);
1096  else if (Shuffle->isSingleSource())
1097  return TargetTTI->getShuffleCost(TTI::SK_PermuteSingleSrc, VecTy,
1098  Shuffle->getShuffleMask(), 0, nullptr);
1099 
1100  return TargetTTI->getShuffleCost(TTI::SK_PermuteTwoSrc, VecTy,
1101  Shuffle->getShuffleMask(), 0, nullptr);
1102  }
1103  case Instruction::ExtractElement: {
1104  unsigned Idx = -1;
1105  auto *EEI = dyn_cast<ExtractElementInst>(U);
1106  if (!EEI)
1107  return TTI::TCC_Basic; // FIXME
1108 
1109  auto *CI = dyn_cast<ConstantInt>(EEI->getOperand(1));
1110  if (CI)
1111  Idx = CI->getZExtValue();
1112 
1113  // Try to match a reduction (a series of shufflevector and vector ops
1114  // followed by an extractelement).
1115  unsigned RdxOpcode;
1116  VectorType *RdxType;
1117  bool IsPairwise;
1118  switch (TTI::matchVectorReduction(EEI, RdxOpcode, RdxType, IsPairwise)) {
1119  case TTI::RK_Arithmetic:
1120  return TargetTTI->getArithmeticReductionCost(RdxOpcode, RdxType,
1121  IsPairwise, CostKind);
1122  case TTI::RK_MinMax:
1123  return TargetTTI->getMinMaxReductionCost(
1124  RdxType, cast<VectorType>(CmpInst::makeCmpResultType(RdxType)),
1125  IsPairwise, /*IsUnsigned=*/false, CostKind);
1127  return TargetTTI->getMinMaxReductionCost(
1128  RdxType, cast<VectorType>(CmpInst::makeCmpResultType(RdxType)),
1129  IsPairwise, /*IsUnsigned=*/true, CostKind);
1130  case TTI::RK_None:
1131  break;
1132  }
1133  return TargetTTI->getVectorInstrCost(Opcode, U->getOperand(0)->getType(),
1134  Idx);
1135  }
1136  }
1137  // By default, just classify everything as 'basic'.
1138  return TTI::TCC_Basic;
1139  }
1140 
1142  SmallVector<const Value *, 4> Operands(I->operand_values());
1143  if (getUserCost(I, Operands, TTI::TCK_Latency) == TTI::TCC_Free)
1144  return 0;
1145 
1146  if (isa<LoadInst>(I))
1147  return 4;
1148 
1149  Type *DstTy = I->getType();
1150 
1151  // Usually an intrinsic is a simple instruction.
1152  // A real function call is much slower.
1153  if (auto *CI = dyn_cast<CallInst>(I)) {
1154  const Function *F = CI->getCalledFunction();
1155  if (!F || static_cast<T *>(this)->isLoweredToCall(F))
1156  return 40;
1157  // Some intrinsics return a value and a flag, we use the value type
1158  // to decide its latency.
1159  if (StructType *StructTy = dyn_cast<StructType>(DstTy))
1160  DstTy = StructTy->getElementType(0);
1161  // Fall through to simple instructions.
1162  }
1163 
1164  if (VectorType *VectorTy = dyn_cast<VectorType>(DstTy))
1165  DstTy = VectorTy->getElementType();
1166  if (DstTy->isFloatingPointTy())
1167  return 3;
1168 
1169  return 1;
1170  }
1171 };
1172 } // namespace llvm
1173 
1174 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::InstructionCost
Definition: InstructionCost.h:26
llvm::TargetTransformInfo::CacheLevel::L1D
@ L1D
llvm::orc::BaseT
RTTIExtends< ObjectLinkingLayer, ObjectLayer > BaseT
Definition: ObjectLinkingLayer.cpp:568
llvm::TargetTransformInfoImplBase::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfoImpl.h:412
llvm::TargetTransformInfo::SK_Select
@ SK_Select
Selects elements from the corresponding lane of either source operand.
Definition: TargetTransformInfo.h:853
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:210
llvm::TargetTransformInfoImplBase::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Definition: TargetTransformInfoImpl.h:152
llvm::TargetTransformInfo::LSRCost::NumRegs
unsigned NumRegs
Definition: TargetTransformInfo.h:413
llvm::TargetTransformInfo::TCC_Expensive
@ TCC_Expensive
The cost of a 'div' instruction on x86.
Definition: TargetTransformInfo.h:263
llvm
Definition: AllocatorList.h:23
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1340
llvm::TargetTransformInfoImplBase::useAA
bool useAA() const
Definition: TargetTransformInfoImpl.h:290
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::TargetTransformInfoImplBase::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI) const
Definition: TargetTransformInfoImpl.h:158
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1291
llvm::TargetTransformInfo::TCK_Latency
@ TCK_Latency
The latency of instruction.
Definition: TargetTransformInfo.h:212
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:722
llvm::TargetTransformInfoImplBase::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfoImpl.h:109
llvm::TargetTransformInfoImplBase::isStridedAccess
bool isStridedAccess(const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:817
IntrinsicInst.h
llvm::Type::isPointerTy
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:229
llvm::ElementCount
Definition: TypeSize.h:386
llvm::TargetTransformInfoImplBase::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfoImpl.h:396
llvm::TypeSize::getFixedSize
ScalarTy getFixedSize() const
Definition: TypeSize.h:426
llvm::Function
Definition: Function.h:61
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::TargetTransformInfoImplBase::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:197
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:586
llvm::TargetTransformInfoImplCRTPBase::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:920
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
GetElementPtrTypeIterator.h
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:317
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:131
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1167
llvm::TargetTransformInfoImplBase::getExtendedAddReductionCost
InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfoImpl.h:633
llvm::TargetTransformInfoImplBase::isLSRCostLess
bool isLSRCostLess(TTI::LSRCost &C1, TTI::LSRCost &C2) const
Definition: TargetTransformInfoImpl.h:207
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1643
llvm::TargetTransformInfoImplBase::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Definition: TargetTransformInfoImpl.h:263
llvm::TargetTransformInfoImplBase::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *, const SCEV *) const
Definition: TargetTransformInfoImpl.h:618
llvm::TargetTransformInfoImplBase::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Definition: TargetTransformInfoImpl.h:100
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:350
llvm::CmpInst::makeCmpResultType
static Type * makeCmpResultType(Type *opnd_type)
Create a result type for fcmp/icmp.
Definition: InstrTypes.h:1034
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:167
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:728
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:443
llvm::TargetTransformInfoImplBase::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfoImpl.h:394
llvm::TargetTransformInfoImplBase::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfoImpl.h:76
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:151
llvm::TargetTransformInfoImplBase::TTI
TargetTransformInfo TTI
Definition: TargetTransformInfoImpl.h:36
llvm::TargetTransformInfoImplBase::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:273
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1383
llvm::TargetTransformInfo::LSRCost::NumIVMuls
unsigned NumIVMuls
Definition: TargetTransformInfo.h:415
llvm::TargetTransformInfoImplBase::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:379
llvm::TargetTransformInfoImplBase::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:702
llvm::TargetTransformInfoImplBase::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Definition: TargetTransformInfoImpl.h:338
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1581
llvm::TargetTransformInfo::VPLegalization::Convert
@ Convert
Definition: TargetTransformInfo.h:1390
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:529
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfoImpl.h:706
llvm::TargetTransformInfoImplBase::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Definition: TargetTransformInfoImpl.h:288
llvm::Optional
Definition: APInt.h:33
T
#define T
Definition: Mips16ISelLowering.cpp:341
Operator.h
llvm::TargetTransformInfoImplBase::areFunctionArgsABICompatible
bool areFunctionArgsABICompatible(const Function *Caller, const Function *Callee, SmallPtrSetImpl< Argument * > &Args) const
Definition: TargetTransformInfoImpl.h:683
llvm::TargetTransformInfoImplBase::hasActiveVectorLength
bool hasActiveVectorLength() const
Definition: TargetTransformInfoImpl.h:751
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::TargetTransformInfoImplBase::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Definition: TargetTransformInfoImpl.h:94
llvm::TargetTransformInfoImplBase::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:355
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:40
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::gep_type_begin
gep_type_iterator gep_type_begin(const User *GEP)
Definition: GetElementPtrTypeIterator.h:139
llvm::Type::isFloatingPointTy
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:163
llvm::TargetTransformInfoImplBase::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:257
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetTransformInfo::SK_PermuteSingleSrc
@ SK_PermuteSingleSrc
Shuffle elements of single source vector with any shuffle mask.
Definition: TargetTransformInfo.h:861
llvm::TargetTransformInfoImplBase::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Definition: TargetTransformInfoImpl.h:342
llvm::Type::getInt8Ty
static IntegerType * getInt8Ty(LLVMContext &C)
Definition: Type.cpp:195
llvm::TargetTransformInfoImplBase::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:326
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:299
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:970
llvm::TargetTransformInfoImplBase::getConstantStrideStep
const SCEVConstant * getConstantStrideStep(ScalarEvolution *SE, const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:821
llvm::TargetTransformInfoImplCRTPBase::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency)
Definition: TargetTransformInfoImpl.h:856
llvm::TargetTransformInfoImplBase::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Definition: TargetTransformInfoImpl.h:102
llvm::TargetTransformInfo::SK_Broadcast
@ SK_Broadcast
Broadcast element 0 to all other elements.
Definition: TargetTransformInfo.h:851
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::TargetTransformInfo::LSRCost::AddRecCost
unsigned AddRecCost
Definition: TargetTransformInfo.h:414
llvm::TargetTransformInfoImplBase::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Definition: TargetTransformInfoImpl.h:286
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:48
llvm::TargetTransformInfoImplBase::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfoImpl.h:675
llvm::TargetTransformInfoImplBase::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfoImpl.h:400
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::TargetTransformInfo::LSRCost::SetupCost
unsigned SetupCost
Definition: TargetTransformInfo.h:418
llvm::TargetTransformInfoImplBase::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Definition: TargetTransformInfoImpl.h:214
llvm::TargetTransformInfoImplBase::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
Definition: TargetTransformInfoImpl.h:88
llvm::TargetTransformInfoImplBase::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, bool *Fast) const
Definition: TargetTransformInfoImpl.h:332
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:77
llvm::TargetTransformInfoImplBase::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Definition: TargetTransformInfoImpl.h:265
llvm::TargetTransformInfo::SK_PermuteTwoSrc
@ SK_PermuteTwoSrc
Merge elements from two source vectors into one with any shuffle mask.
Definition: TargetTransformInfo.h:859
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::LinearPolySize< ElementCount >::get
static ElementCount get(ScalarTy MinVal, bool Scalable)
Definition: TypeSize.h:290
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:731
llvm::TargetTransformInfoImplBase::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfoImpl.h:446
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg)
Definition: TargetTransformInfoImpl.h:46
llvm::TargetTransformInfoImplBase
Base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:34
llvm::TargetTransformInfoImplBase::getCacheAssociativity
llvm::Optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:426
llvm::PatternMatch::match
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
llvm::TargetTransformInfoImplBase::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfoImpl.h:437
llvm::TargetTransformInfoImplBase::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:373
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:908
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:850
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1084
llvm::TargetTransformInfoImplBase::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:231
llvm::User
Definition: User.h:44
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetTransformInfoImplBase::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Definition: TargetTransformInfoImpl.h:298
llvm::TargetTransformInfoImplBase::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const
Definition: TargetTransformInfoImpl.h:537
llvm::TargetTransformInfoImplBase::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfoImpl.h:661
llvm::TargetTransformInfoImplBase::hasBranchDivergence
bool hasBranchDivergence() const
Definition: TargetTransformInfoImpl.h:92
llvm::TargetTransformInfoImplBase::isIndexedStoreLegal
bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:697
llvm::TargetTransformInfoImplBase::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Definition: TargetTransformInfoImpl.h:296
llvm::Instruction
Definition: Instruction.h:45
llvm::TargetTransformInfo::RK_Arithmetic
@ RK_Arithmetic
Not a reduction.
Definition: TargetTransformInfo.h:868
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:147
llvm::TargetTransformInfoImplBase::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfoImpl.h:616
llvm::TargetTransformInfoImplBase::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
Definition: TargetTransformInfoImpl.h:360
llvm::Operator::getOpcode
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
Definition: Operator.h:40
llvm::TargetTransformInfoImplBase::isTypeLegal
bool isTypeLegal(Type *Ty) const
Definition: TargetTransformInfoImpl.h:292
llvm::TargetTransformInfoImplBase::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:199
llvm::TargetTransformInfoImplBase::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:521
llvm::TargetTransformInfoImplBase::getRegUsageForType
InstructionCost getRegUsageForType(Type *Ty) const
Definition: TargetTransformInfoImpl.h:294
llvm::TargetTransformInfoImplBase::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfoImpl.h:656
llvm::TargetTransformInfo::matchVectorReduction
static ReductionKind matchVectorReduction(const ExtractElementInst *ReduxRoot, unsigned &Opcode, VectorType *&Ty, bool &IsPairwise)
Definition: TargetTransformInfo.cpp:1330
llvm::TargetTransformInfoImplCRTPBase
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:845
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetTransformInfoImplBase::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:267
PatternMatch.h
llvm::TargetTransformInfoImplBase::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:639
llvm::TargetTransformInfoImplBase::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfoImpl.h:444
llvm::TargetTransformInfoImplBase::enableMemCmpExpansion
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfoImpl.h:321
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:153
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::TargetTransformInfoImplBase::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Definition: TargetTransformInfoImpl.h:96
llvm::TargetTransformInfoImplBase::getVPLegalizationStrategy
TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: TargetTransformInfoImpl.h:754
llvm::TargetTransformInfoImplBase::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:549
llvm::None
const NoneType None
Definition: None.h:23
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:284
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
Type.h
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:117
llvm::TargetTransformInfo::RK_UnsignedMinMax
@ RK_UnsignedMinMax
Min/max reduction data.
Definition: TargetTransformInfo.h:870
llvm::TargetTransformInfoImplBase::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:555
llvm::TargetTransformInfo::PSK_Software
@ PSK_Software
Definition: TargetTransformInfo.h:586
llvm::TargetTransformInfoImplBase::getCacheSize
llvm::Optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:415
llvm::TargetTransformInfoImplBase::emitGetActiveLaneMask
bool emitGetActiveLaneMask() const
Definition: TargetTransformInfoImpl.h:165
llvm::TargetTransformInfoImplBase::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfoImpl.h:216
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::ARM_PROC::IE
@ IE
Definition: ARMBaseInfo.h:27
llvm::TargetTransformInfoImplBase::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: TargetTransformInfoImpl.h:181
llvm::TargetTransformInfoImplBase::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:740
llvm::TargetTransformInfoImplBase::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfoImpl.h:749
llvm::TargetTransformInfoImplBase::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:328
llvm::TargetTransformInfo::SK_Reverse
@ SK_Reverse
Reverse the order of the vector.
Definition: TargetTransformInfo.h:852
llvm::TargetTransformInfoImplCRTPBase::TargetTransformInfoImplCRTPBase
TargetTransformInfoImplCRTPBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:850
llvm::TargetTransformInfoImplBase::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:610
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:391
VectorUtils.h
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:78
llvm::TargetTransformInfoImplBase::canMacroFuseCmp
bool canMacroFuseCmp() const
Definition: TargetTransformInfoImpl.h:218
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:303
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfoImplBase::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfoImpl.h:63
llvm::TargetTransformInfoImplBase::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:239
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::TargetTransformInfoImplBase::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth() const
Definition: TargetTransformInfoImpl.h:398
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:409
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:713
llvm::PatternMatch::m_LogicalOr
LogicalOp_match< LHS, RHS, Instruction::Or > m_LogicalOr(const LHS &L, const RHS &R)
Matches L || R either in the form of L | R or L ? true : R.
Definition: PatternMatch.h:2506
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::TargetTransformInfoImplBase::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Definition: TargetTransformInfoImpl.h:175
llvm::TargetTransformInfoImplBase::getPreferredAddressingMode
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Definition: TargetTransformInfoImpl.h:227
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:423
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfoImplBase::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:477
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:908
llvm::LoopAccessInfo
Drive the analysis of memory accesses in the loop.
Definition: LoopAccessAnalysis.h:519
llvm::SCEVConstant
This class represents a constant integer value.
Definition: ScalarEvolutionExpressions.h:47
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetTransformInfo::VPLegalization::Discard
@ Discard
Definition: TargetTransformInfo.h:1388
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::TargetTransformInfoImplBase::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfoImpl.h:406
llvm::TargetTransformInfoImplBase::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Definition: TargetTransformInfoImpl.h:116
llvm::CmpInst::BAD_ICMP_PREDICATE
@ BAD_ICMP_PREDICATE
Definition: InstrTypes.h:755
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::TargetTransformInfo::LSRCost::ScaleCost
unsigned ScaleCost
Definition: TargetTransformInfo.h:419
llvm::TargetTransformInfoImplBase::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:310
llvm::TargetTransformInfoImplBase::getInterleavedMemoryOpCost
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) const
Definition: TargetTransformInfoImpl.h:563
llvm::TargetTransformInfoImplBase::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfoImpl.h:643
llvm::TargetTransformInfoImplBase::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Definition: TargetTransformInfoImpl.h:317
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:900
llvm::GEPOperator
Definition: Operator.h:457
llvm::PatternMatch::m_Value
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:76
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::TargetTransformInfoImplBase::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned, unsigned) const
Definition: TargetTransformInfoImpl.h:107
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:752
llvm::TargetTransformInfoImplBase::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:246
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:261
llvm::TargetTransformInfoImplBase::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfoImpl.h:745
llvm::TargetTransformInfoImplBase::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfoImpl.h:73
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1080
DataLayout.h
llvm::StructType
Class to represent struct types.
Definition: DerivedTypes.h:212
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:41
llvm::TargetTransformInfo::TCK_SizeAndLatency
@ TCK_SizeAndLatency
The weighted sum of size and latency.
Definition: TargetTransformInfo.h:214
llvm::TargetTransformInfoImplBase::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfoImpl.h:747
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::TargetTransformInfoImplCRTPBase::getInstructionLatency
InstructionCost getInstructionLatency(const Instruction *I)
Definition: TargetTransformInfoImpl.h:1141
llvm::TargetTransformInfoImplBase::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Definition: TargetTransformInfoImpl.h:284
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::TargetTransformInfoImplBase::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Definition: TargetTransformInfoImpl.h:304
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetTransformInfoImplBase::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
Definition: TargetTransformInfoImpl.h:315
llvm::TargetTransformInfoImplBase::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Definition: TargetTransformInfoImpl.h:344
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::TargetTransformInfoImplBase::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:530
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:633
llvm::TargetTransformInfoImplBase::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:235
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:418
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:901
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:281
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:174
llvm::TargetTransformInfo::SK_Transpose
@ SK_Transpose
Transpose two vectors.
Definition: TargetTransformInfo.h:856
llvm::TargetTransformInfoImplBase::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfoImpl.h:667
llvm::Value::stripPointerCasts
const Value * stripPointerCasts() const
Strip off pointer casts, all-zero GEPs and address space casts.
Definition: Value.cpp:662
llvm::TargetTransformInfo::CacheLevel::L2D
@ L2D
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:140
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:206
llvm::TargetTransformInfoImplBase::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr) const
Definition: TargetTransformInfoImpl.h:448
llvm::TargetTransformInfoImplBase::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc, ElementCount VF) const
Definition: TargetTransformInfoImpl.h:718
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:162
llvm::TargetTransformInfoImplBase::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:735
llvm::TargetTransformInfoImplBase::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned, VectorType *, bool, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:623
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::KnownBits
Definition: KnownBits.h:23
llvm::TargetTransformInfoImplBase::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef< int > Mask, int Index, VectorType *SubTp) const
Definition: TargetTransformInfoImpl.h:471
llvm::TargetTransformInfo::LSRCost::NumBaseAdds
unsigned NumBaseAdds
Definition: TargetTransformInfo.h:416
llvm::TargetTransformInfoImplBase::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfoImpl.h:647
llvm::TargetTransformInfoImplBase::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfoImpl.h:443
llvm::TargetTransformInfoImplBase::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:367
llvm::TargetTransformInfoImplBase::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfoImpl.h:78
llvm::TargetTransformInfoImplBase::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Definition: TargetTransformInfoImpl.h:111
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:390
VPLegalization
TargetTransformInfo::VPLegalization VPLegalization
Definition: ExpandVectorPredication.cpp:36
llvm::APInt::sextOrTrunc
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:960
llvm::TargetTransformInfoImplBase::minRequiredElementSize
unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const
Definition: TargetTransformInfoImpl.h:763
llvm::TypeSize
Definition: TypeSize.h:417
llvm::SCEVAddRecExpr
This node represents a polynomial recurrence on the trip count of the specified loop.
Definition: ScalarEvolutionExpressions.h:352
Function.h
llvm::TargetTransformInfoImplBase::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:723
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::TargetTransformInfoImplBase::isIndexedLoadLegal
bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:692
llvm::TargetTransformInfoImplBase::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Definition: TargetTransformInfoImpl.h:438
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:219
llvm::User::operand_values
iterator_range< value_op_iterator > operand_values()
Definition: User.h:266
llvm::TargetTransformInfo::LSRCost::ImmCost
unsigned ImmCost
Definition: TargetTransformInfo.h:417
llvm::TargetTransformInfoImplBase::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:195
llvm::TargetTransformInfoImplBase::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:542
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:183
llvm::TargetTransformInfoImplBase::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfoImpl.h:375
llvm::TargetTransformInfoImplBase::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: TargetTransformInfoImpl.h:390
llvm::TargetTransformInfoImplBase::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Definition: TargetTransformInfoImpl.h:220
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfoImplBase::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: TargetTransformInfoImpl.h:169
llvm::SCEVConstant::getAPInt
const APInt & getAPInt() const
Definition: ScalarEvolutionExpressions.h:57
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:94
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::TargetTransformInfoImplBase::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
Definition: TargetTransformInfoImpl.h:515
llvm::TargetTransformInfoImplBase::isConstantStridedAccessLessThan
bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
Definition: TargetTransformInfoImpl.h:829
llvm::TargetTransformInfoImplBase::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Definition: TargetTransformInfoImpl.h:330
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
ScalarEvolutionExpressions.h
llvm::TargetTransformInfoImplBase::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfoImpl.h:98
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:67
llvm::TargetTransformInfoImplBase::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Definition: TargetTransformInfoImpl.h:261
llvm::User::getNumOperands
unsigned getNumOperands() const
Definition: User.h:191
llvm::IntrinsicCostAttributes::getID
Intrinsic::ID getID() const
Definition: TargetTransformInfo.h:147
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:929
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfoImpl.h:704
llvm::Type::getPointerElementType
Type * getPointerElementType() const
Definition: Type.h:378
llvm::TargetTransformInfo::RK_MinMax
@ RK_MinMax
Binary reduction data.
Definition: TargetTransformInfo.h:869
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
TargetTransformInfo.h
llvm::TargetTransformInfoImplBase::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *, VectorType *, bool, bool, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:628
llvm::PatternMatch
Definition: PatternMatch.h:47
llvm::SmallVectorImpl< int >
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:69
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1164
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
llvm::TargetTransformInfo::RK_None
@ RK_None
Definition: TargetTransformInfo.h:867
llvm::TargetTransformInfoImplBase::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:729
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:708
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:171
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(const TargetTransformInfoImplBase &Arg)
Definition: TargetTransformInfoImpl.h:44
llvm::TargetTransformInfoImplBase::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:253
llvm::TargetTransformInfo::getOperandInfo
static OperandValueKind getOperandInfo(const Value *V, OperandValueProperties &OpProps)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:659
llvm::TargetTransformInfo::TCC_Basic
@ TCC_Basic
The cost of a typical 'add' instruction.
Definition: TargetTransformInfo.h:262
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3179
llvm::OptimizedStructLayoutField
A field in a structure.
Definition: OptimizedStructLayout.h:45
llvm::TargetTransformInfoImplBase::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Definition: TargetTransformInfoImpl.h:300
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::TargetTransformInfoImplBase::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfoImpl.h:74
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3035
llvm::TargetTransformInfoImplBase::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:570
llvm::TargetTransformInfoImplBase::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Definition: TargetTransformInfoImpl.h:271
llvm::TargetTransformInfoImplBase::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Definition: TargetTransformInfoImpl.h:302
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:211
llvm::TargetTransformInfoImplBase::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
Definition: TargetTransformInfoImpl.h:350
llvm::TargetTransformInfo::AMK_None
@ AMK_None
Definition: TargetTransformInfo.h:636
llvm::TargetTransformInfo::SK_ExtractSubvector
@ SK_ExtractSubvector
ExtractSubvector Index indicates start offset.
Definition: TargetTransformInfo.h:858
llvm::PatternMatch::m_LogicalAnd
LogicalOp_match< LHS, RHS, Instruction::And > m_LogicalAnd(const LHS &L, const RHS &R)
Matches L && R either in the form of L & R or L ? R : false.
Definition: PatternMatch.h:2495
llvm::TargetTransformInfoImplBase::getPeelingPreferences
void getPeelingPreferences(Loop *, ScalarEvolution &, TTI::PeelingPreferences &) const
Definition: TargetTransformInfoImpl.h:192
llvm::TargetTransformInfoImplBase::getUnrollingPreferences
void getUnrollingPreferences(Loop *, ScalarEvolution &, TTI::UnrollingPreferences &) const
Definition: TargetTransformInfoImpl.h:189
llvm::SCEVAddRecExpr::getStepRecurrence
const SCEV * getStepRecurrence(ScalarEvolution &SE) const
Constructs and returns the recurrence indicating how much this expression steps by.
Definition: ScalarEvolutionExpressions.h:369
llvm::TargetTransformInfoImplBase::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfoImpl.h:404
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::TargetTransformInfoImplBase::getFPOpCost
InstructionCost getFPOpCost(Type *Ty) const
Definition: TargetTransformInfoImpl.h:346