LLVM  16.0.0git
TargetTransformInfoImpl.h
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1 //===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file provides helpers for the implementation of
10 /// a TargetTransformInfo-conforming class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
15 #define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
16 
20 #include "llvm/IR/DataLayout.h"
22 #include "llvm/IR/IntrinsicInst.h"
23 #include "llvm/IR/Operator.h"
24 #include "llvm/IR/PatternMatch.h"
25 #include <utility>
26 
27 namespace llvm {
28 
29 class Function;
30 
31 /// Base class for use as a mix-in that aids implementing
32 /// a TargetTransformInfo-compatible class.
34 protected:
36 
37  const DataLayout &DL;
38 
40 
41 public:
42  // Provide value semantics. MSVC requires that we spell all of these out.
45 
46  const DataLayout &getDataLayout() const { return DL; }
47 
48  InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr,
51  // In the basic model, we just assume that all-constant GEPs will be folded
52  // into their uses via addressing modes.
53  for (const Value *Operand : Operands)
54  if (!isa<Constant>(Operand))
55  return TTI::TCC_Basic;
56 
57  return TTI::TCC_Free;
58  }
59 
61  unsigned &JTSize,
62  ProfileSummaryInfo *PSI,
63  BlockFrequencyInfo *BFI) const {
64  (void)PSI;
65  (void)BFI;
66  JTSize = 0;
67  return SI.getNumCases();
68  }
69 
70  unsigned getInliningThresholdMultiplier() const { return 1; }
71  unsigned adjustInliningThreshold(const CallBase *CB) const { return 0; }
72 
73  int getInlinerVectorBonusPercent() const { return 150; }
74 
76  return TTI::TCC_Expensive;
77  }
78 
79  // Although this default value is arbitrary, it is not random. It is assumed
80  // that a condition that evaluates the same way by a higher percentage than
81  // this is best represented as control flow. Therefore, the default value N
82  // should be set such that the win from N% correct executions is greater than
83  // the loss from (100 - N)% mispredicted executions for the majority of
84  // intended targets.
86  return BranchProbability(99, 100);
87  }
88 
89  bool hasBranchDivergence() const { return false; }
90 
91  bool useGPUDivergenceAnalysis() const { return false; }
92 
93  bool isSourceOfDivergence(const Value *V) const { return false; }
94 
95  bool isAlwaysUniform(const Value *V) const { return false; }
96 
97  unsigned getFlatAddressSpace() const { return -1; }
98 
100  Intrinsic::ID IID) const {
101  return false;
102  }
103 
104  bool isNoopAddrSpaceCast(unsigned, unsigned) const { return false; }
106  return AS == 0;
107  };
108 
109  unsigned getAssumedAddrSpace(const Value *V) const { return -1; }
110 
111  bool isSingleThreaded() const { return false; }
112 
113  std::pair<const Value *, unsigned>
114  getPredicatedAddrSpace(const Value *V) const {
115  return std::make_pair(nullptr, -1);
116  }
117 
119  Value *NewV) const {
120  return nullptr;
121  }
122 
123  bool isLoweredToCall(const Function *F) const {
124  assert(F && "A concrete function must be provided to this routine.");
125 
126  // FIXME: These should almost certainly not be handled here, and instead
127  // handled with the help of TLI or the target itself. This was largely
128  // ported from existing analysis heuristics here so that such refactorings
129  // can take place in the future.
130 
131  if (F->isIntrinsic())
132  return false;
133 
134  if (F->hasLocalLinkage() || !F->hasName())
135  return true;
136 
137  StringRef Name = F->getName();
138 
139  // These will all likely lower to a single selection DAG node.
140  if (Name == "copysign" || Name == "copysignf" || Name == "copysignl" ||
141  Name == "fabs" || Name == "fabsf" || Name == "fabsl" || Name == "sin" ||
142  Name == "fmin" || Name == "fminf" || Name == "fminl" ||
143  Name == "fmax" || Name == "fmaxf" || Name == "fmaxl" ||
144  Name == "sinf" || Name == "sinl" || Name == "cos" || Name == "cosf" ||
145  Name == "cosl" || Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl")
146  return false;
147 
148  // These are all likely to be optimized into something smaller.
149  if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" ||
150  Name == "exp2l" || Name == "exp2f" || Name == "floor" ||
151  Name == "floorf" || Name == "ceil" || Name == "round" ||
152  Name == "ffs" || Name == "ffsl" || Name == "abs" || Name == "labs" ||
153  Name == "llabs")
154  return false;
155 
156  return true;
157  }
158 
160  AssumptionCache &AC, TargetLibraryInfo *LibInfo,
161  HardwareLoopInfo &HWLoopInfo) const {
162  return false;
163  }
164 
167  DominatorTree *DT,
169  InterleavedAccessInfo *IAI) const {
170  return false;
171  }
172 
174  return PredicationStyle::None;
175  }
176 
178  IntrinsicInst &II) const {
179  return None;
180  }
181 
184  APInt DemandedMask, KnownBits &Known,
185  bool &KnownBitsComputed) const {
186  return None;
187  }
188 
190  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
191  APInt &UndefElts2, APInt &UndefElts3,
192  std::function<void(Instruction *, unsigned, APInt, APInt &)>
193  SimplifyAndSetOp) const {
194  return None;
195  }
196 
199  OptimizationRemarkEmitter *) const {}
200 
202  TTI::PeelingPreferences &) const {}
203 
204  bool isLegalAddImmediate(int64_t Imm) const { return false; }
205 
206  bool isLegalICmpImmediate(int64_t Imm) const { return false; }
207 
208  bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
209  bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
210  Instruction *I = nullptr) const {
211  // Guess that only reg and reg+reg addressing is allowed. This heuristic is
212  // taken from the implementation of LSR.
213  return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
214  }
215 
216  bool isLSRCostLess(const TTI::LSRCost &C1, const TTI::LSRCost &C2) const {
217  return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
218  C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
219  std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
220  C2.ScaleCost, C2.ImmCost, C2.SetupCost);
221  }
222 
223  bool isNumRegsMajorCostOfLSR() const { return true; }
224 
225  bool isProfitableLSRChainElement(Instruction *I) const { return false; }
226 
227  bool canMacroFuseCmp() const { return false; }
228 
231  TargetLibraryInfo *LibInfo) const {
232  return false;
233  }
234 
237  return TTI::AMK_None;
238  }
239 
240  bool isLegalMaskedStore(Type *DataType, Align Alignment) const {
241  return false;
242  }
243 
244  bool isLegalMaskedLoad(Type *DataType, Align Alignment) const {
245  return false;
246  }
247 
248  bool isLegalNTStore(Type *DataType, Align Alignment) const {
249  // By default, assume nontemporal memory stores are available for stores
250  // that are aligned and have a size that is a power of 2.
251  unsigned DataSize = DL.getTypeStoreSize(DataType);
252  return Alignment >= DataSize && isPowerOf2_32(DataSize);
253  }
254 
255  bool isLegalNTLoad(Type *DataType, Align Alignment) const {
256  // By default, assume nontemporal memory loads are available for loads that
257  // are aligned and have a size that is a power of 2.
258  unsigned DataSize = DL.getTypeStoreSize(DataType);
259  return Alignment >= DataSize && isPowerOf2_32(DataSize);
260  }
261 
262  bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const {
263  return false;
264  }
265 
266  bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
267  return false;
268  }
269 
270  bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
271  return false;
272  }
273 
274  bool forceScalarizeMaskedGather(VectorType *DataType, Align Alignment) const {
275  return false;
276  }
277 
279  Align Alignment) const {
280  return false;
281  }
282 
283  bool isLegalMaskedCompressStore(Type *DataType) const { return false; }
284 
285  bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
286  const SmallBitVector &OpcodeMask) const {
287  return false;
288  }
289 
290  bool isLegalMaskedExpandLoad(Type *DataType) const { return false; }
291 
292  bool enableOrderedReductions() const { return false; }
293 
294  bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; }
295 
296  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const {
297  return false;
298  }
299 
300  bool prefersVectorizedAddressing() const { return true; }
301 
303  int64_t BaseOffset, bool HasBaseReg,
304  int64_t Scale,
305  unsigned AddrSpace) const {
306  // Guess that all legal addressing mode are free.
307  if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
308  AddrSpace))
309  return 0;
310  return -1;
311  }
312 
313  bool LSRWithInstrQueries() const { return false; }
314 
315  bool isTruncateFree(Type *Ty1, Type *Ty2) const { return false; }
316 
317  bool isProfitableToHoist(Instruction *I) const { return true; }
318 
319  bool useAA() const { return false; }
320 
321  bool isTypeLegal(Type *Ty) const { return false; }
322 
323  unsigned getRegUsageForType(Type *Ty) const { return 1; }
324 
325  bool shouldBuildLookupTables() const { return true; }
326 
327  bool shouldBuildLookupTablesForConstant(Constant *C) const { return true; }
328 
329  bool shouldBuildRelLookupTables() const { return false; }
330 
331  bool useColdCCForColdCall(Function &F) const { return false; }
332 
334  const APInt &DemandedElts,
335  bool Insert, bool Extract) const {
336  return 0;
337  }
338 
340  ArrayRef<Type *> Tys) const {
341  return 0;
342  }
343 
344  bool supportsEfficientVectorElementLoadStore() const { return false; }
345 
346  bool supportsTailCalls() const { return true; }
347 
348  bool supportsTailCallFor(const CallBase *CB) const {
349  return supportsTailCalls();
350  }
351 
352  bool enableAggressiveInterleaving(bool LoopHasReductions) const {
353  return false;
354  }
355 
357  bool IsZeroCmp) const {
358  return {};
359  }
360 
361  bool enableInterleavedAccessVectorization() const { return false; }
362 
363  bool enableMaskedInterleavedAccessVectorization() const { return false; }
364 
365  bool isFPVectorizationPotentiallyUnsafe() const { return false; }
366 
368  unsigned AddressSpace, Align Alignment,
369  unsigned *Fast) const {
370  return false;
371  }
372 
373  TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const {
374  return TTI::PSK_Software;
375  }
376 
377  bool haveFastSqrt(Type *Ty) const { return false; }
378 
379  bool isExpensiveToSpeculativelyExecute(const Instruction *I) { return true; }
380 
381  bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; }
382 
385  }
386 
387  InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
388  const APInt &Imm, Type *Ty) const {
389  return 0;
390  }
391 
394  return TTI::TCC_Basic;
395  }
396 
397  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
398  const APInt &Imm, Type *Ty,
400  Instruction *Inst = nullptr) const {
401  return TTI::TCC_Free;
402  }
403 
405  const APInt &Imm, Type *Ty,
407  return TTI::TCC_Free;
408  }
409 
410  unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; }
411 
412  unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
413  return Vector ? 1 : 0;
414  };
415 
416  const char *getRegisterClassName(unsigned ClassID) const {
417  switch (ClassID) {
418  default:
419  return "Generic::Unknown Register Class";
420  case 0:
421  return "Generic::ScalarRC";
422  case 1:
423  return "Generic::VectorRC";
424  }
425  }
426 
428  return TypeSize::getFixed(32);
429  }
430 
431  unsigned getMinVectorRegisterBitWidth() const { return 128; }
432 
435 
436  bool
438  return false;
439  }
440 
441  ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const {
442  return ElementCount::get(0, IsScalable);
443  }
444 
445  unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const { return 0; }
446  unsigned getStoreMinimumVF(unsigned VF, Type *, Type *) const { return VF; }
447 
449  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
450  AllowPromotionWithoutCommonHeader = false;
451  return false;
452  }
453 
454  unsigned getCacheLineSize() const { return 0; }
455 
458  switch (Level) {
460  [[fallthrough]];
462  return llvm::None;
463  }
464  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
465  }
466 
469  switch (Level) {
471  [[fallthrough]];
473  return llvm::None;
474  }
475 
476  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
477  }
478 
479  unsigned getPrefetchDistance() const { return 0; }
480  unsigned getMinPrefetchStride(unsigned NumMemAccesses,
481  unsigned NumStridedMemAccesses,
482  unsigned NumPrefetches, bool HasCall) const {
483  return 1;
484  }
485  unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; }
486  bool enableWritePrefetching() const { return false; }
487  bool shouldPrefetchAddressSpace(unsigned AS) const { return !AS; }
488 
489  unsigned getMaxInterleaveFactor(unsigned VF) const { return 1; }
490 
492  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
493  TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info,
495  const Instruction *CxtI = nullptr) const {
496  // FIXME: A number of transformation tests seem to require these values
497  // which seems a little odd for how arbitary there are.
498  switch (Opcode) {
499  default:
500  break;
501  case Instruction::FDiv:
502  case Instruction::FRem:
503  case Instruction::SDiv:
504  case Instruction::SRem:
505  case Instruction::UDiv:
506  case Instruction::URem:
507  // FIXME: Unlikely to be true for CodeSize.
508  return TTI::TCC_Expensive;
509  }
510 
511  // Assume a 3cy latency for fp arithmetic ops.
512  if (CostKind == TTI::TCK_Latency)
513  if (Ty->getScalarType()->isFloatingPointTy())
514  return 3;
515 
516  return 1;
517  }
518 
522  VectorType *SubTp,
524  return 1;
525  }
526 
527  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
530  const Instruction *I) const {
531  switch (Opcode) {
532  default:
533  break;
534  case Instruction::IntToPtr: {
535  unsigned SrcSize = Src->getScalarSizeInBits();
536  if (DL.isLegalInteger(SrcSize) &&
537  SrcSize <= DL.getPointerTypeSizeInBits(Dst))
538  return 0;
539  break;
540  }
541  case Instruction::PtrToInt: {
542  unsigned DstSize = Dst->getScalarSizeInBits();
543  if (DL.isLegalInteger(DstSize) &&
544  DstSize >= DL.getPointerTypeSizeInBits(Src))
545  return 0;
546  break;
547  }
548  case Instruction::BitCast:
549  if (Dst == Src || (Dst->isPointerTy() && Src->isPointerTy()))
550  // Identity and pointer-to-pointer casts are free.
551  return 0;
552  break;
553  case Instruction::Trunc: {
554  // trunc to a native type is free (assuming the target has compare and
555  // shift-right of the same width).
556  TypeSize DstSize = DL.getTypeSizeInBits(Dst);
557  if (!DstSize.isScalable() && DL.isLegalInteger(DstSize.getFixedSize()))
558  return 0;
559  break;
560  }
561  }
562  return 1;
563  }
564 
566  VectorType *VecTy,
567  unsigned Index) const {
568  return 1;
569  }
570 
572  const Instruction *I = nullptr) const {
573  // A phi would be free, unless we're costing the throughput because it
574  // will require a register.
576  return 0;
577  return 1;
578  }
579 
580  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
581  CmpInst::Predicate VecPred,
583  const Instruction *I) const {
584  return 1;
585  }
586 
587  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
588  unsigned Index) const {
589  return 1;
590  }
591 
593  unsigned Index) const {
594  return 1;
595  }
596 
597  unsigned getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF,
598  const APInt &DemandedDstElts,
600  return 1;
601  }
602 
603  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
604  unsigned AddressSpace,
606  TTI::OperandValueInfo OpInfo,
607  const Instruction *I) const {
608  return 1;
609  }
610 
611  InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
612  unsigned AddressSpace,
614  const Instruction *I) const {
615  return 1;
616  }
617 
619  Align Alignment, unsigned AddressSpace,
621  return 1;
622  }
623 
624  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
625  const Value *Ptr, bool VariableMask,
626  Align Alignment,
628  const Instruction *I = nullptr) const {
629  return 1;
630  }
631 
633  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
634  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
635  bool UseMaskForCond, bool UseMaskForGaps) const {
636  return 1;
637  }
638 
641  switch (ICA.getID()) {
642  default:
643  break;
644  case Intrinsic::annotation:
645  case Intrinsic::assume:
646  case Intrinsic::sideeffect:
647  case Intrinsic::pseudoprobe:
648  case Intrinsic::arithmetic_fence:
649  case Intrinsic::dbg_declare:
650  case Intrinsic::dbg_value:
651  case Intrinsic::dbg_label:
652  case Intrinsic::invariant_start:
653  case Intrinsic::invariant_end:
654  case Intrinsic::launder_invariant_group:
655  case Intrinsic::strip_invariant_group:
656  case Intrinsic::is_constant:
657  case Intrinsic::lifetime_start:
658  case Intrinsic::lifetime_end:
659  case Intrinsic::experimental_noalias_scope_decl:
660  case Intrinsic::objectsize:
661  case Intrinsic::ptr_annotation:
662  case Intrinsic::var_annotation:
663  case Intrinsic::experimental_gc_result:
664  case Intrinsic::experimental_gc_relocate:
665  case Intrinsic::coro_alloc:
666  case Intrinsic::coro_begin:
667  case Intrinsic::coro_free:
668  case Intrinsic::coro_end:
669  case Intrinsic::coro_frame:
670  case Intrinsic::coro_size:
671  case Intrinsic::coro_align:
672  case Intrinsic::coro_suspend:
673  case Intrinsic::coro_subfn_addr:
674  case Intrinsic::threadlocal_address:
675  // These intrinsics don't actually represent code after lowering.
676  return 0;
677  }
678  return 1;
679  }
680 
682  ArrayRef<Type *> Tys,
684  return 1;
685  }
686 
687  // Assume that we have a register of the right size for the type.
688  unsigned getNumberOfParts(Type *Tp) const { return 1; }
689 
691  const SCEV *) const {
692  return 0;
693  }
694 
697  TTI::TargetCostKind) const {
698  return 1;
699  }
700 
702  TTI::TargetCostKind) const {
703  return 1;
704  }
705 
706  InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned,
707  Type *ResTy, VectorType *Ty,
710  return 1;
711  }
712 
713  InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy,
714  VectorType *Ty,
716  return 1;
717  }
718 
720  return 0;
721  }
722 
724  return false;
725  }
726 
728  // Note for overrides: You must ensure for all element unordered-atomic
729  // memory intrinsics that all power-of-2 element sizes up to, and
730  // including, the return value of this method have a corresponding
731  // runtime lib call. These runtime lib call definitions can be found
732  // in RuntimeLibcalls.h
733  return 0;
734  }
735 
737  Type *ExpectedType) const {
738  return nullptr;
739  }
740 
742  unsigned SrcAddrSpace, unsigned DestAddrSpace,
743  unsigned SrcAlign, unsigned DestAlign,
744  Optional<uint32_t> AtomicElementSize) const {
745  return AtomicElementSize ? Type::getIntNTy(Context, *AtomicElementSize * 8)
747  }
748 
751  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
752  unsigned SrcAlign, unsigned DestAlign,
753  Optional<uint32_t> AtomicCpySize) const {
754  unsigned OpSizeInBytes = AtomicCpySize ? *AtomicCpySize : 1;
755  Type *OpType = Type::getIntNTy(Context, OpSizeInBytes * 8);
756  for (unsigned i = 0; i != RemainingBytes; i += OpSizeInBytes)
757  OpsOut.push_back(OpType);
758  }
759 
760  bool areInlineCompatible(const Function *Caller,
761  const Function *Callee) const {
762  return (Caller->getFnAttribute("target-cpu") ==
763  Callee->getFnAttribute("target-cpu")) &&
764  (Caller->getFnAttribute("target-features") ==
765  Callee->getFnAttribute("target-features"));
766  }
767 
768  bool areTypesABICompatible(const Function *Caller, const Function *Callee,
769  const ArrayRef<Type *> &Types) const {
770  return (Caller->getFnAttribute("target-cpu") ==
771  Callee->getFnAttribute("target-cpu")) &&
772  (Caller->getFnAttribute("target-features") ==
773  Callee->getFnAttribute("target-features"));
774  }
775 
777  const DataLayout &DL) const {
778  return false;
779  }
780 
782  const DataLayout &DL) const {
783  return false;
784  }
785 
786  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; }
787 
788  bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; }
789 
790  bool isLegalToVectorizeStore(StoreInst *SI) const { return true; }
791 
792  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
793  unsigned AddrSpace) const {
794  return true;
795  }
796 
797  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
798  unsigned AddrSpace) const {
799  return true;
800  }
801 
803  ElementCount VF) const {
804  return true;
805  }
806 
807  bool isElementTypeLegalForScalableVector(Type *Ty) const { return true; }
808 
809  unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
810  unsigned ChainSizeInBytes,
811  VectorType *VecTy) const {
812  return VF;
813  }
814 
815  unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
816  unsigned ChainSizeInBytes,
817  VectorType *VecTy) const {
818  return VF;
819  }
820 
821  bool preferInLoopReduction(unsigned Opcode, Type *Ty,
822  TTI::ReductionFlags Flags) const {
823  return false;
824  }
825 
826  bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
827  TTI::ReductionFlags Flags) const {
828  return false;
829  }
830 
832  return true;
833  }
834 
835  bool shouldExpandReduction(const IntrinsicInst *II) const { return true; }
836 
837  unsigned getGISelRematGlobalCost() const { return 1; }
838 
839  unsigned getMinTripCountTailFoldingThreshold() const { return 0; }
840 
841  bool supportsScalableVectors() const { return false; }
842 
843  bool enableScalableVectorization() const { return false; }
844 
845  bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
846  Align Alignment) const {
847  return false;
848  }
849 
853  /* EVLParamStrategy */ TargetTransformInfo::VPLegalization::Discard,
854  /* OperatorStrategy */ TargetTransformInfo::VPLegalization::Convert);
855  }
856 
857 protected:
858  // Obtain the minimum required size to hold the value (without the sign)
859  // In case of a vector it returns the min required size for one element.
860  unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const {
861  if (isa<ConstantDataVector>(Val) || isa<ConstantVector>(Val)) {
862  const auto *VectorValue = cast<Constant>(Val);
863 
864  // In case of a vector need to pick the max between the min
865  // required size for each element
866  auto *VT = cast<FixedVectorType>(Val->getType());
867 
868  // Assume unsigned elements
869  isSigned = false;
870 
871  // The max required size is the size of the vector element type
872  unsigned MaxRequiredSize =
873  VT->getElementType()->getPrimitiveSizeInBits().getFixedSize();
874 
875  unsigned MinRequiredSize = 0;
876  for (unsigned i = 0, e = VT->getNumElements(); i < e; ++i) {
877  if (auto *IntElement =
878  dyn_cast<ConstantInt>(VectorValue->getAggregateElement(i))) {
879  bool signedElement = IntElement->getValue().isNegative();
880  // Get the element min required size.
881  unsigned ElementMinRequiredSize =
882  IntElement->getValue().getMinSignedBits() - 1;
883  // In case one element is signed then all the vector is signed.
884  isSigned |= signedElement;
885  // Save the max required bit size between all the elements.
886  MinRequiredSize = std::max(MinRequiredSize, ElementMinRequiredSize);
887  } else {
888  // not an int constant element
889  return MaxRequiredSize;
890  }
891  }
892  return MinRequiredSize;
893  }
894 
895  if (const auto *CI = dyn_cast<ConstantInt>(Val)) {
896  isSigned = CI->getValue().isNegative();
897  return CI->getValue().getMinSignedBits() - 1;
898  }
899 
900  if (const auto *Cast = dyn_cast<SExtInst>(Val)) {
901  isSigned = true;
902  return Cast->getSrcTy()->getScalarSizeInBits() - 1;
903  }
904 
905  if (const auto *Cast = dyn_cast<ZExtInst>(Val)) {
906  isSigned = false;
907  return Cast->getSrcTy()->getScalarSizeInBits();
908  }
909 
910  isSigned = false;
911  return Val->getType()->getScalarSizeInBits();
912  }
913 
914  bool isStridedAccess(const SCEV *Ptr) const {
915  return Ptr && isa<SCEVAddRecExpr>(Ptr);
916  }
917 
919  const SCEV *Ptr) const {
920  if (!isStridedAccess(Ptr))
921  return nullptr;
922  const SCEVAddRecExpr *AddRec = cast<SCEVAddRecExpr>(Ptr);
923  return dyn_cast<SCEVConstant>(AddRec->getStepRecurrence(*SE));
924  }
925 
927  int64_t MergeDistance) const {
928  const SCEVConstant *Step = getConstantStrideStep(SE, Ptr);
929  if (!Step)
930  return false;
931  APInt StrideVal = Step->getAPInt();
932  if (StrideVal.getBitWidth() > 64)
933  return false;
934  // FIXME: Need to take absolute value for negative stride case.
935  return StrideVal.getSExtValue() < MergeDistance;
936  }
937 };
938 
939 /// CRTP base class for use as a mix-in that aids implementing
940 /// a TargetTransformInfo-compatible class.
941 template <typename T>
943 private:
945 
946 protected:
948 
949 public:
950  using BaseT::getGEPCost;
951 
952  InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr,
955  assert(PointeeType && Ptr && "can't get GEPCost of nullptr");
956  assert(cast<PointerType>(Ptr->getType()->getScalarType())
957  ->isOpaqueOrPointeeTypeMatches(PointeeType) &&
958  "explicit pointee type doesn't match operand's pointee type");
959  auto *BaseGV = dyn_cast<GlobalValue>(Ptr->stripPointerCasts());
960  bool HasBaseReg = (BaseGV == nullptr);
961 
962  auto PtrSizeBits = DL.getPointerTypeSizeInBits(Ptr->getType());
963  APInt BaseOffset(PtrSizeBits, 0);
964  int64_t Scale = 0;
965 
966  auto GTI = gep_type_begin(PointeeType, Operands);
967  Type *TargetType = nullptr;
968 
969  // Handle the case where the GEP instruction has a single operand,
970  // the basis, therefore TargetType is a nullptr.
971  if (Operands.empty())
972  return !BaseGV ? TTI::TCC_Free : TTI::TCC_Basic;
973 
974  for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
975  TargetType = GTI.getIndexedType();
976  // We assume that the cost of Scalar GEP with constant index and the
977  // cost of Vector GEP with splat constant index are the same.
978  const ConstantInt *ConstIdx = dyn_cast<ConstantInt>(*I);
979  if (!ConstIdx)
980  if (auto Splat = getSplatValue(*I))
981  ConstIdx = dyn_cast<ConstantInt>(Splat);
982  if (StructType *STy = GTI.getStructTypeOrNull()) {
983  // For structures the index is always splat or scalar constant
984  assert(ConstIdx && "Unexpected GEP index");
985  uint64_t Field = ConstIdx->getZExtValue();
986  BaseOffset += DL.getStructLayout(STy)->getElementOffset(Field);
987  } else {
988  // If this operand is a scalable type, bail out early.
989  // TODO: handle scalable vectors
990  if (isa<ScalableVectorType>(TargetType))
991  return TTI::TCC_Basic;
992  int64_t ElementSize =
993  DL.getTypeAllocSize(GTI.getIndexedType()).getFixedSize();
994  if (ConstIdx) {
995  BaseOffset +=
996  ConstIdx->getValue().sextOrTrunc(PtrSizeBits) * ElementSize;
997  } else {
998  // Needs scale register.
999  if (Scale != 0)
1000  // No addressing mode takes two scale registers.
1001  return TTI::TCC_Basic;
1002  Scale = ElementSize;
1003  }
1004  }
1005  }
1006 
1007  if (static_cast<T *>(this)->isLegalAddressingMode(
1008  TargetType, const_cast<GlobalValue *>(BaseGV),
1009  BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale,
1010  Ptr->getType()->getPointerAddressSpace()))
1011  return TTI::TCC_Free;
1012  return TTI::TCC_Basic;
1013  }
1014 
1018  using namespace llvm::PatternMatch;
1019 
1020  auto *TargetTTI = static_cast<T *>(this);
1021  // Handle non-intrinsic calls, invokes, and callbr.
1022  // FIXME: Unlikely to be true for anything but CodeSize.
1023  auto *CB = dyn_cast<CallBase>(U);
1024  if (CB && !isa<IntrinsicInst>(U)) {
1025  if (const Function *F = CB->getCalledFunction()) {
1026  if (!TargetTTI->isLoweredToCall(F))
1027  return TTI::TCC_Basic; // Give a basic cost if it will be lowered
1028 
1029  return TTI::TCC_Basic * (F->getFunctionType()->getNumParams() + 1);
1030  }
1031  // For indirect or other calls, scale cost by number of arguments.
1032  return TTI::TCC_Basic * (CB->arg_size() + 1);
1033  }
1034 
1035  Type *Ty = U->getType();
1036  unsigned Opcode = Operator::getOpcode(U);
1037  auto *I = dyn_cast<Instruction>(U);
1038  switch (Opcode) {
1039  default:
1040  break;
1041  case Instruction::Call: {
1042  assert(isa<IntrinsicInst>(U) && "Unexpected non-intrinsic call");
1043  auto *Intrinsic = cast<IntrinsicInst>(U);
1044  IntrinsicCostAttributes CostAttrs(Intrinsic->getIntrinsicID(), *CB);
1045  return TargetTTI->getIntrinsicInstrCost(CostAttrs, CostKind);
1046  }
1047  case Instruction::Br:
1048  case Instruction::Ret:
1049  case Instruction::PHI:
1050  case Instruction::Switch:
1051  return TargetTTI->getCFInstrCost(Opcode, CostKind, I);
1052  case Instruction::ExtractValue:
1053  case Instruction::Freeze:
1054  return TTI::TCC_Free;
1055  case Instruction::Alloca:
1056  if (cast<AllocaInst>(U)->isStaticAlloca())
1057  return TTI::TCC_Free;
1058  break;
1059  case Instruction::GetElementPtr: {
1060  const auto *GEP = cast<GEPOperator>(U);
1061  return TargetTTI->getGEPCost(GEP->getSourceElementType(),
1062  GEP->getPointerOperand(),
1063  Operands.drop_front(), CostKind);
1064  }
1065  case Instruction::Add:
1066  case Instruction::FAdd:
1067  case Instruction::Sub:
1068  case Instruction::FSub:
1069  case Instruction::Mul:
1070  case Instruction::FMul:
1071  case Instruction::UDiv:
1072  case Instruction::SDiv:
1073  case Instruction::FDiv:
1074  case Instruction::URem:
1075  case Instruction::SRem:
1076  case Instruction::FRem:
1077  case Instruction::Shl:
1078  case Instruction::LShr:
1079  case Instruction::AShr:
1080  case Instruction::And:
1081  case Instruction::Or:
1082  case Instruction::Xor:
1083  case Instruction::FNeg: {
1084  const TTI::OperandValueInfo Op1Info = TTI::getOperandInfo(U->getOperand(0));
1085  TTI::OperandValueInfo Op2Info;
1086  if (Opcode != Instruction::FNeg)
1087  Op2Info = TTI::getOperandInfo(U->getOperand(1));
1089  return TargetTTI->getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
1090  Op2Info, Operands, I);
1091  }
1092  case Instruction::IntToPtr:
1093  case Instruction::PtrToInt:
1094  case Instruction::SIToFP:
1095  case Instruction::UIToFP:
1096  case Instruction::FPToUI:
1097  case Instruction::FPToSI:
1098  case Instruction::Trunc:
1099  case Instruction::FPTrunc:
1100  case Instruction::BitCast:
1101  case Instruction::FPExt:
1102  case Instruction::SExt:
1103  case Instruction::ZExt:
1104  case Instruction::AddrSpaceCast: {
1105  Type *OpTy = U->getOperand(0)->getType();
1106  return TargetTTI->getCastInstrCost(
1107  Opcode, Ty, OpTy, TTI::getCastContextHint(I), CostKind, I);
1108  }
1109  case Instruction::Store: {
1110  auto *SI = cast<StoreInst>(U);
1111  Type *ValTy = U->getOperand(0)->getType();
1113  return TargetTTI->getMemoryOpCost(Opcode, ValTy, SI->getAlign(),
1114  SI->getPointerAddressSpace(), CostKind,
1115  OpInfo, I);
1116  }
1117  case Instruction::Load: {
1118  // FIXME: Arbitary cost which could come from the backend.
1119  if (CostKind == TTI::TCK_Latency)
1120  return 4;
1121  auto *LI = cast<LoadInst>(U);
1122  Type *LoadType = U->getType();
1123  // If there is a non-register sized type, the cost estimation may expand
1124  // it to be several instructions to load into multiple registers on the
1125  // target. But, if the only use of the load is a trunc instruction to a
1126  // register sized type, the instruction selector can combine these
1127  // instructions to be a single load. So, in this case, we use the
1128  // destination type of the trunc instruction rather than the load to
1129  // accurately estimate the cost of this load instruction.
1130  if (CostKind == TTI::TCK_CodeSize && LI->hasOneUse() &&
1131  !LoadType->isVectorTy()) {
1132  if (const TruncInst *TI = dyn_cast<TruncInst>(*LI->user_begin()))
1133  LoadType = TI->getDestTy();
1134  }
1135  return TargetTTI->getMemoryOpCost(Opcode, LoadType, LI->getAlign(),
1137  {TTI::OK_AnyValue, TTI::OP_None}, I);
1138  }
1139  case Instruction::Select: {
1140  const Value *Op0, *Op1;
1141  if (match(U, m_LogicalAnd(m_Value(Op0), m_Value(Op1))) ||
1142  match(U, m_LogicalOr(m_Value(Op0), m_Value(Op1)))) {
1143  // select x, y, false --> x & y
1144  // select x, true, y --> x | y
1145  const auto Op1Info = TTI::getOperandInfo(Op0);
1146  const auto Op2Info = TTI::getOperandInfo(Op1);
1147  assert(Op0->getType()->getScalarSizeInBits() == 1 &&
1148  Op1->getType()->getScalarSizeInBits() == 1);
1149 
1151  return TargetTTI->getArithmeticInstrCost(
1152  match(U, m_LogicalOr()) ? Instruction::Or : Instruction::And, Ty,
1153  CostKind, Op1Info, Op2Info, Operands, I);
1154  }
1155  Type *CondTy = U->getOperand(0)->getType();
1156  return TargetTTI->getCmpSelInstrCost(Opcode, U->getType(), CondTy,
1158  CostKind, I);
1159  }
1160  case Instruction::ICmp:
1161  case Instruction::FCmp: {
1162  Type *ValTy = U->getOperand(0)->getType();
1163  // TODO: Also handle ICmp/FCmp constant expressions.
1164  return TargetTTI->getCmpSelInstrCost(Opcode, ValTy, U->getType(),
1165  I ? cast<CmpInst>(I)->getPredicate()
1167  CostKind, I);
1168  }
1169  case Instruction::InsertElement: {
1170  auto *IE = dyn_cast<InsertElementInst>(U);
1171  if (!IE)
1172  return TTI::TCC_Basic; // FIXME
1173  unsigned Idx = -1;
1174  if (auto *CI = dyn_cast<ConstantInt>(IE->getOperand(2)))
1175  if (CI->getValue().getActiveBits() <= 32)
1176  Idx = CI->getZExtValue();
1177  return TargetTTI->getVectorInstrCost(*IE, Ty, Idx);
1178  }
1179  case Instruction::ShuffleVector: {
1180  auto *Shuffle = dyn_cast<ShuffleVectorInst>(U);
1181  if (!Shuffle)
1182  return TTI::TCC_Basic; // FIXME
1183 
1184  auto *VecTy = cast<VectorType>(U->getType());
1185  auto *VecSrcTy = cast<VectorType>(U->getOperand(0)->getType());
1186  int NumSubElts, SubIndex;
1187 
1188  if (Shuffle->changesLength()) {
1189  // Treat a 'subvector widening' as a free shuffle.
1190  if (Shuffle->increasesLength() && Shuffle->isIdentityWithPadding())
1191  return 0;
1192 
1193  if (Shuffle->isExtractSubvectorMask(SubIndex))
1194  return TargetTTI->getShuffleCost(TTI::SK_ExtractSubvector, VecSrcTy,
1195  Shuffle->getShuffleMask(), CostKind,
1196  SubIndex, VecTy, Operands);
1197 
1198  if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1199  return TargetTTI->getShuffleCost(
1200  TTI::SK_InsertSubvector, VecTy, Shuffle->getShuffleMask(),
1201  CostKind, SubIndex,
1202  FixedVectorType::get(VecTy->getScalarType(), NumSubElts),
1203  Operands);
1204 
1205  int ReplicationFactor, VF;
1206  if (Shuffle->isReplicationMask(ReplicationFactor, VF)) {
1207  APInt DemandedDstElts =
1208  APInt::getNullValue(Shuffle->getShuffleMask().size());
1209  for (auto I : enumerate(Shuffle->getShuffleMask())) {
1210  if (I.value() != UndefMaskElem)
1211  DemandedDstElts.setBit(I.index());
1212  }
1213  return TargetTTI->getReplicationShuffleCost(
1214  VecSrcTy->getElementType(), ReplicationFactor, VF,
1215  DemandedDstElts, CostKind);
1216  }
1217 
1218  return CostKind == TTI::TCK_RecipThroughput ? -1 : 1;
1219  }
1220 
1221  if (Shuffle->isIdentity())
1222  return 0;
1223 
1224  if (Shuffle->isReverse())
1225  return TargetTTI->getShuffleCost(TTI::SK_Reverse, VecTy,
1226  Shuffle->getShuffleMask(), CostKind, 0,
1227  nullptr, Operands);
1228 
1229  if (Shuffle->isSelect())
1230  return TargetTTI->getShuffleCost(TTI::SK_Select, VecTy,
1231  Shuffle->getShuffleMask(), CostKind, 0,
1232  nullptr, Operands);
1233 
1234  if (Shuffle->isTranspose())
1235  return TargetTTI->getShuffleCost(TTI::SK_Transpose, VecTy,
1236  Shuffle->getShuffleMask(), CostKind, 0,
1237  nullptr, Operands);
1238 
1239  if (Shuffle->isZeroEltSplat())
1240  return TargetTTI->getShuffleCost(TTI::SK_Broadcast, VecTy,
1241  Shuffle->getShuffleMask(), CostKind, 0,
1242  nullptr, Operands);
1243 
1244  if (Shuffle->isSingleSource())
1245  return TargetTTI->getShuffleCost(TTI::SK_PermuteSingleSrc, VecTy,
1246  Shuffle->getShuffleMask(), CostKind, 0,
1247  nullptr, Operands);
1248 
1249  if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1250  return TargetTTI->getShuffleCost(
1251  TTI::SK_InsertSubvector, VecTy, Shuffle->getShuffleMask(), CostKind,
1252  SubIndex, FixedVectorType::get(VecTy->getScalarType(), NumSubElts),
1253  Operands);
1254 
1255  if (Shuffle->isSplice(SubIndex))
1256  return TargetTTI->getShuffleCost(TTI::SK_Splice, VecTy,
1257  Shuffle->getShuffleMask(), CostKind,
1258  SubIndex, nullptr, Operands);
1259 
1260  return TargetTTI->getShuffleCost(TTI::SK_PermuteTwoSrc, VecTy,
1261  Shuffle->getShuffleMask(), CostKind, 0,
1262  nullptr, Operands);
1263  }
1264  case Instruction::ExtractElement: {
1265  auto *EEI = dyn_cast<ExtractElementInst>(U);
1266  if (!EEI)
1267  return TTI::TCC_Basic; // FIXME
1268  unsigned Idx = -1;
1269  if (auto *CI = dyn_cast<ConstantInt>(EEI->getOperand(1)))
1270  if (CI->getValue().getActiveBits() <= 32)
1271  Idx = CI->getZExtValue();
1272  Type *DstTy = U->getOperand(0)->getType();
1273  return TargetTTI->getVectorInstrCost(*EEI, DstTy, Idx);
1274  }
1275  }
1276 
1277  // By default, just classify everything as 'basic' or -1 to represent that
1278  // don't know the throughput cost.
1280  }
1281 
1283  auto *TargetTTI = static_cast<T *>(this);
1284  SmallVector<const Value *, 4> Ops(I->operand_values());
1285  InstructionCost Cost = TargetTTI->getInstructionCost(
1288  }
1289 };
1290 } // namespace llvm
1291 
1292 #endif
i
i
Definition: README.txt:29
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::CacheLevel::L1D
@ L1D
llvm::TargetTransformInfoImplBase::canHaveNonUndefGlobalInitializerInAddressSpace
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Definition: TargetTransformInfoImpl.h:105
llvm::TargetTransformInfoImplBase::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfoImpl.h:454
llvm::TargetTransformInfo::SK_Select
@ SK_Select
Selects elements from the corresponding lane of either source operand.
Definition: TargetTransformInfo.h:889
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:217
llvm::TargetTransformInfoImplBase::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Definition: TargetTransformInfoImpl.h:159
llvm::TargetTransformInfo::LSRCost::NumRegs
unsigned NumRegs
Definition: TargetTransformInfo.h:406
llvm::TargetTransformInfo::TCC_Expensive
@ TCC_Expensive
The cost of a 'div' instruction on x86.
Definition: TargetTransformInfo.h:245
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1454
llvm::TargetTransformInfoImplBase::getVectorInstrCost
InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, unsigned Index) const
Definition: TargetTransformInfoImpl.h:592
llvm::TargetTransformInfoImplBase::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None) const
Definition: TargetTransformInfoImpl.h:519
llvm::TargetTransformInfoImplBase::useAA
bool useAA() const
Definition: TargetTransformInfoImpl.h:319
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1402
llvm::TargetTransformInfo::TCK_Latency
@ TCK_Latency
The latency of instruction.
Definition: TargetTransformInfo.h:219
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::TargetTransformInfoImplBase::preferEpilogueVectorization
bool preferEpilogueVectorization() const
Definition: TargetTransformInfoImpl.h:831
llvm::TargetTransformInfoImplBase::enableOrderedReductions
bool enableOrderedReductions() const
Definition: TargetTransformInfoImpl.h:292
llvm::TargetTransformInfoImplBase::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfoImpl.h:109
PHI
Rewrite undef for PHI
Definition: AMDGPURewriteUndefForPHI.cpp:101
llvm::TargetTransformInfoImplBase::isStridedAccess
bool isStridedAccess(const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:914
IntrinsicInst.h
llvm::TargetTransformInfoImplBase::isLSRCostLess
bool isLSRCostLess(const TTI::LSRCost &C1, const TTI::LSRCost &C2) const
Definition: TargetTransformInfoImpl.h:216
llvm::ElementCount
Definition: TypeSize.h:404
llvm::TargetTransformInfoImplBase::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfoImpl.h:433
llvm::TypeSize::getFixedSize
ScalarTy getFixedSize() const
Definition: TypeSize.h:444
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:547
llvm::TargetTransformInfoImplBase::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:206
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:585
llvm::DataLayout::getTypeSizeInBits
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:673
llvm::TargetTransformInfoImplCRTPBase::getInstructionCost
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:1015
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
GetElementPtrTypeIterator.h
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:328
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:133
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::DataLayout::getPointerTypeSizeInBits
unsigned getPointerTypeSizeInBits(Type *) const
Layout pointer size, in bits, based on the type.
Definition: DataLayout.cpp:721
llvm::enumerate
detail::enumerator< R > enumerate(R &&TheRange)
Given an input range, returns a new range whose values are are pair (A,B) such that A is the 0-based ...
Definition: STLExtras.h:2238
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1498
llvm::DataLayout::getTypeStoreSize
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Definition: DataLayout.h:474
llvm::TargetTransformInfoImplBase::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Definition: TargetTransformInfoImpl.h:290
llvm::TargetTransformInfoImplBase::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *, const SCEV *) const
Definition: TargetTransformInfoImpl.h:690
llvm::TargetTransformInfoImplBase::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Definition: TargetTransformInfoImpl.h:97
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:371
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:172
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:729
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::LoopVectorizationLegality
LoopVectorizationLegality checks if it is legal to vectorize a loop, and to what vectorization factor...
Definition: LoopVectorizationLegality.h:241
llvm::TargetTransformInfoImplBase::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfoImpl.h:431
llvm::TargetTransformInfoImplBase::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfoImpl.h:73
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:166
llvm::TargetTransformInfoImplBase::TTI
TargetTransformInfo TTI
Definition: TargetTransformInfoImpl.h:35
llvm::TargetTransformInfoImplBase::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:302
llvm::TargetTransformInfo::TCK_CodeSize
@ TCK_CodeSize
Instruction code size.
Definition: TargetTransformInfo.h:220
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1512
llvm::DataLayout::getStructLayout
const StructLayout * getStructLayout(StructType *Ty) const
Returns a StructLayout object, indicating the alignment of the struct, its size, and the offsets of i...
Definition: DataLayout.cpp:678
llvm::TargetTransformInfo::LSRCost::NumIVMuls
unsigned NumIVMuls
Definition: TargetTransformInfo.h:408
llvm::TargetTransformInfoImplBase::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:416
llvm::TargetTransformInfoImplBase::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:786
llvm::TargetTransformInfoImplBase::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Definition: TargetTransformInfoImpl.h:373
llvm::TargetTransformInfoImplBase::getMulAccReductionCost
InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:713
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1431
llvm::TargetTransformInfo::VPLegalization::Convert
@ Convert
Definition: TargetTransformInfo.h:1519
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:528
llvm::TargetTransformInfoImplBase::isLegalAltInstr
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
Definition: TargetTransformInfoImpl.h:285
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfoImpl.h:790
llvm::TargetTransformInfoImplBase::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Definition: TargetTransformInfoImpl.h:317
llvm::Optional
Definition: APInt.h:33
llvm::TargetTransformInfoImplBase::supportsTailCalls
bool supportsTailCalls() const
Definition: TargetTransformInfoImpl.h:346
Vector
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
Operator.h
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
llvm::TargetTransformInfoImplBase::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Definition: TargetTransformInfoImpl.h:91
llvm::TargetTransformInfoImplBase::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:392
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:39
llvm::TargetTransformInfoImplCRTPBase::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:952
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:458
llvm::gep_type_begin
gep_type_iterator gep_type_begin(const User *GEP)
Definition: GetElementPtrTypeIterator.h:123
llvm::TargetTransformInfoImplBase::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *, VectorType *, bool, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:701
llvm::Type::isFloatingPointTy
bool isFloatingPointTy() const
Return true if this is one of the floating-point types.
Definition: Type.h:184
llvm::TargetTransformInfo::OperandValueInfo
Definition: TargetTransformInfo.h:923
llvm::TargetTransformInfoImplBase::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:270
llvm::TargetTransformInfo::SK_PermuteSingleSrc
@ SK_PermuteSingleSrc
Shuffle elements of single source vector with any shuffle mask.
Definition: TargetTransformInfo.h:897
llvm::TargetTransformInfoImplBase::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Definition: TargetTransformInfoImpl.h:377
llvm::Type::getInt8Ty
static IntegerType * getInt8Ty(LLVMContext &C)
Definition: Type.cpp:237
llvm::TargetTransformInfoImplBase::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:361
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:298
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:1020
llvm::TargetTransformInfoImplBase::getConstantStrideStep
const SCEVConstant * getConstantStrideStep(ScalarEvolution *SE, const SCEV *Ptr) const
Definition: TargetTransformInfoImpl.h:918
llvm::TargetTransformInfoImplBase::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Definition: TargetTransformInfoImpl.h:99
llvm::TargetTransformInfo::SK_Broadcast
@ SK_Broadcast
Broadcast element 0 to all other elements.
Definition: TargetTransformInfo.h:887
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::TargetTransformInfo::LSRCost::AddRecCost
unsigned AddRecCost
Definition: TargetTransformInfo.h:407
llvm::TargetTransformInfoImplBase::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Definition: TargetTransformInfoImpl.h:315
llvm::UndefMaskElem
constexpr int UndefMaskElem
Definition: Instructions.h:1995
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:46
llvm::TargetTransformInfoImplBase::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfoImpl.h:760
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:35
llvm::TargetTransformInfoImplBase::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfoImpl.h:441
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::TargetTransformInfo::LSRCost::SetupCost
unsigned SetupCost
Definition: TargetTransformInfo.h:411
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetTransformInfoImplBase::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Definition: TargetTransformInfoImpl.h:223
llvm::TargetTransformInfoImplBase::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: TargetTransformInfoImpl.h:802
llvm::TargetTransformInfoImplBase::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, LoopVectorizationLegality *LVL, InterleavedAccessInfo *IAI) const
Definition: TargetTransformInfoImpl.h:165
llvm::TargetTransformInfoImplBase::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
Definition: TargetTransformInfoImpl.h:85
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::TargetTransformInfoImplBase::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Definition: TargetTransformInfoImpl.h:294
llvm::TargetTransformInfo::SK_PermuteTwoSrc
@ SK_PermuteTwoSrc
Merge elements from two source vectors into one with any shuffle mask.
Definition: TargetTransformInfo.h:895
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::LinearPolySize< ElementCount >::get
static ElementCount get(ScalarTy MinVal, bool Scalable)
Definition: TypeSize.h:289
llvm::TargetTransformInfoImplBase::getReplicationShuffleCost
unsigned getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:597
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:813
llvm::TargetTransformInfoImplBase::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfoImpl.h:489
llvm::APInt::setBit
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
Definition: APInt.h:1300
llvm::TargetTransformInfoImplBase::TargetTransformInfoImplBase
TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg)
Definition: TargetTransformInfoImpl.h:44
llvm::TargetTransformInfoImplBase
Base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:33
llvm::TargetTransformInfoImplBase::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, unsigned *Fast) const
Definition: TargetTransformInfoImpl.h:367
llvm::TargetTransformInfoImplBase::getCacheAssociativity
llvm::Optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:468
llvm::PatternMatch::match
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
llvm::TargetTransformInfoImplBase::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfoImpl.h:479
llvm::TargetTransformInfoImplBase::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfoImpl.h:410
InlinePriorityMode::Cost
@ Cost
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:886
llvm::TargetTransformInfoImplBase::hasActiveVectorLength
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:845
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1138
llvm::TargetTransformInfoImplBase::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:240
llvm::User
Definition: User.h:44
llvm::TargetTransformInfoImplBase::forceScalarizeMaskedScatter
bool forceScalarizeMaskedScatter(VectorType *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:278
llvm::TargetTransformInfoImplCRTPBase::isExpensiveToSpeculativelyExecute
bool isExpensiveToSpeculativelyExecute(const Instruction *I)
Definition: TargetTransformInfoImpl.h:1282
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetTransformInfoImplBase::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Definition: TargetTransformInfoImpl.h:327
llvm::TargetTransformInfoImplBase::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const
Definition: TargetTransformInfoImpl.h:587
SI
@ SI
Definition: SIInstrInfo.cpp:7882
llvm::TargetTransformInfoImplBase::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicElementSize) const
Definition: TargetTransformInfoImpl.h:741
llvm::TargetTransformInfoImplBase::isSingleThreaded
bool isSingleThreaded() const
Definition: TargetTransformInfoImpl.h:111
llvm::Type::isVectorTy
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:246
llvm::TargetTransformInfoImplBase::hasBranchDivergence
bool hasBranchDivergence() const
Definition: TargetTransformInfoImpl.h:89
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::TargetTransformInfoImplBase::isIndexedStoreLegal
bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:781
llvm::TargetTransformInfoImplBase::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Definition: TargetTransformInfoImpl.h:325
llvm::Instruction
Definition: Instruction.h:42
llvm::InterleavedAccessInfo
Drive the analysis of interleaved memory accesses in the loop.
Definition: VectorUtils.h:759
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:189
llvm::TargetTransformInfoImplBase::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfoImpl.h:688
llvm::TargetTransformInfoImplBase::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
Definition: TargetTransformInfoImpl.h:397
llvm::Operator::getOpcode
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
Definition: Operator.h:42
llvm::TargetTransformInfoImplBase::isTypeLegal
bool isTypeLegal(Type *Ty) const
Definition: TargetTransformInfoImpl.h:321
llvm::TargetTransformInfoImplBase::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:208
llvm::TargetTransformInfoImplBase::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicCpySize) const
Definition: TargetTransformInfoImpl.h:749
llvm::TargetTransformInfoImplBase::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:571
llvm::TargetTransformInfoImplBase::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfoImpl.h:736
llvm::TargetTransformInfoImplCRTPBase
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:942
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetTransformInfoImplBase::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:296
llvm::TargetTransformInfoImplBase::getPredicatedAddrSpace
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
Definition: TargetTransformInfoImpl.h:114
PatternMatch.h
llvm::TargetTransformInfoImplBase::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:719
llvm::TargetTransformInfoImplBase::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfoImpl.h:486
llvm::FixedVectorType::get
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
Definition: Type.cpp:684
llvm::TargetTransformInfoImplBase::enableMemCmpExpansion
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfoImpl.h:356
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:155
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::TargetTransformInfoImplBase::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Definition: TargetTransformInfoImpl.h:93
llvm::TargetTransformInfoImplBase::getVPLegalizationStrategy
TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: TargetTransformInfoImpl.h:851
llvm::TargetTransformInfoImplBase::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:618
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:119
llvm::TargetTransformInfoImplBase::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:603
llvm::TargetTransformInfoImplBase::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
Definition: TargetTransformInfoImpl.h:624
llvm::TargetTransformInfo::PSK_Software
@ PSK_Software
Definition: TargetTransformInfo.h:585
llvm::TargetTransformInfoImplBase::getCacheSize
llvm::Optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const
Definition: TargetTransformInfoImpl.h:457
llvm::TargetTransformInfoImplBase::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfoImpl.h:225
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::TargetTransformInfoImplBase::supportsTailCallFor
bool supportsTailCallFor(const CallBase *CB) const
Definition: TargetTransformInfoImpl.h:348
llvm::ARM_PROC::IE
@ IE
Definition: ARMBaseInfo.h:27
llvm::TargetTransformInfoImplBase::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:48
llvm::TargetTransformInfoImplBase::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: TargetTransformInfoImpl.h:189
llvm::TargetTransformInfoImplBase::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:826
llvm::TargetTransformInfoImplBase::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfoImpl.h:841
llvm::TargetTransformInfoImplBase::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Definition: TargetTransformInfoImpl.h:363
llvm::TargetTransformInfo::SK_Reverse
@ SK_Reverse
Reverse the order of the vector.
Definition: TargetTransformInfo.h:888
llvm::TargetTransformInfoImplCRTPBase::TargetTransformInfoImplCRTPBase
TargetTransformInfoImplCRTPBase(const DataLayout &DL)
Definition: TargetTransformInfoImpl.h:947
llvm::TargetTransformInfoImplBase::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:681
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
VectorUtils.h
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:75
llvm::TargetTransformInfoImplBase::canMacroFuseCmp
bool canMacroFuseCmp() const
Definition: TargetTransformInfoImpl.h:227
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:297
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::TargetTransformInfo::SK_InsertSubvector
@ SK_InsertSubvector
InsertSubvector. Index indicates start offset.
Definition: TargetTransformInfo.h:893
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfoImplBase::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfoImpl.h:60
llvm::TargetTransformInfoImplBase::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:248
uint64_t
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:402
llvm::TargetTransformInfoImplBase::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:797
llvm::PatternMatch::m_LogicalOr
LogicalOp_match< LHS, RHS, Instruction::Or > m_LogicalOr(const LHS &L, const RHS &R)
Matches L || R either in the form of L | R or L ? true : R.
Definition: PatternMatch.h:2561
llvm::TargetTransformInfoImplBase::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned, VectorType *, Optional< FastMathFlags > FMF, TTI::TargetCostKind) const
Definition: TargetTransformInfoImpl.h:695
llvm::TruncInst
This class represents a truncation of integer types.
Definition: Instructions.h:4810
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::TargetTransformInfoImplBase::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Definition: TargetTransformInfoImpl.h:183
llvm::TargetTransformInfoImplBase::getPreferredAddressingMode
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Definition: TargetTransformInfoImpl.h:236
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:416
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetTransformInfoImplBase::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:527
llvm::SCEVConstant
This class represents a constant integer value.
Definition: ScalarEvolutionExpressions.h:60
llvm::TargetTransformInfoImplBase::isExpensiveToSpeculativelyExecute
bool isExpensiveToSpeculativelyExecute(const Instruction *I)
Definition: TargetTransformInfoImpl.h:379
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetTransformInfo::VPLegalization::Discard
@ Discard
Definition: TargetTransformInfo.h:1517
llvm::TargetTransformInfoImplBase::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfoImpl.h:448
llvm::TargetTransformInfoImplBase::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Definition: TargetTransformInfoImpl.h:123
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::CmpInst::BAD_ICMP_PREDICATE
@ BAD_ICMP_PREDICATE
Definition: InstrTypes.h:752
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:264
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::TargetTransformInfo::LSRCost::ScaleCost
unsigned ScaleCost
Definition: TargetTransformInfo.h:412
llvm::TargetTransformInfoImplBase::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Definition: TargetTransformInfoImpl.h:339
llvm::TargetTransformInfo::SK_Splice
@ SK_Splice
Concatenates elements from the first input vector with elements of the second input vector.
Definition: TargetTransformInfo.h:899
llvm::TargetTransformInfoImplBase::getInterleavedMemoryOpCost
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) const
Definition: TargetTransformInfoImpl.h:632
llvm::TargetTransformInfoImplBase::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfoImpl.h:723
llvm::TargetTransformInfoImplBase::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Definition: TargetTransformInfoImpl.h:352
llvm::TargetTransformInfoImplBase::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr) const
Definition: TargetTransformInfoImpl.h:491
llvm::PatternMatch::m_Value
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:76
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfoImplBase::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned, unsigned) const
Definition: TargetTransformInfoImpl.h:104
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:780
llvm::TargetTransformInfoImplBase::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:255
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:243
llvm::TargetTransformInfoImplBase::isElementTypeLegalForScalableVector
bool isElementTypeLegalForScalableVector(Type *Ty) const
Definition: TargetTransformInfoImpl.h:807
llvm::TargetTransformInfoImplBase::getVPMemoryOpCost
InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:611
llvm::TargetTransformInfoImplBase::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfoImpl.h:835
llvm::TargetTransformInfoImplBase::getStoreMinimumVF
unsigned getStoreMinimumVF(unsigned VF, Type *, Type *) const
Definition: TargetTransformInfoImpl.h:446
llvm::TargetTransformInfoImplBase::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfoImpl.h:70
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1108
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
Mul
BinaryOperator * Mul
Definition: X86PartialReduction.cpp:70
DataLayout.h
llvm::StructType
Class to represent struct types.
Definition: DerivedTypes.h:213
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::TargetTransformInfoImplBase::isLegalBroadcastLoad
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
Definition: TargetTransformInfoImpl.h:262
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:42
llvm::TargetTransformInfo::TCK_SizeAndLatency
@ TCK_SizeAndLatency
The weighted sum of size and latency.
Definition: TargetTransformInfo.h:221
llvm::TargetTransformInfoImplBase::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfoImpl.h:837
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::TargetTransformInfoImplBase::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Definition: TargetTransformInfoImpl.h:313
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::TargetTransformInfoImplBase::getVScaleForTuning
Optional< unsigned > getVScaleForTuning() const
Definition: TargetTransformInfoImpl.h:434
llvm::TargetTransformInfoImplBase::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Definition: TargetTransformInfoImpl.h:333
llvm::TargetTransformInfoImplBase::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
Definition: TargetTransformInfoImpl.h:344
llvm::TargetTransformInfoImplBase::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Definition: TargetTransformInfoImpl.h:381
llvm::TargetTransformInfoImplBase::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:580
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:632
llvm::TargetTransformInfoImplBase::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:244
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:432
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:173
llvm::TargetTransformInfo::SK_Transpose
@ SK_Transpose
Transpose two vectors.
Definition: TargetTransformInfo.h:892
llvm::ComplexDeinterleavingOperation::Shuffle
@ Shuffle
llvm::DataLayout::isLegalInteger
bool isLegalInteger(uint64_t Width) const
Returns true if the specified type is known to be a native integer type supported by the CPU.
Definition: DataLayout.h:266
llvm::TargetTransformInfo::CacheLevel::L2D
@ L2D
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:142
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:187
llvm::APInt::getNullValue
static APInt getNullValue(unsigned numBits)
NOTE: This is soft-deprecated. Please use getZero() instead.
Definition: APInt.h:180
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:164
llvm::TargetTransformInfoImplBase::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: TargetTransformInfoImpl.h:821
llvm::KnownBits
Definition: KnownBits.h:23
llvm::Type::getIntNTy
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
Definition: Type.cpp:243
llvm::TargetTransformInfo::LSRCost::NumBaseAdds
unsigned NumBaseAdds
Definition: TargetTransformInfo.h:409
llvm::TargetTransformInfoImplBase::forceScalarizeMaskedGather
bool forceScalarizeMaskedGather(VectorType *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:274
llvm::None
constexpr std::nullopt_t None
Definition: None.h:27
llvm::TargetTransformInfoImplBase::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfoImpl.h:727
llvm::TargetTransformInfoImplBase::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfoImpl.h:485
llvm::TargetTransformInfoImplBase::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:404
llvm::StructLayout::getElementOffset
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:652
llvm::TargetTransformInfoImplBase::getExtendedReductionCost
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:706
llvm::TargetTransformInfoImplBase::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfoImpl.h:75
llvm::TargetTransformInfoImplBase::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Definition: TargetTransformInfoImpl.h:118
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:475
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
VPLegalization
TargetTransformInfo::VPLegalization VPLegalization
Definition: ExpandVectorPredication.cpp:35
llvm::TargetTransformInfo::getOperandInfo
static OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:730
llvm::APInt::sextOrTrunc
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:1002
llvm::TargetTransformInfoImplBase::minRequiredElementSize
unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const
Definition: TargetTransformInfoImpl.h:860
llvm::TypeSize
Definition: TypeSize.h:435
llvm::SCEVAddRecExpr
This node represents a polynomial recurrence on the trip count of the specified loop.
Definition: ScalarEvolutionExpressions.h:342
llvm::TargetTransformInfoImplBase::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:809
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::TargetTransformInfoImplBase::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
Definition: TargetTransformInfoImpl.h:437
llvm::TargetTransformInfoImplBase::isIndexedLoadLegal
bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
Definition: TargetTransformInfoImpl.h:776
llvm::TargetTransformInfoImplBase::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Definition: TargetTransformInfoImpl.h:480
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:225
llvm::User::operand_values
iterator_range< value_op_iterator > operand_values()
Definition: User.h:266
llvm::TargetTransformInfo::LSRCost::ImmCost
unsigned ImmCost
Definition: TargetTransformInfo.h:410
llvm::TargetTransformInfoImplBase::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Definition: TargetTransformInfoImpl.h:204
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:185
llvm::TargetTransformInfoImplBase::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfoImpl.h:412
llvm::PredicationStyle
PredicationStyle
Definition: TargetTransformInfo.h:165
llvm::TargetTransformInfoImplBase::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: TargetTransformInfoImpl.h:427
llvm::TargetTransformInfoImplBase::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Definition: TargetTransformInfoImpl.h:229
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfoImplBase::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: TargetTransformInfoImpl.h:177
llvm::TargetTransformInfoImplBase::DL
const DataLayout & DL
Definition: TargetTransformInfoImpl.h:37
llvm::SCEVConstant::getAPInt
const APInt & getAPInt() const
Definition: ScalarEvolutionExpressions.h:70
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:96
llvm::TargetTransformInfoImplBase::getUnrollingPreferences
void getUnrollingPreferences(Loop *, ScalarEvolution &, TTI::UnrollingPreferences &, OptimizationRemarkEmitter *) const
Definition: TargetTransformInfoImpl.h:197
llvm::TargetTransformInfoImplBase::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
Definition: TargetTransformInfoImpl.h:565
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::TargetTransformInfoImplBase::isConstantStridedAccessLessThan
bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
Definition: TargetTransformInfoImpl.h:926
llvm::TargetTransformInfoImplBase::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Definition: TargetTransformInfoImpl.h:365
ScalarEvolutionExpressions.h
llvm::TargetTransformInfoImplBase::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfoImpl.h:95
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:69
llvm::TargetTransformInfoImplBase::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Definition: TargetTransformInfoImpl.h:283
llvm::TargetTransformInfoImplBase::getMinTripCountTailFoldingThreshold
unsigned getMinTripCountTailFoldingThreshold() const
Definition: TargetTransformInfoImpl.h:839
isSigned
static bool isSigned(unsigned int Opcode)
Definition: ExpandLargeDivRem.cpp:52
llvm::IntrinsicCostAttributes::getID
Intrinsic::ID getID() const
Definition: TargetTransformInfo.h:150
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:964
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfoImpl.h:788
TargetTransformInfo.h
llvm::TargetTransformInfoImplBase::shouldPrefetchAddressSpace
bool shouldPrefetchAddressSpace(unsigned AS) const
Definition: TargetTransformInfoImpl.h:487
llvm::PatternMatch
Definition: PatternMatch.h:47
llvm::SmallVectorImpl< int >
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:71
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1174
llvm::TargetTransformInfoImplBase::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfoImpl.h:815
llvm::TargetTransformInfoImplBase::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfoImpl.h:792
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:171
llvm::TargetTransformInfoImplBase::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:266
llvm::TargetTransformInfoImplBase::enableScalableVectorization
bool enableScalableVectorization() const
Definition: TargetTransformInfoImpl.h:843
llvm::TargetTransformInfo::TCC_Basic
@ TCC_Basic
The cost of a typical 'add' instruction.
Definition: TargetTransformInfo.h:244
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3277
llvm::OptimizedStructLayoutField
A field in a structure.
Definition: OptimizedStructLayout.h:45
llvm::TargetTransformInfoImplBase::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Definition: TargetTransformInfoImpl.h:329
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::TargetTransformInfoImplBase::emitGetActiveLaneMask
PredicationStyle emitGetActiveLaneMask() const
Definition: TargetTransformInfoImpl.h:173
llvm::TargetTransformInfoImplBase::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfoImpl.h:71
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3133
llvm::TargetTransformInfoImplBase::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:639
llvm::TargetTransformInfoImplBase::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Definition: TargetTransformInfoImpl.h:300
llvm::TargetTransformInfoImplBase::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Definition: TargetTransformInfoImpl.h:331
llvm::PredicationStyle::None
@ None
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:218
llvm::TargetTransformInfoImplBase::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
Definition: TargetTransformInfoImpl.h:387
llvm::TargetTransformInfo::AMK_None
@ AMK_None
Definition: TargetTransformInfo.h:635
llvm::TargetTransformInfo::SK_ExtractSubvector
@ SK_ExtractSubvector
ExtractSubvector Index indicates start offset.
Definition: TargetTransformInfo.h:894
llvm::PatternMatch::m_LogicalAnd
LogicalOp_match< LHS, RHS, Instruction::And > m_LogicalAnd(const LHS &L, const RHS &R)
Matches L && R either in the form of L & R or L ? R : false.
Definition: PatternMatch.h:2543
llvm::codeview::PublicSymFlags::Function
@ Function
llvm::TargetTransformInfoImplBase::getPeelingPreferences
void getPeelingPreferences(Loop *, ScalarEvolution &, TTI::PeelingPreferences &) const
Definition: TargetTransformInfoImpl.h:201
llvm::SCEVAddRecExpr::getStepRecurrence
const SCEV * getStepRecurrence(ScalarEvolution &SE) const
Constructs and returns the recurrence indicating how much this expression steps by.
Definition: ScalarEvolutionExpressions.h:360
llvm::TargetTransformInfoImplBase::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfoImpl.h:445
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::DataLayout::getTypeAllocSize
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:506
llvm::TargetTransformInfoImplBase::getFPOpCost
InstructionCost getFPOpCost(Type *Ty) const
Definition: TargetTransformInfoImpl.h:383
llvm::TargetTransformInfoImplBase::areTypesABICompatible
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
Definition: TargetTransformInfoImpl.h:768
llvm::TargetTransformInfoImplBase::getRegUsageForType
unsigned getRegUsageForType(Type *Ty) const
Definition: TargetTransformInfoImpl.h:323