27using namespace PatternMatch;
29#define DEBUG_TYPE "tti"
33 cl::desc(
"Recognize reduction patterns."));
37 cl::desc(
"Use this to override the target cache line size when "
38 "specified by the user."));
43 "Use this to override the target's predictable branch threshold (%)."));
61 if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
70 ScalarizationCost(ScalarizationCost) {
72 if (
const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
73 FMF = FPMO->getFastMathFlags();
86 : II(
I),
RetTy(RTy), IID(Id), FMF(
Flags), ScalarizationCost(ScalarCost) {
87 ParamTys.insert(ParamTys.begin(), Tys.
begin(), Tys.
end());
92 :
RetTy(Ty), IID(Id) {
94 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
95 ParamTys.reserve(Arguments.size());
106 : II(
I),
RetTy(RTy), IID(Id), FMF(
Flags), ScalarizationCost(ScalarCost) {
107 ParamTys.insert(ParamTys.begin(), Tys.
begin(), Tys.
end());
108 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
127 if (isa<SCEVCouldNotCompute>(EC))
129 if (
const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
130 if (ConstEC->getValue()->isZero())
151 bool NotAlways =
false;
170 if (
BranchInst *BI = dyn_cast<BranchInst>(TI)) {
171 if (!BI->isConditional())
191 : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(
DL))) {}
199 TTIImpl = std::move(
RHS.TTIImpl);
204 return TTIImpl->getInliningThresholdMultiplier();
209 return TTIImpl->adjustInliningThreshold(CB);
213 return TTIImpl->getInlinerVectorBonusPercent();
227 "If pointers have same base address it has to be provided.");
234 return TTIImpl->getEstimatedNumberOfCaseClusters(
SI, JTSize, PSI, BFI);
243 "TTI should not produce negative costs!");
250 : TTIImpl->getPredictableBranchThreshold();
254 return TTIImpl->hasBranchDivergence();
258 return TTIImpl->useGPUDivergenceAnalysis();
262 return TTIImpl->isSourceOfDivergence(V);
266 return TTIImpl->isAlwaysUniform(V);
270 return TTIImpl->getFlatAddressSpace();
275 return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
279 unsigned ToAS)
const {
280 return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
285 return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
289 return TTIImpl->getAssumedAddrSpace(V);
293 return TTIImpl->isSingleThreaded();
296std::pair<const Value *, unsigned>
298 return TTIImpl->getPredicatedAddrSpace(V);
303 return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
307 return TTIImpl->isLoweredToCall(
F);
313 return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
320 return TTIImpl->preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LVL, IAI);
324 bool IVUpdateMayOverflow)
const {
325 return TTIImpl->getPreferredTailFoldingStyle(IVUpdateMayOverflow);
328std::optional<Instruction *>
331 return TTIImpl->instCombineIntrinsic(IC, II);
336 bool &KnownBitsComputed)
const {
337 return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
345 SimplifyAndSetOp)
const {
346 return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
347 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
354 return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
359 return TTIImpl->getPeelingPreferences(L, SE, PP);
363 return TTIImpl->isLegalAddImmediate(Imm);
367 return TTIImpl->isLegalICmpImmediate(Imm);
372 bool HasBaseReg, int64_t Scale,
375 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
376 Scale, AddrSpace,
I);
381 return TTIImpl->isLSRCostLess(C1, C2);
385 return TTIImpl->isNumRegsMajorCostOfLSR();
389 return TTIImpl->isProfitableLSRChainElement(
I);
393 return TTIImpl->canMacroFuseCmp();
400 return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
406 return TTIImpl->getPreferredAddressingMode(L, SE);
410 Align Alignment)
const {
411 return TTIImpl->isLegalMaskedStore(DataType, Alignment);
415 Align Alignment)
const {
416 return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
420 Align Alignment)
const {
421 return TTIImpl->isLegalNTStore(DataType, Alignment);
425 return TTIImpl->isLegalNTLoad(DataType, Alignment);
430 return TTIImpl->isLegalBroadcastLoad(ElementTy, NumElements);
434 Align Alignment)
const {
435 return TTIImpl->isLegalMaskedGather(DataType, Alignment);
439 VectorType *VecTy,
unsigned Opcode0,
unsigned Opcode1,
441 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask);
445 Align Alignment)
const {
446 return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
450 Align Alignment)
const {
451 return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment);
455 Align Alignment)
const {
456 return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment);
460 return TTIImpl->isLegalMaskedCompressStore(DataType);
464 return TTIImpl->isLegalMaskedExpandLoad(DataType);
468 return TTIImpl->enableOrderedReductions();
472 return TTIImpl->hasDivRemOp(DataType, IsSigned);
476 unsigned AddrSpace)
const {
477 return TTIImpl->hasVolatileVariant(
I, AddrSpace);
481 return TTIImpl->prefersVectorizedAddressing();
486 int64_t Scale,
unsigned AddrSpace)
const {
488 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
489 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
494 return TTIImpl->LSRWithInstrQueries();
498 return TTIImpl->isTruncateFree(Ty1, Ty2);
502 return TTIImpl->isProfitableToHoist(
I);
508 return TTIImpl->isTypeLegal(Ty);
512 return TTIImpl->getRegUsageForType(Ty);
516 return TTIImpl->shouldBuildLookupTables();
521 return TTIImpl->shouldBuildLookupTablesForConstant(
C);
525 return TTIImpl->shouldBuildRelLookupTables();
529 return TTIImpl->useColdCCForColdCall(
F);
535 return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
542 return TTIImpl->getOperandsScalarizationOverhead(Args, Tys,
CostKind);
546 return TTIImpl->supportsEfficientVectorElementLoadStore();
550 return TTIImpl->supportsTailCalls();
554 return TTIImpl->supportsTailCallFor(CB);
558 bool LoopHasReductions)
const {
559 return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
564 return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
568 return TTIImpl->enableSelectOptimize();
572 return TTIImpl->enableInterleavedAccessVectorization();
576 return TTIImpl->enableMaskedInterleavedAccessVectorization();
580 return TTIImpl->isFPVectorizationPotentiallyUnsafe();
588 unsigned *
Fast)
const {
595 return TTIImpl->getPopcntSupport(IntTyWidthInBit);
599 return TTIImpl->haveFastSqrt(Ty);
604 return TTIImpl->isExpensiveToSpeculativelyExecute(
I);
608 return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
613 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
622 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
630 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
635 unsigned Opcode,
unsigned Idx,
const APInt &Imm,
Type *Ty,
638 TTIImpl->getIntImmCostInst(Opcode,
Idx, Imm, Ty,
CostKind, Inst);
639 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
648 TTIImpl->getIntImmCostIntrin(IID,
Idx, Imm, Ty,
CostKind);
649 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
654 return TTIImpl->getNumberOfRegisters(ClassID);
659 return TTIImpl->getRegisterClassForType(
Vector, Ty);
663 return TTIImpl->getRegisterClassName(ClassID);
668 return TTIImpl->getRegisterBitWidth(K);
672 return TTIImpl->getMinVectorRegisterBitWidth();
676 return TTIImpl->getMaxVScale();
680 return TTIImpl->getVScaleForTuning();
684 return TTIImpl->isVScaleKnownToBeAPowerOfTwo();
689 return TTIImpl->shouldMaximizeVectorBandwidth(K);
693 bool IsScalable)
const {
694 return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
698 unsigned Opcode)
const {
699 return TTIImpl->getMaximumVF(ElemWidth, Opcode);
703 Type *ScalarValTy)
const {
704 return TTIImpl->getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy);
708 const Instruction &
I,
bool &AllowPromotionWithoutCommonHeader)
const {
709 return TTIImpl->shouldConsiderAddressTypePromotion(
710 I, AllowPromotionWithoutCommonHeader);
715 : TTIImpl->getCacheLineSize();
718std::optional<unsigned>
720 return TTIImpl->getCacheSize(Level);
723std::optional<unsigned>
725 return TTIImpl->getCacheAssociativity(Level);
729 return TTIImpl->getPrefetchDistance();
733 unsigned NumMemAccesses,
unsigned NumStridedMemAccesses,
734 unsigned NumPrefetches,
bool HasCall)
const {
735 return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
736 NumPrefetches, HasCall);
740 return TTIImpl->getMaxPrefetchIterationsAhead();
744 return TTIImpl->enableWritePrefetching();
748 return TTIImpl->shouldPrefetchAddressSpace(AS);
752 return TTIImpl->getMaxInterleaveFactor(VF);
760 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
761 if (
const auto *CI = dyn_cast<ConstantInt>(V)) {
762 if (CI->getValue().isPowerOf2())
764 else if (CI->getValue().isNegatedPowerOf2())
773 if (
const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
774 if (ShuffleInst->isZeroEltSplat())
781 if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
785 if (
auto *CI = dyn_cast<ConstantInt>(Splat)) {
786 if (CI->getValue().isPowerOf2())
788 else if (CI->getValue().isNegatedPowerOf2())
791 }
else if (
const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
792 bool AllPow2 =
true, AllNegPow2 =
true;
793 for (
unsigned I = 0,
E = CDS->getNumElements();
I !=
E; ++
I) {
794 if (
auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(
I))) {
795 AllPow2 &= CI->getValue().isPowerOf2();
796 AllNegPow2 &= CI->getValue().isNegatedPowerOf2();
797 if (AllPow2 || AllNegPow2)
800 AllPow2 = AllNegPow2 =
false;
810 if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
813 return {OpInfo, OpProps};
821 TTIImpl->getArithmeticInstrCost(Opcode, Ty,
CostKind,
824 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
833 TTIImpl->getShuffleCost(Kind, Ty, Mask,
CostKind,
Index, SubTp, Args);
834 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
843 auto getLoadStoreKind = [](
const Value *V,
unsigned LdStOp,
unsigned MaskedOp,
844 unsigned GatScatOp) {
849 if (
I->getOpcode() == LdStOp)
862 switch (
I->getOpcode()) {
863 case Instruction::ZExt:
864 case Instruction::SExt:
865 case Instruction::FPExt:
866 return getLoadStoreKind(
I->getOperand(0), Instruction::Load,
867 Intrinsic::masked_load, Intrinsic::masked_gather);
868 case Instruction::Trunc:
869 case Instruction::FPTrunc:
871 return getLoadStoreKind(*
I->user_begin(), Instruction::Store,
872 Intrinsic::masked_store,
873 Intrinsic::masked_scatter);
885 assert((
I ==
nullptr ||
I->getOpcode() == Opcode) &&
886 "Opcode should reflect passed instruction.");
888 TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH,
CostKind,
I);
889 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
896 TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy,
Index);
897 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
903 assert((
I ==
nullptr ||
I->getOpcode() == Opcode) &&
904 "Opcode should reflect passed instruction.");
906 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
913 assert((
I ==
nullptr ||
I->getOpcode() == Opcode) &&
914 "Opcode should reflect passed instruction.");
916 TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred,
CostKind,
I);
917 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
928 TTIImpl->getVectorInstrCost(Opcode, Val,
CostKind,
Index, Op0, Op1);
929 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
936 unsigned Index)
const {
941 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
946 Type *EltTy,
int ReplicationFactor,
int VF,
const APInt &DemandedDstElts,
949 EltTy, ReplicationFactor, VF, DemandedDstElts,
CostKind);
950 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
958 assert((
I ==
nullptr ||
I->getOpcode() == Opcode) &&
959 "Opcode should reflect passed instruction.");
962 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
971 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
976 unsigned Opcode,
Type *DataTy,
const Value *
Ptr,
bool VariableMask,
979 Opcode, DataTy,
Ptr, VariableMask, Alignment,
CostKind,
I);
980 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
987 bool UseMaskForCond,
bool UseMaskForGaps)
const {
990 UseMaskForCond, UseMaskForGaps);
991 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
999 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1008 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1013 return TTIImpl->getNumberOfParts(Tp);
1020 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1026 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1031 unsigned Opcode,
VectorType *Ty, std::optional<FastMathFlags> FMF,
1034 TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF,
CostKind);
1035 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1043 TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsUnsigned,
CostKind);
1044 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1051 return TTIImpl->getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
1058 return TTIImpl->getMulAccReductionCost(IsUnsigned, ResTy, Ty,
CostKind);
1063 return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
1068 return TTIImpl->getTgtMemIntrinsic(Inst,
Info);
1072 return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
1077 return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
1082 unsigned DestAddrSpace,
unsigned SrcAlign,
unsigned DestAlign,
1083 std::optional<uint32_t> AtomicElementSize)
const {
1084 return TTIImpl->getMemcpyLoopLoweringType(
Context,
Length, SrcAddrSpace,
1085 DestAddrSpace, SrcAlign, DestAlign,
1091 unsigned RemainingBytes,
unsigned SrcAddrSpace,
unsigned DestAddrSpace,
1092 unsigned SrcAlign,
unsigned DestAlign,
1093 std::optional<uint32_t> AtomicCpySize)
const {
1094 TTIImpl->getMemcpyLoopResidualLoweringType(
1095 OpsOut,
Context, RemainingBytes, SrcAddrSpace, DestAddrSpace, SrcAlign,
1096 DestAlign, AtomicCpySize);
1101 return TTIImpl->areInlineCompatible(Caller,
Callee);
1107 return TTIImpl->areTypesABICompatible(Caller,
Callee, Types);
1112 return TTIImpl->isIndexedLoadLegal(Mode, Ty);
1117 return TTIImpl->isIndexedStoreLegal(Mode, Ty);
1121 return TTIImpl->getLoadStoreVecRegBitWidth(AS);
1125 return TTIImpl->isLegalToVectorizeLoad(LI);
1129 return TTIImpl->isLegalToVectorizeStore(
SI);
1133 unsigned ChainSizeInBytes,
Align Alignment,
unsigned AddrSpace)
const {
1134 return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1139 unsigned ChainSizeInBytes,
Align Alignment,
unsigned AddrSpace)
const {
1140 return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1146 return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1150 return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1155 unsigned ChainSizeInBytes,
1157 return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1162 unsigned ChainSizeInBytes,
1164 return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1169 return TTIImpl->preferInLoopReduction(Opcode, Ty,
Flags);
1174 return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty,
Flags);
1178 return TTIImpl->preferEpilogueVectorization();
1183 return TTIImpl->getVPLegalizationStrategy(VPI);
1187 return TTIImpl->hasArmWideBranch(Thumb);
1191 return TTIImpl->shouldExpandReduction(II);
1195 return TTIImpl->getGISelRematGlobalCost();
1199 return TTIImpl->getMinTripCountTailFoldingThreshold();
1203 return TTIImpl->supportsScalableVectors();
1207 return TTIImpl->enableScalableVectorization();
1211 Align Alignment)
const {
1212 return TTIImpl->hasActiveVectorLength(Opcode, DataType, Alignment);
1221 : TTICallback(
std::
move(TTICallback)) {}
1225 return TTICallback(
F);
1231 return Result(
F.getParent()->getDataLayout());
1236 "Target Transform Information",
false,
true)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Callee
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
mir Rename Register Operands
Module.h This file contains the declarations for the Module class.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static SymbolRef::Type getType(const Symbol *Sym)
Class for arbitrary precision integers.
A container for analyses that lazily runs them and caches their results.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
A cache of @llvm.assume calls within a function.
LLVM Basic Block Representation.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Conditional or Unconditional Branch instruction.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation or the function signa...
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
This is an important base class in LLVM.
A parsed version of the target data layout string in and methods for querying it.
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Convenience struct for specifying and reasoning about fast-math flags.
Class to represent function types.
param_iterator param_begin() const
param_iterator param_end() const
FunctionType * getFunctionType() const
Returns the FunctionType for me.
ImmutablePass class - This class is used to provide information that does not need to be run.
The core instruction combiner logic.
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Drive the analysis of interleaved memory accesses in the loop.
IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false)
A wrapper class for inspecting calls to intrinsic functions.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
This is an important class for using LLVM in a threaded context.
An instruction for reading from memory.
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
BlockT * getHeader() const
bool isLoopLatch(const BlockT *BB) const
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
void perform(LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
LoopVectorizationLegality checks if it is legal to vectorize a loop, and to what vectorization factor...
Represents a single loop in the control flow graph.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
This class represents a constant integer value.
This class represents an analyzed expression in the program.
The main scalar evolution driver.
uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An instruction for storing to memory.
Analysis pass providing the TargetTransformInfo.
Result run(const Function &F, FunctionAnalysisManager &)
TargetTransformInfo Result
TargetIRAnalysis()
Default construct a target IR analysis.
Provides information about what library functions are available for the current target.
The instances of the Type class are immutable: once they are created, they are never changed.
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Base class of all SIMD vector types.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
void initializeTargetTransformInfoWrapperPassPass(PassRegistry &)
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
constexpr unsigned BitWidth
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
auto predecessors(const MachineBasicBlock *BB)
This struct is a compact representation of a valid (non-zero power of two) alignment.
A special type used by analysis passes to provide an address that identifies that particular analysis...
Attributes of a target dependent hardware loop.
bool canAnalyze(LoopInfo &LI)
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Information about a load/store intrinsic defined by the target.