LLVM 24.0.0git
TargetTransformInfo.cpp
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1//===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
11#include "llvm/Analysis/CFG.h"
15#include "llvm/IR/CFG.h"
16#include "llvm/IR/Dominators.h"
17#include "llvm/IR/Instruction.h"
20#include "llvm/IR/Module.h"
21#include "llvm/IR/Operator.h"
24#include <optional>
25#include <utility>
26
27using namespace llvm;
28using namespace PatternMatch;
29
30#define DEBUG_TYPE "tti"
31
32static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
34 cl::desc("Recognize reduction patterns."));
35
37 "cache-line-size", cl::init(0), cl::Hidden,
38 cl::desc("Use this to override the target cache line size when "
39 "specified by the user."));
40
42 "min-page-size", cl::init(0), cl::Hidden,
43 cl::desc("Use this to override the target's minimum page size."));
44
46 "predictable-branch-threshold", cl::init(99), cl::Hidden,
48 "Use this to override the target's predictable branch threshold (%)."));
49
50namespace {
51/// No-op implementation of the TTI interface using the utility base
52/// classes.
53///
54/// This is used when no target specific information is available.
55struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
56 explicit NoTTIImpl(const DataLayout &DL)
57 : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
58};
59} // namespace
60
62 std::unique_ptr<const TargetTransformInfoImplBase> Impl)
63 : TTIImpl(std::move(Impl)) {}
64
66 // If the loop has irreducible control flow, it can not be converted to
67 // Hardware loop.
68 LoopBlocksRPO RPOT(L);
69 RPOT.perform(&LI);
71 return false;
72 return true;
73}
74
76 Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost,
77 bool TypeBasedOnly)
78 : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
79 ScalarizationCost(ScalarizationCost) {
80
81 if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
82 FMF = FPMO->getFastMathFlags();
83
84 if (!TypeBasedOnly)
85 Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
86 for (const Value *Arg : CI.args())
87 ParamTys.push_back(Arg->getType());
88}
89
92 FastMathFlags Flags,
93 const IntrinsicInst *I,
94 InstructionCost ScalarCost)
95 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
96 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
97}
98
101 : RetTy(Ty), IID(Id) {
102
103 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
104 ParamTys.reserve(Arguments.size());
105 for (const Value *Argument : Arguments)
106 ParamTys.push_back(Argument->getType());
107}
108
112 InstructionCost ScalarCost, VectorInstrContext VIC)
113 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost),
114 VIC(VIC) {
115 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
116 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
117}
118
120 // Match default options:
121 // - hardware-loop-counter-bitwidth = 32
122 // - hardware-loop-decrement = 1
123 CountType = Type::getInt32Ty(L->getHeader()->getContext());
124 LoopDecrement = ConstantInt::get(CountType, 1);
125}
126
128 LoopInfo &LI, DominatorTree &DT,
129 bool ForceNestedLoop,
131 SmallVector<BasicBlock *, 4> ExitingBlocks;
132 L->getExitingBlocks(ExitingBlocks);
133
134 for (BasicBlock *BB : ExitingBlocks) {
135 // If we pass the updated counter back through a phi, we need to know
136 // which latch the updated value will be coming from.
137 if (!L->isLoopLatch(BB)) {
139 continue;
140 }
141
142 const SCEV *EC = SE.getExitCount(L, BB);
144 continue;
145 if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
146 if (ConstEC->getValue()->isZero())
147 continue;
148 } else if (!SE.isLoopInvariant(EC, L))
149 continue;
150
151 if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
152 continue;
153
154 // If this exiting block is contained in a nested loop, it is not eligible
155 // for insertion of the branch-and-decrement since the inner loop would
156 // end up messing up the value in the CTR.
157 if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
158 continue;
159
160 // We now have a loop-invariant count of loop iterations (which is not the
161 // constant zero) for which we know that this loop will not exit via this
162 // existing block.
163
164 // We need to make sure that this block will run on every loop iteration.
165 // For this to be true, we must dominate all blocks with backedges. Such
166 // blocks are in-loop predecessors to the header block.
167 bool NotAlways = false;
168 for (BasicBlock *Pred : predecessors(L->getHeader())) {
169 if (!L->contains(Pred))
170 continue;
171
172 if (!DT.dominates(BB, Pred)) {
173 NotAlways = true;
174 break;
175 }
176 }
177
178 if (NotAlways)
179 continue;
180
181 // Make sure this blocks ends with a conditional branch.
182 Instruction *TI = BB->getTerminator();
183 if (!TI)
184 continue;
185
186 if (CondBrInst *BI = dyn_cast<CondBrInst>(TI))
187 ExitBranch = BI;
188 else
189 continue;
190
191 // Note that this block may not be the loop latch block, even if the loop
192 // has a latch block.
193 ExitBlock = BB;
194 ExitCount = EC;
195 break;
196 }
197
198 if (!ExitBlock)
199 return false;
200 return true;
201}
202
204 : TTIImpl(std::make_unique<NoTTIImpl>(DL)) {}
205
207
210
212 TTIImpl = std::move(RHS.TTIImpl);
213 return *this;
214}
215
217 return TTIImpl->getInliningThresholdMultiplier();
218}
219
220unsigned
222 return TTIImpl->getInliningCostBenefitAnalysisSavingsMultiplier();
223}
224
225unsigned
227 const {
228 return TTIImpl->getInliningCostBenefitAnalysisProfitableMultiplier();
229}
230
232 return TTIImpl->getInliningLastCallToStaticBonus();
233}
234
235unsigned
237 return TTIImpl->adjustInliningThreshold(CB);
238}
239
241 const AllocaInst *AI) const {
242 return TTIImpl->getCallerAllocaCost(CB, AI);
243}
244
246 return TTIImpl->getInlinerVectorBonusPercent();
247}
248
250 Type *PointeeType, const Value *Ptr, ArrayRef<const Value *> Operands,
251 TTI::TargetCostKind CostKind, Type *AccessType) const {
252 return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, CostKind, AccessType);
253}
254
257 const TTI::PointersChainInfo &Info, Type *AccessTy,
259 assert((Base || !Info.isSameBase()) &&
260 "If pointers have same base address it has to be provided.");
261 return TTIImpl->getPointersChainCost(Ptrs, Base, Info, AccessTy, CostKind);
262}
263
265 const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
266 BlockFrequencyInfo *BFI) const {
267 return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
268}
269
273 enum TargetCostKind CostKind) const {
274 InstructionCost Cost = TTIImpl->getInstructionCost(U, Operands, CostKind);
276 "TTI should not produce negative costs!");
277 return Cost;
278}
279
281 return PredictableBranchThreshold.getNumOccurrences() > 0
283 : TTIImpl->getPredictableBranchThreshold();
284}
285
287 return TTIImpl->getBranchMispredictPenalty();
288}
289
291 return TTIImpl->hasBranchDivergence(F);
292}
293
296 ValueUniformity VU = TTIImpl->getValueUniformity(V);
297 if (const auto *Call = dyn_cast<CallBase>(V)) {
299 Call->hasFnAttr(Attribute::NoDivergenceSource))
301 }
302 return VU;
303}
304
306 unsigned ToAS) const {
307 return TTIImpl->isValidAddrSpaceCast(FromAS, ToAS);
308}
309
311 unsigned ToAS) const {
312 return TTIImpl->addrspacesMayAlias(FromAS, ToAS);
313}
314
316 return TTIImpl->getFlatAddressSpace();
317}
318
320 unsigned AS2) const {
321 assert(AS1 != AS2 && "Expected distinct address spaces");
322 return TTIImpl->getAddressSpaceJoin(AS1, AS2);
323}
324
326 SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
327 return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
328}
329
331 unsigned ToAS) const {
332 return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
333}
334
335std::pair<KnownBits, KnownBits>
337 const Value &PtrOp) const {
338 return TTIImpl->computeKnownBitsAddrSpaceCast(ToAS, PtrOp);
339}
340
342 unsigned FromAS, unsigned ToAS, const KnownBits &FromPtrBits) const {
343 return TTIImpl->computeKnownBitsAddrSpaceCast(FromAS, ToAS, FromPtrBits);
344}
345
347 unsigned SrcAS, unsigned DstAS) const {
348 return TTIImpl->getAddrSpaceCastPreservedPtrMask(SrcAS, DstAS);
349}
350
352 unsigned AS) const {
353 return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
354}
355
357 return TTIImpl->getAssumedAddrSpace(V);
358}
359
360std::pair<const Value *, unsigned>
362 return TTIImpl->getPredicatedAddrSpace(V);
363}
364
366 IntrinsicInst *II, Value *OldV, Value *NewV) const {
367 return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
368}
369
371 return TTIImpl->isLoweredToCall(F);
372}
373
376 TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
377 return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
378}
379
381 return TTIImpl->getEpilogueVectorizationMinVF();
382}
383
385 TailFoldingInfo *TFI) const {
386 return TTIImpl->preferTailFoldingOverEpilogue(TFI);
387}
388
390 return TTIImpl->getPreferredTailFoldingStyle();
391}
392
393std::optional<Instruction *>
395 IntrinsicInst &II) const {
396 return TTIImpl->instCombineIntrinsic(IC, II);
397}
398
400 InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
401 bool &KnownBitsComputed) const {
402 return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
403 KnownBitsComputed);
404}
405
407 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
408 APInt &UndefElts2, APInt &UndefElts3,
409 std::function<void(Instruction *, unsigned, APInt, APInt &)>
410 SimplifyAndSetOp) const {
411 return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
412 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
413 SimplifyAndSetOp);
414}
415
418 OptimizationRemarkEmitter *ORE) const {
419 return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
420}
421
423 PeelingPreferences &PP) const {
424 return TTIImpl->getPeelingPreferences(L, SE, PP);
425}
426
428 return TTIImpl->isLegalAddImmediate(Imm);
429}
430
432 return TTIImpl->isLegalAddScalableImmediate(Imm);
433}
434
436 return TTIImpl->isLegalICmpImmediate(Imm);
437}
438
440 int64_t BaseOffset,
441 bool HasBaseReg, int64_t Scale,
442 unsigned AddrSpace,
443 Instruction *I,
444 int64_t ScalableOffset) const {
445 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
446 Scale, AddrSpace, I, ScalableOffset);
447}
448
450 const LSRCost &C2) const {
451 return TTIImpl->isLSRCostLess(C1, C2);
452}
453
455 return TTIImpl->isNumRegsMajorCostOfLSR();
456}
457
459 return TTIImpl->shouldDropLSRSolutionIfLessProfitable();
460}
461
463 return TTIImpl->isProfitableLSRChainElement(I);
464}
465
467 return TTIImpl->canMacroFuseCmp();
468}
469
471 ScalarEvolution *SE, LoopInfo *LI,
473 TargetLibraryInfo *LibInfo) const {
474 return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
475}
476
479 ScalarEvolution *SE) const {
480 return TTIImpl->getPreferredAddressingMode(L, SE);
481}
482
484 unsigned AddressSpace,
485 TTI::MaskKind MaskKind) const {
486 return TTIImpl->isLegalMaskedStore(DataType, Alignment, AddressSpace,
487 MaskKind);
488}
489
491 unsigned AddressSpace,
492 TTI::MaskKind MaskKind) const {
493 return TTIImpl->isLegalMaskedLoad(DataType, Alignment, AddressSpace,
494 MaskKind);
495}
496
498 unsigned AddressSpace) const {
499 return TTIImpl->isLegalSpeculativeLoad(DataType, AddressSpace);
500}
501
503 Align Alignment) const {
504 return TTIImpl->isLegalNTStore(DataType, Alignment);
505}
506
507bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
508 return TTIImpl->isLegalNTLoad(DataType, Alignment);
509}
510
512 ElementCount NumElements) const {
513 return TTIImpl->isLegalBroadcastLoad(ElementTy, NumElements);
514}
515
517 Align Alignment) const {
518 return TTIImpl->isLegalMaskedGather(DataType, Alignment);
519}
520
522 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
523 const SmallBitVector &OpcodeMask, ArrayRef<const Value *> Scalars) const {
524 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask, Scalars);
525}
526
528 Align Alignment) const {
529 return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
530}
531
533 Align Alignment) const {
534 return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment);
535}
536
538 Align Alignment) const {
539 return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment);
540}
541
543 Align Alignment) const {
544 return TTIImpl->isLegalMaskedCompressStore(DataType, Alignment);
545}
546
548 Align Alignment) const {
549 return TTIImpl->isLegalMaskedExpandLoad(DataType, Alignment);
550}
551
553 Align Alignment) const {
554 return TTIImpl->isLegalStridedLoadStore(DataType, Alignment);
555}
556
558 unsigned NumVectors, TTI::MaskSource Mask, VectorType *VectorTy,
559 bool IsStore, std::optional<Instruction::CastOps> CastHint) const {
560 return TTIImpl->hasMultiVectorLoadStore(NumVectors, Mask, VectorTy, IsStore,
561 CastHint);
562}
563
565 VectorType *VTy, unsigned Factor, Align Alignment,
566 unsigned AddrSpace) const {
567 return TTIImpl->isLegalInterleavedAccessType(VTy, Factor, Alignment,
568 AddrSpace);
569}
570
572 Type *DataType) const {
573 return TTIImpl->isLegalMaskedVectorHistogram(AddrType, DataType);
574}
575
577 return TTIImpl->enableOrderedReductions();
578}
579
580bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
581 return TTIImpl->hasDivRemOp(DataType, IsSigned);
582}
583
585 unsigned AddrSpace) const {
586 return TTIImpl->hasVolatileVariant(I, AddrSpace);
587}
588
590 return TTIImpl->prefersVectorizedAddressing();
591}
592
594 Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg,
595 int64_t Scale, unsigned AddrSpace) const {
596 InstructionCost Cost = TTIImpl->getScalingFactorCost(
597 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
598 assert(Cost >= 0 && "TTI should not produce negative costs!");
599 return Cost;
600}
601
603 return TTIImpl->LSRWithInstrQueries();
604}
605
607 return TTIImpl->isTruncateFree(Ty1, Ty2);
608}
609
611 return TTIImpl->isProfitableToHoist(I);
612}
613
614bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
615
617 return TTIImpl->isTypeLegal(Ty);
618}
619
621 return TTIImpl->getRegUsageForType(Ty);
622}
623
625 return TTIImpl->shouldBuildLookupTables();
626}
627
629 Constant *C) const {
630 return TTIImpl->shouldBuildLookupTablesForConstant(C);
631}
632
634 return TTIImpl->getMinimumLookupTableEntryBitWidth();
635}
636
638 return TTIImpl->shouldBuildRelLookupTables();
639}
640
642 return TTIImpl->useColdCCForColdCall(F);
643}
644
646 return TTIImpl->useFastCCForInternalCall(F);
647}
648
650 Intrinsic::ID ID, unsigned ScalarOpdIdx) const {
651 return TTIImpl->isTargetIntrinsicWithScalarOpAtArg(ID, ScalarOpdIdx);
652}
653
655 Intrinsic::ID ID, int OpdIdx) const {
656 return TTIImpl->isTargetIntrinsicWithOverloadTypeAtArg(ID, OpdIdx);
657}
658
660 Intrinsic::ID ID, int RetIdx) const {
661 return TTIImpl->isTargetIntrinsicWithStructReturnOverloadAtField(ID, RetIdx);
662}
663
668 return Ctx1 == Ctx2 ? Ctx1 : TargetTransformInfo::VectorInstrContext::None;
669}
670
673 if (!I)
675
676 // For inserts, check if the value being inserted comes from a single-use
677 // load.
678 if (isa<InsertElementInst>(I) && isa<LoadInst>(I->getOperand(1)) &&
679 I->getOperand(1)->hasOneUse())
681
682 // For extracts, check if it has a single use that is a store.
683 if (isa<ExtractElementInst>(I) && I->hasOneUse() &&
684 isa<StoreInst>(*I->user_begin()))
686
688}
689
692 ArrayRef<int> Mask, ArrayRef<Value *> Scalars,
694 const {
695 return TTIImpl->getBuildVectorContextHint(Mask, Scalars, GatherUseOps);
696}
697
699 VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract,
700 TTI::TargetCostKind CostKind, bool ForPoisonSrc, ArrayRef<Value *> VL,
701 TTI::VectorInstrContext VIC) const {
702 return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
703 CostKind, ForPoisonSrc, VL, VIC);
704}
705
708 TTI::VectorInstrContext VIC) const {
709 return TTIImpl->getOperandsScalarizationOverhead(Tys, CostKind, VIC);
710}
711
713 return TTIImpl->supportsEfficientVectorElementLoadStore();
714}
715
717 return TTIImpl->supportsTailCalls();
718}
719
721 return TTIImpl->supportsTailCallFor(CB);
722}
723
725 bool LoopHasReductions) const {
726 return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
727}
728
730TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
731 return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
732}
733
735 return TTIImpl->enableSelectOptimize();
736}
737
739 const Instruction *I) const {
740 return TTIImpl->shouldTreatInstructionLikeSelect(I);
741}
742
744 return TTIImpl->enableInterleavedAccessVectorization();
745}
746
748 return TTIImpl->enableMaskedInterleavedAccessVectorization();
749}
750
752 return TTIImpl->isFPVectorizationPotentiallyUnsafe();
753}
754
755bool
757 unsigned BitWidth,
758 unsigned AddressSpace,
759 Align Alignment,
760 unsigned *Fast) const {
761 return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
762 AddressSpace, Alignment, Fast);
763}
764
766TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
767 return TTIImpl->getPopcntSupport(IntTyWidthInBit);
768}
769
771 return TTIImpl->haveFastSqrt(Ty);
772}
773
775 return TTIImpl->haveFastClmul(Ty);
776}
777
779 const Instruction *I) const {
780 return TTIImpl->isExpensiveToSpeculativelyExecute(I);
781}
782
784 return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
785}
786
788 InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
789 assert(Cost >= 0 && "TTI should not produce negative costs!");
790 return Cost;
791}
792
794 unsigned Idx,
795 const APInt &Imm,
796 Type *Ty) const {
797 InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
798 assert(Cost >= 0 && "TTI should not produce negative costs!");
799 return Cost;
800}
801
805 InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
806 assert(Cost >= 0 && "TTI should not produce negative costs!");
807 return Cost;
808}
809
811 unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
814 TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
815 assert(Cost >= 0 && "TTI should not produce negative costs!");
816 return Cost;
817}
818
821 const APInt &Imm, Type *Ty,
824 TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
825 assert(Cost >= 0 && "TTI should not produce negative costs!");
826 return Cost;
827}
828
830 const Instruction &Inst, const Function &Fn) const {
831 return TTIImpl->preferToKeepConstantsAttached(Inst, Fn);
832}
833
834unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
835 return TTIImpl->getNumberOfRegisters(ClassID);
836}
837
839 bool IsStore) const {
840 return TTIImpl->hasConditionalLoadStoreForType(Ty, IsStore);
841}
842
844 Type *Ty) const {
845 return TTIImpl->getRegisterClassForType(Vector, Ty);
846}
847
848const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
849 return TTIImpl->getRegisterClassName(ClassID);
850}
851
853 unsigned ClassID, TTI::TargetCostKind CostKind) const {
854 return TTIImpl->getRegisterClassSpillCost(ClassID, CostKind);
855}
856
858 unsigned ClassID, TTI::TargetCostKind CostKind) const {
859 return TTIImpl->getRegisterClassReloadCost(ClassID, CostKind);
860}
861
864 return TTIImpl->getRegisterBitWidth(K);
865}
866
868 return TTIImpl->getMinVectorRegisterBitWidth();
869}
870
871std::optional<unsigned> TargetTransformInfo::getVScaleForTuning() const {
872 return TTIImpl->getVScaleForTuning();
873}
874
877 return TTIImpl->shouldMaximizeVectorBandwidth(K);
878}
879
881 bool IsScalable) const {
882 return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
883}
884
885unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
886 unsigned Opcode) const {
887 return TTIImpl->getMaximumVF(ElemWidth, Opcode);
888}
889
890unsigned TargetTransformInfo::getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
891 Type *ScalarValTy,
892 Align Alignment,
893 unsigned AddrSpace) const {
894 return TTIImpl->getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy, Alignment,
895 AddrSpace);
896}
897
899 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
900 return TTIImpl->shouldConsiderAddressTypePromotion(
901 I, AllowPromotionWithoutCommonHeader);
902}
903
905 return CacheLineSize.getNumOccurrences() > 0 ? CacheLineSize
906 : TTIImpl->getCacheLineSize();
907}
908
909std::optional<unsigned>
911 return TTIImpl->getCacheSize(Level);
912}
913
914std::optional<unsigned>
916 return TTIImpl->getCacheAssociativity(Level);
917}
918
919std::optional<unsigned> TargetTransformInfo::getMinPageSize() const {
920 return MinPageSize.getNumOccurrences() > 0 ? MinPageSize
921 : TTIImpl->getMinPageSize();
922}
923
925 return TTIImpl->getPrefetchDistance();
926}
927
929 unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
930 unsigned NumPrefetches, bool HasCall) const {
931 return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
932 NumPrefetches, HasCall);
933}
934
936 return TTIImpl->getMaxPrefetchIterationsAhead();
937}
938
940 return TTIImpl->enableWritePrefetching();
941}
942
944 return TTIImpl->shouldPrefetchAddressSpace(AS);
945}
946
948 unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
950 PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
951 TTI::TargetCostKind CostKind, std::optional<FastMathFlags> FMF) const {
952 return TTIImpl->getPartialReductionCost(Opcode, InputTypeA, InputTypeB,
953 AccumType, VF, OpAExtend, OpBExtend,
954 BinOp, CostKind, FMF);
955}
956
957unsigned
959 bool HasUnorderedReductions) const {
960 return TTIImpl->getMaxInterleaveFactor(VF, HasUnorderedReductions);
961}
962
967
968 // undef/poison don't materialize constants.
969 if (isa<UndefValue>(V))
970 return {OK_AnyValue, OP_None};
971
972 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
973 if (const auto *CI = dyn_cast<ConstantInt>(V)) {
974 if (CI->getValue().isPowerOf2())
975 OpProps = OP_PowerOf2;
976 else if (CI->getValue().isNegatedPowerOf2())
977 OpProps = OP_NegatedPowerOf2;
978 }
979 return {OK_UniformConstantValue, OpProps};
980 }
981
982 // A broadcast shuffle creates a uniform value.
983 // TODO: Add support for non-zero index broadcasts.
984 // TODO: Add support for different source vector width.
985 if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
986 if (ShuffleInst->isZeroEltSplat())
987 OpInfo = OK_UniformValue;
988
989 const Value *Splat = getSplatValue(V);
990
991 // Check for a splat of a constant or for a non uniform vector of constants
992 // and check if the constant(s) are all powers of two.
993 if (Splat) {
994 // Check for a splat of a uniform value. This is not loop aware, so return
995 // true only for the obviously uniform cases (argument, globalvalue)
997 OpInfo = OK_UniformValue;
998 } else if (isa<Constant>(Splat)) {
1000 if (auto *CI = dyn_cast<ConstantInt>(Splat)) {
1001 if (CI->getValue().isPowerOf2())
1002 OpProps = OP_PowerOf2;
1003 else if (CI->getValue().isNegatedPowerOf2())
1004 OpProps = OP_NegatedPowerOf2;
1005 }
1006 }
1007 } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
1009 bool AllPow2 = true, AllNegPow2 = true;
1010 for (uint64_t I = 0, E = CDS->getNumElements(); I != E; ++I) {
1011 if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I))) {
1012 AllPow2 &= CI->getValue().isPowerOf2();
1013 AllNegPow2 &= CI->getValue().isNegatedPowerOf2();
1014 if (AllPow2 || AllNegPow2)
1015 continue;
1016 }
1017 AllPow2 = AllNegPow2 = false;
1018 break;
1019 }
1020 OpProps = AllPow2 ? OP_PowerOf2 : OpProps;
1021 OpProps = AllNegPow2 ? OP_NegatedPowerOf2 : OpProps;
1022 } else if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
1024 }
1025
1026 return {OpInfo, OpProps};
1027}
1028
1031 assert(!Ops.empty());
1032 const auto *Op0 = Ops.front();
1033
1034 const bool IsConstant = all_of(Ops, [](Value *V) {
1035 // TODO: We should allow undef elements here
1037 !isa<UndefValue>(V);
1038 });
1039 const bool IsUniform = all_of(Ops, [=](Value *V) {
1040 // TODO: We should allow undef elements here
1041 return V == Op0;
1042 });
1043 const bool IsPowerOfTwo = all_of(Ops, [](Value *V) {
1044 // TODO: We should allow undef elements here
1045 if (auto *CI = dyn_cast<ConstantInt>(V))
1046 return CI->getValue().isPowerOf2();
1047 return false;
1048 });
1049 const bool IsNegatedPowerOfTwo = all_of(Ops, [](Value *V) {
1050 // TODO: We should allow undef elements here
1051 if (auto *CI = dyn_cast<ConstantInt>(V))
1052 return CI->getValue().isNegatedPowerOf2();
1053 return false;
1054 });
1055
1057 if (IsConstant && IsUniform)
1059 else if (IsConstant)
1061 else if (IsUniform)
1063
1065 VP = IsPowerOfTwo ? TTI::OP_PowerOf2 : VP;
1066 VP = IsNegatedPowerOfTwo ? TTI::OP_NegatedPowerOf2 : VP;
1067
1068 return {VK, VP};
1069}
1070
1074 if (X == Y)
1075 return OpInfoX;
1076 return OpInfoX.mergeWith(getOperandInfo(Y));
1077}
1078
1080 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
1081 OperandValueInfo Op1Info, OperandValueInfo Op2Info,
1082 ArrayRef<const Value *> Args, const Instruction *CtxI,
1083 const TargetLibraryInfo *TLibInfo) const {
1084
1085 // Use call cost for frem intructions that have platform specific vector math
1086 // functions, as those will be replaced with calls later by SelectionDAG or
1087 // ReplaceWithVecLib pass.
1088 if (TLibInfo && Opcode == Instruction::FRem) {
1089 VectorType *VecTy = dyn_cast<VectorType>(Ty);
1090 LibFunc Func = TLibInfo->getLibFunc(Instruction::FRem, Ty->getScalarType());
1091 if (VecTy && Func != NotLibFunc &&
1092 TLibInfo->isFunctionVectorizable(TLibInfo->getName(Func),
1093 VecTy->getElementCount()))
1094 return getCallInstrCost(nullptr, VecTy, {VecTy, VecTy}, CostKind);
1095 }
1096
1097 InstructionCost Cost = TTIImpl->getArithmeticInstrCost(
1098 Opcode, Ty, CostKind, Op1Info, Op2Info, Args, CtxI);
1099 assert(Cost >= 0 && "TTI should not produce negative costs!");
1100 return Cost;
1101}
1102
1104 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1105 const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind,
1106 ArrayRef<const Value *> Scalars) const {
1107 InstructionCost Cost = TTIImpl->getAltInstrCost(
1108 VecTy, Opcode0, Opcode1, OpcodeMask, CostKind, Scalars);
1109 assert(Cost >= 0 && "TTI should not produce negative costs!");
1110 return Cost;
1111}
1112
1114 ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy,
1116 VectorType *SubTp, ArrayRef<const Value *> Args, const Instruction *CtxI,
1117 TTI::VectorInstrContext VIC) const {
1118 assert((Mask.empty() || DstTy->isScalableTy() ||
1119 Mask.size() == DstTy->getElementCount().getKnownMinValue()) &&
1120 "Expected the Mask to match the return size if given");
1121 assert(SrcTy->getScalarType() == DstTy->getScalarType() &&
1122 "Expected the same scalar types");
1123 InstructionCost Cost = TTIImpl->getShuffleCost(
1124 Kind, DstTy, SrcTy, CostKind, Mask, Index, SubTp, Args, CtxI, VIC);
1125 assert(Cost >= 0 && "TTI should not produce negative costs!");
1126 return Cost;
1127}
1128
1131 if (auto *Cast = dyn_cast<CastInst>(I))
1132 return getPartialReductionExtendKind(Cast->getOpcode());
1133 return PR_None;
1134}
1135
1139 switch (Kind) {
1141 return Instruction::CastOps::ZExt;
1143 return Instruction::CastOps::SExt;
1145 return Instruction::CastOps::FPExt;
1146 default:
1147 break;
1148 }
1149 llvm_unreachable("Unhandled partial reduction extend kind");
1150}
1151
1154 Instruction::CastOps CastOpc) {
1155 switch (CastOpc) {
1156 case Instruction::CastOps::ZExt:
1157 return PR_ZeroExtend;
1158 case Instruction::CastOps::SExt:
1159 return PR_SignExtend;
1160 case Instruction::CastOps::FPExt:
1161 return PR_FPExtend;
1162 default:
1163 return PR_None;
1164 }
1165 llvm_unreachable("Unhandled cast opcode");
1166}
1167
1170 if (!I)
1171 return CastContextHint::None;
1172
1173 auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
1174 unsigned GatScatOp) {
1176 if (!I)
1177 return CastContextHint::None;
1178
1179 if (I->getOpcode() == LdStOp)
1181
1182 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1183 if (II->getIntrinsicID() == MaskedOp)
1185 if (II->getIntrinsicID() == GatScatOp)
1187 }
1188
1190 };
1191
1192 switch (I->getOpcode()) {
1193 case Instruction::ZExt:
1194 case Instruction::SExt:
1195 case Instruction::FPExt:
1196 return getLoadStoreKind(I->getOperand(0), Instruction::Load,
1197 Intrinsic::masked_load, Intrinsic::masked_gather);
1198 case Instruction::Trunc:
1199 case Instruction::FPTrunc:
1200 if (I->hasOneUse())
1201 return getLoadStoreKind(*I->user_begin(), Instruction::Store,
1202 Intrinsic::masked_store,
1203 Intrinsic::masked_scatter);
1204 break;
1205 default:
1206 return CastContextHint::None;
1207 }
1208
1210}
1211
1213 unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
1214 TTI::TargetCostKind CostKind, const Instruction *I) const {
1215 assert((I == nullptr || I->getOpcode() == Opcode) &&
1216 "Opcode should reflect passed instruction.");
1218 TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
1219 assert(Cost >= 0 && "TTI should not produce negative costs!");
1220 return Cost;
1221}
1222
1224 unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index,
1227 TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index, CostKind);
1228 assert(Cost >= 0 && "TTI should not produce negative costs!");
1229 return Cost;
1230}
1231
1233 unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
1234 assert((I == nullptr || I->getOpcode() == Opcode) &&
1235 "Opcode should reflect passed instruction.");
1236 InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
1237 assert(Cost >= 0 && "TTI should not produce negative costs!");
1238 return Cost;
1239}
1240
1242 unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
1244 OperandValueInfo Op2Info, const Instruction *I) const {
1245 assert((I == nullptr || I->getOpcode() == Opcode) &&
1246 "Opcode should reflect passed instruction.");
1247 InstructionCost Cost = TTIImpl->getCmpSelInstrCost(
1248 Opcode, ValTy, CondTy, VecPred, CostKind, Op1Info, Op2Info, I);
1249 assert(Cost >= 0 && "TTI should not produce negative costs!");
1250 return Cost;
1251}
1252
1254 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1255 const Value *Op0, const Value *Op1, TTI::VectorInstrContext VIC) const {
1256 assert((Opcode == Instruction::InsertElement ||
1257 Opcode == Instruction::ExtractElement) &&
1258 "Expecting Opcode to be insertelement/extractelement.");
1260 TTIImpl->getVectorInstrCost(Opcode, Val, CostKind, Index, Op0, Op1, VIC);
1261 assert(Cost >= 0 && "TTI should not produce negative costs!");
1262 return Cost;
1263}
1264
1266 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1267 Value *Scalar, ArrayRef<std::tuple<Value *, User *, int>> ScalarUserAndIdx,
1268 TTI::VectorInstrContext VIC) const {
1269 assert((Opcode == Instruction::InsertElement ||
1270 Opcode == Instruction::ExtractElement) &&
1271 "Expecting Opcode to be insertelement/extractelement.");
1272 InstructionCost Cost = TTIImpl->getVectorInstrCost(
1273 Opcode, Val, CostKind, Index, Scalar, ScalarUserAndIdx, VIC);
1274 assert(Cost >= 0 && "TTI should not produce negative costs!");
1275 return Cost;
1276}
1277
1280 unsigned Index, TTI::VectorInstrContext VIC) const {
1281 // FIXME: Assert that Opcode is either InsertElement or ExtractElement.
1282 // This is mentioned in the interface description and respected by all
1283 // callers, but never asserted upon.
1285 TTIImpl->getVectorInstrCost(I, Val, CostKind, Index, VIC);
1286 assert(Cost >= 0 && "TTI should not produce negative costs!");
1287 return Cost;
1288}
1289
1291 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind,
1292 unsigned Index) const {
1294 TTIImpl->getIndexedVectorInstrCostFromEnd(Opcode, Val, CostKind, Index);
1295 assert(Cost >= 0 && "TTI should not produce negative costs!");
1296 return Cost;
1297}
1298
1300 unsigned Opcode, TTI::TargetCostKind CostKind) const {
1301 assert((Opcode == Instruction::InsertValue ||
1302 Opcode == Instruction::ExtractValue) &&
1303 "Expecting Opcode to be insertvalue/extractvalue.");
1304 InstructionCost Cost = TTIImpl->getInsertExtractValueCost(Opcode, CostKind);
1305 assert(Cost >= 0 && "TTI should not produce negative costs!");
1306 return Cost;
1307}
1308
1310 Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts,
1312 InstructionCost Cost = TTIImpl->getReplicationShuffleCost(
1313 EltTy, ReplicationFactor, VF, DemandedDstElts, CostKind);
1314 assert(Cost >= 0 && "TTI should not produce negative costs!");
1315 return Cost;
1316}
1317
1319 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1321 const Instruction *I) const {
1322 assert((I == nullptr || I->getOpcode() == Opcode) &&
1323 "Opcode should reflect passed instruction.");
1324 InstructionCost Cost = TTIImpl->getMemoryOpCost(
1325 Opcode, Src, Alignment, AddressSpace, CostKind, OpInfo, I);
1326 assert(Cost >= 0 && "TTI should not produce negative costs!");
1327 return Cost;
1328}
1329
1331 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
1332 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
1333 bool UseMaskForCond, bool UseMaskForGaps) const {
1334 InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
1335 Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
1336 UseMaskForCond, UseMaskForGaps);
1337 assert(Cost >= 0 && "TTI should not produce negative costs!");
1338 return Cost;
1339}
1340
1344 InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
1345 assert(Cost >= 0 && "TTI should not produce negative costs!");
1346 return Cost;
1347}
1348
1350 const MemIntrinsicCostAttributes &MICA,
1352 InstructionCost Cost = TTIImpl->getMemIntrinsicInstrCost(MICA, CostKind);
1353 assert(Cost >= 0 && "TTI should not produce negative costs!");
1354 return Cost;
1355}
1356
1359 ArrayRef<Type *> Tys,
1361 InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
1362 assert(Cost >= 0 && "TTI should not produce negative costs!");
1363 return Cost;
1364}
1365
1367 return TTIImpl->getNumberOfParts(Tp);
1368}
1369
1371 Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr,
1374 TTIImpl->getAddressComputationCost(PtrTy, SE, Ptr, CostKind);
1375 assert(Cost >= 0 && "TTI should not produce negative costs!");
1376 return Cost;
1377}
1378
1380 InstructionCost Cost = TTIImpl->getMemcpyCost(I);
1381 assert(Cost >= 0 && "TTI should not produce negative costs!");
1382 return Cost;
1383}
1384
1386 return TTIImpl->getMaxMemIntrinsicInlineSizeThreshold();
1387}
1388
1390 unsigned Opcode, VectorType *Ty, std::optional<FastMathFlags> FMF,
1393 TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
1394 assert(Cost >= 0 && "TTI should not produce negative costs!");
1395 return Cost;
1396}
1397
1402 TTIImpl->getMinMaxReductionCost(IID, Ty, FMF, CostKind);
1403 assert(Cost >= 0 && "TTI should not produce negative costs!");
1404 return Cost;
1405}
1406
1408 unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1409 std::optional<FastMathFlags> FMF, TTI::TargetCostKind CostKind) const {
1410 return TTIImpl->getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
1411 CostKind);
1412}
1413
1415 bool IsUnsigned, unsigned RedOpcode, Type *ResTy, VectorType *Ty,
1417 return TTIImpl->getMulAccReductionCost(IsUnsigned, RedOpcode, ResTy, Ty,
1418 CostKind);
1419}
1420
1423 return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
1424}
1425
1427 MemIntrinsicInfo &Info) const {
1428 return TTIImpl->getTgtMemIntrinsic(Inst, Info);
1429}
1430
1432 return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
1433}
1434
1436 IntrinsicInst *Inst, Type *ExpectedType, bool CanCreate) const {
1437 return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType,
1438 CanCreate);
1439}
1440
1442 LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
1443 unsigned DestAddrSpace, Align SrcAlign, Align DestAlign,
1444 std::optional<uint32_t> AtomicElementSize) const {
1445 return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
1446 DestAddrSpace, SrcAlign, DestAlign,
1447 AtomicElementSize);
1448}
1449
1451 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
1452 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1453 Align SrcAlign, Align DestAlign,
1454 std::optional<uint32_t> AtomicCpySize) const {
1455 TTIImpl->getMemcpyLoopResidualLoweringType(
1456 OpsOut, Context, RemainingBytes, SrcAddrSpace, DestAddrSpace, SrcAlign,
1457 DestAlign, AtomicCpySize);
1458}
1459
1461 const Function *Callee) const {
1462 return TTIImpl->areInlineCompatible(Caller, Callee);
1463}
1464
1465unsigned
1467 const CallBase &Call,
1468 unsigned DefaultCallPenalty) const {
1469 return TTIImpl->getInlineCallPenalty(F, Call, DefaultCallPenalty);
1470}
1471
1473 const Function *Caller, const Attribute &Attr) const {
1474 return TTIImpl->shouldCopyAttributeWhenOutliningFrom(Caller, Attr);
1475}
1477 const Function *Callee,
1478 ArrayRef<Type *> Types) const {
1479 return TTIImpl->areTypesABICompatible(Caller, Callee, Types);
1480}
1481
1483 Type *Ty) const {
1484 return TTIImpl->isIndexedLoadLegal(Mode, Ty);
1485}
1486
1488 Type *Ty) const {
1489 return TTIImpl->isIndexedStoreLegal(Mode, Ty);
1490}
1491
1493 return TTIImpl->getLoadStoreVecRegBitWidth(AS);
1494}
1495
1497 return TTIImpl->isLegalToVectorizeLoad(LI);
1498}
1499
1501 return TTIImpl->isLegalToVectorizeStore(SI);
1502}
1503
1505 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1506 return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1507 AddrSpace);
1508}
1509
1511 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1512 return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1513 AddrSpace);
1514}
1515
1517 const RecurrenceDescriptor &RdxDesc, ElementCount VF) const {
1518 return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1519}
1520
1522 return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1523}
1524
1526 unsigned LoadSize,
1527 unsigned ChainSizeInBytes,
1528 VectorType *VecTy) const {
1529 return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1530}
1531
1533 unsigned StoreSize,
1534 unsigned ChainSizeInBytes,
1535 VectorType *VecTy) const {
1536 return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1537}
1538
1540 return TTIImpl->preferFixedOverScalableIfEqualCost();
1541}
1542
1544 Type *Ty) const {
1545 return TTIImpl->preferInLoopReduction(Kind, Ty);
1546}
1547
1549 return TTIImpl->preferAlternateOpcodeVectorization();
1550}
1551
1553 return TTIImpl->preferSLPInstCountCheck();
1554}
1555
1557 return TTIImpl->preferPredicatedReductionSelect();
1558}
1559
1561 ElementCount Iters) const {
1562 return TTIImpl->preferEpilogueVectorization(Iters);
1563}
1564
1566 return TTIImpl->shouldConsiderVectorizationRegPressure();
1567}
1568
1571 return TTIImpl->getVPLegalizationStrategy(VPI);
1572}
1573
1575 return TTIImpl->hasArmWideBranch(Thumb);
1576}
1577
1579 return TTIImpl->getFeatureMask(F);
1580}
1581
1583 return TTIImpl->getPriorityMask(F);
1584}
1585
1587 return TTIImpl->isMultiversionedFunction(F);
1588}
1589
1591 return TTIImpl->getMaxNumArgs();
1592}
1593
1595 return TTIImpl->shouldExpandReduction(II);
1596}
1597
1600 const IntrinsicInst *II) const {
1601 return TTIImpl->getPreferredExpandedReductionShuffle(II);
1602}
1603
1605 return TTIImpl->getGISelRematGlobalCost();
1606}
1607
1609 return TTIImpl->getMinTripCountTailFoldingThreshold();
1610}
1611
1613 return TTIImpl->supportsScalableVectors();
1614}
1615
1617 return TTIImpl->enableScalableVectorization();
1618}
1619
1621 return TTIImpl->hasActiveVectorLength();
1622}
1623
1625 Instruction *I, SmallVectorImpl<Use *> &OpsToSink) const {
1626 return TTIImpl->isProfitableToSinkOperands(I, OpsToSink);
1627}
1628
1630 return TTIImpl->isVectorShiftByScalarCheap(Ty);
1631}
1632
1633unsigned
1635 Type *ArrayType) const {
1636 return TTIImpl->getNumBytesToPadGlobalArray(Size, ArrayType);
1637}
1638
1640 const Function &F,
1641 SmallVectorImpl<std::pair<StringRef, int64_t>> &LB) const {
1642 return TTIImpl->collectKernelLaunchBounds(F, LB);
1643}
1644
1646 return TTIImpl->allowVectorElementIndexingUsingGEP();
1647}
1648
1650 const SmallBitVector &UniformArgs) const {
1651 return TTIImpl->isUniform(I, UniformArgs);
1652}
1653
1655
1656TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1657
1659 std::function<Result(const Function &)> TTICallback)
1660 : TTICallback(std::move(TTICallback)) {}
1661
1664 assert(!F.isIntrinsic() && "Should not request TTI for intrinsics");
1665 return TTICallback(F);
1666}
1667
1668AnalysisKey TargetIRAnalysis::Key;
1669
1670TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1671 return Result(F.getDataLayout());
1672}
1673
1674// Register the basic pass.
1676 "Target Transform Information", false, true)
1678
1679void TargetTransformInfoWrapperPass::anchor() {}
1680
1683
1687
1689 FunctionAnalysisManager DummyFAM;
1690 TTI = TIRA.run(F, DummyFAM);
1691 return *TTI;
1692}
1693
for(const MachineOperand &MO :llvm::drop_begin(OldMI.operands(), Desc.getNumOperands()))
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
unsigned Imm
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
#define X(NUM, ENUM, NAME)
Definition ELF.h:857
static GCRegistry::Add< ShadowStackGC > C("shadow-stack", "Very portable GC for uncooperative code generators")
static cl::opt< OutputCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(OutputCostKind::RecipThroughput), cl::values(clEnumValN(OutputCostKind::RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(OutputCostKind::Latency, "latency", "Instruction latency"), clEnumValN(OutputCostKind::CodeSize, "code-size", "Code size"), clEnumValN(OutputCostKind::SizeAndLatency, "size-latency", "Code size and latency"), clEnumValN(OutputCostKind::All, "all", "Print all cost kinds")))
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
Module.h This file contains the declarations for the Module class.
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
#define F(x, y, z)
Definition MD5.cpp:54
#define I(x, y, z)
Definition MD5.cpp:57
uint64_t IntrinsicInst * II
if(PassOpts->AAPipeline)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
SI Fold Operands
This file defines the SmallVector class.
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static SymbolRef::Type getType(const Symbol *Sym)
Definition TapiFile.cpp:39
This file provides helpers for the implementation of a TargetTransformInfo-conforming class.
static cl::opt< unsigned > PredictableBranchThreshold("predictable-branch-threshold", cl::init(99), cl::Hidden, cl::desc("Use this to override the target's predictable branch threshold (%)."))
static cl::opt< bool > EnableReduxCost("costmodel-reduxcost", cl::init(false), cl::Hidden, cl::desc("Recognize reduction patterns."))
static cl::opt< unsigned > MinPageSize("min-page-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target's minimum page size."))
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
This pass exposes codegen information to IR-level passes.
Class for arbitrary precision integers.
Definition APInt.h:78
an instruction to allocate memory on the stack
This class represents an incoming formal argument to a Function.
Definition Argument.h:32
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
iterator end() const
Definition ArrayRef.h:130
iterator begin() const
Definition ArrayRef.h:129
Class to represent array types.
A cache of @llvm.assume calls within a function.
Functions, function parameters, and return types can have attributes to indicate how they should be t...
Definition Attributes.h:106
LLVM Basic Block Representation.
Definition BasicBlock.h:62
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
iterator_range< User::op_iterator > args()
Iteration adapter for range-for loops.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition InstrTypes.h:740
Conditional Branch instruction.
This is an important base class in LLVM.
Definition Constant.h:43
A parsed version of the target data layout string in and methods for querying it.
Definition DataLayout.h:64
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition Dominators.h:122
LLVM_ABI bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Convenience struct for specifying and reasoning about fast-math flags.
Definition FMF.h:23
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition Pass.h:285
ImmutablePass(char &pid)
Definition Pass.h:287
The core instruction combiner logic.
Class to represent integer types.
LLVM_ABI IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false)
A wrapper class for inspecting calls to intrinsic functions.
This is an important class for using LLVM in a threaded context.
Definition LLVMContext.h:68
An instruction for reading from memory.
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
void perform(const LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Represents a single loop in the control flow graph.
Definition LoopInfo.h:40
Information for memory intrinsic cost model.
The optimization diagnostic interface.
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
This class represents a constant integer value.
This class represents an analyzed expression in the program.
The main scalar evolution driver.
LLVM_ABI uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
LLVM_ABI bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
LLVM_ABI const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
Definition TypeSize.h:30
An instruction for storing to memory.
Multiway switch.
Analysis pass providing the TargetTransformInfo.
LLVM_ABI Result run(const Function &F, FunctionAnalysisManager &)
LLVM_ABI TargetIRAnalysis()
Default construct a target IR analysis.
Provides information about what library functions are available for the current target.
StringRef getName(LibFunc F) const
bool isFunctionVectorizable(StringRef F, const ElementCount &VF) const
LibFunc getLibFunc(StringRef funcName) const
Searches for a particular function name.
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Wrapper pass for TargetTransformInfo.
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
TargetTransformInfo & getTTI(const Function &F)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
LLVM_ABI bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
LLVM_ABI Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType, bool CanCreate=true) const
LLVM_ABI bool isLegalToVectorizeLoad(LoadInst *LI) const
LLVM_ABI std::optional< unsigned > getVScaleForTuning() const
static LLVM_ABI CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
LLVM_ABI unsigned getMaxNumArgs() const
LLVM_ABI bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const
Return false if a AS0 address cannot possibly alias a AS1 address.
LLVM_ABI bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
LLVM_ABI bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
LLVM_ABI VectorInstrContext getBuildVectorContextHint(ArrayRef< int > Mask, ArrayRef< Value * > Scalars, function_ref< bool(SmallVectorImpl< BuildVectorUseOp > &)> GatherUseOps) const
Calculates a VectorInstrContext for buildvector-like gather sequences.
LLVM_ABI bool isLegalToVectorizeStore(StoreInst *SI) const
LLVM_ABI bool areTypesABICompatible(const Function *Caller, const Function *Callee, ArrayRef< Type * > Types) const
LLVM_ABI bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
LLVM_ABI bool isLegalSpeculativeLoad(Type *DataType, unsigned AddressSpace) const
Return true if the target supports speculatively loading DataType from address space AddressSpace,...
LLVM_ABI bool isMultiversionedFunction(const Function &F) const
Returns true if this is an instance of a function with multiple versions.
LLVM_ABI unsigned getMaxInterleaveFactor(ElementCount VF, bool HasUnorderedReductions) const
LLVM_ABI bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
LLVM_ABI bool isLegalMaskedStore(Type *DataType, Align Alignment, unsigned AddressSpace, MaskKind MaskKind=VariableOrConstantMask) const
Return true if the target supports masked store.
LLVM_ABI unsigned getMinimumLookupTableEntryBitWidth() const
Return the minimum bit width to use for integer switch lookup table elements on this target.
LLVM_ABI bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
LLVM_ABI unsigned getAssumedAddrSpace(const Value *V) const
LLVM_ABI bool preferAlternateOpcodeVectorization() const
LLVM_ABI bool shouldDropLSRSolutionIfLessProfitable() const
Return true if LSR should drop a found solution if it's calculated to be less profitable than the bas...
LLVM_ABI bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C2.
LLVM_ABI unsigned getPrefetchDistance() const
LLVM_ABI Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicElementSize=std::nullopt) const
LLVM_ABI bool haveFastClmul(IntegerType *Ty) const
Return true if the hardware has a fast carry-less multiplication instruction.
LLVM_ABI bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked expand load.
LLVM_ABI bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
LLVM_ABI InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
LLVM_ABI bool hasBranchDivergence(const Function *F=nullptr) const
Return true if branch divergence exists.
LLVM_ABI bool preferEpilogueVectorization(ElementCount Iters) const
Return true if the loop vectorizer should consider vectorizing an otherwise scalar epilogue loop if t...
LLVM_ABI MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
LLVM_ABI void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
LLVM_ABI bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
LLVM_ABI InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TargetCostKind CostKind, Type *AccessType=nullptr) const
Estimate the cost of a GEP operation when lowered.
LLVM_ABI TailFoldingStyle getPreferredTailFoldingStyle() const
Query the target what the preferred style of tail folding is.
LLVM_ABI bool supportsTailCallFor(const CallBase *CB) const
If target supports tail call on CB.
LLVM_ABI std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
LLVM_ABI bool isProfitableLSRChainElement(Instruction *I) const
LLVM_ABI TypeSize getRegisterBitWidth(RegisterKind K) const
MaskKind
Some targets only support masked load/store with a constant mask.
LLVM_ABI unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
Returns a penalty for invoking call Call in F.
LLVM_ABI InstructionCost getOperandsScalarizationOverhead(ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
Estimate the overhead of scalarizing operands with the given types.
LLVM_ABI bool hasActiveVectorLength() const
LLVM_ABI bool isExpensiveToSpeculativelyExecute(const Instruction *I) const
Return true if the cost of the instruction is too high to speculatively execute and should be kept be...
LLVM_ABI InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, OperandValueInfo OpdInfo={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
LLVM_ABI bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
LLVM_ABI ValueUniformity getValueUniformity(const Value *V) const
Get target-specific uniformity information for a value.
static LLVM_ABI OperandValueInfo commonOperandInfo(const Value *X, const Value *Y)
Collect common data between two OperandValueInfo inputs.
LLVM_ABI InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind) const
LLVM_ABI bool allowVectorElementIndexingUsingGEP() const
Returns true if GEP should not be used to index into vectors for this target.
LLVM_ABI bool preferTailFoldingOverEpilogue(TailFoldingInfo *TFI) const
Query the target whether it would be preferred to create a tail-folded vector loop,...
LLVM_ABI std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
LLVM_ABI bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
LLVM_ABI unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const
LLVM_ABI bool hasMultiVectorLoadStore(unsigned NumVectors, MaskSource Mask, VectorType *VectorTy=nullptr, bool IsStore=false, std::optional< Instruction::CastOps > CastHint=std::nullopt) const
Return true if the target supports loading or storing NumVectors contiguous vectors of type VectorTy ...
LLVM_ABI InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
LLVM_ABI unsigned getAtomicMemIntrinsicMaxElementSize() const
LLVM_ABI InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index=-1, const Value *Op0=nullptr, const Value *Op1=nullptr, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
LLVM_ABI std::pair< KnownBits, KnownBits > computeKnownBitsAddrSpaceCast(unsigned ToAS, const Value &PtrOp) const
LLVM_ABI bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
LLVM_ABI unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
LLVM_ABI VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
static LLVM_ABI PartialReductionExtendKind getPartialReductionExtendKind(Instruction *I)
Get the kind of extension that an instruction represents.
LLVM_ABI InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, OperandValueInfo Op1Info={OK_AnyValue, OP_None}, OperandValueInfo Op2Info={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
LLVM_ABI bool shouldConsiderVectorizationRegPressure() const
LLVM_ABI bool enableWritePrefetching() const
LLVM_ABI bool shouldTreatInstructionLikeSelect(const Instruction *I) const
Should the Select Optimization pass treat the given instruction like a select, potentially converting...
LLVM_ABI bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
LLVM_ABI bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
LLVM_ABI InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy, TTI::TargetCostKind CostKind, ArrayRef< int > Mask={}, int Index=0, VectorType *SubTp=nullptr, ArrayRef< const Value * > Args={}, const Instruction *CtxI=nullptr, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
LLVM_ABI bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace) const
Return true is the target supports interleaved access for the given vector type VTy,...
LLVM_ABI unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
LLVM_ABI bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy...
LLVM_ABI bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
LLVM_ABI std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
static LLVM_ABI TargetTransformInfo::VectorInstrContext combineVectorInstrContexts(TargetTransformInfo::VectorInstrContext Ctx1, TargetTransformInfo::VectorInstrContext Ctx2)
Combines 2 context hints into a single value.
LLVM_ABI unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
LLVM_ABI InstructionCost getRegisterClassReloadCost(unsigned ClassID, TargetCostKind CostKind) const
LLVM_ABI ReductionShuffle getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const
static LLVM_ABI OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
LLVM_ABI InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
LLVM_ABI InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
LLVM_ABI unsigned getAddressSpaceJoin(unsigned AS1, unsigned AS2) const
Return the most specific common address space containing AS1 and AS2.
LLVM_ABI unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
LLVM_ABI bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr, int64_t ScalableOffset=0) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
LLVM_ABI PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
LLVM_ABI unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
LLVM_ABI bool isElementTypeLegalForScalableVector(Type *Ty) const
LLVM_ABI bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
LLVM_ABI InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind) const
Calculate the cost of vector reduction intrinsics.
LLVM_ABI unsigned getMaxPrefetchIterationsAhead() const
LLVM_ABI bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
LLVM_ABI ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
LLVM_ABI InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
LLVM_ABI bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
LLVM_ABI InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
LLVM_ABI bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const
Return true if the target supports strided load.
LLVM_ABI TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
LLVM_ABI InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduc...
TargetCostKind
The kind of cost model.
@ TCK_RecipThroughput
Reciprocal throughput.
LLVM_ABI bool enableSelectOptimize() const
Should the Select Optimization pass be enabled and ran.
LLVM_ABI bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
OperandValueProperties
Additional properties of an operand's values.
LLVM_ABI int getInliningLastCallToStaticBonus() const
LLVM_ABI bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
LLVM_ABI InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
LLVM_ABI unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
LLVM_ABI unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
LLVM_ABI bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
LLVM_ABI bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
LLVM_ABI std::optional< unsigned > getCacheAssociativity(CacheLevel Level) const
LLVM_ABI bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
LLVM_ABI bool isUniform(const Instruction *I, const SmallBitVector &UniformArgs) const
Determine if an instruction with Custom uniformity can be proven uniform based on which operands are ...
LLVM_ABI InstructionCost getMemcpyCost(const Instruction *I) const
LLVM_ABI unsigned adjustInliningThreshold(const CallBase *CB) const
LLVM_ABI bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
LLVM_ABI bool isTargetIntrinsicWithStructReturnOverloadAtField(Intrinsic::ID ID, int RetIdx) const
Identifies if the vector form of the intrinsic that returns a struct is overloaded at the struct elem...
LLVM_ABI unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
LLVM_ABI InstructionCost getMemIntrinsicInstrCost(const MemIntrinsicCostAttributes &MICA, TTI::TargetCostKind CostKind) const
LLVM_ABI InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind) const
LLVM_ABI Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
LLVM_ABI InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
LLVM_ABI bool canSaveCmp(Loop *L, CondBrInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
LLVM_ABI unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
LLVM_ABI bool shouldPrefetchAddressSpace(unsigned AS) const
LLVM_ABI InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
LLVM_ABI unsigned getMinVectorRegisterBitWidth() const
LLVM_ABI InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr, TTI::TargetCostKind CostKind) const
LLVM_ABI bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
LLVM_ABI unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
LLVM_ABI bool preferToKeepConstantsAttached(const Instruction &Inst, const Function &Fn) const
It can be advantageous to detach complex constants from their uses to make their generation cheaper.
LLVM_ABI bool hasArmWideBranch(bool Thumb) const
LLVM_ABI const char * getRegisterClassName(unsigned ClassID) const
MaskSource
Enum describing the source/producer of a mask.
LLVM_ABI bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
LLVM_ABI APInt getPriorityMask(const Function &F) const
Returns a bitmask constructed from the target-features or fmv-features metadata of a function corresp...
LLVM_ABI BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
LLVM_ABI TargetTransformInfo(std::unique_ptr< const TargetTransformInfoImplBase > Impl)
Construct a TTI object using a type implementing the Concept API below.
LLVM_ABI bool preferInLoopReduction(RecurKind Kind, Type *Ty) const
LLVM_ABI unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const
LLVM_ABI bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const
LLVM_ABI InstructionCost getMulAccReductionCost(bool IsUnsigned, unsigned RedOpcode, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add/...
LLVM_ABI unsigned getCacheLineSize() const
LLVM_ABI bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), unsigned *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
LLVM_ABI InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind, ArrayRef< const Value * > Scalars={}) const
Returns the cost estimation for alternating opcode pattern that can be lowered to a single instructio...
LLVM_ABI bool shouldCopyAttributeWhenOutliningFrom(const Function *Caller, const Attribute &Attr) const
LLVM_ABI APInt getAddrSpaceCastPreservedPtrMask(unsigned SrcAS, unsigned DstAS) const
Returns a mask indicating which bits of a pointer remain unchanged when casting between address space...
LLVM_ABI int getInlinerVectorBonusPercent() const
LLVM_ABI unsigned getEpilogueVectorizationMinVF() const
LLVM_ABI void collectKernelLaunchBounds(const Function &F, SmallVectorImpl< std::pair< StringRef, int64_t > > &LB) const
Collect kernel launch bounds for F into LB.
PopcntSupportKind
Flags indicating the kind of support for population count.
LLVM_ABI bool preferPredicatedReductionSelect() const
LLVM_ABI InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
LLVM_ABI AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
LLVM_ABI bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
llvm::VectorInstrContext VectorInstrContext
LLVM_ABI bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
LLVM_ABI unsigned getInliningThresholdMultiplier() const
LLVM_ABI InstructionCost getBranchMispredictPenalty() const
Returns estimated penalty of a branch misprediction in latency.
LLVM_ABI unsigned getNumberOfRegisters(unsigned ClassID) const
LLVM_ABI bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
LLVM_ABI bool supportsScalableVectors() const
LLVM_ABI bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
LLVM_ABI bool isLegalMaskedCompressStore(Type *DataType, Align Alignment) const
Return true if the target supports masked compress store.
LLVM_ABI std::optional< unsigned > getMinPageSize() const
LLVM_ABI bool preferSLPInstCountCheck() const
LLVM_ABI bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
LLVM_ABI InstructionCost getInsertExtractValueCost(unsigned Opcode, TTI::TargetCostKind CostKind) const
LLVM_ABI bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
LLVM_ABI std::optional< unsigned > getCacheSize(CacheLevel Level) const
LLVM_ABI std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
LLVM_ABI InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args={}, const Instruction *CtxI=nullptr, const TargetLibraryInfo *TLibInfo=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
LLVM_ABI bool isLegalAddScalableImmediate(int64_t Imm) const
Return true if adding the specified scalable immediate is legal, that is the target has add instructi...
LLVM_ABI bool isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, unsigned ScalarOpdIdx) const
Identifies if the vector form of the intrinsic has a scalar operand.
LLVM_ABI bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
LLVM_ABI bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
LLVM_ABI unsigned getMinTripCountTailFoldingThreshold() const
LLVM_ABI InstructionCost getPartialReductionCost(unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType, ElementCount VF, PartialReductionExtendKind OpAExtend, PartialReductionExtendKind OpBExtend, std::optional< unsigned > BinOp, TTI::TargetCostKind CostKind, std::optional< FastMathFlags > FMF) const
LLVM_ABI InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
LLVM_ABI bool enableScalableVectorization() const
LLVM_ABI bool useFastCCForInternalCall(Function &F) const
Return true if the input function is internal, should use fastcc calling convention.
LLVM_ABI bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
LLVM_ABI bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
LLVM_ABI unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const
LLVM_ABI bool isLegalMaskedVectorHistogram(Type *AddrType, Type *DataType) const
LLVM_ABI unsigned getGISelRematGlobalCost() const
LLVM_ABI unsigned getNumBytesToPadGlobalArray(unsigned Size, Type *ArrayType) const
static LLVM_ABI Instruction::CastOps getOpcodeForPartialReductionExtendKind(PartialReductionExtendKind Kind)
Get the cast opcode for an extension kind.
MemIndexedMode
The type of load/store indexing.
LLVM_ABI bool isLegalMaskedLoad(Type *DataType, Align Alignment, unsigned AddressSpace, MaskKind MaskKind=VariableOrConstantMask) const
Return true if the target supports masked load.
LLVM_ABI InstructionCost getIndexedVectorInstrCostFromEnd(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index) const
LLVM_ABI bool areInlineCompatible(const Function *Caller, const Function *Callee) const
LLVM_ABI bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
LLVM_ABI InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
LLVM_ABI bool supportsTailCalls() const
If the target supports tail calls.
LLVM_ABI bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
LLVM_ABI bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Query the target whether the specified address space cast from FromAS to ToAS is valid.
LLVM_ABI unsigned getNumberOfParts(Type *Tp) const
AddressingModeKind
Which addressing mode Loop Strength Reduction will try to generate.
LLVM_ABI InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
LLVM_ABI bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
LLVM_ABI bool isProfitableToSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const
Return true if sinking I's operands to the same basic block as I is profitable, e....
LLVM_ABI void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicCpySize=std::nullopt) const
LLVM_ABI bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
LLVM_ABI bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, int OpdIdx) const
Identifies if the vector form of the intrinsic is overloaded on the type of the operand at index OpdI...
static LLVM_ABI VectorInstrContext getVectorInstrContextHint(const Instruction *I)
Calculates a VectorInstrContext from I.
LLVM_ABI InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const PointersChainInfo &Info, Type *AccessTy, const TargetCostKind CostKind) const
Estimate the cost of a chain of pointers (typically pointer operands of a chain of loads or stores wi...
LLVM_ABI bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
LLVM_ABI bool shouldExpandReduction(const IntrinsicInst *II) const
LLVM_ABI InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind, bool ForPoisonSrc=true, ArrayRef< Value * > VL={}, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
Estimate the overhead of scalarizing an instruction.
LLVM_ABI uint64_t getMaxMemIntrinsicInlineSizeThreshold() const
Returns the maximum memset / memcpy size in bytes that still makes it profitable to inline the call.
LLVM_ABI bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, ArrayRef< const Value * > Scalars={}) const
Return true if this is an alternating opcode pattern that can be lowered to a single instruction on t...
ShuffleKind
The various kinds of shuffle patterns for vector queries.
LLVM_ABI APInt getFeatureMask(const Function &F) const
Returns a bitmask constructed from the target-features or fmv-features metadata of a function corresp...
LLVM_ABI void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
CastContextHint
Represents a hint about the context in which a cast is used.
@ Masked
The cast is used with a masked load/store.
@ None
The cast is not used with a load/store of any kind.
@ Normal
The cast is used with a normal load/store.
@ GatherScatter
The cast is used with a gather/scatter.
LLVM_ABI InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index, TTI::TargetCostKind CostKind) const
LLVM_ABI InstructionCost getRegisterClassSpillCost(unsigned ClassID, TargetCostKind CostKind) const
OperandValueKind
Additional information about an operand's possible values.
CacheLevel
The possible cache levels.
LLVM_ABI bool preferFixedOverScalableIfEqualCost() const
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:46
static LLVM_ABI IntegerType * getInt32Ty(LLVMContext &C)
Definition Type.cpp:299
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition Type.h:363
LLVM_ABI bool isScalableTy() const
Return true if this is a type whose size is a known multiple of vscale.
Definition Type.cpp:61
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Definition Value.h:75
Type * getType() const
All values are typed, get the type of this value.
Definition Value.h:257
Base class of all SIMD vector types.
ElementCount getElementCount() const
Return an ElementCount instance to represent the (possibly scalable) number of elements in the vector...
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition TypeSize.h:165
An efficient, type-erasing, non-owning reference to a callable.
CallInst * Call
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
@ Length
Definition DWP.cpp:577
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1755
InstructionCost Cost
@ Known
Known to have no common set bits.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:643
VectorInstrContext
Represents a hint about the context in which a vector instruction or intrinsic is used.
@ None
The instruction is not folded.
@ Load
The value being inserted comes from a load (InsertElement only).
@ Store
The extracted value is stored (ExtractElement only).
LLVM_ABI Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
bool containsIrreducibleCFG(RPOTraversalT &RPOTraversal, const LoopInfoT &LI)
Return true if the control flow in RPOTraversal is irreducible.
Definition CFG.h:154
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
Definition Casting.h:547
LLVM_ABI ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
RecurKind
These are the kinds of recurrences that we support.
@ Fast
Assign the register banks as fast as possible (default).
constexpr unsigned BitWidth
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1933
auto predecessors(const MachineBasicBlock *BB)
AnalysisManager< Function > FunctionAnalysisManager
Convenience typedef for the Function analysis manager.
ValueUniformity
Enum describing how values behave with respect to uniformity and divergence, to answer the question: ...
Definition Uniformity.h:18
@ NeverUniform
The result value can never be assumed to be uniform.
Definition Uniformity.h:26
@ Default
The result value is uniform if and only if all operands are uniform.
Definition Uniformity.h:20
Implement std::hash so that hash_code can be used in STL containers.
Definition BitVector.h:878
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition Analysis.h:29
Attributes of a target dependent hardware loop.
LLVM_ABI bool canAnalyze(LoopInfo &LI)
LLVM_ABI bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Information about a load/store intrinsic defined by the target.
Returns options for expansion of memcmp. IsZeroCmp is.
OperandValueInfo mergeWith(const OperandValueInfo OpInfoY)
Describe known properties for a set of pointers.
Parameters that control the generic loop unrolling transformation.