LLVM 24.0.0git
TargetTransformInfo.cpp
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1//===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
11#include "llvm/Analysis/CFG.h"
15#include "llvm/IR/CFG.h"
16#include "llvm/IR/Dominators.h"
17#include "llvm/IR/Instruction.h"
20#include "llvm/IR/Module.h"
21#include "llvm/IR/Operator.h"
24#include <optional>
25#include <utility>
26
27using namespace llvm;
28using namespace PatternMatch;
29
30#define DEBUG_TYPE "tti"
31
33 "cache-line-size", cl::init(0), cl::Hidden,
34 cl::desc("Use this to override the target cache line size when "
35 "specified by the user."));
36
38 "min-page-size", cl::init(0), cl::Hidden,
39 cl::desc("Use this to override the target's minimum page size."));
40
42 "predictable-branch-threshold", cl::init(99), cl::Hidden,
44 "Use this to override the target's predictable branch threshold (%)."));
45
46namespace {
47/// No-op implementation of the TTI interface using the utility base
48/// classes.
49///
50/// This is used when no target specific information is available.
51struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
52 explicit NoTTIImpl(const DataLayout &DL)
53 : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
54};
55} // namespace
56
58 std::unique_ptr<const TargetTransformInfoImplBase> Impl)
59 : TTIImpl(std::move(Impl)) {}
60
62 // If the loop has irreducible control flow, it can not be converted to
63 // Hardware loop.
64 LoopBlocksRPO RPOT(L);
65 RPOT.perform(&LI);
67 return false;
68 return true;
69}
70
72 Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost,
73 bool TypeBasedOnly)
74 : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
75 ScalarizationCost(ScalarizationCost) {
76
77 if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
78 FMF = FPMO->getFastMathFlags();
79
80 if (!TypeBasedOnly)
81 Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
82 for (const Value *Arg : CI.args())
83 ParamTys.push_back(Arg->getType());
84}
85
88 FastMathFlags Flags,
89 const IntrinsicInst *I,
90 InstructionCost ScalarCost)
91 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
92 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
93}
94
97 : RetTy(Ty), IID(Id) {
98
99 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
100 ParamTys.reserve(Arguments.size());
101 for (const Value *Argument : Arguments)
102 ParamTys.push_back(Argument->getType());
103}
104
108 InstructionCost ScalarCost, VectorInstrContext VIC)
109 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost),
110 VIC(VIC) {
111 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
112 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
113}
114
116 // Match default options:
117 // - hardware-loop-counter-bitwidth = 32
118 // - hardware-loop-decrement = 1
119 CountType = Type::getInt32Ty(L->getHeader()->getContext());
120 LoopDecrement = ConstantInt::get(CountType, 1);
121}
122
124 LoopInfo &LI, DominatorTree &DT,
125 bool ForceNestedLoop,
127 SmallVector<BasicBlock *, 4> ExitingBlocks;
128 L->getExitingBlocks(ExitingBlocks);
129
130 for (BasicBlock *BB : ExitingBlocks) {
131 // If we pass the updated counter back through a phi, we need to know
132 // which latch the updated value will be coming from.
133 if (!L->isLoopLatch(BB)) {
135 continue;
136 }
137
138 const SCEV *EC = SE.getExitCount(L, BB);
140 continue;
141 if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
142 if (ConstEC->getValue()->isZero())
143 continue;
144 } else if (!SE.isLoopInvariant(EC, L))
145 continue;
146
147 if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
148 continue;
149
150 // If this exiting block is contained in a nested loop, it is not eligible
151 // for insertion of the branch-and-decrement since the inner loop would
152 // end up messing up the value in the CTR.
153 if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
154 continue;
155
156 // We now have a loop-invariant count of loop iterations (which is not the
157 // constant zero) for which we know that this loop will not exit via this
158 // existing block.
159
160 // We need to make sure that this block will run on every loop iteration.
161 // For this to be true, we must dominate all blocks with backedges. Such
162 // blocks are in-loop predecessors to the header block.
163 bool NotAlways = false;
164 for (BasicBlock *Pred : predecessors(L->getHeader())) {
165 if (!L->contains(Pred))
166 continue;
167
168 if (!DT.dominates(BB, Pred)) {
169 NotAlways = true;
170 break;
171 }
172 }
173
174 if (NotAlways)
175 continue;
176
177 // Make sure this blocks ends with a conditional branch.
178 if (CondBrInst *BI = dyn_cast<CondBrInst>(BB->getTerminator()))
179 ExitBranch = BI;
180 else
181 continue;
182
183 // Note that this block may not be the loop latch block, even if the loop
184 // has a latch block.
185 ExitBlock = BB;
186 ExitCount = EC;
187 break;
188 }
189
190 if (!ExitBlock)
191 return false;
192 return true;
193}
194
196 : TTIImpl(std::make_unique<NoTTIImpl>(DL)) {}
197
199
202
204 TTIImpl = std::move(RHS.TTIImpl);
205 return *this;
206}
207
209 return TTIImpl->getInliningThresholdMultiplier();
210}
211
212unsigned
214 return TTIImpl->getInliningCostBenefitAnalysisSavingsMultiplier();
215}
216
217unsigned
219 const {
220 return TTIImpl->getInliningCostBenefitAnalysisProfitableMultiplier();
221}
222
224 return TTIImpl->getInliningLastCallToStaticBonus();
225}
226
227unsigned
229 return TTIImpl->adjustInliningThreshold(CB);
230}
231
233 const AllocaInst *AI) const {
234 return TTIImpl->getCallerAllocaCost(CB, AI);
235}
236
238 return TTIImpl->getInlinerVectorBonusPercent();
239}
240
242 Type *PointeeType, const Value *Ptr, ArrayRef<const Value *> Operands,
243 TTI::TargetCostKind CostKind, Type *AccessType) const {
244 return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, CostKind, AccessType);
245}
246
249 const TTI::PointersChainInfo &Info, Type *AccessTy,
250 TTI::TargetCostKind CostKind) const {
251 assert((Base || !Info.isSameBase()) &&
252 "If pointers have same base address it has to be provided.");
253 return TTIImpl->getPointersChainCost(Ptrs, Base, Info, AccessTy, CostKind);
254}
255
257 const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
258 BlockFrequencyInfo *BFI) const {
259 return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
260}
261
265 enum TargetCostKind CostKind) const {
266 InstructionCost Cost = TTIImpl->getInstructionCost(U, Operands, CostKind);
267 assert((CostKind == TTI::TCK_RecipThroughput || Cost >= 0) &&
268 "TTI should not produce negative costs!");
269 return Cost;
270}
271
273 return PredictableBranchThreshold.getNumOccurrences() > 0
275 : TTIImpl->getPredictableBranchThreshold();
276}
277
279 return TTIImpl->getBranchMispredictPenalty();
280}
281
283 return TTIImpl->hasBranchDivergence(F);
284}
285
288 ValueUniformity VU = TTIImpl->getValueUniformity(V);
289 if (const auto *Call = dyn_cast<CallBase>(V)) {
291 Call->hasFnAttr(Attribute::NoDivergenceSource))
293 }
294 return VU;
295}
296
298 unsigned ToAS) const {
299 return TTIImpl->isValidAddrSpaceCast(FromAS, ToAS);
300}
301
303 unsigned ToAS) const {
304 return TTIImpl->addrspacesMayAlias(FromAS, ToAS);
305}
306
308 return TTIImpl->getFlatAddressSpace();
309}
310
312 unsigned AS2) const {
313 assert(AS1 != AS2 && "Expected distinct address spaces");
314 return TTIImpl->getAddressSpaceJoin(AS1, AS2);
315}
316
318 SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
319 return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
320}
321
323 unsigned ToAS) const {
324 return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
325}
326
327std::pair<KnownBits, KnownBits>
329 const Value &PtrOp) const {
330 return TTIImpl->computeKnownBitsAddrSpaceCast(ToAS, PtrOp);
331}
332
334 unsigned FromAS, unsigned ToAS, const KnownBits &FromPtrBits) const {
335 return TTIImpl->computeKnownBitsAddrSpaceCast(FromAS, ToAS, FromPtrBits);
336}
337
339 unsigned SrcAS, unsigned DstAS) const {
340 return TTIImpl->getAddrSpaceCastPreservedPtrMask(SrcAS, DstAS);
341}
342
344 unsigned AS) const {
345 return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
346}
347
349 return TTIImpl->getAssumedAddrSpace(V);
350}
351
352std::pair<const Value *, unsigned>
354 return TTIImpl->getPredicatedAddrSpace(V);
355}
356
358 IntrinsicInst *II, Value *OldV, Value *NewV) const {
359 return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
360}
361
363 return TTIImpl->isLoweredToCall(F);
364}
365
368 TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
369 return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
370}
371
373 return TTIImpl->getEpilogueVectorizationMinVF();
374}
375
377 TailFoldingInfo *TFI) const {
378 return TTIImpl->preferTailFoldingOverEpilogue(TFI);
379}
380
382 return TTIImpl->getPreferredTailFoldingStyle();
383}
384
385std::optional<Instruction *>
387 IntrinsicInst &II) const {
388 return TTIImpl->instCombineIntrinsic(IC, II);
389}
390
392 InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
393 bool &KnownBitsComputed) const {
394 return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
395 KnownBitsComputed);
396}
397
399 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
400 APInt &UndefElts2, APInt &UndefElts3,
401 std::function<void(Instruction *, unsigned, APInt, APInt &)>
402 SimplifyAndSetOp) const {
403 return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
404 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
405 SimplifyAndSetOp);
406}
407
410 OptimizationRemarkEmitter *ORE) const {
411 return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
412}
413
415 PeelingPreferences &PP) const {
416 return TTIImpl->getPeelingPreferences(L, SE, PP);
417}
418
420 return TTIImpl->isLegalAddImmediate(Imm);
421}
422
424 return TTIImpl->isLegalAddScalableImmediate(Imm);
425}
426
428 return TTIImpl->isLegalICmpImmediate(Imm);
429}
430
432 const ICmpInst &Cond, const APInt &PostIncExitValue) const {
433 return TTIImpl->preferLoopExitWithEqualityComparison(Cond, PostIncExitValue);
434}
435
437 int64_t BaseOffset,
438 bool HasBaseReg, int64_t Scale,
439 unsigned AddrSpace,
440 Instruction *I,
441 int64_t ScalableOffset) const {
442 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
443 Scale, AddrSpace, I, ScalableOffset);
444}
445
447 const LSRCost &C2) const {
448 return TTIImpl->isLSRCostLess(C1, C2);
449}
450
452 return TTIImpl->isNumRegsMajorCostOfLSR();
453}
454
456 return TTIImpl->shouldDropLSRSolutionIfLessProfitable();
457}
458
460 return TTIImpl->isProfitableLSRChainElement(I);
461}
462
464 return TTIImpl->canMacroFuseCmp();
465}
466
468 ScalarEvolution *SE, LoopInfo *LI,
470 TargetLibraryInfo *LibInfo) const {
471 return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
472}
473
476 ScalarEvolution *SE) const {
477 return TTIImpl->getPreferredAddressingMode(L, SE);
478}
479
481 unsigned AddressSpace,
482 TTI::MaskKind MaskKind) const {
483 return TTIImpl->isLegalMaskedStore(DataType, Alignment, AddressSpace,
484 MaskKind);
485}
486
488 unsigned AddressSpace,
489 TTI::MaskKind MaskKind) const {
490 return TTIImpl->isLegalMaskedLoad(DataType, Alignment, AddressSpace,
491 MaskKind);
492}
493
495 unsigned AddressSpace) const {
496 return TTIImpl->isLegalSpeculativeLoad(DataType, AddressSpace);
497}
498
500 Align Alignment) const {
501 return TTIImpl->isLegalNTStore(DataType, Alignment);
502}
503
504bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
505 return TTIImpl->isLegalNTLoad(DataType, Alignment);
506}
507
509 ElementCount NumElements) const {
510 return TTIImpl->isLegalBroadcastLoad(ElementTy, NumElements);
511}
512
514 Align Alignment) const {
515 return TTIImpl->isLegalMaskedGather(DataType, Alignment);
516}
517
519 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
520 const SmallBitVector &OpcodeMask, ArrayRef<const Value *> Scalars) const {
521 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask, Scalars);
522}
523
525 Align Alignment) const {
526 return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
527}
528
530 Align Alignment) const {
531 return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment);
532}
533
535 Align Alignment) const {
536 return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment);
537}
538
540 Align Alignment) const {
541 return TTIImpl->isLegalMaskedCompressStore(DataType, Alignment);
542}
543
545 Align Alignment) const {
546 return TTIImpl->isLegalMaskedExpandLoad(DataType, Alignment);
547}
548
550 Align Alignment) const {
551 return TTIImpl->isLegalStridedLoadStore(DataType, Alignment);
552}
553
555 unsigned NumVectors, TTI::MaskSource Mask, VectorType *VectorTy,
556 bool IsStore, std::optional<Instruction::CastOps> CastHint) const {
557 return TTIImpl->hasMultiVectorLoadStore(NumVectors, Mask, VectorTy, IsStore,
558 CastHint);
559}
560
562 VectorType *VTy, unsigned Factor, Align Alignment,
563 unsigned AddrSpace) const {
564 return TTIImpl->isLegalInterleavedAccessType(VTy, Factor, Alignment,
565 AddrSpace);
566}
567
569 Type *DataType) const {
570 return TTIImpl->isLegalMaskedVectorHistogram(AddrType, DataType);
571}
572
574 return TTIImpl->enableOrderedReductions();
575}
576
577bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
578 return TTIImpl->hasDivRemOp(DataType, IsSigned);
579}
580
582 unsigned AddrSpace) const {
583 return TTIImpl->hasVolatileVariant(I, AddrSpace);
584}
585
587 return TTIImpl->prefersVectorizedAddressing();
588}
589
591 Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg,
592 int64_t Scale, unsigned AddrSpace) const {
593 InstructionCost Cost = TTIImpl->getScalingFactorCost(
594 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
595 assert(Cost >= 0 && "TTI should not produce negative costs!");
596 return Cost;
597}
598
600 return TTIImpl->LSRWithInstrQueries();
601}
602
604 return TTIImpl->isTruncateFree(Ty1, Ty2);
605}
606
608 return TTIImpl->isProfitableToHoist(I);
609}
610
611bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
612
614 return TTIImpl->isTypeLegal(Ty);
615}
616
618 return TTIImpl->getRegUsageForType(Ty);
619}
620
622 return TTIImpl->shouldBuildLookupTables();
623}
624
626 Constant *C) const {
627 return TTIImpl->shouldBuildLookupTablesForConstant(C);
628}
629
631 return TTIImpl->getMinimumLookupTableEntryBitWidth();
632}
633
635 return TTIImpl->shouldBuildRelLookupTables();
636}
637
639 return TTIImpl->useColdCCForColdCall(F);
640}
641
643 return TTIImpl->useFastCCForInternalCall(F);
644}
645
647 Intrinsic::ID ID, unsigned ScalarOpdIdx) const {
648 return TTIImpl->isTargetIntrinsicWithScalarOpAtArg(ID, ScalarOpdIdx);
649}
650
652 Intrinsic::ID ID, int OpdIdx) const {
653 return TTIImpl->isTargetIntrinsicWithOverloadTypeAtArg(ID, OpdIdx);
654}
655
657 Intrinsic::ID ID, int RetIdx) const {
658 return TTIImpl->isTargetIntrinsicWithStructReturnOverloadAtField(ID, RetIdx);
659}
660
665 return Ctx1 == Ctx2 ? Ctx1 : TargetTransformInfo::VectorInstrContext::None;
666}
667
670 if (!I)
672
673 // For inserts, check if the value being inserted comes from a single-use
674 // load.
675 if (isa<InsertElementInst>(I) && isa<LoadInst>(I->getOperand(1)) &&
676 I->getOperand(1)->hasOneUse())
678
679 // For extracts, check if it has a single use that is a store.
680 if (isa<ExtractElementInst>(I) && I->hasOneUse() &&
681 isa<StoreInst>(*I->user_begin()))
683
685}
686
689 ArrayRef<int> Mask, ArrayRef<Value *> Scalars,
691 const {
692 return TTIImpl->getBuildVectorContextHint(Mask, Scalars, GatherUseOps);
693}
694
696 VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract,
697 TTI::TargetCostKind CostKind, bool ForPoisonSrc, ArrayRef<Value *> VL,
698 TTI::VectorInstrContext VIC) const {
699 return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
700 CostKind, ForPoisonSrc, VL, VIC);
701}
702
705 TTI::VectorInstrContext VIC) const {
706 return TTIImpl->getOperandsScalarizationOverhead(Tys, CostKind, VIC);
707}
708
710 return TTIImpl->supportsEfficientVectorElementLoadStore();
711}
712
714 return TTIImpl->supportsTailCalls();
715}
716
718 return TTIImpl->supportsTailCallFor(CB);
719}
720
722 bool LoopHasReductions) const {
723 return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
724}
725
727TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
728 return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
729}
730
732 return TTIImpl->enableSelectOptimize();
733}
734
736 const Instruction *I) const {
737 return TTIImpl->shouldTreatInstructionLikeSelect(I);
738}
739
741 return TTIImpl->enableInterleavedAccessVectorization();
742}
743
745 return TTIImpl->enableMaskedInterleavedAccessVectorization();
746}
747
749 return TTIImpl->isFPVectorizationPotentiallyUnsafe();
750}
751
752bool
754 unsigned BitWidth,
755 unsigned AddressSpace,
756 Align Alignment,
757 unsigned *Fast) const {
758 return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
759 AddressSpace, Alignment, Fast);
760}
761
763TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
764 return TTIImpl->getPopcntSupport(IntTyWidthInBit);
765}
766
768 return TTIImpl->haveFastSqrt(Ty);
769}
770
772 const Instruction *I) const {
773 return TTIImpl->isExpensiveToSpeculativelyExecute(I);
774}
775
777 return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
778}
779
781 InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
782 assert(Cost >= 0 && "TTI should not produce negative costs!");
783 return Cost;
784}
785
787 unsigned Idx,
788 const APInt &Imm,
789 Type *Ty) const {
790 InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
791 assert(Cost >= 0 && "TTI should not produce negative costs!");
792 return Cost;
793}
794
797 TTI::TargetCostKind CostKind) const {
798 InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
799 assert(Cost >= 0 && "TTI should not produce negative costs!");
800 return Cost;
801}
802
804 unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
805 TTI::TargetCostKind CostKind, Instruction *Inst) const {
807 TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
808 assert(Cost >= 0 && "TTI should not produce negative costs!");
809 return Cost;
810}
811
814 const APInt &Imm, Type *Ty,
815 TTI::TargetCostKind CostKind) const {
817 TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
818 assert(Cost >= 0 && "TTI should not produce negative costs!");
819 return Cost;
820}
821
823 const Instruction &Inst, const Function &Fn) const {
824 return TTIImpl->preferToKeepConstantsAttached(Inst, Fn);
825}
826
827unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
828 return TTIImpl->getNumberOfRegisters(ClassID);
829}
830
832 bool IsStore) const {
833 return TTIImpl->hasConditionalLoadStoreForType(Ty, IsStore);
834}
835
837 Type *Ty) const {
838 return TTIImpl->getRegisterClassForType(Vector, Ty);
839}
840
841const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
842 return TTIImpl->getRegisterClassName(ClassID);
843}
844
846 unsigned ClassID, TTI::TargetCostKind CostKind) const {
847 return TTIImpl->getRegisterClassSpillCost(ClassID, CostKind);
848}
849
851 unsigned ClassID, TTI::TargetCostKind CostKind) const {
852 return TTIImpl->getRegisterClassReloadCost(ClassID, CostKind);
853}
854
857 return TTIImpl->getRegisterBitWidth(K);
858}
859
861 return TTIImpl->getMinVectorRegisterBitWidth();
862}
863
864std::optional<unsigned> TargetTransformInfo::getVScaleForTuning() const {
865 return TTIImpl->getVScaleForTuning();
866}
867
870 return TTIImpl->shouldMaximizeVectorBandwidth(K);
871}
872
874 bool IsScalable) const {
875 return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
876}
877
878unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
879 unsigned Opcode) const {
880 return TTIImpl->getMaximumVF(ElemWidth, Opcode);
881}
882
883unsigned TargetTransformInfo::getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
884 Type *ScalarValTy,
885 Align Alignment,
886 unsigned AddrSpace) const {
887 return TTIImpl->getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy, Alignment,
888 AddrSpace);
889}
890
892 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
893 return TTIImpl->shouldConsiderAddressTypePromotion(
894 I, AllowPromotionWithoutCommonHeader);
895}
896
898 return CacheLineSize.getNumOccurrences() > 0 ? CacheLineSize
899 : TTIImpl->getCacheLineSize();
900}
901
902std::optional<unsigned>
904 return TTIImpl->getCacheSize(Level);
905}
906
907std::optional<unsigned>
909 return TTIImpl->getCacheAssociativity(Level);
910}
911
912std::optional<unsigned> TargetTransformInfo::getMinPageSize() const {
913 return MinPageSize.getNumOccurrences() > 0 ? MinPageSize
914 : TTIImpl->getMinPageSize();
915}
916
918 return TTIImpl->getPrefetchDistance();
919}
920
922 unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
923 unsigned NumPrefetches, bool HasCall) const {
924 return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
925 NumPrefetches, HasCall);
926}
927
929 return TTIImpl->getMaxPrefetchIterationsAhead();
930}
931
933 return TTIImpl->enableWritePrefetching();
934}
935
937 return TTIImpl->shouldPrefetchAddressSpace(AS);
938}
939
941 unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
943 PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
944 TTI::TargetCostKind CostKind, std::optional<FastMathFlags> FMF) const {
945 return TTIImpl->getPartialReductionCost(Opcode, InputTypeA, InputTypeB,
946 AccumType, VF, OpAExtend, OpBExtend,
947 BinOp, CostKind, FMF);
948}
949
950unsigned
952 bool HasUnorderedReductions) const {
953 return TTIImpl->getMaxInterleaveFactor(VF, HasUnorderedReductions);
954}
955
960
961 // undef/poison don't materialize constants.
962 if (isa<UndefValue>(V))
963 return {OK_AnyValue, OP_None};
964
965 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
966 if (const auto *CI = dyn_cast<ConstantInt>(V)) {
967 if (CI->getValue().isPowerOf2())
968 OpProps = OP_PowerOf2;
969 else if (CI->getValue().isNegatedPowerOf2())
970 OpProps = OP_NegatedPowerOf2;
971 }
972 return {OK_UniformConstantValue, OpProps};
973 }
974
975 // A broadcast shuffle creates a uniform value.
976 // TODO: Add support for non-zero index broadcasts.
977 // TODO: Add support for different source vector width.
978 if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
979 if (ShuffleInst->isZeroEltSplat())
980 OpInfo = OK_UniformValue;
981
982 const Value *Splat = getSplatValue(V);
983
984 // Check for a splat of a constant or for a non uniform vector of constants
985 // and check if the constant(s) are all powers of two.
986 if (Splat) {
987 // Check for a splat of a uniform value. This is not loop aware, so return
988 // true only for the obviously uniform cases (argument, globalvalue)
990 OpInfo = OK_UniformValue;
991 } else if (isa<Constant>(Splat)) {
993 if (auto *CI = dyn_cast<ConstantInt>(Splat)) {
994 if (CI->getValue().isPowerOf2())
995 OpProps = OP_PowerOf2;
996 else if (CI->getValue().isNegatedPowerOf2())
997 OpProps = OP_NegatedPowerOf2;
998 }
999 }
1000 } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
1002 bool AllPow2 = true, AllNegPow2 = true;
1003 for (uint64_t I = 0, E = CDS->getNumElements(); I != E; ++I) {
1004 if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I))) {
1005 AllPow2 &= CI->getValue().isPowerOf2();
1006 AllNegPow2 &= CI->getValue().isNegatedPowerOf2();
1007 if (AllPow2 || AllNegPow2)
1008 continue;
1009 }
1010 AllPow2 = AllNegPow2 = false;
1011 break;
1012 }
1013 OpProps = AllPow2 ? OP_PowerOf2 : OpProps;
1014 OpProps = AllNegPow2 ? OP_NegatedPowerOf2 : OpProps;
1015 } else if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
1017 }
1018
1019 return {OpInfo, OpProps};
1020}
1021
1024 assert(!Ops.empty());
1025 const auto *Op0 = Ops.front();
1026
1027 const bool IsConstant = all_of(Ops, [](Value *V) {
1028 // TODO: We should allow undef elements here
1030 !isa<UndefValue>(V);
1031 });
1032 const bool IsUniform = all_of(Ops, [=](Value *V) {
1033 // TODO: We should allow undef elements here
1034 return V == Op0;
1035 });
1036 const bool IsPowerOfTwo = all_of(Ops, [](Value *V) {
1037 // TODO: We should allow undef elements here
1038 if (auto *CI = dyn_cast<ConstantInt>(V))
1039 return CI->getValue().isPowerOf2();
1040 return false;
1041 });
1042 const bool IsNegatedPowerOfTwo = all_of(Ops, [](Value *V) {
1043 // TODO: We should allow undef elements here
1044 if (auto *CI = dyn_cast<ConstantInt>(V))
1045 return CI->getValue().isNegatedPowerOf2();
1046 return false;
1047 });
1048
1050 if (IsConstant && IsUniform)
1052 else if (IsConstant)
1054 else if (IsUniform)
1056
1058 VP = IsPowerOfTwo ? TTI::OP_PowerOf2 : VP;
1059 VP = IsNegatedPowerOfTwo ? TTI::OP_NegatedPowerOf2 : VP;
1060
1061 return {VK, VP};
1062}
1063
1067 if (X == Y)
1068 return OpInfoX;
1069 return OpInfoX.mergeWith(getOperandInfo(Y));
1070}
1071
1073 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
1074 OperandValueInfo Op1Info, OperandValueInfo Op2Info,
1075 ArrayRef<const Value *> Args, const Instruction *CtxI,
1076 const TargetLibraryInfo *TLibInfo) const {
1077
1078 // Use call cost for frem instructions that have platform specific vector math
1079 // functions, as those will be replaced with calls later by SelectionDAG or
1080 // ReplaceWithVecLib pass.
1081 if (TLibInfo && Opcode == Instruction::FRem) {
1082 VectorType *VecTy = dyn_cast<VectorType>(Ty);
1083 LibFunc Func = TLibInfo->getLibFunc(Instruction::FRem, Ty->getScalarType());
1084 if (VecTy && Func != NotLibFunc &&
1085 TLibInfo->isFunctionVectorizable(TLibInfo->getName(Func),
1086 VecTy->getElementCount()))
1087 return getCallInstrCost(nullptr, VecTy, {VecTy, VecTy}, CostKind);
1088 }
1089
1090 InstructionCost Cost = TTIImpl->getArithmeticInstrCost(
1091 Opcode, Ty, CostKind, Op1Info, Op2Info, Args, CtxI);
1092 assert(Cost >= 0 && "TTI should not produce negative costs!");
1093 return Cost;
1094}
1095
1097 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1098 const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind,
1099 ArrayRef<const Value *> Scalars) const {
1100 InstructionCost Cost = TTIImpl->getAltInstrCost(
1101 VecTy, Opcode0, Opcode1, OpcodeMask, CostKind, Scalars);
1102 assert(Cost >= 0 && "TTI should not produce negative costs!");
1103 return Cost;
1104}
1105
1107 ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy,
1108 TTI::TargetCostKind CostKind, ArrayRef<int> Mask, int Index,
1109 VectorType *SubTp, ArrayRef<const Value *> Args, const Instruction *CtxI,
1110 TTI::VectorInstrContext VIC) const {
1111 assert((Mask.empty() || DstTy->isScalableTy() ||
1112 Mask.size() == DstTy->getElementCount().getKnownMinValue()) &&
1113 "Expected the Mask to match the return size if given");
1114 assert(SrcTy->getScalarType() == DstTy->getScalarType() &&
1115 "Expected the same scalar types");
1116 InstructionCost Cost = TTIImpl->getShuffleCost(
1117 Kind, DstTy, SrcTy, CostKind, Mask, Index, SubTp, Args, CtxI, VIC);
1118 assert(Cost >= 0 && "TTI should not produce negative costs!");
1119 return Cost;
1120}
1121
1124 if (auto *Cast = dyn_cast<CastInst>(I))
1125 return getPartialReductionExtendKind(Cast->getOpcode());
1126 return PR_None;
1127}
1128
1132 switch (Kind) {
1134 return Instruction::CastOps::ZExt;
1136 return Instruction::CastOps::SExt;
1138 return Instruction::CastOps::FPExt;
1139 default:
1140 break;
1141 }
1142 llvm_unreachable("Unhandled partial reduction extend kind");
1143}
1144
1147 Instruction::CastOps CastOpc) {
1148 switch (CastOpc) {
1149 case Instruction::CastOps::ZExt:
1150 return PR_ZeroExtend;
1151 case Instruction::CastOps::SExt:
1152 return PR_SignExtend;
1153 case Instruction::CastOps::FPExt:
1154 return PR_FPExtend;
1155 default:
1156 return PR_None;
1157 }
1158 llvm_unreachable("Unhandled cast opcode");
1159}
1160
1163 if (!I)
1164 return CastContextHint::None;
1165
1166 auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
1167 unsigned GatScatOp) {
1169 if (!I)
1170 return CastContextHint::None;
1171
1172 if (I->getOpcode() == LdStOp)
1174
1175 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1176 if (II->getIntrinsicID() == MaskedOp)
1178 if (II->getIntrinsicID() == GatScatOp)
1180 }
1181
1183 };
1184
1185 switch (I->getOpcode()) {
1186 case Instruction::ZExt:
1187 case Instruction::SExt:
1188 case Instruction::FPExt:
1189 return getLoadStoreKind(I->getOperand(0), Instruction::Load,
1190 Intrinsic::masked_load, Intrinsic::masked_gather);
1191 case Instruction::Trunc:
1192 case Instruction::FPTrunc:
1193 if (I->hasOneUse())
1194 return getLoadStoreKind(*I->user_begin(), Instruction::Store,
1195 Intrinsic::masked_store,
1196 Intrinsic::masked_scatter);
1197 break;
1198 default:
1199 return CastContextHint::None;
1200 }
1201
1203}
1204
1206 unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
1207 TTI::TargetCostKind CostKind, const Instruction *I) const {
1208 assert((I == nullptr || I->getOpcode() == Opcode) &&
1209 "Opcode should reflect passed instruction.");
1211 TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
1212 assert(Cost >= 0 && "TTI should not produce negative costs!");
1213 return Cost;
1214}
1215
1217 unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index,
1218 TTI::TargetCostKind CostKind) const {
1220 TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index, CostKind);
1221 assert(Cost >= 0 && "TTI should not produce negative costs!");
1222 return Cost;
1223}
1224
1226 unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
1227 assert((I == nullptr || I->getOpcode() == Opcode) &&
1228 "Opcode should reflect passed instruction.");
1229 InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
1230 assert(Cost >= 0 && "TTI should not produce negative costs!");
1231 return Cost;
1232}
1233
1235 unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
1236 TTI::TargetCostKind CostKind, OperandValueInfo Op1Info,
1237 OperandValueInfo Op2Info, const Instruction *I) const {
1238 assert((I == nullptr || I->getOpcode() == Opcode) &&
1239 "Opcode should reflect passed instruction.");
1240 InstructionCost Cost = TTIImpl->getCmpSelInstrCost(
1241 Opcode, ValTy, CondTy, VecPred, CostKind, Op1Info, Op2Info, I);
1242 assert(Cost >= 0 && "TTI should not produce negative costs!");
1243 return Cost;
1244}
1245
1247 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1248 const Value *Op0, const Value *Op1, TTI::VectorInstrContext VIC) const {
1249 assert((Opcode == Instruction::InsertElement ||
1250 Opcode == Instruction::ExtractElement) &&
1251 "Expecting Opcode to be insertelement/extractelement.");
1253 TTIImpl->getVectorInstrCost(Opcode, Val, CostKind, Index, Op0, Op1, VIC);
1254 assert(Cost >= 0 && "TTI should not produce negative costs!");
1255 return Cost;
1256}
1257
1259 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1260 Value *Scalar, ArrayRef<std::tuple<Value *, User *, int>> ScalarUserAndIdx,
1261 TTI::VectorInstrContext VIC) const {
1262 assert((Opcode == Instruction::InsertElement ||
1263 Opcode == Instruction::ExtractElement) &&
1264 "Expecting Opcode to be insertelement/extractelement.");
1265 InstructionCost Cost = TTIImpl->getVectorInstrCost(
1266 Opcode, Val, CostKind, Index, Scalar, ScalarUserAndIdx, VIC);
1267 assert(Cost >= 0 && "TTI should not produce negative costs!");
1268 return Cost;
1269}
1270
1272 const Instruction &I, Type *Val, TTI::TargetCostKind CostKind,
1273 unsigned Index, TTI::VectorInstrContext VIC) const {
1274 // FIXME: Assert that Opcode is either InsertElement or ExtractElement.
1275 // This is mentioned in the interface description and respected by all
1276 // callers, but never asserted upon.
1278 TTIImpl->getVectorInstrCost(I, Val, CostKind, Index, VIC);
1279 assert(Cost >= 0 && "TTI should not produce negative costs!");
1280 return Cost;
1281}
1282
1284 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind,
1285 unsigned Index) const {
1287 TTIImpl->getIndexedVectorInstrCostFromEnd(Opcode, Val, CostKind, Index);
1288 assert(Cost >= 0 && "TTI should not produce negative costs!");
1289 return Cost;
1290}
1291
1293 unsigned Opcode, TTI::TargetCostKind CostKind) const {
1294 assert((Opcode == Instruction::InsertValue ||
1295 Opcode == Instruction::ExtractValue) &&
1296 "Expecting Opcode to be insertvalue/extractvalue.");
1297 InstructionCost Cost = TTIImpl->getInsertExtractValueCost(Opcode, CostKind);
1298 assert(Cost >= 0 && "TTI should not produce negative costs!");
1299 return Cost;
1300}
1301
1303 Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts,
1304 TTI::TargetCostKind CostKind) const {
1305 InstructionCost Cost = TTIImpl->getReplicationShuffleCost(
1306 EltTy, ReplicationFactor, VF, DemandedDstElts, CostKind);
1307 assert(Cost >= 0 && "TTI should not produce negative costs!");
1308 return Cost;
1309}
1310
1312 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1314 const Instruction *I) const {
1315 assert((I == nullptr || I->getOpcode() == Opcode) &&
1316 "Opcode should reflect passed instruction.");
1317 InstructionCost Cost = TTIImpl->getMemoryOpCost(
1318 Opcode, Src, Alignment, AddressSpace, CostKind, OpInfo, I);
1319 assert(Cost >= 0 && "TTI should not produce negative costs!");
1320 return Cost;
1321}
1322
1324 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
1325 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
1326 bool UseMaskForCond, bool UseMaskForGaps) const {
1327 InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
1328 Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
1329 UseMaskForCond, UseMaskForGaps);
1330 assert(Cost >= 0 && "TTI should not produce negative costs!");
1331 return Cost;
1332}
1333
1336 TTI::TargetCostKind CostKind) const {
1337 InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
1338 assert(Cost >= 0 && "TTI should not produce negative costs!");
1339 return Cost;
1340}
1341
1343 const MemIntrinsicCostAttributes &MICA,
1344 TTI::TargetCostKind CostKind) const {
1345 InstructionCost Cost = TTIImpl->getMemIntrinsicInstrCost(MICA, CostKind);
1346 assert(Cost >= 0 && "TTI should not produce negative costs!");
1347 return Cost;
1348}
1349
1352 ArrayRef<Type *> Tys,
1353 TTI::TargetCostKind CostKind) const {
1354 InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
1355 assert(Cost >= 0 && "TTI should not produce negative costs!");
1356 return Cost;
1357}
1358
1360 return TTIImpl->getNumberOfParts(Tp);
1361}
1362
1364 Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr,
1365 TTI::TargetCostKind CostKind) const {
1367 TTIImpl->getAddressComputationCost(PtrTy, SE, Ptr, CostKind);
1368 assert(Cost >= 0 && "TTI should not produce negative costs!");
1369 return Cost;
1370}
1371
1373 InstructionCost Cost = TTIImpl->getMemcpyCost(I);
1374 assert(Cost >= 0 && "TTI should not produce negative costs!");
1375 return Cost;
1376}
1377
1379 return TTIImpl->getMaxMemIntrinsicInlineSizeThreshold();
1380}
1381
1383 unsigned Opcode, VectorType *Ty, std::optional<FastMathFlags> FMF,
1384 TTI::TargetCostKind CostKind) const {
1386 TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
1387 assert(Cost >= 0 && "TTI should not produce negative costs!");
1388 return Cost;
1389}
1390
1393 TTI::TargetCostKind CostKind) const {
1395 TTIImpl->getMinMaxReductionCost(IID, Ty, FMF, CostKind);
1396 assert(Cost >= 0 && "TTI should not produce negative costs!");
1397 return Cost;
1398}
1399
1401 unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1402 std::optional<FastMathFlags> FMF, TTI::TargetCostKind CostKind) const {
1403 return TTIImpl->getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
1404 CostKind);
1405}
1406
1408 bool IsUnsigned, unsigned RedOpcode, Type *ResTy, VectorType *Ty,
1409 TTI::TargetCostKind CostKind) const {
1410 return TTIImpl->getMulAccReductionCost(IsUnsigned, RedOpcode, ResTy, Ty,
1411 CostKind);
1412}
1413
1416 return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
1417}
1418
1420 MemIntrinsicInfo &Info) const {
1421 return TTIImpl->getTgtMemIntrinsic(Inst, Info);
1422}
1423
1425 return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
1426}
1427
1429 IntrinsicInst *Inst, Type *ExpectedType, bool CanCreate) const {
1430 return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType,
1431 CanCreate);
1432}
1433
1435 LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
1436 unsigned DestAddrSpace, Align SrcAlign, Align DestAlign,
1437 std::optional<uint32_t> AtomicElementSize) const {
1438 return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
1439 DestAddrSpace, SrcAlign, DestAlign,
1440 AtomicElementSize);
1441}
1442
1444 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
1445 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1446 Align SrcAlign, Align DestAlign,
1447 std::optional<uint32_t> AtomicCpySize) const {
1448 TTIImpl->getMemcpyLoopResidualLoweringType(
1449 OpsOut, Context, RemainingBytes, SrcAddrSpace, DestAddrSpace, SrcAlign,
1450 DestAlign, AtomicCpySize);
1451}
1452
1454 const Function *Callee) const {
1455 return TTIImpl->areInlineCompatible(Caller, Callee);
1456}
1457
1458unsigned
1460 const CallBase &Call,
1461 unsigned DefaultCallPenalty) const {
1462 return TTIImpl->getInlineCallPenalty(F, Call, DefaultCallPenalty);
1463}
1464
1466 const Function *Caller, const Attribute &Attr) const {
1467 return TTIImpl->shouldCopyAttributeWhenOutliningFrom(Caller, Attr);
1468}
1470 const Function *Callee,
1471 ArrayRef<Type *> Types) const {
1472 return TTIImpl->areTypesABICompatible(Caller, Callee, Types);
1473}
1474
1476 Type *Ty) const {
1477 return TTIImpl->isIndexedLoadLegal(Mode, Ty);
1478}
1479
1481 Type *Ty) const {
1482 return TTIImpl->isIndexedStoreLegal(Mode, Ty);
1483}
1484
1486 return TTIImpl->getLoadStoreVecRegBitWidth(AS);
1487}
1488
1490 return TTIImpl->isLegalToVectorizeLoad(LI);
1491}
1492
1494 return TTIImpl->isLegalToVectorizeStore(SI);
1495}
1496
1498 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1499 return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1500 AddrSpace);
1501}
1502
1504 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1505 return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1506 AddrSpace);
1507}
1508
1510 const RecurrenceDescriptor &RdxDesc, ElementCount VF) const {
1511 return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1512}
1513
1515 return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1516}
1517
1519 unsigned LoadSize,
1520 unsigned ChainSizeInBytes,
1521 VectorType *VecTy) const {
1522 return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1523}
1524
1526 unsigned StoreSize,
1527 unsigned ChainSizeInBytes,
1528 VectorType *VecTy) const {
1529 return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1530}
1531
1533 return TTIImpl->preferFixedOverScalableIfEqualCost();
1534}
1535
1537 Type *Ty) const {
1538 return TTIImpl->preferInLoopReduction(Kind, Ty);
1539}
1540
1542 return TTIImpl->preferAlternateOpcodeVectorization();
1543}
1544
1546 return TTIImpl->preferSLPInstCountCheck();
1547}
1548
1550 return TTIImpl->preferPredicatedReductionSelect();
1551}
1552
1554 ElementCount Iters) const {
1555 return TTIImpl->preferEpilogueVectorization(Iters);
1556}
1557
1559 return TTIImpl->shouldConsiderVectorizationRegPressure();
1560}
1561
1564 return TTIImpl->getVPLegalizationStrategy(VPI);
1565}
1566
1568 return TTIImpl->hasArmWideBranch(Thumb);
1569}
1570
1572 return TTIImpl->getFeatureMask(F);
1573}
1574
1576 return TTIImpl->getPriorityMask(F);
1577}
1578
1580 return TTIImpl->isMultiversionedFunction(F);
1581}
1582
1584 return TTIImpl->getMaxNumArgs();
1585}
1586
1588 return TTIImpl->shouldExpandReduction(II);
1589}
1590
1593 const IntrinsicInst *II) const {
1594 return TTIImpl->getPreferredExpandedReductionShuffle(II);
1595}
1596
1598 return TTIImpl->getGISelRematGlobalCost();
1599}
1600
1602 return TTIImpl->getMinTripCountTailFoldingThreshold();
1603}
1604
1606 return TTIImpl->supportsScalableVectors();
1607}
1608
1610 return TTIImpl->enableScalableVectorization();
1611}
1612
1614 return TTIImpl->hasActiveVectorLength();
1615}
1616
1618 Instruction *I, SmallVectorImpl<Use *> &OpsToSink) const {
1619 return TTIImpl->isProfitableToSinkOperands(I, OpsToSink);
1620}
1621
1623 return TTIImpl->isVectorShiftByScalarCheap(Ty);
1624}
1625
1627 const Function &F,
1628 SmallVectorImpl<std::pair<StringRef, int64_t>> &LB) const {
1629 return TTIImpl->collectKernelLaunchBounds(F, LB);
1630}
1631
1633 return TTIImpl->allowVectorElementIndexingUsingGEP();
1634}
1635
1637 const SmallBitVector &UniformArgs) const {
1638 return TTIImpl->isUniform(I, UniformArgs);
1639}
1640
1642
1643TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1644
1646 std::function<Result(const Function &)> TTICallback)
1647 : TTICallback(std::move(TTICallback)) {}
1648
1651 assert(!F.isIntrinsic() && "Should not request TTI for intrinsics");
1652 return TTICallback(F);
1653}
1654
1655AnalysisKey TargetIRAnalysis::Key;
1656
1657TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1658 return Result(F.getDataLayout());
1659}
1660
1661// Register the basic pass.
1663 "Target Transform Information", false, true)
1665
1666void TargetTransformInfoWrapperPass::anchor() {}
1667
1670
1674
1676 FunctionAnalysisManager DummyFAM;
1677 TTI = TIRA.run(F, DummyFAM);
1678 return *TTI;
1679}
1680
for(const MachineOperand &MO :llvm::drop_begin(OldMI.operands(), Desc.getNumOperands()))
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
uint64_t Imm
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
#define X(NUM, ENUM, NAME)
Definition ELF.h:665
static GCRegistry::Add< ShadowStackGC > C("shadow-stack", "Very portable GC for uncooperative code generators")
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
Module.h This file contains the declarations for the Module class.
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
#define F(x, y, z)
Definition MD5.cpp:54
#define I(x, y, z)
Definition MD5.cpp:57
uint64_t IntrinsicInst * II
if(PassOpts->AAPipeline)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
SmallVector< MachineOperand, 4 > Cond
int64_t C1
SI Fold Operands
This file defines the SmallVector class.
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static SymbolRef::Type getType(const Symbol *Sym)
Definition TapiFile.cpp:39
This file provides helpers for the implementation of a TargetTransformInfo-conforming class.
static cl::opt< unsigned > PredictableBranchThreshold("predictable-branch-threshold", cl::init(99), cl::Hidden, cl::desc("Use this to override the target's predictable branch threshold (%)."))
static cl::opt< unsigned > MinPageSize("min-page-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target's minimum page size."))
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
This pass exposes codegen information to IR-level passes.
Class for arbitrary precision integers.
Definition APInt.h:78
an instruction to allocate memory on the stack
This class represents an incoming formal argument to a Function.
Definition Argument.h:32
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
iterator end() const
Definition ArrayRef.h:130
iterator begin() const
Definition ArrayRef.h:129
A cache of @llvm.assume calls within a function.
Functions, function parameters, and return types can have attributes to indicate how they should be t...
Definition Attributes.h:106
LLVM Basic Block Representation.
Definition BasicBlock.h:62
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
iterator_range< User::op_iterator > args()
Iteration adapter for range-for loops.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition InstrTypes.h:740
Conditional Branch instruction.
This is an important base class in LLVM.
Definition Constant.h:44
A parsed version of the target data layout string in and methods for querying it.
Definition DataLayout.h:64
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition Dominators.h:122
LLVM_ABI bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Convenience struct for specifying and reasoning about fast-math flags.
Definition FMF.h:23
This instruction compares its operands according to the predicate given to the constructor.
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition Pass.h:283
ImmutablePass(char &pid)
Definition Pass.h:285
The core instruction combiner logic.
LLVM_ABI IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false)
A wrapper class for inspecting calls to intrinsic functions.
This is an important class for using LLVM in a threaded context.
Definition LLVMContext.h:76
An instruction for reading from memory.
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
void perform(const LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Represents a single loop in the control flow graph.
Definition LoopInfo.h:40
Information for memory intrinsic cost model.
The optimization diagnostic interface.
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
This class represents a constant integer value.
This class represents an analyzed expression in the program.
The main scalar evolution driver.
LLVM_ABI uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
LLVM_ABI bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
LLVM_ABI const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
Definition TypeSize.h:31
An instruction for storing to memory.
Multiway switch.
Analysis pass providing the TargetTransformInfo.
LLVM_ABI Result run(const Function &F, FunctionAnalysisManager &)
LLVM_ABI TargetIRAnalysis()
Default construct a target IR analysis.
Provides information about what library functions are available for the current target.
StringRef getName(LibFunc F) const
bool isFunctionVectorizable(StringRef F, const ElementCount &VF) const
LibFunc getLibFunc(StringRef funcName) const
Searches for a particular function name.
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Wrapper pass for TargetTransformInfo.
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
TargetTransformInfo & getTTI(const Function &F)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
LLVM_ABI bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
LLVM_ABI Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType, bool CanCreate=true) const
LLVM_ABI bool isLegalToVectorizeLoad(LoadInst *LI) const
LLVM_ABI std::optional< unsigned > getVScaleForTuning() const
static LLVM_ABI CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
LLVM_ABI unsigned getMaxNumArgs() const
LLVM_ABI bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const
Return false if a AS0 address cannot possibly alias a AS1 address.
LLVM_ABI bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
LLVM_ABI bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
LLVM_ABI VectorInstrContext getBuildVectorContextHint(ArrayRef< int > Mask, ArrayRef< Value * > Scalars, function_ref< bool(SmallVectorImpl< BuildVectorUseOp > &)> GatherUseOps) const
Calculates a VectorInstrContext for buildvector-like gather sequences.
LLVM_ABI bool isLegalToVectorizeStore(StoreInst *SI) const
LLVM_ABI bool areTypesABICompatible(const Function *Caller, const Function *Callee, ArrayRef< Type * > Types) const
LLVM_ABI bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
LLVM_ABI bool isLegalSpeculativeLoad(Type *DataType, unsigned AddressSpace) const
Return true if the target supports speculatively loading DataType from address space AddressSpace,...
LLVM_ABI bool isMultiversionedFunction(const Function &F) const
Returns true if this is an instance of a function with multiple versions.
LLVM_ABI unsigned getMaxInterleaveFactor(ElementCount VF, bool HasUnorderedReductions) const
LLVM_ABI bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
LLVM_ABI bool isLegalMaskedStore(Type *DataType, Align Alignment, unsigned AddressSpace, MaskKind MaskKind=VariableOrConstantMask) const
Return true if the target supports masked store.
LLVM_ABI unsigned getMinimumLookupTableEntryBitWidth() const
Return the minimum bit width to use for integer switch lookup table elements on this target.
LLVM_ABI bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
LLVM_ABI unsigned getAssumedAddrSpace(const Value *V) const
LLVM_ABI bool preferAlternateOpcodeVectorization() const
LLVM_ABI bool shouldDropLSRSolutionIfLessProfitable() const
Return true if LSR should drop a found solution if it's calculated to be less profitable than the bas...
LLVM_ABI bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C2.
LLVM_ABI unsigned getPrefetchDistance() const
LLVM_ABI Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicElementSize=std::nullopt) const
LLVM_ABI bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked expand load.
LLVM_ABI bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
LLVM_ABI InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
LLVM_ABI bool hasBranchDivergence(const Function *F=nullptr) const
Return true if branch divergence exists.
LLVM_ABI bool preferEpilogueVectorization(ElementCount Iters) const
Return true if the loop vectorizer should consider vectorizing an otherwise scalar epilogue loop if t...
LLVM_ABI MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
LLVM_ABI void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
LLVM_ABI bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
LLVM_ABI InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TargetCostKind CostKind, Type *AccessType=nullptr) const
Estimate the cost of a GEP operation when lowered.
LLVM_ABI TailFoldingStyle getPreferredTailFoldingStyle() const
Query the target what the preferred style of tail folding is.
LLVM_ABI bool supportsTailCallFor(const CallBase *CB) const
If target supports tail call on CB.
LLVM_ABI std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
LLVM_ABI bool isProfitableLSRChainElement(Instruction *I) const
LLVM_ABI TypeSize getRegisterBitWidth(RegisterKind K) const
MaskKind
Some targets only support masked load/store with a constant mask.
LLVM_ABI unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
Returns a penalty for invoking call Call in F.
LLVM_ABI InstructionCost getOperandsScalarizationOverhead(ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
Estimate the overhead of scalarizing operands with the given types.
LLVM_ABI bool hasActiveVectorLength() const
LLVM_ABI bool isExpensiveToSpeculativelyExecute(const Instruction *I) const
Return true if the cost of the instruction is too high to speculatively execute and should be kept be...
LLVM_ABI InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, OperandValueInfo OpdInfo={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
LLVM_ABI bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
LLVM_ABI ValueUniformity getValueUniformity(const Value *V) const
Get target-specific uniformity information for a value.
static LLVM_ABI OperandValueInfo commonOperandInfo(const Value *X, const Value *Y)
Collect common data between two OperandValueInfo inputs.
LLVM_ABI InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind) const
LLVM_ABI bool allowVectorElementIndexingUsingGEP() const
Returns true if GEP should not be used to index into vectors for this target.
LLVM_ABI bool preferTailFoldingOverEpilogue(TailFoldingInfo *TFI) const
Query the target whether it would be preferred to create a tail-folded vector loop,...
LLVM_ABI std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
LLVM_ABI bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
LLVM_ABI unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const
LLVM_ABI bool hasMultiVectorLoadStore(unsigned NumVectors, MaskSource Mask, VectorType *VectorTy=nullptr, bool IsStore=false, std::optional< Instruction::CastOps > CastHint=std::nullopt) const
Return true if the target supports loading or storing NumVectors contiguous vectors of type VectorTy ...
LLVM_ABI InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
LLVM_ABI unsigned getAtomicMemIntrinsicMaxElementSize() const
LLVM_ABI InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index=-1, const Value *Op0=nullptr, const Value *Op1=nullptr, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
LLVM_ABI std::pair< KnownBits, KnownBits > computeKnownBitsAddrSpaceCast(unsigned ToAS, const Value &PtrOp) const
LLVM_ABI bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
LLVM_ABI unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
LLVM_ABI VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
static LLVM_ABI PartialReductionExtendKind getPartialReductionExtendKind(Instruction *I)
Get the kind of extension that an instruction represents.
LLVM_ABI InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, OperandValueInfo Op1Info={OK_AnyValue, OP_None}, OperandValueInfo Op2Info={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
LLVM_ABI bool shouldConsiderVectorizationRegPressure() const
LLVM_ABI bool enableWritePrefetching() const
LLVM_ABI bool shouldTreatInstructionLikeSelect(const Instruction *I) const
Should the Select Optimization pass treat the given instruction like a select, potentially converting...
LLVM_ABI bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
LLVM_ABI bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
LLVM_ABI InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy, TTI::TargetCostKind CostKind, ArrayRef< int > Mask={}, int Index=0, VectorType *SubTp=nullptr, ArrayRef< const Value * > Args={}, const Instruction *CtxI=nullptr, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
LLVM_ABI bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace) const
Return true is the target supports interleaved access for the given vector type VTy,...
LLVM_ABI unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
LLVM_ABI bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy...
LLVM_ABI bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
LLVM_ABI std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
static LLVM_ABI TargetTransformInfo::VectorInstrContext combineVectorInstrContexts(TargetTransformInfo::VectorInstrContext Ctx1, TargetTransformInfo::VectorInstrContext Ctx2)
Combines 2 context hints into a single value.
LLVM_ABI unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
LLVM_ABI InstructionCost getRegisterClassReloadCost(unsigned ClassID, TargetCostKind CostKind) const
LLVM_ABI ReductionShuffle getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const
static LLVM_ABI OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
LLVM_ABI InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
LLVM_ABI InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
LLVM_ABI unsigned getAddressSpaceJoin(unsigned AS1, unsigned AS2) const
Return the most specific common address space containing AS1 and AS2.
LLVM_ABI unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
LLVM_ABI bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr, int64_t ScalableOffset=0) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
LLVM_ABI PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
LLVM_ABI unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
LLVM_ABI bool isElementTypeLegalForScalableVector(Type *Ty) const
LLVM_ABI bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
LLVM_ABI InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind) const
Calculate the cost of vector reduction intrinsics.
LLVM_ABI unsigned getMaxPrefetchIterationsAhead() const
LLVM_ABI bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
LLVM_ABI ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
LLVM_ABI InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
LLVM_ABI bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
LLVM_ABI InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
LLVM_ABI bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const
Return true if the target supports strided load.
LLVM_ABI TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
LLVM_ABI InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduc...
TargetCostKind
The kind of cost model.
@ TCK_RecipThroughput
Reciprocal throughput.
LLVM_ABI bool enableSelectOptimize() const
Should the Select Optimization pass be enabled and ran.
LLVM_ABI bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
OperandValueProperties
Additional properties of an operand's values.
LLVM_ABI int getInliningLastCallToStaticBonus() const
LLVM_ABI bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
LLVM_ABI InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
LLVM_ABI unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
LLVM_ABI unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
LLVM_ABI bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
LLVM_ABI bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
LLVM_ABI std::optional< unsigned > getCacheAssociativity(CacheLevel Level) const
LLVM_ABI bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
LLVM_ABI bool isUniform(const Instruction *I, const SmallBitVector &UniformArgs) const
Determine if an instruction with Custom uniformity can be proven uniform based on which operands are ...
LLVM_ABI InstructionCost getMemcpyCost(const Instruction *I) const
LLVM_ABI unsigned adjustInliningThreshold(const CallBase *CB) const
LLVM_ABI bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
LLVM_ABI bool isTargetIntrinsicWithStructReturnOverloadAtField(Intrinsic::ID ID, int RetIdx) const
Identifies if the vector form of the intrinsic that returns a struct is overloaded at the struct elem...
LLVM_ABI unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
LLVM_ABI InstructionCost getMemIntrinsicInstrCost(const MemIntrinsicCostAttributes &MICA, TTI::TargetCostKind CostKind) const
LLVM_ABI InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind) const
LLVM_ABI Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
LLVM_ABI InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
LLVM_ABI bool canSaveCmp(Loop *L, CondBrInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
LLVM_ABI unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
LLVM_ABI bool shouldPrefetchAddressSpace(unsigned AS) const
LLVM_ABI InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
LLVM_ABI unsigned getMinVectorRegisterBitWidth() const
LLVM_ABI InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr, TTI::TargetCostKind CostKind) const
LLVM_ABI bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
LLVM_ABI unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
LLVM_ABI bool preferToKeepConstantsAttached(const Instruction &Inst, const Function &Fn) const
It can be advantageous to detach complex constants from their uses to make their generation cheaper.
LLVM_ABI bool hasArmWideBranch(bool Thumb) const
LLVM_ABI const char * getRegisterClassName(unsigned ClassID) const
MaskSource
Enum describing the source/producer of a mask.
LLVM_ABI bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
LLVM_ABI APInt getPriorityMask(const Function &F) const
Returns a bitmask constructed from the target-features or fmv-features metadata of a function corresp...
LLVM_ABI BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
LLVM_ABI TargetTransformInfo(std::unique_ptr< const TargetTransformInfoImplBase > Impl)
Construct a TTI object using a type implementing the Concept API below.
LLVM_ABI bool preferInLoopReduction(RecurKind Kind, Type *Ty) const
LLVM_ABI unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const
LLVM_ABI bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const
LLVM_ABI InstructionCost getMulAccReductionCost(bool IsUnsigned, unsigned RedOpcode, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add/...
LLVM_ABI unsigned getCacheLineSize() const
LLVM_ABI bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), unsigned *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
LLVM_ABI InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind, ArrayRef< const Value * > Scalars={}) const
Returns the cost estimation for alternating opcode pattern that can be lowered to a single instructio...
LLVM_ABI bool shouldCopyAttributeWhenOutliningFrom(const Function *Caller, const Attribute &Attr) const
LLVM_ABI APInt getAddrSpaceCastPreservedPtrMask(unsigned SrcAS, unsigned DstAS) const
Returns a mask indicating which bits of a pointer remain unchanged when casting between address space...
LLVM_ABI int getInlinerVectorBonusPercent() const
LLVM_ABI unsigned getEpilogueVectorizationMinVF() const
LLVM_ABI void collectKernelLaunchBounds(const Function &F, SmallVectorImpl< std::pair< StringRef, int64_t > > &LB) const
Collect kernel launch bounds for F into LB.
PopcntSupportKind
Flags indicating the kind of support for population count.
LLVM_ABI bool preferPredicatedReductionSelect() const
LLVM_ABI InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
LLVM_ABI AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
LLVM_ABI bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
llvm::VectorInstrContext VectorInstrContext
LLVM_ABI bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
LLVM_ABI unsigned getInliningThresholdMultiplier() const
LLVM_ABI InstructionCost getBranchMispredictPenalty() const
Returns estimated penalty of a branch misprediction in latency.
LLVM_ABI unsigned getNumberOfRegisters(unsigned ClassID) const
LLVM_ABI bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
LLVM_ABI bool supportsScalableVectors() const
LLVM_ABI bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
LLVM_ABI bool isLegalMaskedCompressStore(Type *DataType, Align Alignment) const
Return true if the target supports masked compress store.
LLVM_ABI std::optional< unsigned > getMinPageSize() const
LLVM_ABI bool preferSLPInstCountCheck() const
LLVM_ABI bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
LLVM_ABI InstructionCost getInsertExtractValueCost(unsigned Opcode, TTI::TargetCostKind CostKind) const
LLVM_ABI bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
LLVM_ABI std::optional< unsigned > getCacheSize(CacheLevel Level) const
LLVM_ABI std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
LLVM_ABI InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args={}, const Instruction *CtxI=nullptr, const TargetLibraryInfo *TLibInfo=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
LLVM_ABI bool isLegalAddScalableImmediate(int64_t Imm) const
Return true if adding the specified scalable immediate is legal, that is the target has add instructi...
LLVM_ABI bool isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, unsigned ScalarOpdIdx) const
Identifies if the vector form of the intrinsic has a scalar operand.
LLVM_ABI bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
LLVM_ABI bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
LLVM_ABI unsigned getMinTripCountTailFoldingThreshold() const
LLVM_ABI InstructionCost getPartialReductionCost(unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType, ElementCount VF, PartialReductionExtendKind OpAExtend, PartialReductionExtendKind OpBExtend, std::optional< unsigned > BinOp, TTI::TargetCostKind CostKind, std::optional< FastMathFlags > FMF) const
LLVM_ABI InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
LLVM_ABI bool enableScalableVectorization() const
LLVM_ABI bool useFastCCForInternalCall(Function &F) const
Return true if the input function is internal, should use fastcc calling convention.
LLVM_ABI bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
LLVM_ABI bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
LLVM_ABI unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const
LLVM_ABI bool isLegalMaskedVectorHistogram(Type *AddrType, Type *DataType) const
LLVM_ABI unsigned getGISelRematGlobalCost() const
static LLVM_ABI Instruction::CastOps getOpcodeForPartialReductionExtendKind(PartialReductionExtendKind Kind)
Get the cast opcode for an extension kind.
MemIndexedMode
The type of load/store indexing.
LLVM_ABI bool isLegalMaskedLoad(Type *DataType, Align Alignment, unsigned AddressSpace, MaskKind MaskKind=VariableOrConstantMask) const
Return true if the target supports masked load.
LLVM_ABI InstructionCost getIndexedVectorInstrCostFromEnd(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index) const
LLVM_ABI bool areInlineCompatible(const Function *Caller, const Function *Callee) const
LLVM_ABI bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
LLVM_ABI InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
LLVM_ABI bool supportsTailCalls() const
If the target supports tail calls.
LLVM_ABI bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
LLVM_ABI bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Query the target whether the specified address space cast from FromAS to ToAS is valid.
LLVM_ABI unsigned getNumberOfParts(Type *Tp) const
AddressingModeKind
Which addressing mode Loop Strength Reduction will try to generate.
LLVM_ABI bool preferLoopExitWithEqualityComparison(const ICmpInst &Cond, const APInt &PostIncExitValue) const
Return true if replacing the relational loop exit comparison Cond with an equality comparison against...
LLVM_ABI InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
LLVM_ABI bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
LLVM_ABI bool isProfitableToSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const
Return true if sinking I's operands to the same basic block as I is profitable, e....
LLVM_ABI void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicCpySize=std::nullopt) const
LLVM_ABI bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
LLVM_ABI bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, int OpdIdx) const
Identifies if the vector form of the intrinsic is overloaded on the type of the operand at index OpdI...
static LLVM_ABI VectorInstrContext getVectorInstrContextHint(const Instruction *I)
Calculates a VectorInstrContext from I.
LLVM_ABI InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const PointersChainInfo &Info, Type *AccessTy, const TargetCostKind CostKind) const
Estimate the cost of a chain of pointers (typically pointer operands of a chain of loads or stores wi...
LLVM_ABI bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
LLVM_ABI bool shouldExpandReduction(const IntrinsicInst *II) const
LLVM_ABI InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind, bool ForPoisonSrc=true, ArrayRef< Value * > VL={}, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
Estimate the overhead of scalarizing an instruction.
LLVM_ABI uint64_t getMaxMemIntrinsicInlineSizeThreshold() const
Returns the maximum memset / memcpy size in bytes that still makes it profitable to inline the call.
LLVM_ABI bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, ArrayRef< const Value * > Scalars={}) const
Return true if this is an alternating opcode pattern that can be lowered to a single instruction on t...
ShuffleKind
The various kinds of shuffle patterns for vector queries.
LLVM_ABI APInt getFeatureMask(const Function &F) const
Returns a bitmask constructed from the target-features or fmv-features metadata of a function corresp...
LLVM_ABI void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
CastContextHint
Represents a hint about the context in which a cast is used.
@ Masked
The cast is used with a masked load/store.
@ None
The cast is not used with a load/store of any kind.
@ Normal
The cast is used with a normal load/store.
@ GatherScatter
The cast is used with a gather/scatter.
LLVM_ABI InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index, TTI::TargetCostKind CostKind) const
LLVM_ABI InstructionCost getRegisterClassSpillCost(unsigned ClassID, TargetCostKind CostKind) const
OperandValueKind
Additional information about an operand's possible values.
CacheLevel
The possible cache levels.
LLVM_ABI bool preferFixedOverScalableIfEqualCost() const
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:46
static LLVM_ABI IntegerType * getInt32Ty(LLVMContext &C)
Definition Type.cpp:299
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition Type.h:363
LLVM_ABI bool isScalableTy() const
Return true if this is a type whose size is a known multiple of vscale.
Definition Type.cpp:61
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Definition Value.h:75
Type * getType() const
All values are typed, get the type of this value.
Definition Value.h:257
Base class of all SIMD vector types.
ElementCount getElementCount() const
Return an ElementCount instance to represent the (possibly scalable) number of elements in the vector...
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition TypeSize.h:166
An efficient, type-erasing, non-owning reference to a callable.
CallInst * Call
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
@ Length
Definition DWP.cpp:577
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1755
InstructionCost Cost
@ Known
Known to have no common set bits.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:643
VectorInstrContext
Represents a hint about the context in which a vector instruction or intrinsic is used.
@ None
The instruction is not folded.
@ Load
The value being inserted comes from a load (InsertElement only).
@ Store
The extracted value is stored (ExtractElement only).
LLVM_ABI Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
bool containsIrreducibleCFG(RPOTraversalT &RPOTraversal, const LoopInfoT &LI)
Return true if the control flow in RPOTraversal is irreducible.
Definition CFG.h:154
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
Definition Casting.h:547
LLVM_ABI ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
RecurKind
These are the kinds of recurrences that we support.
@ Fast
Assign the register banks as fast as possible (default).
constexpr unsigned BitWidth
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1933
auto predecessors(const MachineBasicBlock *BB)
AnalysisManager< Function > FunctionAnalysisManager
Convenience typedef for the Function analysis manager.
ValueUniformity
Enum describing how values behave with respect to uniformity and divergence, to answer the question: ...
Definition Uniformity.h:18
@ NeverUniform
The result value can never be assumed to be uniform.
Definition Uniformity.h:26
@ Default
The result value is uniform if and only if all operands are uniform.
Definition Uniformity.h:20
Implement std::hash so that hash_code can be used in STL containers.
Definition BitVector.h:878
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition Analysis.h:29
Attributes of a target dependent hardware loop.
LLVM_ABI bool canAnalyze(LoopInfo &LI)
LLVM_ABI bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Information about a load/store intrinsic defined by the target.
Returns options for expansion of memcmp. IsZeroCmp is.
OperandValueInfo mergeWith(const OperandValueInfo OpInfoY)
Describe known properties for a set of pointers.
Parameters that control the generic loop unrolling transformation.