LLVM 24.0.0git
TargetTransformInfo.cpp
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1//===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
11#include "llvm/Analysis/CFG.h"
15#include "llvm/IR/CFG.h"
16#include "llvm/IR/Dominators.h"
17#include "llvm/IR/Instruction.h"
20#include "llvm/IR/Module.h"
21#include "llvm/IR/Operator.h"
24#include <optional>
25#include <utility>
26
27using namespace llvm;
28using namespace PatternMatch;
29
30#define DEBUG_TYPE "tti"
31
32static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
34 cl::desc("Recognize reduction patterns."));
35
37 "cache-line-size", cl::init(0), cl::Hidden,
38 cl::desc("Use this to override the target cache line size when "
39 "specified by the user."));
40
42 "min-page-size", cl::init(0), cl::Hidden,
43 cl::desc("Use this to override the target's minimum page size."));
44
46 "predictable-branch-threshold", cl::init(99), cl::Hidden,
48 "Use this to override the target's predictable branch threshold (%)."));
49
50namespace {
51/// No-op implementation of the TTI interface using the utility base
52/// classes.
53///
54/// This is used when no target specific information is available.
55struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
56 explicit NoTTIImpl(const DataLayout &DL)
57 : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
58};
59} // namespace
60
62 std::unique_ptr<const TargetTransformInfoImplBase> Impl)
63 : TTIImpl(std::move(Impl)) {}
64
66 // If the loop has irreducible control flow, it can not be converted to
67 // Hardware loop.
68 LoopBlocksRPO RPOT(L);
69 RPOT.perform(&LI);
71 return false;
72 return true;
73}
74
76 Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost,
77 bool TypeBasedOnly)
78 : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
79 ScalarizationCost(ScalarizationCost) {
80
81 if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
82 FMF = FPMO->getFastMathFlags();
83
84 if (!TypeBasedOnly)
85 Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
86 for (const Value *Arg : CI.args())
87 ParamTys.push_back(Arg->getType());
88}
89
92 FastMathFlags Flags,
93 const IntrinsicInst *I,
94 InstructionCost ScalarCost)
95 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
96 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
97}
98
101 : RetTy(Ty), IID(Id) {
102
103 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
104 ParamTys.reserve(Arguments.size());
105 for (const Value *Argument : Arguments)
106 ParamTys.push_back(Argument->getType());
107}
108
112 InstructionCost ScalarCost, VectorInstrContext VIC)
113 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost),
114 VIC(VIC) {
115 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
116 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
117}
118
120 // Match default options:
121 // - hardware-loop-counter-bitwidth = 32
122 // - hardware-loop-decrement = 1
123 CountType = Type::getInt32Ty(L->getHeader()->getContext());
124 LoopDecrement = ConstantInt::get(CountType, 1);
125}
126
128 LoopInfo &LI, DominatorTree &DT,
129 bool ForceNestedLoop,
131 SmallVector<BasicBlock *, 4> ExitingBlocks;
132 L->getExitingBlocks(ExitingBlocks);
133
134 for (BasicBlock *BB : ExitingBlocks) {
135 // If we pass the updated counter back through a phi, we need to know
136 // which latch the updated value will be coming from.
137 if (!L->isLoopLatch(BB)) {
139 continue;
140 }
141
142 const SCEV *EC = SE.getExitCount(L, BB);
144 continue;
145 if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
146 if (ConstEC->getValue()->isZero())
147 continue;
148 } else if (!SE.isLoopInvariant(EC, L))
149 continue;
150
151 if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
152 continue;
153
154 // If this exiting block is contained in a nested loop, it is not eligible
155 // for insertion of the branch-and-decrement since the inner loop would
156 // end up messing up the value in the CTR.
157 if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
158 continue;
159
160 // We now have a loop-invariant count of loop iterations (which is not the
161 // constant zero) for which we know that this loop will not exit via this
162 // existing block.
163
164 // We need to make sure that this block will run on every loop iteration.
165 // For this to be true, we must dominate all blocks with backedges. Such
166 // blocks are in-loop predecessors to the header block.
167 bool NotAlways = false;
168 for (BasicBlock *Pred : predecessors(L->getHeader())) {
169 if (!L->contains(Pred))
170 continue;
171
172 if (!DT.dominates(BB, Pred)) {
173 NotAlways = true;
174 break;
175 }
176 }
177
178 if (NotAlways)
179 continue;
180
181 // Make sure this blocks ends with a conditional branch.
182 Instruction *TI = BB->getTerminator();
183 if (!TI)
184 continue;
185
186 if (CondBrInst *BI = dyn_cast<CondBrInst>(TI))
187 ExitBranch = BI;
188 else
189 continue;
190
191 // Note that this block may not be the loop latch block, even if the loop
192 // has a latch block.
193 ExitBlock = BB;
194 ExitCount = EC;
195 break;
196 }
197
198 if (!ExitBlock)
199 return false;
200 return true;
201}
202
204 : TTIImpl(std::make_unique<NoTTIImpl>(DL)) {}
205
207
210
212 TTIImpl = std::move(RHS.TTIImpl);
213 return *this;
214}
215
217 return TTIImpl->getInliningThresholdMultiplier();
218}
219
220unsigned
222 return TTIImpl->getInliningCostBenefitAnalysisSavingsMultiplier();
223}
224
225unsigned
227 const {
228 return TTIImpl->getInliningCostBenefitAnalysisProfitableMultiplier();
229}
230
232 return TTIImpl->getInliningLastCallToStaticBonus();
233}
234
235unsigned
237 return TTIImpl->adjustInliningThreshold(CB);
238}
239
241 const AllocaInst *AI) const {
242 return TTIImpl->getCallerAllocaCost(CB, AI);
243}
244
246 return TTIImpl->getInlinerVectorBonusPercent();
247}
248
250 Type *PointeeType, const Value *Ptr, ArrayRef<const Value *> Operands,
251 TTI::TargetCostKind CostKind, Type *AccessType) const {
252 return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, CostKind, AccessType);
253}
254
257 const TTI::PointersChainInfo &Info, Type *AccessTy,
259 assert((Base || !Info.isSameBase()) &&
260 "If pointers have same base address it has to be provided.");
261 return TTIImpl->getPointersChainCost(Ptrs, Base, Info, AccessTy, CostKind);
262}
263
265 const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
266 BlockFrequencyInfo *BFI) const {
267 return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
268}
269
273 enum TargetCostKind CostKind) const {
274 InstructionCost Cost = TTIImpl->getInstructionCost(U, Operands, CostKind);
276 "TTI should not produce negative costs!");
277 return Cost;
278}
279
281 return PredictableBranchThreshold.getNumOccurrences() > 0
283 : TTIImpl->getPredictableBranchThreshold();
284}
285
287 return TTIImpl->getBranchMispredictPenalty();
288}
289
291 return TTIImpl->hasBranchDivergence(F);
292}
293
296 ValueUniformity VU = TTIImpl->getValueUniformity(V);
297 if (const auto *Call = dyn_cast<CallBase>(V)) {
299 Call->hasFnAttr(Attribute::NoDivergenceSource))
301 }
302 return VU;
303}
304
306 unsigned ToAS) const {
307 return TTIImpl->isValidAddrSpaceCast(FromAS, ToAS);
308}
309
311 unsigned ToAS) const {
312 return TTIImpl->addrspacesMayAlias(FromAS, ToAS);
313}
314
316 return TTIImpl->getFlatAddressSpace();
317}
318
320 SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
321 return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
322}
323
325 unsigned ToAS) const {
326 return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
327}
328
329std::pair<KnownBits, KnownBits>
331 const Value &PtrOp) const {
332 return TTIImpl->computeKnownBitsAddrSpaceCast(ToAS, PtrOp);
333}
334
336 unsigned FromAS, unsigned ToAS, const KnownBits &FromPtrBits) const {
337 return TTIImpl->computeKnownBitsAddrSpaceCast(FromAS, ToAS, FromPtrBits);
338}
339
341 unsigned SrcAS, unsigned DstAS) const {
342 return TTIImpl->getAddrSpaceCastPreservedPtrMask(SrcAS, DstAS);
343}
344
346 unsigned AS) const {
347 return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
348}
349
351 return TTIImpl->getAssumedAddrSpace(V);
352}
353
354std::pair<const Value *, unsigned>
356 return TTIImpl->getPredicatedAddrSpace(V);
357}
358
360 IntrinsicInst *II, Value *OldV, Value *NewV) const {
361 return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
362}
363
365 return TTIImpl->isLoweredToCall(F);
366}
367
370 TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
371 return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
372}
373
375 return TTIImpl->getEpilogueVectorizationMinVF();
376}
377
379 TailFoldingInfo *TFI) const {
380 return TTIImpl->preferTailFoldingOverEpilogue(TFI);
381}
382
384 return TTIImpl->getPreferredTailFoldingStyle();
385}
386
387std::optional<Instruction *>
389 IntrinsicInst &II) const {
390 return TTIImpl->instCombineIntrinsic(IC, II);
391}
392
394 InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
395 bool &KnownBitsComputed) const {
396 return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
397 KnownBitsComputed);
398}
399
401 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
402 APInt &UndefElts2, APInt &UndefElts3,
403 std::function<void(Instruction *, unsigned, APInt, APInt &)>
404 SimplifyAndSetOp) const {
405 return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
406 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
407 SimplifyAndSetOp);
408}
409
412 OptimizationRemarkEmitter *ORE) const {
413 return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
414}
415
417 PeelingPreferences &PP) const {
418 return TTIImpl->getPeelingPreferences(L, SE, PP);
419}
420
422 return TTIImpl->isLegalAddImmediate(Imm);
423}
424
426 return TTIImpl->isLegalAddScalableImmediate(Imm);
427}
428
430 return TTIImpl->isLegalICmpImmediate(Imm);
431}
432
434 int64_t BaseOffset,
435 bool HasBaseReg, int64_t Scale,
436 unsigned AddrSpace,
437 Instruction *I,
438 int64_t ScalableOffset) const {
439 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
440 Scale, AddrSpace, I, ScalableOffset);
441}
442
444 const LSRCost &C2) const {
445 return TTIImpl->isLSRCostLess(C1, C2);
446}
447
449 return TTIImpl->isNumRegsMajorCostOfLSR();
450}
451
453 return TTIImpl->shouldDropLSRSolutionIfLessProfitable();
454}
455
457 return TTIImpl->isProfitableLSRChainElement(I);
458}
459
461 return TTIImpl->canMacroFuseCmp();
462}
463
465 ScalarEvolution *SE, LoopInfo *LI,
467 TargetLibraryInfo *LibInfo) const {
468 return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
469}
470
473 ScalarEvolution *SE) const {
474 return TTIImpl->getPreferredAddressingMode(L, SE);
475}
476
478 unsigned AddressSpace,
479 TTI::MaskKind MaskKind) const {
480 return TTIImpl->isLegalMaskedStore(DataType, Alignment, AddressSpace,
481 MaskKind);
482}
483
485 unsigned AddressSpace,
486 TTI::MaskKind MaskKind) const {
487 return TTIImpl->isLegalMaskedLoad(DataType, Alignment, AddressSpace,
488 MaskKind);
489}
490
492 Align Alignment) const {
493 return TTIImpl->isLegalNTStore(DataType, Alignment);
494}
495
496bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
497 return TTIImpl->isLegalNTLoad(DataType, Alignment);
498}
499
501 ElementCount NumElements) const {
502 return TTIImpl->isLegalBroadcastLoad(ElementTy, NumElements);
503}
504
506 Align Alignment) const {
507 return TTIImpl->isLegalMaskedGather(DataType, Alignment);
508}
509
511 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
512 const SmallBitVector &OpcodeMask) const {
513 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask);
514}
515
517 Align Alignment) const {
518 return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
519}
520
522 Align Alignment) const {
523 return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment);
524}
525
527 Align Alignment) const {
528 return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment);
529}
530
532 Align Alignment) const {
533 return TTIImpl->isLegalMaskedCompressStore(DataType, Alignment);
534}
535
537 Align Alignment) const {
538 return TTIImpl->isLegalMaskedExpandLoad(DataType, Alignment);
539}
540
542 Align Alignment) const {
543 return TTIImpl->isLegalStridedLoadStore(DataType, Alignment);
544}
545
547 VectorType *VTy, unsigned Factor, Align Alignment,
548 unsigned AddrSpace) const {
549 return TTIImpl->isLegalInterleavedAccessType(VTy, Factor, Alignment,
550 AddrSpace);
551}
552
554 Type *DataType) const {
555 return TTIImpl->isLegalMaskedVectorHistogram(AddrType, DataType);
556}
557
559 return TTIImpl->enableOrderedReductions();
560}
561
562bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
563 return TTIImpl->hasDivRemOp(DataType, IsSigned);
564}
565
567 unsigned AddrSpace) const {
568 return TTIImpl->hasVolatileVariant(I, AddrSpace);
569}
570
572 return TTIImpl->prefersVectorizedAddressing();
573}
574
576 Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg,
577 int64_t Scale, unsigned AddrSpace) const {
578 InstructionCost Cost = TTIImpl->getScalingFactorCost(
579 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
580 assert(Cost >= 0 && "TTI should not produce negative costs!");
581 return Cost;
582}
583
585 return TTIImpl->LSRWithInstrQueries();
586}
587
589 return TTIImpl->isTruncateFree(Ty1, Ty2);
590}
591
593 return TTIImpl->isProfitableToHoist(I);
594}
595
596bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
597
599 return TTIImpl->isTypeLegal(Ty);
600}
601
603 return TTIImpl->getRegUsageForType(Ty);
604}
605
607 return TTIImpl->shouldBuildLookupTables();
608}
609
611 Constant *C) const {
612 return TTIImpl->shouldBuildLookupTablesForConstant(C);
613}
614
616 return TTIImpl->getMinimumLookupTableEntryBitWidth();
617}
618
620 return TTIImpl->shouldBuildRelLookupTables();
621}
622
624 return TTIImpl->useColdCCForColdCall(F);
625}
626
628 return TTIImpl->useFastCCForInternalCall(F);
629}
630
632 Intrinsic::ID ID, unsigned ScalarOpdIdx) const {
633 return TTIImpl->isTargetIntrinsicWithScalarOpAtArg(ID, ScalarOpdIdx);
634}
635
637 Intrinsic::ID ID, int OpdIdx) const {
638 return TTIImpl->isTargetIntrinsicWithOverloadTypeAtArg(ID, OpdIdx);
639}
640
642 Intrinsic::ID ID, int RetIdx) const {
643 return TTIImpl->isTargetIntrinsicWithStructReturnOverloadAtField(ID, RetIdx);
644}
645
648 if (!I)
650
651 // For inserts, check if the value being inserted comes from a single-use
652 // load.
653 if (isa<InsertElementInst>(I) && isa<LoadInst>(I->getOperand(1)) &&
654 I->getOperand(1)->hasOneUse())
656
657 // For extracts, check if it has a single use that is a store.
658 if (isa<ExtractElementInst>(I) && I->hasOneUse() &&
659 isa<StoreInst>(*I->user_begin()))
661
663}
664
666 VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract,
667 TTI::TargetCostKind CostKind, bool ForPoisonSrc, ArrayRef<Value *> VL,
668 TTI::VectorInstrContext VIC) const {
669 return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
670 CostKind, ForPoisonSrc, VL, VIC);
671}
672
675 TTI::VectorInstrContext VIC) const {
676 return TTIImpl->getOperandsScalarizationOverhead(Tys, CostKind, VIC);
677}
678
680 return TTIImpl->supportsEfficientVectorElementLoadStore();
681}
682
684 return TTIImpl->supportsTailCalls();
685}
686
688 return TTIImpl->supportsTailCallFor(CB);
689}
690
692 bool LoopHasReductions) const {
693 return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
694}
695
697TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
698 return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
699}
700
702 return TTIImpl->enableSelectOptimize();
703}
704
706 const Instruction *I) const {
707 return TTIImpl->shouldTreatInstructionLikeSelect(I);
708}
709
711 return TTIImpl->enableInterleavedAccessVectorization();
712}
713
715 return TTIImpl->enableMaskedInterleavedAccessVectorization();
716}
717
719 return TTIImpl->isFPVectorizationPotentiallyUnsafe();
720}
721
722bool
724 unsigned BitWidth,
725 unsigned AddressSpace,
726 Align Alignment,
727 unsigned *Fast) const {
728 return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
729 AddressSpace, Alignment, Fast);
730}
731
733TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
734 return TTIImpl->getPopcntSupport(IntTyWidthInBit);
735}
736
738 return TTIImpl->haveFastSqrt(Ty);
739}
740
742 return TTIImpl->haveFastClmul(Ty);
743}
744
746 const Instruction *I) const {
747 return TTIImpl->isExpensiveToSpeculativelyExecute(I);
748}
749
751 return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
752}
753
755 InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
756 assert(Cost >= 0 && "TTI should not produce negative costs!");
757 return Cost;
758}
759
761 unsigned Idx,
762 const APInt &Imm,
763 Type *Ty) const {
764 InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
765 assert(Cost >= 0 && "TTI should not produce negative costs!");
766 return Cost;
767}
768
772 InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
773 assert(Cost >= 0 && "TTI should not produce negative costs!");
774 return Cost;
775}
776
778 unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
781 TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
782 assert(Cost >= 0 && "TTI should not produce negative costs!");
783 return Cost;
784}
785
788 const APInt &Imm, Type *Ty,
791 TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
792 assert(Cost >= 0 && "TTI should not produce negative costs!");
793 return Cost;
794}
795
797 const Instruction &Inst, const Function &Fn) const {
798 return TTIImpl->preferToKeepConstantsAttached(Inst, Fn);
799}
800
801unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
802 return TTIImpl->getNumberOfRegisters(ClassID);
803}
804
806 bool IsStore) const {
807 return TTIImpl->hasConditionalLoadStoreForType(Ty, IsStore);
808}
809
811 Type *Ty) const {
812 return TTIImpl->getRegisterClassForType(Vector, Ty);
813}
814
815const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
816 return TTIImpl->getRegisterClassName(ClassID);
817}
818
820 unsigned ClassID, TTI::TargetCostKind CostKind) const {
821 return TTIImpl->getRegisterClassSpillCost(ClassID, CostKind);
822}
823
825 unsigned ClassID, TTI::TargetCostKind CostKind) const {
826 return TTIImpl->getRegisterClassReloadCost(ClassID, CostKind);
827}
828
831 return TTIImpl->getRegisterBitWidth(K);
832}
833
835 return TTIImpl->getMinVectorRegisterBitWidth();
836}
837
838std::optional<unsigned> TargetTransformInfo::getVScaleForTuning() const {
839 return TTIImpl->getVScaleForTuning();
840}
841
844 return TTIImpl->shouldMaximizeVectorBandwidth(K);
845}
846
848 bool IsScalable) const {
849 return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
850}
851
852unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
853 unsigned Opcode) const {
854 return TTIImpl->getMaximumVF(ElemWidth, Opcode);
855}
856
857unsigned TargetTransformInfo::getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
858 Type *ScalarValTy,
859 Align Alignment,
860 unsigned AddrSpace) const {
861 return TTIImpl->getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy, Alignment,
862 AddrSpace);
863}
864
866 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
867 return TTIImpl->shouldConsiderAddressTypePromotion(
868 I, AllowPromotionWithoutCommonHeader);
869}
870
872 return CacheLineSize.getNumOccurrences() > 0 ? CacheLineSize
873 : TTIImpl->getCacheLineSize();
874}
875
876std::optional<unsigned>
878 return TTIImpl->getCacheSize(Level);
879}
880
881std::optional<unsigned>
883 return TTIImpl->getCacheAssociativity(Level);
884}
885
886std::optional<unsigned> TargetTransformInfo::getMinPageSize() const {
887 return MinPageSize.getNumOccurrences() > 0 ? MinPageSize
888 : TTIImpl->getMinPageSize();
889}
890
892 return TTIImpl->getPrefetchDistance();
893}
894
896 unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
897 unsigned NumPrefetches, bool HasCall) const {
898 return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
899 NumPrefetches, HasCall);
900}
901
903 return TTIImpl->getMaxPrefetchIterationsAhead();
904}
905
907 return TTIImpl->enableWritePrefetching();
908}
909
911 return TTIImpl->shouldPrefetchAddressSpace(AS);
912}
913
915 unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
917 PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
918 TTI::TargetCostKind CostKind, std::optional<FastMathFlags> FMF) const {
919 return TTIImpl->getPartialReductionCost(Opcode, InputTypeA, InputTypeB,
920 AccumType, VF, OpAExtend, OpBExtend,
921 BinOp, CostKind, FMF);
922}
923
924unsigned
926 bool HasUnorderedReductions) const {
927 return TTIImpl->getMaxInterleaveFactor(VF, HasUnorderedReductions);
928}
929
934
935 // undef/poison don't materialize constants.
936 if (isa<UndefValue>(V))
937 return {OK_AnyValue, OP_None};
938
939 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
940 if (const auto *CI = dyn_cast<ConstantInt>(V)) {
941 if (CI->getValue().isPowerOf2())
942 OpProps = OP_PowerOf2;
943 else if (CI->getValue().isNegatedPowerOf2())
944 OpProps = OP_NegatedPowerOf2;
945 }
946 return {OK_UniformConstantValue, OpProps};
947 }
948
949 // A broadcast shuffle creates a uniform value.
950 // TODO: Add support for non-zero index broadcasts.
951 // TODO: Add support for different source vector width.
952 if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
953 if (ShuffleInst->isZeroEltSplat())
954 OpInfo = OK_UniformValue;
955
956 const Value *Splat = getSplatValue(V);
957
958 // Check for a splat of a constant or for a non uniform vector of constants
959 // and check if the constant(s) are all powers of two.
960 if (Splat) {
961 // Check for a splat of a uniform value. This is not loop aware, so return
962 // true only for the obviously uniform cases (argument, globalvalue)
964 OpInfo = OK_UniformValue;
965 } else if (isa<Constant>(Splat)) {
967 if (auto *CI = dyn_cast<ConstantInt>(Splat)) {
968 if (CI->getValue().isPowerOf2())
969 OpProps = OP_PowerOf2;
970 else if (CI->getValue().isNegatedPowerOf2())
971 OpProps = OP_NegatedPowerOf2;
972 }
973 }
974 } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
976 bool AllPow2 = true, AllNegPow2 = true;
977 for (uint64_t I = 0, E = CDS->getNumElements(); I != E; ++I) {
978 if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I))) {
979 AllPow2 &= CI->getValue().isPowerOf2();
980 AllNegPow2 &= CI->getValue().isNegatedPowerOf2();
981 if (AllPow2 || AllNegPow2)
982 continue;
983 }
984 AllPow2 = AllNegPow2 = false;
985 break;
986 }
987 OpProps = AllPow2 ? OP_PowerOf2 : OpProps;
988 OpProps = AllNegPow2 ? OP_NegatedPowerOf2 : OpProps;
989 } else if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
991 }
992
993 return {OpInfo, OpProps};
994}
995
999 if (X == Y)
1000 return OpInfoX;
1001 return OpInfoX.mergeWith(getOperandInfo(Y));
1002}
1003
1005 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
1006 OperandValueInfo Op1Info, OperandValueInfo Op2Info,
1007 ArrayRef<const Value *> Args, const Instruction *CxtI,
1008 const TargetLibraryInfo *TLibInfo) const {
1009
1010 // Use call cost for frem intructions that have platform specific vector math
1011 // functions, as those will be replaced with calls later by SelectionDAG or
1012 // ReplaceWithVecLib pass.
1013 if (TLibInfo && Opcode == Instruction::FRem) {
1014 VectorType *VecTy = dyn_cast<VectorType>(Ty);
1015 LibFunc Func = TLibInfo->getLibFunc(Instruction::FRem, Ty->getScalarType());
1016 if (VecTy && Func != NotLibFunc &&
1017 TLibInfo->isFunctionVectorizable(TLibInfo->getName(Func),
1018 VecTy->getElementCount()))
1019 return getCallInstrCost(nullptr, VecTy, {VecTy, VecTy}, CostKind);
1020 }
1021
1022 InstructionCost Cost = TTIImpl->getArithmeticInstrCost(
1023 Opcode, Ty, CostKind, Op1Info, Op2Info, Args, CxtI);
1024 assert(Cost >= 0 && "TTI should not produce negative costs!");
1025 return Cost;
1026}
1027
1029 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1030 const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const {
1032 TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind);
1033 assert(Cost >= 0 && "TTI should not produce negative costs!");
1034 return Cost;
1035}
1036
1038 ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy,
1041 const Instruction *CxtI) const {
1042 assert((Mask.empty() || DstTy->isScalableTy() ||
1043 Mask.size() == DstTy->getElementCount().getKnownMinValue()) &&
1044 "Expected the Mask to match the return size if given");
1045 assert(SrcTy->getScalarType() == DstTy->getScalarType() &&
1046 "Expected the same scalar types");
1047 InstructionCost Cost = TTIImpl->getShuffleCost(
1048 Kind, DstTy, SrcTy, CostKind, Mask, Index, SubTp, Args, CxtI);
1049 assert(Cost >= 0 && "TTI should not produce negative costs!");
1050 return Cost;
1051}
1052
1055 if (auto *Cast = dyn_cast<CastInst>(I))
1056 return getPartialReductionExtendKind(Cast->getOpcode());
1057 return PR_None;
1058}
1059
1063 switch (Kind) {
1065 return Instruction::CastOps::ZExt;
1067 return Instruction::CastOps::SExt;
1069 return Instruction::CastOps::FPExt;
1070 default:
1071 break;
1072 }
1073 llvm_unreachable("Unhandled partial reduction extend kind");
1074}
1075
1078 Instruction::CastOps CastOpc) {
1079 switch (CastOpc) {
1080 case Instruction::CastOps::ZExt:
1081 return PR_ZeroExtend;
1082 case Instruction::CastOps::SExt:
1083 return PR_SignExtend;
1084 case Instruction::CastOps::FPExt:
1085 return PR_FPExtend;
1086 default:
1087 return PR_None;
1088 }
1089 llvm_unreachable("Unhandled cast opcode");
1090}
1091
1094 if (!I)
1095 return CastContextHint::None;
1096
1097 auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
1098 unsigned GatScatOp) {
1100 if (!I)
1101 return CastContextHint::None;
1102
1103 if (I->getOpcode() == LdStOp)
1105
1106 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1107 if (II->getIntrinsicID() == MaskedOp)
1109 if (II->getIntrinsicID() == GatScatOp)
1111 }
1112
1114 };
1115
1116 switch (I->getOpcode()) {
1117 case Instruction::ZExt:
1118 case Instruction::SExt:
1119 case Instruction::FPExt:
1120 return getLoadStoreKind(I->getOperand(0), Instruction::Load,
1121 Intrinsic::masked_load, Intrinsic::masked_gather);
1122 case Instruction::Trunc:
1123 case Instruction::FPTrunc:
1124 if (I->hasOneUse())
1125 return getLoadStoreKind(*I->user_begin(), Instruction::Store,
1126 Intrinsic::masked_store,
1127 Intrinsic::masked_scatter);
1128 break;
1129 default:
1130 return CastContextHint::None;
1131 }
1132
1134}
1135
1137 unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
1138 TTI::TargetCostKind CostKind, const Instruction *I) const {
1139 assert((I == nullptr || I->getOpcode() == Opcode) &&
1140 "Opcode should reflect passed instruction.");
1142 TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
1143 assert(Cost >= 0 && "TTI should not produce negative costs!");
1144 return Cost;
1145}
1146
1148 unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index,
1151 TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index, CostKind);
1152 assert(Cost >= 0 && "TTI should not produce negative costs!");
1153 return Cost;
1154}
1155
1157 unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
1158 assert((I == nullptr || I->getOpcode() == Opcode) &&
1159 "Opcode should reflect passed instruction.");
1160 InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
1161 assert(Cost >= 0 && "TTI should not produce negative costs!");
1162 return Cost;
1163}
1164
1166 unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
1168 OperandValueInfo Op2Info, const Instruction *I) const {
1169 assert((I == nullptr || I->getOpcode() == Opcode) &&
1170 "Opcode should reflect passed instruction.");
1171 InstructionCost Cost = TTIImpl->getCmpSelInstrCost(
1172 Opcode, ValTy, CondTy, VecPred, CostKind, Op1Info, Op2Info, I);
1173 assert(Cost >= 0 && "TTI should not produce negative costs!");
1174 return Cost;
1175}
1176
1178 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1179 const Value *Op0, const Value *Op1, TTI::VectorInstrContext VIC) const {
1180 assert((Opcode == Instruction::InsertElement ||
1181 Opcode == Instruction::ExtractElement) &&
1182 "Expecting Opcode to be insertelement/extractelement.");
1184 TTIImpl->getVectorInstrCost(Opcode, Val, CostKind, Index, Op0, Op1, VIC);
1185 assert(Cost >= 0 && "TTI should not produce negative costs!");
1186 return Cost;
1187}
1188
1190 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1191 Value *Scalar, ArrayRef<std::tuple<Value *, User *, int>> ScalarUserAndIdx,
1192 TTI::VectorInstrContext VIC) const {
1193 assert((Opcode == Instruction::InsertElement ||
1194 Opcode == Instruction::ExtractElement) &&
1195 "Expecting Opcode to be insertelement/extractelement.");
1196 InstructionCost Cost = TTIImpl->getVectorInstrCost(
1197 Opcode, Val, CostKind, Index, Scalar, ScalarUserAndIdx, VIC);
1198 assert(Cost >= 0 && "TTI should not produce negative costs!");
1199 return Cost;
1200}
1201
1204 unsigned Index, TTI::VectorInstrContext VIC) const {
1205 // FIXME: Assert that Opcode is either InsertElement or ExtractElement.
1206 // This is mentioned in the interface description and respected by all
1207 // callers, but never asserted upon.
1209 TTIImpl->getVectorInstrCost(I, Val, CostKind, Index, VIC);
1210 assert(Cost >= 0 && "TTI should not produce negative costs!");
1211 return Cost;
1212}
1213
1215 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind,
1216 unsigned Index) const {
1218 TTIImpl->getIndexedVectorInstrCostFromEnd(Opcode, Val, CostKind, Index);
1219 assert(Cost >= 0 && "TTI should not produce negative costs!");
1220 return Cost;
1221}
1222
1224 unsigned Opcode, TTI::TargetCostKind CostKind) const {
1225 assert((Opcode == Instruction::InsertValue ||
1226 Opcode == Instruction::ExtractValue) &&
1227 "Expecting Opcode to be insertvalue/extractvalue.");
1228 InstructionCost Cost = TTIImpl->getInsertExtractValueCost(Opcode, CostKind);
1229 assert(Cost >= 0 && "TTI should not produce negative costs!");
1230 return Cost;
1231}
1232
1234 Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts,
1236 InstructionCost Cost = TTIImpl->getReplicationShuffleCost(
1237 EltTy, ReplicationFactor, VF, DemandedDstElts, CostKind);
1238 assert(Cost >= 0 && "TTI should not produce negative costs!");
1239 return Cost;
1240}
1241
1243 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1245 const Instruction *I) const {
1246 assert((I == nullptr || I->getOpcode() == Opcode) &&
1247 "Opcode should reflect passed instruction.");
1248 InstructionCost Cost = TTIImpl->getMemoryOpCost(
1249 Opcode, Src, Alignment, AddressSpace, CostKind, OpInfo, I);
1250 assert(Cost >= 0 && "TTI should not produce negative costs!");
1251 return Cost;
1252}
1253
1255 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
1256 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
1257 bool UseMaskForCond, bool UseMaskForGaps) const {
1258 InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
1259 Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
1260 UseMaskForCond, UseMaskForGaps);
1261 assert(Cost >= 0 && "TTI should not produce negative costs!");
1262 return Cost;
1263}
1264
1268 InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
1269 assert(Cost >= 0 && "TTI should not produce negative costs!");
1270 return Cost;
1271}
1272
1274 const MemIntrinsicCostAttributes &MICA,
1276 InstructionCost Cost = TTIImpl->getMemIntrinsicInstrCost(MICA, CostKind);
1277 assert(Cost >= 0 && "TTI should not produce negative costs!");
1278 return Cost;
1279}
1280
1283 ArrayRef<Type *> Tys,
1285 InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
1286 assert(Cost >= 0 && "TTI should not produce negative costs!");
1287 return Cost;
1288}
1289
1291 return TTIImpl->getNumberOfParts(Tp);
1292}
1293
1295 Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr,
1298 TTIImpl->getAddressComputationCost(PtrTy, SE, Ptr, CostKind);
1299 assert(Cost >= 0 && "TTI should not produce negative costs!");
1300 return Cost;
1301}
1302
1304 InstructionCost Cost = TTIImpl->getMemcpyCost(I);
1305 assert(Cost >= 0 && "TTI should not produce negative costs!");
1306 return Cost;
1307}
1308
1310 return TTIImpl->getMaxMemIntrinsicInlineSizeThreshold();
1311}
1312
1314 unsigned Opcode, VectorType *Ty, std::optional<FastMathFlags> FMF,
1317 TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
1318 assert(Cost >= 0 && "TTI should not produce negative costs!");
1319 return Cost;
1320}
1321
1326 TTIImpl->getMinMaxReductionCost(IID, Ty, FMF, CostKind);
1327 assert(Cost >= 0 && "TTI should not produce negative costs!");
1328 return Cost;
1329}
1330
1332 unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1333 std::optional<FastMathFlags> FMF, TTI::TargetCostKind CostKind) const {
1334 return TTIImpl->getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
1335 CostKind);
1336}
1337
1339 bool IsUnsigned, unsigned RedOpcode, Type *ResTy, VectorType *Ty,
1341 return TTIImpl->getMulAccReductionCost(IsUnsigned, RedOpcode, ResTy, Ty,
1342 CostKind);
1343}
1344
1347 return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
1348}
1349
1351 MemIntrinsicInfo &Info) const {
1352 return TTIImpl->getTgtMemIntrinsic(Inst, Info);
1353}
1354
1356 return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
1357}
1358
1360 IntrinsicInst *Inst, Type *ExpectedType, bool CanCreate) const {
1361 return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType,
1362 CanCreate);
1363}
1364
1366 LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
1367 unsigned DestAddrSpace, Align SrcAlign, Align DestAlign,
1368 std::optional<uint32_t> AtomicElementSize) const {
1369 return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
1370 DestAddrSpace, SrcAlign, DestAlign,
1371 AtomicElementSize);
1372}
1373
1375 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
1376 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1377 Align SrcAlign, Align DestAlign,
1378 std::optional<uint32_t> AtomicCpySize) const {
1379 TTIImpl->getMemcpyLoopResidualLoweringType(
1380 OpsOut, Context, RemainingBytes, SrcAddrSpace, DestAddrSpace, SrcAlign,
1381 DestAlign, AtomicCpySize);
1382}
1383
1385 const Function *Callee) const {
1386 return TTIImpl->areInlineCompatible(Caller, Callee);
1387}
1388
1389unsigned
1391 const CallBase &Call,
1392 unsigned DefaultCallPenalty) const {
1393 return TTIImpl->getInlineCallPenalty(F, Call, DefaultCallPenalty);
1394}
1395
1397 const Function *Caller, const Attribute &Attr) const {
1398 return TTIImpl->shouldCopyAttributeWhenOutliningFrom(Caller, Attr);
1399}
1401 const Function *Callee,
1402 ArrayRef<Type *> Types) const {
1403 return TTIImpl->areTypesABICompatible(Caller, Callee, Types);
1404}
1405
1407 Type *Ty) const {
1408 return TTIImpl->isIndexedLoadLegal(Mode, Ty);
1409}
1410
1412 Type *Ty) const {
1413 return TTIImpl->isIndexedStoreLegal(Mode, Ty);
1414}
1415
1417 return TTIImpl->getLoadStoreVecRegBitWidth(AS);
1418}
1419
1421 return TTIImpl->isLegalToVectorizeLoad(LI);
1422}
1423
1425 return TTIImpl->isLegalToVectorizeStore(SI);
1426}
1427
1429 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1430 return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1431 AddrSpace);
1432}
1433
1435 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1436 return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1437 AddrSpace);
1438}
1439
1441 const RecurrenceDescriptor &RdxDesc, ElementCount VF) const {
1442 return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1443}
1444
1446 return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1447}
1448
1450 unsigned LoadSize,
1451 unsigned ChainSizeInBytes,
1452 VectorType *VecTy) const {
1453 return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1454}
1455
1457 unsigned StoreSize,
1458 unsigned ChainSizeInBytes,
1459 VectorType *VecTy) const {
1460 return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1461}
1462
1464 return TTIImpl->preferFixedOverScalableIfEqualCost();
1465}
1466
1468 Type *Ty) const {
1469 return TTIImpl->preferInLoopReduction(Kind, Ty);
1470}
1471
1473 return TTIImpl->preferAlternateOpcodeVectorization();
1474}
1475
1477 return TTIImpl->preferSLPInstCountCheck();
1478}
1479
1481 return TTIImpl->preferPredicatedReductionSelect();
1482}
1483
1485 ElementCount Iters) const {
1486 return TTIImpl->preferEpilogueVectorization(Iters);
1487}
1488
1490 return TTIImpl->shouldConsiderVectorizationRegPressure();
1491}
1492
1495 return TTIImpl->getVPLegalizationStrategy(VPI);
1496}
1497
1499 return TTIImpl->hasArmWideBranch(Thumb);
1500}
1501
1503 return TTIImpl->getFeatureMask(F);
1504}
1505
1507 return TTIImpl->getPriorityMask(F);
1508}
1509
1511 return TTIImpl->isMultiversionedFunction(F);
1512}
1513
1515 return TTIImpl->getMaxNumArgs();
1516}
1517
1519 return TTIImpl->shouldExpandReduction(II);
1520}
1521
1524 const IntrinsicInst *II) const {
1525 return TTIImpl->getPreferredExpandedReductionShuffle(II);
1526}
1527
1529 return TTIImpl->getGISelRematGlobalCost();
1530}
1531
1533 return TTIImpl->getMinTripCountTailFoldingThreshold();
1534}
1535
1537 return TTIImpl->supportsScalableVectors();
1538}
1539
1541 return TTIImpl->enableScalableVectorization();
1542}
1543
1545 return TTIImpl->hasActiveVectorLength();
1546}
1547
1549 Instruction *I, SmallVectorImpl<Use *> &OpsToSink) const {
1550 return TTIImpl->isProfitableToSinkOperands(I, OpsToSink);
1551}
1552
1554 return TTIImpl->isVectorShiftByScalarCheap(Ty);
1555}
1556
1557unsigned
1559 Type *ArrayType) const {
1560 return TTIImpl->getNumBytesToPadGlobalArray(Size, ArrayType);
1561}
1562
1564 const Function &F,
1565 SmallVectorImpl<std::pair<StringRef, int64_t>> &LB) const {
1566 return TTIImpl->collectKernelLaunchBounds(F, LB);
1567}
1568
1570 return TTIImpl->allowVectorElementIndexingUsingGEP();
1571}
1572
1574 const SmallBitVector &UniformArgs) const {
1575 return TTIImpl->isUniform(I, UniformArgs);
1576}
1577
1579
1580TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1581
1583 std::function<Result(const Function &)> TTICallback)
1584 : TTICallback(std::move(TTICallback)) {}
1585
1588 assert(!F.isIntrinsic() && "Should not request TTI for intrinsics");
1589 return TTICallback(F);
1590}
1591
1592AnalysisKey TargetIRAnalysis::Key;
1593
1594TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1595 return Result(F.getDataLayout());
1596}
1597
1598// Register the basic pass.
1600 "Target Transform Information", false, true)
1602
1603void TargetTransformInfoWrapperPass::anchor() {}
1604
1607
1611
1613 FunctionAnalysisManager DummyFAM;
1614 TTI = TIRA.run(F, DummyFAM);
1615 return *TTI;
1616}
1617
for(const MachineOperand &MO :llvm::drop_begin(OldMI.operands(), Desc.getNumOperands()))
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
unsigned Imm
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
#define X(NUM, ENUM, NAME)
Definition ELF.h:857
static GCRegistry::Add< ShadowStackGC > C("shadow-stack", "Very portable GC for uncooperative code generators")
static cl::opt< OutputCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(OutputCostKind::RecipThroughput), cl::values(clEnumValN(OutputCostKind::RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(OutputCostKind::Latency, "latency", "Instruction latency"), clEnumValN(OutputCostKind::CodeSize, "code-size", "Code size"), clEnumValN(OutputCostKind::SizeAndLatency, "size-latency", "Code size and latency"), clEnumValN(OutputCostKind::All, "all", "Print all cost kinds")))
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
Module.h This file contains the declarations for the Module class.
#define F(x, y, z)
Definition MD5.cpp:54
#define I(x, y, z)
Definition MD5.cpp:57
uint64_t IntrinsicInst * II
if(PassOpts->AAPipeline)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
SI Fold Operands
This file defines the SmallVector class.
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static SymbolRef::Type getType(const Symbol *Sym)
Definition TapiFile.cpp:39
This file provides helpers for the implementation of a TargetTransformInfo-conforming class.
static cl::opt< unsigned > PredictableBranchThreshold("predictable-branch-threshold", cl::init(99), cl::Hidden, cl::desc("Use this to override the target's predictable branch threshold (%)."))
static cl::opt< bool > EnableReduxCost("costmodel-reduxcost", cl::init(false), cl::Hidden, cl::desc("Recognize reduction patterns."))
static cl::opt< unsigned > MinPageSize("min-page-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target's minimum page size."))
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
This pass exposes codegen information to IR-level passes.
Class for arbitrary precision integers.
Definition APInt.h:78
an instruction to allocate memory on the stack
This class represents an incoming formal argument to a Function.
Definition Argument.h:32
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
iterator end() const
Definition ArrayRef.h:130
iterator begin() const
Definition ArrayRef.h:129
Class to represent array types.
A cache of @llvm.assume calls within a function.
Functions, function parameters, and return types can have attributes to indicate how they should be t...
Definition Attributes.h:106
LLVM Basic Block Representation.
Definition BasicBlock.h:62
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
iterator_range< User::op_iterator > args()
Iteration adapter for range-for loops.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition InstrTypes.h:740
Conditional Branch instruction.
This is an important base class in LLVM.
Definition Constant.h:43
A parsed version of the target data layout string in and methods for querying it.
Definition DataLayout.h:64
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition Dominators.h:122
LLVM_ABI bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Convenience struct for specifying and reasoning about fast-math flags.
Definition FMF.h:23
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition Pass.h:285
ImmutablePass(char &pid)
Definition Pass.h:287
The core instruction combiner logic.
Class to represent integer types.
LLVM_ABI IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false)
A wrapper class for inspecting calls to intrinsic functions.
This is an important class for using LLVM in a threaded context.
Definition LLVMContext.h:68
An instruction for reading from memory.
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
void perform(const LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Represents a single loop in the control flow graph.
Definition LoopInfo.h:40
Information for memory intrinsic cost model.
The optimization diagnostic interface.
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
This class represents a constant integer value.
This class represents an analyzed expression in the program.
The main scalar evolution driver.
LLVM_ABI uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
LLVM_ABI bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
LLVM_ABI const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
Definition TypeSize.h:30
An instruction for storing to memory.
Multiway switch.
Analysis pass providing the TargetTransformInfo.
LLVM_ABI Result run(const Function &F, FunctionAnalysisManager &)
LLVM_ABI TargetIRAnalysis()
Default construct a target IR analysis.
Provides information about what library functions are available for the current target.
StringRef getName(LibFunc F) const
bool isFunctionVectorizable(StringRef F, const ElementCount &VF) const
LibFunc getLibFunc(StringRef funcName) const
Searches for a particular function name.
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Wrapper pass for TargetTransformInfo.
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
TargetTransformInfo & getTTI(const Function &F)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
LLVM_ABI bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
LLVM_ABI Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType, bool CanCreate=true) const
LLVM_ABI bool isLegalToVectorizeLoad(LoadInst *LI) const
LLVM_ABI std::optional< unsigned > getVScaleForTuning() const
static LLVM_ABI CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
LLVM_ABI unsigned getMaxNumArgs() const
LLVM_ABI bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const
Return false if a AS0 address cannot possibly alias a AS1 address.
LLVM_ABI bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
LLVM_ABI bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
LLVM_ABI bool isLegalToVectorizeStore(StoreInst *SI) const
LLVM_ABI bool areTypesABICompatible(const Function *Caller, const Function *Callee, ArrayRef< Type * > Types) const
LLVM_ABI bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
LLVM_ABI bool isMultiversionedFunction(const Function &F) const
Returns true if this is an instance of a function with multiple versions.
LLVM_ABI unsigned getMaxInterleaveFactor(ElementCount VF, bool HasUnorderedReductions) const
LLVM_ABI bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
LLVM_ABI bool isLegalMaskedStore(Type *DataType, Align Alignment, unsigned AddressSpace, MaskKind MaskKind=VariableOrConstantMask) const
Return true if the target supports masked store.
LLVM_ABI unsigned getMinimumLookupTableEntryBitWidth() const
Return the minimum bit width to use for integer switch lookup table elements on this target.
LLVM_ABI bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
LLVM_ABI unsigned getAssumedAddrSpace(const Value *V) const
LLVM_ABI bool preferAlternateOpcodeVectorization() const
LLVM_ABI bool shouldDropLSRSolutionIfLessProfitable() const
Return true if LSR should drop a found solution if it's calculated to be less profitable than the bas...
LLVM_ABI bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C2.
LLVM_ABI unsigned getPrefetchDistance() const
LLVM_ABI Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicElementSize=std::nullopt) const
LLVM_ABI bool haveFastClmul(IntegerType *Ty) const
Return true if the hardware has a fast carry-less multiplication instruction.
LLVM_ABI bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked expand load.
LLVM_ABI bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
LLVM_ABI InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
LLVM_ABI bool hasBranchDivergence(const Function *F=nullptr) const
Return true if branch divergence exists.
LLVM_ABI bool preferEpilogueVectorization(ElementCount Iters) const
Return true if the loop vectorizer should consider vectorizing an otherwise scalar epilogue loop if t...
LLVM_ABI MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
LLVM_ABI void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
LLVM_ABI bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
LLVM_ABI InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TargetCostKind CostKind, Type *AccessType=nullptr) const
Estimate the cost of a GEP operation when lowered.
LLVM_ABI TailFoldingStyle getPreferredTailFoldingStyle() const
Query the target what the preferred style of tail folding is.
LLVM_ABI bool supportsTailCallFor(const CallBase *CB) const
If target supports tail call on CB.
LLVM_ABI std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
LLVM_ABI bool isProfitableLSRChainElement(Instruction *I) const
LLVM_ABI TypeSize getRegisterBitWidth(RegisterKind K) const
MaskKind
Some targets only support masked load/store with a constant mask.
LLVM_ABI unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
Returns a penalty for invoking call Call in F.
LLVM_ABI InstructionCost getOperandsScalarizationOverhead(ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
Estimate the overhead of scalarizing operands with the given types.
LLVM_ABI bool hasActiveVectorLength() const
LLVM_ABI bool isExpensiveToSpeculativelyExecute(const Instruction *I) const
Return true if the cost of the instruction is too high to speculatively execute and should be kept be...
LLVM_ABI InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, OperandValueInfo OpdInfo={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
LLVM_ABI bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
LLVM_ABI ValueUniformity getValueUniformity(const Value *V) const
Get target-specific uniformity information for a value.
static LLVM_ABI OperandValueInfo commonOperandInfo(const Value *X, const Value *Y)
Collect common data between two OperandValueInfo inputs.
LLVM_ABI InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind) const
LLVM_ABI bool allowVectorElementIndexingUsingGEP() const
Returns true if GEP should not be used to index into vectors for this target.
LLVM_ABI bool preferTailFoldingOverEpilogue(TailFoldingInfo *TFI) const
Query the target whether it would be preferred to create a tail-folded vector loop,...
LLVM_ABI std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
LLVM_ABI bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
LLVM_ABI unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const
LLVM_ABI InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
LLVM_ABI unsigned getAtomicMemIntrinsicMaxElementSize() const
LLVM_ABI InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index=-1, const Value *Op0=nullptr, const Value *Op1=nullptr, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
LLVM_ABI std::pair< KnownBits, KnownBits > computeKnownBitsAddrSpaceCast(unsigned ToAS, const Value &PtrOp) const
LLVM_ABI bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
LLVM_ABI unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
LLVM_ABI VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
static LLVM_ABI PartialReductionExtendKind getPartialReductionExtendKind(Instruction *I)
Get the kind of extension that an instruction represents.
LLVM_ABI InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, OperandValueInfo Op1Info={OK_AnyValue, OP_None}, OperandValueInfo Op2Info={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
LLVM_ABI bool shouldConsiderVectorizationRegPressure() const
LLVM_ABI bool enableWritePrefetching() const
LLVM_ABI bool shouldTreatInstructionLikeSelect(const Instruction *I) const
Should the Select Optimization pass treat the given instruction like a select, potentially converting...
LLVM_ABI bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
LLVM_ABI bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
LLVM_ABI bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace) const
Return true is the target supports interleaved access for the given vector type VTy,...
LLVM_ABI unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
LLVM_ABI bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy...
LLVM_ABI bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
LLVM_ABI std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
LLVM_ABI unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
LLVM_ABI InstructionCost getRegisterClassReloadCost(unsigned ClassID, TargetCostKind CostKind) const
LLVM_ABI ReductionShuffle getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const
static LLVM_ABI OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
LLVM_ABI InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
LLVM_ABI InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
LLVM_ABI unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
LLVM_ABI bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr, int64_t ScalableOffset=0) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
LLVM_ABI PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
LLVM_ABI unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
LLVM_ABI bool isElementTypeLegalForScalableVector(Type *Ty) const
LLVM_ABI bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
LLVM_ABI InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind) const
Calculate the cost of vector reduction intrinsics.
LLVM_ABI unsigned getMaxPrefetchIterationsAhead() const
LLVM_ABI bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
LLVM_ABI ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
LLVM_ABI InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
LLVM_ABI bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
LLVM_ABI InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
LLVM_ABI bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const
Return true if the target supports strided load.
LLVM_ABI TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
LLVM_ABI InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduc...
TargetCostKind
The kind of cost model.
@ TCK_RecipThroughput
Reciprocal throughput.
LLVM_ABI bool enableSelectOptimize() const
Should the Select Optimization pass be enabled and ran.
LLVM_ABI bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
OperandValueProperties
Additional properties of an operand's values.
LLVM_ABI int getInliningLastCallToStaticBonus() const
LLVM_ABI bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
LLVM_ABI InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
LLVM_ABI unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
LLVM_ABI unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
LLVM_ABI bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
LLVM_ABI bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
LLVM_ABI std::optional< unsigned > getCacheAssociativity(CacheLevel Level) const
LLVM_ABI bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
LLVM_ABI bool isUniform(const Instruction *I, const SmallBitVector &UniformArgs) const
Determine if an instruction with Custom uniformity can be proven uniform based on which operands are ...
LLVM_ABI InstructionCost getMemcpyCost(const Instruction *I) const
LLVM_ABI unsigned adjustInliningThreshold(const CallBase *CB) const
LLVM_ABI bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
LLVM_ABI bool isTargetIntrinsicWithStructReturnOverloadAtField(Intrinsic::ID ID, int RetIdx) const
Identifies if the vector form of the intrinsic that returns a struct is overloaded at the struct elem...
LLVM_ABI unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
LLVM_ABI InstructionCost getMemIntrinsicInstrCost(const MemIntrinsicCostAttributes &MICA, TTI::TargetCostKind CostKind) const
LLVM_ABI InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind) const
LLVM_ABI InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const
Returns the cost estimation for alternating opcode pattern that can be lowered to a single instructio...
LLVM_ABI Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
LLVM_ABI InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
LLVM_ABI bool canSaveCmp(Loop *L, CondBrInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
LLVM_ABI unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
LLVM_ABI bool shouldPrefetchAddressSpace(unsigned AS) const
LLVM_ABI InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
LLVM_ABI unsigned getMinVectorRegisterBitWidth() const
LLVM_ABI InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr, TTI::TargetCostKind CostKind) const
LLVM_ABI bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
LLVM_ABI unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
LLVM_ABI bool preferToKeepConstantsAttached(const Instruction &Inst, const Function &Fn) const
It can be advantageous to detach complex constants from their uses to make their generation cheaper.
LLVM_ABI bool hasArmWideBranch(bool Thumb) const
LLVM_ABI const char * getRegisterClassName(unsigned ClassID) const
LLVM_ABI bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
LLVM_ABI APInt getPriorityMask(const Function &F) const
Returns a bitmask constructed from the target-features or fmv-features metadata of a function corresp...
LLVM_ABI BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
LLVM_ABI TargetTransformInfo(std::unique_ptr< const TargetTransformInfoImplBase > Impl)
Construct a TTI object using a type implementing the Concept API below.
LLVM_ABI bool preferInLoopReduction(RecurKind Kind, Type *Ty) const
LLVM_ABI unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const
LLVM_ABI bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const
LLVM_ABI InstructionCost getMulAccReductionCost(bool IsUnsigned, unsigned RedOpcode, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add/...
LLVM_ABI unsigned getCacheLineSize() const
LLVM_ABI bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), unsigned *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
LLVM_ABI bool shouldCopyAttributeWhenOutliningFrom(const Function *Caller, const Attribute &Attr) const
LLVM_ABI APInt getAddrSpaceCastPreservedPtrMask(unsigned SrcAS, unsigned DstAS) const
Returns a mask indicating which bits of a pointer remain unchanged when casting between address space...
LLVM_ABI int getInlinerVectorBonusPercent() const
LLVM_ABI unsigned getEpilogueVectorizationMinVF() const
LLVM_ABI void collectKernelLaunchBounds(const Function &F, SmallVectorImpl< std::pair< StringRef, int64_t > > &LB) const
Collect kernel launch bounds for F into LB.
PopcntSupportKind
Flags indicating the kind of support for population count.
LLVM_ABI bool preferPredicatedReductionSelect() const
LLVM_ABI InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
LLVM_ABI AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
LLVM_ABI bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
llvm::VectorInstrContext VectorInstrContext
LLVM_ABI bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
LLVM_ABI unsigned getInliningThresholdMultiplier() const
LLVM_ABI InstructionCost getBranchMispredictPenalty() const
Returns estimated penalty of a branch misprediction in latency.
LLVM_ABI unsigned getNumberOfRegisters(unsigned ClassID) const
LLVM_ABI bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
Return true if this is an alternating opcode pattern that can be lowered to a single instruction on t...
LLVM_ABI bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
LLVM_ABI bool supportsScalableVectors() const
LLVM_ABI bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
LLVM_ABI bool isLegalMaskedCompressStore(Type *DataType, Align Alignment) const
Return true if the target supports masked compress store.
LLVM_ABI std::optional< unsigned > getMinPageSize() const
LLVM_ABI InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy, TTI::TargetCostKind CostKind, ArrayRef< int > Mask={}, int Index=0, VectorType *SubTp=nullptr, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr) const
LLVM_ABI bool preferSLPInstCountCheck() const
LLVM_ABI bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
LLVM_ABI InstructionCost getInsertExtractValueCost(unsigned Opcode, TTI::TargetCostKind CostKind) const
LLVM_ABI bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
LLVM_ABI std::optional< unsigned > getCacheSize(CacheLevel Level) const
LLVM_ABI std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
LLVM_ABI bool isLegalAddScalableImmediate(int64_t Imm) const
Return true if adding the specified scalable immediate is legal, that is the target has add instructi...
LLVM_ABI bool isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, unsigned ScalarOpdIdx) const
Identifies if the vector form of the intrinsic has a scalar operand.
LLVM_ABI bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
LLVM_ABI bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
LLVM_ABI unsigned getMinTripCountTailFoldingThreshold() const
LLVM_ABI InstructionCost getPartialReductionCost(unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType, ElementCount VF, PartialReductionExtendKind OpAExtend, PartialReductionExtendKind OpBExtend, std::optional< unsigned > BinOp, TTI::TargetCostKind CostKind, std::optional< FastMathFlags > FMF) const
LLVM_ABI InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
LLVM_ABI bool enableScalableVectorization() const
LLVM_ABI bool useFastCCForInternalCall(Function &F) const
Return true if the input function is internal, should use fastcc calling convention.
LLVM_ABI bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
LLVM_ABI bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
LLVM_ABI unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const
LLVM_ABI bool isLegalMaskedVectorHistogram(Type *AddrType, Type *DataType) const
LLVM_ABI unsigned getGISelRematGlobalCost() const
LLVM_ABI unsigned getNumBytesToPadGlobalArray(unsigned Size, Type *ArrayType) const
static LLVM_ABI Instruction::CastOps getOpcodeForPartialReductionExtendKind(PartialReductionExtendKind Kind)
Get the cast opcode for an extension kind.
MemIndexedMode
The type of load/store indexing.
LLVM_ABI InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr, const TargetLibraryInfo *TLibInfo=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
LLVM_ABI bool isLegalMaskedLoad(Type *DataType, Align Alignment, unsigned AddressSpace, MaskKind MaskKind=VariableOrConstantMask) const
Return true if the target supports masked load.
LLVM_ABI InstructionCost getIndexedVectorInstrCostFromEnd(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index) const
LLVM_ABI bool areInlineCompatible(const Function *Caller, const Function *Callee) const
LLVM_ABI bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
LLVM_ABI InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
LLVM_ABI bool supportsTailCalls() const
If the target supports tail calls.
LLVM_ABI bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
LLVM_ABI bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Query the target whether the specified address space cast from FromAS to ToAS is valid.
LLVM_ABI unsigned getNumberOfParts(Type *Tp) const
AddressingModeKind
Which addressing mode Loop Strength Reduction will try to generate.
LLVM_ABI InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
LLVM_ABI bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
LLVM_ABI bool isProfitableToSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const
Return true if sinking I's operands to the same basic block as I is profitable, e....
LLVM_ABI void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicCpySize=std::nullopt) const
LLVM_ABI bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
LLVM_ABI bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, int OpdIdx) const
Identifies if the vector form of the intrinsic is overloaded on the type of the operand at index OpdI...
static LLVM_ABI VectorInstrContext getVectorInstrContextHint(const Instruction *I)
Calculates a VectorInstrContext from I.
LLVM_ABI InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const PointersChainInfo &Info, Type *AccessTy, const TargetCostKind CostKind) const
Estimate the cost of a chain of pointers (typically pointer operands of a chain of loads or stores wi...
LLVM_ABI bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
LLVM_ABI bool shouldExpandReduction(const IntrinsicInst *II) const
LLVM_ABI InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind, bool ForPoisonSrc=true, ArrayRef< Value * > VL={}, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
Estimate the overhead of scalarizing an instruction.
LLVM_ABI uint64_t getMaxMemIntrinsicInlineSizeThreshold() const
Returns the maximum memset / memcpy size in bytes that still makes it profitable to inline the call.
ShuffleKind
The various kinds of shuffle patterns for vector queries.
LLVM_ABI APInt getFeatureMask(const Function &F) const
Returns a bitmask constructed from the target-features or fmv-features metadata of a function corresp...
LLVM_ABI void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
CastContextHint
Represents a hint about the context in which a cast is used.
@ Masked
The cast is used with a masked load/store.
@ None
The cast is not used with a load/store of any kind.
@ Normal
The cast is used with a normal load/store.
@ GatherScatter
The cast is used with a gather/scatter.
LLVM_ABI InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index, TTI::TargetCostKind CostKind) const
LLVM_ABI InstructionCost getRegisterClassSpillCost(unsigned ClassID, TargetCostKind CostKind) const
OperandValueKind
Additional information about an operand's possible values.
CacheLevel
The possible cache levels.
LLVM_ABI bool preferFixedOverScalableIfEqualCost() const
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:46
static LLVM_ABI IntegerType * getInt32Ty(LLVMContext &C)
Definition Type.cpp:299
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition Type.h:363
LLVM_ABI bool isScalableTy() const
Return true if this is a type whose size is a known multiple of vscale.
Definition Type.cpp:61
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Definition Value.h:75
Type * getType() const
All values are typed, get the type of this value.
Definition Value.h:257
Base class of all SIMD vector types.
ElementCount getElementCount() const
Return an ElementCount instance to represent the (possibly scalable) number of elements in the vector...
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition TypeSize.h:165
CallInst * Call
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
@ Length
Definition DWP.cpp:577
InstructionCost Cost
@ Known
Known to have no common set bits.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:643
VectorInstrContext
Represents a hint about the context in which a vector instruction or intrinsic is used.
@ None
The instruction is not folded.
@ Load
The value being inserted comes from a load (InsertElement only).
@ Store
The extracted value is stored (ExtractElement only).
LLVM_ABI Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
bool containsIrreducibleCFG(RPOTraversalT &RPOTraversal, const LoopInfoT &LI)
Return true if the control flow in RPOTraversal is irreducible.
Definition CFG.h:154
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
Definition Casting.h:547
LLVM_ABI ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
RecurKind
These are the kinds of recurrences that we support.
@ Fast
Assign the register banks as fast as possible (default).
constexpr unsigned BitWidth
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1933
auto predecessors(const MachineBasicBlock *BB)
AnalysisManager< Function > FunctionAnalysisManager
Convenience typedef for the Function analysis manager.
ValueUniformity
Enum describing how values behave with respect to uniformity and divergence, to answer the question: ...
Definition Uniformity.h:18
@ NeverUniform
The result value can never be assumed to be uniform.
Definition Uniformity.h:26
@ Default
The result value is uniform if and only if all operands are uniform.
Definition Uniformity.h:20
Implement std::hash so that hash_code can be used in STL containers.
Definition BitVector.h:878
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition Analysis.h:29
Attributes of a target dependent hardware loop.
LLVM_ABI bool canAnalyze(LoopInfo &LI)
LLVM_ABI bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Information about a load/store intrinsic defined by the target.
Returns options for expansion of memcmp. IsZeroCmp is.
OperandValueInfo mergeWith(const OperandValueInfo OpInfoY)
Describe known properties for a set of pointers.
Parameters that control the generic loop unrolling transformation.