LLVM 20.0.0git
TargetTransformInfo.cpp
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1//===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
10#include "llvm/Analysis/CFG.h"
14#include "llvm/IR/CFG.h"
15#include "llvm/IR/Dominators.h"
16#include "llvm/IR/Instruction.h"
19#include "llvm/IR/Module.h"
20#include "llvm/IR/Operator.h"
23#include <optional>
24#include <utility>
25
26using namespace llvm;
27using namespace PatternMatch;
28
29#define DEBUG_TYPE "tti"
30
31static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
33 cl::desc("Recognize reduction patterns."));
34
36 "cache-line-size", cl::init(0), cl::Hidden,
37 cl::desc("Use this to override the target cache line size when "
38 "specified by the user."));
39
41 "min-page-size", cl::init(0), cl::Hidden,
42 cl::desc("Use this to override the target's minimum page size."));
43
45 "predictable-branch-threshold", cl::init(99), cl::Hidden,
47 "Use this to override the target's predictable branch threshold (%)."));
48
49namespace {
50/// No-op implementation of the TTI interface using the utility base
51/// classes.
52///
53/// This is used when no target specific information is available.
54struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
55 explicit NoTTIImpl(const DataLayout &DL)
56 : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
57};
58} // namespace
59
61 // If the loop has irreducible control flow, it can not be converted to
62 // Hardware loop.
63 LoopBlocksRPO RPOT(L);
64 RPOT.perform(&LI);
65 if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
66 return false;
67 return true;
68}
69
71 Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost,
72 bool TypeBasedOnly)
73 : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
74 ScalarizationCost(ScalarizationCost) {
75
76 if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
77 FMF = FPMO->getFastMathFlags();
78
79 if (!TypeBasedOnly)
80 Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
82 ParamTys.insert(ParamTys.begin(), FTy->param_begin(), FTy->param_end());
83}
84
87 FastMathFlags Flags,
88 const IntrinsicInst *I,
89 InstructionCost ScalarCost)
90 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
91 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
92}
93
96 : RetTy(Ty), IID(Id) {
97
98 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
99 ParamTys.reserve(Arguments.size());
100 for (const Value *Argument : Arguments)
101 ParamTys.push_back(Argument->getType());
102}
103
107 FastMathFlags Flags,
108 const IntrinsicInst *I,
109 InstructionCost ScalarCost)
110 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
111 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
112 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
113}
114
116 // Match default options:
117 // - hardware-loop-counter-bitwidth = 32
118 // - hardware-loop-decrement = 1
120 LoopDecrement = ConstantInt::get(CountType, 1);
121}
122
124 LoopInfo &LI, DominatorTree &DT,
125 bool ForceNestedLoop,
127 SmallVector<BasicBlock *, 4> ExitingBlocks;
128 L->getExitingBlocks(ExitingBlocks);
129
130 for (BasicBlock *BB : ExitingBlocks) {
131 // If we pass the updated counter back through a phi, we need to know
132 // which latch the updated value will be coming from.
133 if (!L->isLoopLatch(BB)) {
135 continue;
136 }
137
138 const SCEV *EC = SE.getExitCount(L, BB);
139 if (isa<SCEVCouldNotCompute>(EC))
140 continue;
141 if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
142 if (ConstEC->getValue()->isZero())
143 continue;
144 } else if (!SE.isLoopInvariant(EC, L))
145 continue;
146
147 if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
148 continue;
149
150 // If this exiting block is contained in a nested loop, it is not eligible
151 // for insertion of the branch-and-decrement since the inner loop would
152 // end up messing up the value in the CTR.
153 if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
154 continue;
155
156 // We now have a loop-invariant count of loop iterations (which is not the
157 // constant zero) for which we know that this loop will not exit via this
158 // existing block.
159
160 // We need to make sure that this block will run on every loop iteration.
161 // For this to be true, we must dominate all blocks with backedges. Such
162 // blocks are in-loop predecessors to the header block.
163 bool NotAlways = false;
164 for (BasicBlock *Pred : predecessors(L->getHeader())) {
165 if (!L->contains(Pred))
166 continue;
167
168 if (!DT.dominates(BB, Pred)) {
169 NotAlways = true;
170 break;
171 }
172 }
173
174 if (NotAlways)
175 continue;
176
177 // Make sure this blocks ends with a conditional branch.
178 Instruction *TI = BB->getTerminator();
179 if (!TI)
180 continue;
181
182 if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
183 if (!BI->isConditional())
184 continue;
185
186 ExitBranch = BI;
187 } else
188 continue;
189
190 // Note that this block may not be the loop latch block, even if the loop
191 // has a latch block.
192 ExitBlock = BB;
193 ExitCount = EC;
194 break;
195 }
196
197 if (!ExitBlock)
198 return false;
199 return true;
200}
201
203 : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
204
206
208 : TTIImpl(std::move(Arg.TTIImpl)) {}
209
211 TTIImpl = std::move(RHS.TTIImpl);
212 return *this;
213}
214
216 return TTIImpl->getInliningThresholdMultiplier();
217}
218
219unsigned
221 return TTIImpl->getInliningCostBenefitAnalysisSavingsMultiplier();
222}
223
224unsigned
226 const {
227 return TTIImpl->getInliningCostBenefitAnalysisProfitableMultiplier();
228}
229
231 return TTIImpl->getInliningLastCallToStaticBonus();
232}
233
234unsigned
236 return TTIImpl->adjustInliningThreshold(CB);
237}
238
240 const AllocaInst *AI) const {
241 return TTIImpl->getCallerAllocaCost(CB, AI);
242}
243
245 return TTIImpl->getInlinerVectorBonusPercent();
246}
247
249 Type *PointeeType, const Value *Ptr, ArrayRef<const Value *> Operands,
250 Type *AccessType, TTI::TargetCostKind CostKind) const {
251 return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, AccessType, CostKind);
252}
253
256 const TTI::PointersChainInfo &Info, Type *AccessTy,
258 assert((Base || !Info.isSameBase()) &&
259 "If pointers have same base address it has to be provided.");
260 return TTIImpl->getPointersChainCost(Ptrs, Base, Info, AccessTy, CostKind);
261}
262
264 const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
265 BlockFrequencyInfo *BFI) const {
266 return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
267}
268
272 enum TargetCostKind CostKind) const {
273 InstructionCost Cost = TTIImpl->getInstructionCost(U, Operands, CostKind);
275 "TTI should not produce negative costs!");
276 return Cost;
277}
278
280 return PredictableBranchThreshold.getNumOccurrences() > 0
282 : TTIImpl->getPredictableBranchThreshold();
283}
284
286 return TTIImpl->getBranchMispredictPenalty();
287}
288
290 return TTIImpl->hasBranchDivergence(F);
291}
292
294 if (const auto *Call = dyn_cast<CallBase>(V)) {
295 if (Call->hasFnAttr(Attribute::NoDivergenceSource))
296 return false;
297 }
298 return TTIImpl->isSourceOfDivergence(V);
299}
300
302 return TTIImpl->isAlwaysUniform(V);
303}
304
306 unsigned ToAS) const {
307 return TTIImpl->isValidAddrSpaceCast(FromAS, ToAS);
308}
309
311 unsigned ToAS) const {
312 return TTIImpl->addrspacesMayAlias(FromAS, ToAS);
313}
314
316 return TTIImpl->getFlatAddressSpace();
317}
318
320 SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
321 return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
322}
323
325 unsigned ToAS) const {
326 return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
327}
328
330 unsigned AS) const {
331 return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
332}
333
335 return TTIImpl->getAssumedAddrSpace(V);
336}
337
339 return TTIImpl->isSingleThreaded();
340}
341
342std::pair<const Value *, unsigned>
344 return TTIImpl->getPredicatedAddrSpace(V);
345}
346
348 IntrinsicInst *II, Value *OldV, Value *NewV) const {
349 return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
350}
351
353 return TTIImpl->isLoweredToCall(F);
354}
355
358 TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
359 return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
360}
361
363 return TTIImpl->getEpilogueVectorizationMinVF();
364}
365
367 TailFoldingInfo *TFI) const {
368 return TTIImpl->preferPredicateOverEpilogue(TFI);
369}
370
372 bool IVUpdateMayOverflow) const {
373 return TTIImpl->getPreferredTailFoldingStyle(IVUpdateMayOverflow);
374}
375
376std::optional<Instruction *>
378 IntrinsicInst &II) const {
379 return TTIImpl->instCombineIntrinsic(IC, II);
380}
381
383 InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
384 bool &KnownBitsComputed) const {
385 return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
386 KnownBitsComputed);
387}
388
390 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
391 APInt &UndefElts2, APInt &UndefElts3,
392 std::function<void(Instruction *, unsigned, APInt, APInt &)>
393 SimplifyAndSetOp) const {
394 return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
395 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
396 SimplifyAndSetOp);
397}
398
401 OptimizationRemarkEmitter *ORE) const {
402 return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
403}
404
406 PeelingPreferences &PP) const {
407 return TTIImpl->getPeelingPreferences(L, SE, PP);
408}
409
411 return TTIImpl->isLegalAddImmediate(Imm);
412}
413
415 return TTIImpl->isLegalAddScalableImmediate(Imm);
416}
417
419 return TTIImpl->isLegalICmpImmediate(Imm);
420}
421
423 int64_t BaseOffset,
424 bool HasBaseReg, int64_t Scale,
425 unsigned AddrSpace,
426 Instruction *I,
427 int64_t ScalableOffset) const {
428 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
429 Scale, AddrSpace, I, ScalableOffset);
430}
431
433 const LSRCost &C2) const {
434 return TTIImpl->isLSRCostLess(C1, C2);
435}
436
438 return TTIImpl->isNumRegsMajorCostOfLSR();
439}
440
442 return TTIImpl->shouldDropLSRSolutionIfLessProfitable();
443}
444
446 return TTIImpl->isProfitableLSRChainElement(I);
447}
448
450 return TTIImpl->canMacroFuseCmp();
451}
452
454 ScalarEvolution *SE, LoopInfo *LI,
456 TargetLibraryInfo *LibInfo) const {
457 return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
458}
459
462 ScalarEvolution *SE) const {
463 return TTIImpl->getPreferredAddressingMode(L, SE);
464}
465
467 Align Alignment) const {
468 return TTIImpl->isLegalMaskedStore(DataType, Alignment);
469}
470
472 Align Alignment) const {
473 return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
474}
475
477 Align Alignment) const {
478 return TTIImpl->isLegalNTStore(DataType, Alignment);
479}
480
481bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
482 return TTIImpl->isLegalNTLoad(DataType, Alignment);
483}
484
486 ElementCount NumElements) const {
487 return TTIImpl->isLegalBroadcastLoad(ElementTy, NumElements);
488}
489
491 Align Alignment) const {
492 return TTIImpl->isLegalMaskedGather(DataType, Alignment);
493}
494
496 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
497 const SmallBitVector &OpcodeMask) const {
498 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask);
499}
500
502 Align Alignment) const {
503 return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
504}
505
507 Align Alignment) const {
508 return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment);
509}
510
512 Align Alignment) const {
513 return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment);
514}
515
517 Align Alignment) const {
518 return TTIImpl->isLegalMaskedCompressStore(DataType, Alignment);
519}
520
522 Align Alignment) const {
523 return TTIImpl->isLegalMaskedExpandLoad(DataType, Alignment);
524}
525
527 Align Alignment) const {
528 return TTIImpl->isLegalStridedLoadStore(DataType, Alignment);
529}
530
532 VectorType *VTy, unsigned Factor, Align Alignment,
533 unsigned AddrSpace) const {
534 return TTIImpl->isLegalInterleavedAccessType(VTy, Factor, Alignment,
535 AddrSpace);
536}
537
539 Type *DataType) const {
540 return TTIImpl->isLegalMaskedVectorHistogram(AddrType, DataType);
541}
542
544 return TTIImpl->enableOrderedReductions();
545}
546
547bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
548 return TTIImpl->hasDivRemOp(DataType, IsSigned);
549}
550
552 unsigned AddrSpace) const {
553 return TTIImpl->hasVolatileVariant(I, AddrSpace);
554}
555
557 return TTIImpl->prefersVectorizedAddressing();
558}
559
561 Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg,
562 int64_t Scale, unsigned AddrSpace) const {
563 InstructionCost Cost = TTIImpl->getScalingFactorCost(
564 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
565 assert(Cost >= 0 && "TTI should not produce negative costs!");
566 return Cost;
567}
568
570 return TTIImpl->LSRWithInstrQueries();
571}
572
574 return TTIImpl->isTruncateFree(Ty1, Ty2);
575}
576
578 return TTIImpl->isProfitableToHoist(I);
579}
580
581bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
582
584 return TTIImpl->isTypeLegal(Ty);
585}
586
588 return TTIImpl->getRegUsageForType(Ty);
589}
590
592 return TTIImpl->shouldBuildLookupTables();
593}
594
596 Constant *C) const {
597 return TTIImpl->shouldBuildLookupTablesForConstant(C);
598}
599
601 return TTIImpl->shouldBuildRelLookupTables();
602}
603
605 return TTIImpl->useColdCCForColdCall(F);
606}
607
609 Intrinsic::ID ID) const {
610 return TTIImpl->isTargetIntrinsicTriviallyScalarizable(ID);
611}
612
614 Intrinsic::ID ID, unsigned ScalarOpdIdx) const {
615 return TTIImpl->isTargetIntrinsicWithScalarOpAtArg(ID, ScalarOpdIdx);
616}
617
619 Intrinsic::ID ID, int OpdIdx) const {
620 return TTIImpl->isTargetIntrinsicWithOverloadTypeAtArg(ID, OpdIdx);
621}
622
624 Intrinsic::ID ID, int RetIdx) const {
625 return TTIImpl->isTargetIntrinsicWithStructReturnOverloadAtField(ID, RetIdx);
626}
627
629 VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract,
631 return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
632 CostKind, VL);
633}
634
638 return TTIImpl->getOperandsScalarizationOverhead(Args, Tys, CostKind);
639}
640
642 return TTIImpl->supportsEfficientVectorElementLoadStore();
643}
644
646 return TTIImpl->supportsTailCalls();
647}
648
650 return TTIImpl->supportsTailCallFor(CB);
651}
652
654 bool LoopHasReductions) const {
655 return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
656}
657
659TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
660 return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
661}
662
664 return TTIImpl->enableSelectOptimize();
665}
666
668 const Instruction *I) const {
669 return TTIImpl->shouldTreatInstructionLikeSelect(I);
670}
671
673 return TTIImpl->enableInterleavedAccessVectorization();
674}
675
677 return TTIImpl->enableMaskedInterleavedAccessVectorization();
678}
679
681 return TTIImpl->isFPVectorizationPotentiallyUnsafe();
682}
683
684bool
686 unsigned BitWidth,
687 unsigned AddressSpace,
688 Align Alignment,
689 unsigned *Fast) const {
690 return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
691 AddressSpace, Alignment, Fast);
692}
693
695TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
696 return TTIImpl->getPopcntSupport(IntTyWidthInBit);
697}
698
700 return TTIImpl->haveFastSqrt(Ty);
701}
702
704 const Instruction *I) const {
705 return TTIImpl->isExpensiveToSpeculativelyExecute(I);
706}
707
709 return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
710}
711
713 InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
714 assert(Cost >= 0 && "TTI should not produce negative costs!");
715 return Cost;
716}
717
719 unsigned Idx,
720 const APInt &Imm,
721 Type *Ty) const {
722 InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
723 assert(Cost >= 0 && "TTI should not produce negative costs!");
724 return Cost;
725}
726
730 InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
731 assert(Cost >= 0 && "TTI should not produce negative costs!");
732 return Cost;
733}
734
736 unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
739 TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
740 assert(Cost >= 0 && "TTI should not produce negative costs!");
741 return Cost;
742}
743
746 const APInt &Imm, Type *Ty,
749 TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
750 assert(Cost >= 0 && "TTI should not produce negative costs!");
751 return Cost;
752}
753
755 const Instruction &Inst, const Function &Fn) const {
756 return TTIImpl->preferToKeepConstantsAttached(Inst, Fn);
757}
758
759unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
760 return TTIImpl->getNumberOfRegisters(ClassID);
761}
762
764 return TTIImpl->hasConditionalLoadStoreForType(Ty);
765}
766
768 Type *Ty) const {
769 return TTIImpl->getRegisterClassForType(Vector, Ty);
770}
771
772const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
773 return TTIImpl->getRegisterClassName(ClassID);
774}
775
778 return TTIImpl->getRegisterBitWidth(K);
779}
780
782 return TTIImpl->getMinVectorRegisterBitWidth();
783}
784
785std::optional<unsigned> TargetTransformInfo::getMaxVScale() const {
786 return TTIImpl->getMaxVScale();
787}
788
789std::optional<unsigned> TargetTransformInfo::getVScaleForTuning() const {
790 return TTIImpl->getVScaleForTuning();
791}
792
794 return TTIImpl->isVScaleKnownToBeAPowerOfTwo();
795}
796
799 return TTIImpl->shouldMaximizeVectorBandwidth(K);
800}
801
803 bool IsScalable) const {
804 return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
805}
806
807unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
808 unsigned Opcode) const {
809 return TTIImpl->getMaximumVF(ElemWidth, Opcode);
810}
811
812unsigned TargetTransformInfo::getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
813 Type *ScalarValTy) const {
814 return TTIImpl->getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy);
815}
816
818 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
819 return TTIImpl->shouldConsiderAddressTypePromotion(
820 I, AllowPromotionWithoutCommonHeader);
821}
822
824 return CacheLineSize.getNumOccurrences() > 0 ? CacheLineSize
825 : TTIImpl->getCacheLineSize();
826}
827
828std::optional<unsigned>
830 return TTIImpl->getCacheSize(Level);
831}
832
833std::optional<unsigned>
835 return TTIImpl->getCacheAssociativity(Level);
836}
837
838std::optional<unsigned> TargetTransformInfo::getMinPageSize() const {
839 return MinPageSize.getNumOccurrences() > 0 ? MinPageSize
840 : TTIImpl->getMinPageSize();
841}
842
844 return TTIImpl->getPrefetchDistance();
845}
846
848 unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
849 unsigned NumPrefetches, bool HasCall) const {
850 return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
851 NumPrefetches, HasCall);
852}
853
855 return TTIImpl->getMaxPrefetchIterationsAhead();
856}
857
859 return TTIImpl->enableWritePrefetching();
860}
861
863 return TTIImpl->shouldPrefetchAddressSpace(AS);
864}
865
867 return TTIImpl->getMaxInterleaveFactor(VF);
868}
869
874
875 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
876 if (const auto *CI = dyn_cast<ConstantInt>(V)) {
877 if (CI->getValue().isPowerOf2())
878 OpProps = OP_PowerOf2;
879 else if (CI->getValue().isNegatedPowerOf2())
880 OpProps = OP_NegatedPowerOf2;
881 }
882 return {OK_UniformConstantValue, OpProps};
883 }
884
885 // A broadcast shuffle creates a uniform value.
886 // TODO: Add support for non-zero index broadcasts.
887 // TODO: Add support for different source vector width.
888 if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
889 if (ShuffleInst->isZeroEltSplat())
890 OpInfo = OK_UniformValue;
891
892 const Value *Splat = getSplatValue(V);
893
894 // Check for a splat of a constant or for a non uniform vector of constants
895 // and check if the constant(s) are all powers of two.
896 if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
898 if (Splat) {
900 if (auto *CI = dyn_cast<ConstantInt>(Splat)) {
901 if (CI->getValue().isPowerOf2())
902 OpProps = OP_PowerOf2;
903 else if (CI->getValue().isNegatedPowerOf2())
904 OpProps = OP_NegatedPowerOf2;
905 }
906 } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
907 bool AllPow2 = true, AllNegPow2 = true;
908 for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
909 if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I))) {
910 AllPow2 &= CI->getValue().isPowerOf2();
911 AllNegPow2 &= CI->getValue().isNegatedPowerOf2();
912 if (AllPow2 || AllNegPow2)
913 continue;
914 }
915 AllPow2 = AllNegPow2 = false;
916 break;
917 }
918 OpProps = AllPow2 ? OP_PowerOf2 : OpProps;
919 OpProps = AllNegPow2 ? OP_NegatedPowerOf2 : OpProps;
920 }
921 }
922
923 // Check for a splat of a uniform value. This is not loop aware, so return
924 // true only for the obviously uniform cases (argument, globalvalue)
925 if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
926 OpInfo = OK_UniformValue;
927
928 return {OpInfo, OpProps};
929}
930
932 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
933 OperandValueInfo Op1Info, OperandValueInfo Op2Info,
934 ArrayRef<const Value *> Args, const Instruction *CxtI,
935 const TargetLibraryInfo *TLibInfo) const {
936
937 // Use call cost for frem intructions that have platform specific vector math
938 // functions, as those will be replaced with calls later by SelectionDAG or
939 // ReplaceWithVecLib pass.
940 if (TLibInfo && Opcode == Instruction::FRem) {
941 VectorType *VecTy = dyn_cast<VectorType>(Ty);
942 LibFunc Func;
943 if (VecTy &&
944 TLibInfo->getLibFunc(Instruction::FRem, Ty->getScalarType(), Func) &&
945 TLibInfo->isFunctionVectorizable(TLibInfo->getName(Func),
946 VecTy->getElementCount()))
947 return getCallInstrCost(nullptr, VecTy, {VecTy, VecTy}, CostKind);
948 }
949
951 TTIImpl->getArithmeticInstrCost(Opcode, Ty, CostKind,
952 Op1Info, Op2Info,
953 Args, CxtI);
954 assert(Cost >= 0 && "TTI should not produce negative costs!");
955 return Cost;
956}
957
959 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
960 const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const {
962 TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind);
963 assert(Cost >= 0 && "TTI should not produce negative costs!");
964 return Cost;
965}
966
968 ShuffleKind Kind, VectorType *Ty, ArrayRef<int> Mask,
969 TTI::TargetCostKind CostKind, int Index, VectorType *SubTp,
970 ArrayRef<const Value *> Args, const Instruction *CxtI) const {
971 InstructionCost Cost = TTIImpl->getShuffleCost(Kind, Ty, Mask, CostKind,
972 Index, SubTp, Args, CxtI);
973 assert(Cost >= 0 && "TTI should not produce negative costs!");
974 return Cost;
975}
976
979 if (!I)
981
982 auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
983 unsigned GatScatOp) {
984 const Instruction *I = dyn_cast<Instruction>(V);
985 if (!I)
987
988 if (I->getOpcode() == LdStOp)
990
991 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
992 if (II->getIntrinsicID() == MaskedOp)
994 if (II->getIntrinsicID() == GatScatOp)
996 }
997
999 };
1000
1001 switch (I->getOpcode()) {
1002 case Instruction::ZExt:
1003 case Instruction::SExt:
1004 case Instruction::FPExt:
1005 return getLoadStoreKind(I->getOperand(0), Instruction::Load,
1006 Intrinsic::masked_load, Intrinsic::masked_gather);
1007 case Instruction::Trunc:
1008 case Instruction::FPTrunc:
1009 if (I->hasOneUse())
1010 return getLoadStoreKind(*I->user_begin(), Instruction::Store,
1011 Intrinsic::masked_store,
1012 Intrinsic::masked_scatter);
1013 break;
1014 default:
1015 return CastContextHint::None;
1016 }
1017
1019}
1020
1022 unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
1023 TTI::TargetCostKind CostKind, const Instruction *I) const {
1024 assert((I == nullptr || I->getOpcode() == Opcode) &&
1025 "Opcode should reflect passed instruction.");
1027 TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
1028 assert(Cost >= 0 && "TTI should not produce negative costs!");
1029 return Cost;
1030}
1031
1033 unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const {
1035 TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
1036 assert(Cost >= 0 && "TTI should not produce negative costs!");
1037 return Cost;
1038}
1039
1041 unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
1042 assert((I == nullptr || I->getOpcode() == Opcode) &&
1043 "Opcode should reflect passed instruction.");
1044 InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
1045 assert(Cost >= 0 && "TTI should not produce negative costs!");
1046 return Cost;
1047}
1048
1050 unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
1052 OperandValueInfo Op2Info, const Instruction *I) const {
1053 assert((I == nullptr || I->getOpcode() == Opcode) &&
1054 "Opcode should reflect passed instruction.");
1055 InstructionCost Cost = TTIImpl->getCmpSelInstrCost(
1056 Opcode, ValTy, CondTy, VecPred, CostKind, Op1Info, Op2Info, I);
1057 assert(Cost >= 0 && "TTI should not produce negative costs!");
1058 return Cost;
1059}
1060
1062 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1063 Value *Op0, Value *Op1) const {
1064 assert((Opcode == Instruction::InsertElement ||
1065 Opcode == Instruction::ExtractElement) &&
1066 "Expecting Opcode to be insertelement/extractelement.");
1068 TTIImpl->getVectorInstrCost(Opcode, Val, CostKind, Index, Op0, Op1);
1069 assert(Cost >= 0 && "TTI should not produce negative costs!");
1070 return Cost;
1071}
1072
1074 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1075 Value *Scalar,
1076 ArrayRef<std::tuple<Value *, User *, int>> ScalarUserAndIdx) const {
1077 assert((Opcode == Instruction::InsertElement ||
1078 Opcode == Instruction::ExtractElement) &&
1079 "Expecting Opcode to be insertelement/extractelement.");
1080 InstructionCost Cost = TTIImpl->getVectorInstrCost(
1081 Opcode, Val, CostKind, Index, Scalar, ScalarUserAndIdx);
1082 assert(Cost >= 0 && "TTI should not produce negative costs!");
1083 return Cost;
1084}
1085
1089 unsigned Index) const {
1090 // FIXME: Assert that Opcode is either InsertElement or ExtractElement.
1091 // This is mentioned in the interface description and respected by all
1092 // callers, but never asserted upon.
1093 InstructionCost Cost = TTIImpl->getVectorInstrCost(I, Val, CostKind, Index);
1094 assert(Cost >= 0 && "TTI should not produce negative costs!");
1095 return Cost;
1096}
1097
1099 Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts,
1101 InstructionCost Cost = TTIImpl->getReplicationShuffleCost(
1102 EltTy, ReplicationFactor, VF, DemandedDstElts, CostKind);
1103 assert(Cost >= 0 && "TTI should not produce negative costs!");
1104 return Cost;
1105}
1106
1108 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1110 const Instruction *I) const {
1111 assert((I == nullptr || I->getOpcode() == Opcode) &&
1112 "Opcode should reflect passed instruction.");
1113 InstructionCost Cost = TTIImpl->getMemoryOpCost(
1114 Opcode, Src, Alignment, AddressSpace, CostKind, OpInfo, I);
1115 assert(Cost >= 0 && "TTI should not produce negative costs!");
1116 return Cost;
1117}
1118
1120 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1122 InstructionCost Cost = TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment,
1124 assert(Cost >= 0 && "TTI should not produce negative costs!");
1125 return Cost;
1126}
1127
1129 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
1130 Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const {
1131 InstructionCost Cost = TTIImpl->getGatherScatterOpCost(
1132 Opcode, DataTy, Ptr, VariableMask, Alignment, CostKind, I);
1133 assert((!Cost.isValid() || Cost >= 0) &&
1134 "TTI should not produce negative costs!");
1135 return Cost;
1136}
1137
1139 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
1140 Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const {
1141 InstructionCost Cost = TTIImpl->getStridedMemoryOpCost(
1142 Opcode, DataTy, Ptr, VariableMask, Alignment, CostKind, I);
1143 assert(Cost >= 0 && "TTI should not produce negative costs!");
1144 return Cost;
1145}
1146
1148 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
1149 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
1150 bool UseMaskForCond, bool UseMaskForGaps) const {
1151 InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
1152 Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
1153 UseMaskForCond, UseMaskForGaps);
1154 assert(Cost >= 0 && "TTI should not produce negative costs!");
1155 return Cost;
1156}
1157
1161 InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
1162 assert(Cost >= 0 && "TTI should not produce negative costs!");
1163 return Cost;
1164}
1165
1168 ArrayRef<Type *> Tys,
1170 InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
1171 assert(Cost >= 0 && "TTI should not produce negative costs!");
1172 return Cost;
1173}
1174
1176 return TTIImpl->getNumberOfParts(Tp);
1177}
1178
1181 const SCEV *Ptr) const {
1182 InstructionCost Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
1183 assert(Cost >= 0 && "TTI should not produce negative costs!");
1184 return Cost;
1185}
1186
1188 InstructionCost Cost = TTIImpl->getMemcpyCost(I);
1189 assert(Cost >= 0 && "TTI should not produce negative costs!");
1190 return Cost;
1191}
1192
1194 return TTIImpl->getMaxMemIntrinsicInlineSizeThreshold();
1195}
1196
1198 unsigned Opcode, VectorType *Ty, std::optional<FastMathFlags> FMF,
1201 TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
1202 assert(Cost >= 0 && "TTI should not produce negative costs!");
1203 return Cost;
1204}
1205
1210 TTIImpl->getMinMaxReductionCost(IID, Ty, FMF, CostKind);
1211 assert(Cost >= 0 && "TTI should not produce negative costs!");
1212 return Cost;
1213}
1214
1216 unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1218 return TTIImpl->getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
1219 CostKind);
1220}
1221
1223 bool IsUnsigned, Type *ResTy, VectorType *Ty,
1225 return TTIImpl->getMulAccReductionCost(IsUnsigned, ResTy, Ty, CostKind);
1226}
1227
1230 return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
1231}
1232
1234 MemIntrinsicInfo &Info) const {
1235 return TTIImpl->getTgtMemIntrinsic(Inst, Info);
1236}
1237
1239 return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
1240}
1241
1243 IntrinsicInst *Inst, Type *ExpectedType) const {
1244 return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
1245}
1246
1248 LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
1249 unsigned DestAddrSpace, Align SrcAlign, Align DestAlign,
1250 std::optional<uint32_t> AtomicElementSize) const {
1251 return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
1252 DestAddrSpace, SrcAlign, DestAlign,
1253 AtomicElementSize);
1254}
1255
1257 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
1258 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1259 Align SrcAlign, Align DestAlign,
1260 std::optional<uint32_t> AtomicCpySize) const {
1261 TTIImpl->getMemcpyLoopResidualLoweringType(
1262 OpsOut, Context, RemainingBytes, SrcAddrSpace, DestAddrSpace, SrcAlign,
1263 DestAlign, AtomicCpySize);
1264}
1265
1267 const Function *Callee) const {
1268 return TTIImpl->areInlineCompatible(Caller, Callee);
1269}
1270
1271unsigned
1273 const CallBase &Call,
1274 unsigned DefaultCallPenalty) const {
1275 return TTIImpl->getInlineCallPenalty(F, Call, DefaultCallPenalty);
1276}
1277
1279 const Function *Caller, const Function *Callee,
1280 const ArrayRef<Type *> &Types) const {
1281 return TTIImpl->areTypesABICompatible(Caller, Callee, Types);
1282}
1283
1285 Type *Ty) const {
1286 return TTIImpl->isIndexedLoadLegal(Mode, Ty);
1287}
1288
1290 Type *Ty) const {
1291 return TTIImpl->isIndexedStoreLegal(Mode, Ty);
1292}
1293
1295 return TTIImpl->getLoadStoreVecRegBitWidth(AS);
1296}
1297
1299 return TTIImpl->isLegalToVectorizeLoad(LI);
1300}
1301
1303 return TTIImpl->isLegalToVectorizeStore(SI);
1304}
1305
1307 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1308 return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1309 AddrSpace);
1310}
1311
1313 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1314 return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1315 AddrSpace);
1316}
1317
1319 const RecurrenceDescriptor &RdxDesc, ElementCount VF) const {
1320 return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1321}
1322
1324 return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1325}
1326
1328 unsigned LoadSize,
1329 unsigned ChainSizeInBytes,
1330 VectorType *VecTy) const {
1331 return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1332}
1333
1335 unsigned StoreSize,
1336 unsigned ChainSizeInBytes,
1337 VectorType *VecTy) const {
1338 return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1339}
1340
1342 return TTIImpl->preferFixedOverScalableIfEqualCost();
1343}
1344
1346 ReductionFlags Flags) const {
1347 return TTIImpl->preferInLoopReduction(Opcode, Ty, Flags);
1348}
1349
1351 unsigned Opcode, Type *Ty, ReductionFlags Flags) const {
1352 return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty, Flags);
1353}
1354
1356 return TTIImpl->preferEpilogueVectorization();
1357}
1358
1361 return TTIImpl->getVPLegalizationStrategy(VPI);
1362}
1363
1365 return TTIImpl->hasArmWideBranch(Thumb);
1366}
1367
1369 return TTIImpl->getMaxNumArgs();
1370}
1371
1373 return TTIImpl->shouldExpandReduction(II);
1374}
1375
1378 const IntrinsicInst *II) const {
1379 return TTIImpl->getPreferredExpandedReductionShuffle(II);
1380}
1381
1383 return TTIImpl->getGISelRematGlobalCost();
1384}
1385
1387 return TTIImpl->getMinTripCountTailFoldingThreshold();
1388}
1389
1391 return TTIImpl->supportsScalableVectors();
1392}
1393
1395 return TTIImpl->enableScalableVectorization();
1396}
1397
1398bool TargetTransformInfo::hasActiveVectorLength(unsigned Opcode, Type *DataType,
1399 Align Alignment) const {
1400 return TTIImpl->hasActiveVectorLength(Opcode, DataType, Alignment);
1401}
1402
1404 Instruction *I, SmallVectorImpl<Use *> &OpsToSink) const {
1405 return TTIImpl->isProfitableToSinkOperands(I, OpsToSink);
1406}
1407
1409 return TTIImpl->isVectorShiftByScalarCheap(Ty);
1410}
1411
1412unsigned
1414 Type *ArrayType) const {
1415 return TTIImpl->getNumBytesToPadGlobalArray(Size, ArrayType);
1416}
1417
1419
1420TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1421
1423 std::function<Result(const Function &)> TTICallback)
1424 : TTICallback(std::move(TTICallback)) {}
1425
1428 return TTICallback(F);
1429}
1430
1431AnalysisKey TargetIRAnalysis::Key;
1432
1433TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1434 return Result(F.getDataLayout());
1435}
1436
1437// Register the basic pass.
1439 "Target Transform Information", false, true)
1441
1442void TargetTransformInfoWrapperPass::anchor() {}
1443
1445 : ImmutablePass(ID) {
1448}
1449
1451 TargetIRAnalysis TIRA)
1452 : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1455}
1456
1458 FunctionAnalysisManager DummyFAM;
1459 TTI = TIRA.run(F, DummyFAM);
1460 return *TTI;
1461}
1462
1465 return new TargetTransformInfoWrapperPass(std::move(TIRA));
1466}
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
return RetTy
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
Module.h This file contains the declarations for the Module class.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
uint64_t IntrinsicInst * II
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static SymbolRef::Type getType(const Symbol *Sym)
Definition: TapiFile.cpp:39
This file provides helpers for the implementation of a TargetTransformInfo-conforming class.
static cl::opt< unsigned > PredictableBranchThreshold("predictable-branch-threshold", cl::init(99), cl::Hidden, cl::desc("Use this to override the target's predictable branch threshold (%)."))
static cl::opt< bool > EnableReduxCost("costmodel-reduxcost", cl::init(false), cl::Hidden, cl::desc("Recognize reduction patterns."))
static cl::opt< unsigned > MinPageSize("min-page-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target's minimum page size."))
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
This pass exposes codegen information to IR-level passes.
Value * RHS
Class for arbitrary precision integers.
Definition: APInt.h:78
an instruction to allocate memory on the stack
Definition: Instructions.h:63
A container for analyses that lazily runs them and caches their results.
Definition: PassManager.h:253
This class represents an incoming formal argument to a Function.
Definition: Argument.h:31
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Class to represent array types.
Definition: DerivedTypes.h:395
A cache of @llvm.assume calls within a function.
LLVM Basic Block Representation.
Definition: BasicBlock.h:61
LLVMContext & getContext() const
Get the context in which this basic block lives.
Definition: BasicBlock.cpp:168
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Conditional or Unconditional Branch instruction.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1120
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation or the function signa...
Definition: InstrTypes.h:1349
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
Definition: InstrTypes.h:1269
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Definition: InstrTypes.h:1275
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:673
This is an important base class in LLVM.
Definition: Constant.h:42
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:63
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:162
bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Definition: Dominators.cpp:122
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:20
Class to represent function types.
Definition: DerivedTypes.h:105
param_iterator param_begin() const
Definition: DerivedTypes.h:130
param_iterator param_end() const
Definition: DerivedTypes.h:131
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:216
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:281
The core instruction combiner logic.
Definition: InstCombiner.h:48
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:74
IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false)
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:48
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:176
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
BlockT * getHeader() const
bool isLoopLatch(const BlockT *BB) const
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
Definition: LoopIterator.h:172
void perform(const LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
Definition: LoopIterator.h:180
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:39
The optimization diagnostic interface.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:77
This class represents a constant integer value.
This class represents an analyzed expression in the program.
The main scalar evolution driver.
uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1196
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
An instruction for storing to memory.
Definition: Instructions.h:292
Multiway switch.
Analysis pass providing the TargetTransformInfo.
Result run(const Function &F, FunctionAnalysisManager &)
TargetTransformInfo Result
TargetIRAnalysis()
Default construct a target IR analysis.
Provides information about what library functions are available for the current target.
bool getLibFunc(StringRef funcName, LibFunc &F) const
Searches for a particular function name.
StringRef getName(LibFunc F) const
bool isFunctionVectorizable(StringRef F, const ElementCount &VF) const
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Wrapper pass for TargetTransformInfo.
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
TargetTransformInfo & getTTI(const Function &F)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
bool isLegalToVectorizeLoad(LoadInst *LI) const
std::optional< unsigned > getVScaleForTuning() const
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const
Return false if a AS0 address cannot possibly alias a AS1 address.
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
InstructionCost getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
bool isLegalToVectorizeStore(StoreInst *SI) const
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
bool preferInLoopReduction(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
bool isAlwaysUniform(const Value *V) const
unsigned getAssumedAddrSpace(const Value *V) const
bool shouldDropLSRSolutionIfLessProfitable() const
Return true if LSR should drop a found solution if it's calculated to be less profitable than the bas...
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C2.
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicElementSize=std::nullopt) const
bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked expand load.
bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueInfo Op1Info={OK_AnyValue, OP_None}, OperandValueInfo Op2Info={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
bool hasBranchDivergence(const Function *F=nullptr) const
Return true if branch divergence exists.
MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE=nullptr, const SCEV *Ptr=nullptr) const
void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
Estimate the overhead of scalarizing an instructions unique non-constant operands.
bool supportsTailCallFor(const CallBase *CB) const
If target supports tail call on CB.
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
bool isProfitableLSRChainElement(Instruction *I) const
TypeSize getRegisterBitWidth(RegisterKind K) const
unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
Returns a penalty for invoking call Call in F.
bool isExpensiveToSpeculativelyExecute(const Instruction *I) const
Return true if the cost of the instruction is too high to speculatively execute and should be kept be...
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueInfo OpdInfo={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
std::optional< unsigned > getMaxVScale() const
InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind) const
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of vector reduction intrinsics.
unsigned getAtomicMemIntrinsicMaxElementSize() const
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
bool shouldTreatInstructionLikeSelect(const Instruction *I) const
Should the Select Optimization pass treat the given instruction like a select, potentially converting...
bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
TailFoldingStyle getPreferredTailFoldingStyle(bool IVUpdateMayOverflow=true) const
Query the target what the preferred style of tail folding is.
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType=nullptr, TargetCostKind CostKind=TCK_SizeAndLatency) const
Estimate the cost of a GEP operation when lowered.
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace) const
Return true is the target supports interleaved access for the given vector type VTy,...
unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy...
bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
ReductionShuffle getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduc...
static OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add ...
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr, int64_t ScalableOffset=0) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
bool isElementTypeLegalForScalableVector(Type *Ty) const
bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
unsigned getMaxPrefetchIterationsAhead() const
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const
Return true if the target supports strided load.
TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF=FastMathFlags(), TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
TargetCostKind
The kind of cost model.
@ TCK_RecipThroughput
Reciprocal throughput.
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr, const TargetLibraryInfo *TLibInfo=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
bool enableSelectOptimize() const
Should the Select Optimization pass be enabled and ran.
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
OperandValueProperties
Additional properties of an operand's values.
InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const PointersChainInfo &Info, Type *AccessTy, TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Estimate the cost of a chain of pointers (typically pointer operands of a chain of loads or stores wi...
bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
bool isSourceOfDivergence(const Value *V) const
Returns whether V is a source of divergence.
bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
std::optional< unsigned > getCacheAssociativity(CacheLevel Level) const
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
InstructionCost getMemcpyCost(const Instruction *I) const
unsigned adjustInliningThreshold(const CallBase *CB) const
bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
bool isTargetIntrinsicWithStructReturnOverloadAtField(Intrinsic::ID ID, int RetIdx) const
Identifies if the vector form of the intrinsic that returns a struct is overloaded at the struct elem...
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
bool isTargetIntrinsicTriviallyScalarizable(Intrinsic::ID ID) const
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask={}, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, int Index=0, VectorType *SubTp=nullptr, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr) const
bool shouldPrefetchAddressSpace(unsigned AS) const
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
unsigned getMinVectorRegisterBitWidth() const
bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
bool preferToKeepConstantsAttached(const Instruction &Inst, const Function &Fn) const
It can be advantageous to detach complex constants from their uses to make their generation cheaper.
bool hasArmWideBranch(bool Thumb) const
const char * getRegisterClassName(unsigned ClassID) const
bool preferEpilogueVectorization() const
Return true if the loop vectorizer should consider vectorizing an otherwise scalar epilogue loop.
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), unsigned *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
unsigned getEpilogueVectorizationMinVF() const
PopcntSupportKind
Flags indicating the kind of support for population count.
InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
unsigned getInliningThresholdMultiplier() const
InstructionCost getBranchMispredictPenalty() const
Returns estimated penalty of a branch misprediction in latency.
unsigned getNumberOfRegisters(unsigned ClassID) const
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
Return true if this is an alternating opcode pattern that can be lowered to a single instruction on t...
bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
bool isLegalMaskedCompressStore(Type *DataType, Align Alignment) const
Return true if the target supports masked compress store.
std::optional< unsigned > getMinPageSize() const
bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Return true if the target supports masked store.
bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const
std::optional< unsigned > getCacheSize(CacheLevel Level) const
std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
bool isLegalAddScalableImmediate(int64_t Imm) const
Return true if adding the specified scalable immediate is legal, that is the target has add instructi...
bool isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, unsigned ScalarOpdIdx) const
Identifies if the vector form of the intrinsic has a scalar operand.
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Returns the cost estimation for alternating opcode pattern that can be lowered to a single instructio...
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind, ArrayRef< Value * > VL={}) const
Estimate the overhead of scalarizing an instruction.
bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
unsigned getMinTripCountTailFoldingThreshold() const
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
unsigned getMaxInterleaveFactor(ElementCount VF) const
bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const
bool isLegalMaskedVectorHistogram(Type *AddrType, Type *DataType) const
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
unsigned getGISelRematGlobalCost() const
unsigned getNumBytesToPadGlobalArray(unsigned Size, Type *ArrayType) const
MemIndexedMode
The type of load/store indexing.
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
bool supportsTailCalls() const
If the target supports tail calls.
bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Query the target whether the specified address space cast from FromAS to ToAS is valid.
unsigned getNumberOfParts(Type *Tp) const
bool hasConditionalLoadStoreForType(Type *Ty=nullptr) const
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
bool isProfitableToSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const
Return true if sinking I's operands to the same basic block as I is profitable, e....
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicCpySize=std::nullopt) const
bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const
Query the target whether it would be prefered to create a predicated vector loop, which can avoid the...
bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, int OpdIdx) const
Identifies if the vector form of the intrinsic is overloaded on the type of the operand at index OpdI...
bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
bool shouldExpandReduction(const IntrinsicInst *II) const
TargetTransformInfo(T Impl)
Construct a TTI object using a type implementing the Concept API below.
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const
Returns the maximum memset / memcpy size in bytes that still makes it profitable to inline the call.
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index=-1, Value *Op0=nullptr, Value *Op1=nullptr) const
ShuffleKind
The various kinds of shuffle patterns for vector queries.
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency) const
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
CastContextHint
Represents a hint about the context in which a cast is used.
@ Masked
The cast is used with a masked load/store.
@ None
The cast is not used with a load/store of any kind.
@ Normal
The cast is used with a normal load/store.
@ GatherScatter
The cast is used with a gather/scatter.
OperandValueKind
Additional information about an operand's possible values.
CacheLevel
The possible cache levels.
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked load.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
static IntegerType * getInt32Ty(LLVMContext &C)
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:355
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
Base class of all SIMD vector types.
Definition: DerivedTypes.h:427
ElementCount getElementCount() const
Return an ElementCount instance to represent the (possibly scalable) number of elements in the vector...
Definition: DerivedTypes.h:665
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Length
Definition: DWP.cpp:480
void initializeTargetTransformInfoWrapperPassPass(PassRegistry &)
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition: Casting.h:649
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:217
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1873
auto predecessors(const MachineBasicBlock *BB)
InstructionCost Cost
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: Analysis.h:28
Attributes of a target dependent hardware loop.
bool canAnalyze(LoopInfo &LI)
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Information about a load/store intrinsic defined by the target.
Returns options for expansion of memcmp. IsZeroCmp is.
Describe known properties for a set of pointers.
Flags describing the kind of vector reduction.
Parameters that control the generic loop unrolling transformation.