LLVM  16.0.0git
TargetTransformInfo.cpp
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1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "llvm/Analysis/CFG.h"
13 #include "llvm/IR/CFG.h"
14 #include "llvm/IR/Dominators.h"
15 #include "llvm/IR/Instruction.h"
16 #include "llvm/IR/Instructions.h"
17 #include "llvm/IR/IntrinsicInst.h"
18 #include "llvm/IR/Module.h"
19 #include "llvm/IR/Operator.h"
20 #include "llvm/IR/PatternMatch.h"
21 #include "llvm/InitializePasses.h"
23 #include <utility>
24 
25 using namespace llvm;
26 using namespace PatternMatch;
27 
28 #define DEBUG_TYPE "tti"
29 
30 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
31  cl::Hidden,
32  cl::desc("Recognize reduction patterns."));
33 
35  "cache-line-size", cl::init(0), cl::Hidden,
36  cl::desc("Use this to override the target cache line size when "
37  "specified by the user."));
38 
39 namespace {
40 /// No-op implementation of the TTI interface using the utility base
41 /// classes.
42 ///
43 /// This is used when no target specific information is available.
44 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
45  explicit NoTTIImpl(const DataLayout &DL)
46  : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
47 };
48 } // namespace
49 
51  // If the loop has irreducible control flow, it can not be converted to
52  // Hardware loop.
53  LoopBlocksRPO RPOT(L);
54  RPOT.perform(&LI);
55  if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
56  return false;
57  return true;
58 }
59 
61  Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost,
62  bool TypeBasedOnly)
63  : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
64  ScalarizationCost(ScalarizationCost) {
65 
66  if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
67  FMF = FPMO->getFastMathFlags();
68 
69  if (!TypeBasedOnly)
70  Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
72  ParamTys.insert(ParamTys.begin(), FTy->param_begin(), FTy->param_end());
73 }
74 
76  ArrayRef<Type *> Tys,
77  FastMathFlags Flags,
78  const IntrinsicInst *I,
79  InstructionCost ScalarCost)
80  : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
81  ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
82 }
83 
86  : RetTy(Ty), IID(Id) {
87 
88  Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
89  ParamTys.reserve(Arguments.size());
90  for (unsigned Idx = 0, Size = Arguments.size(); Idx != Size; ++Idx)
91  ParamTys.push_back(Arguments[Idx]->getType());
92 }
93 
96  ArrayRef<Type *> Tys,
97  FastMathFlags Flags,
98  const IntrinsicInst *I,
99  InstructionCost ScalarCost)
100  : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
101  ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
102  Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
103 }
104 
106  LoopInfo &LI, DominatorTree &DT,
107  bool ForceNestedLoop,
108  bool ForceHardwareLoopPHI) {
109  SmallVector<BasicBlock *, 4> ExitingBlocks;
110  L->getExitingBlocks(ExitingBlocks);
111 
112  for (BasicBlock *BB : ExitingBlocks) {
113  // If we pass the updated counter back through a phi, we need to know
114  // which latch the updated value will be coming from.
115  if (!L->isLoopLatch(BB)) {
117  continue;
118  }
119 
120  const SCEV *EC = SE.getExitCount(L, BB);
121  if (isa<SCEVCouldNotCompute>(EC))
122  continue;
123  if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
124  if (ConstEC->getValue()->isZero())
125  continue;
126  } else if (!SE.isLoopInvariant(EC, L))
127  continue;
128 
129  if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
130  continue;
131 
132  // If this exiting block is contained in a nested loop, it is not eligible
133  // for insertion of the branch-and-decrement since the inner loop would
134  // end up messing up the value in the CTR.
135  if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
136  continue;
137 
138  // We now have a loop-invariant count of loop iterations (which is not the
139  // constant zero) for which we know that this loop will not exit via this
140  // existing block.
141 
142  // We need to make sure that this block will run on every loop iteration.
143  // For this to be true, we must dominate all blocks with backedges. Such
144  // blocks are in-loop predecessors to the header block.
145  bool NotAlways = false;
146  for (BasicBlock *Pred : predecessors(L->getHeader())) {
147  if (!L->contains(Pred))
148  continue;
149 
150  if (!DT.dominates(BB, Pred)) {
151  NotAlways = true;
152  break;
153  }
154  }
155 
156  if (NotAlways)
157  continue;
158 
159  // Make sure this blocks ends with a conditional branch.
160  Instruction *TI = BB->getTerminator();
161  if (!TI)
162  continue;
163 
164  if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
165  if (!BI->isConditional())
166  continue;
167 
168  ExitBranch = BI;
169  } else
170  continue;
171 
172  // Note that this block may not be the loop latch block, even if the loop
173  // has a latch block.
174  ExitBlock = BB;
175  ExitCount = EC;
176  break;
177  }
178 
179  if (!ExitBlock)
180  return false;
181  return true;
182 }
183 
185  : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
186 
188 
190  : TTIImpl(std::move(Arg.TTIImpl)) {}
191 
193  TTIImpl = std::move(RHS.TTIImpl);
194  return *this;
195 }
196 
198  return TTIImpl->getInliningThresholdMultiplier();
199 }
200 
201 unsigned
203  return TTIImpl->adjustInliningThreshold(CB);
204 }
205 
207  return TTIImpl->getInlinerVectorBonusPercent();
208 }
209 
214  return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, CostKind);
215 }
216 
218  const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
219  BlockFrequencyInfo *BFI) const {
220  return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
221 }
222 
226  enum TargetCostKind CostKind) const {
227  InstructionCost Cost = TTIImpl->getInstructionCost(U, Operands, CostKind);
229  "TTI should not produce negative costs!");
230  return Cost;
231 }
232 
234  return TTIImpl->getPredictableBranchThreshold();
235 }
236 
238  return TTIImpl->hasBranchDivergence();
239 }
240 
242  return TTIImpl->useGPUDivergenceAnalysis();
243 }
244 
246  return TTIImpl->isSourceOfDivergence(V);
247 }
248 
250  return TTIImpl->isAlwaysUniform(V);
251 }
252 
254  return TTIImpl->getFlatAddressSpace();
255 }
256 
258  SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
259  return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
260 }
261 
263  unsigned ToAS) const {
264  return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
265 }
266 
268  unsigned AS) const {
269  return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
270 }
271 
273  return TTIImpl->getAssumedAddrSpace(V);
274 }
275 
277  return TTIImpl->isSingleThreaded();
278 }
279 
280 std::pair<const Value *, unsigned>
282  return TTIImpl->getPredicatedAddrSpace(V);
283 }
284 
286  IntrinsicInst *II, Value *OldV, Value *NewV) const {
287  return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
288 }
289 
291  return TTIImpl->isLoweredToCall(F);
292 }
293 
295  Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
296  TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
297  return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
298 }
299 
301  Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC,
303  InterleavedAccessInfo *IAI) const {
304  return TTIImpl->preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LVL, IAI);
305 }
306 
308  return TTIImpl->emitGetActiveLaneMask();
309 }
310 
313  IntrinsicInst &II) const {
314  return TTIImpl->instCombineIntrinsic(IC, II);
315 }
316 
318  InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
319  bool &KnownBitsComputed) const {
320  return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
321  KnownBitsComputed);
322 }
323 
325  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
326  APInt &UndefElts2, APInt &UndefElts3,
327  std::function<void(Instruction *, unsigned, APInt, APInt &)>
328  SimplifyAndSetOp) const {
329  return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
330  IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
331  SimplifyAndSetOp);
332 }
333 
336  OptimizationRemarkEmitter *ORE) const {
337  return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
338 }
339 
341  PeelingPreferences &PP) const {
342  return TTIImpl->getPeelingPreferences(L, SE, PP);
343 }
344 
346  return TTIImpl->isLegalAddImmediate(Imm);
347 }
348 
350  return TTIImpl->isLegalICmpImmediate(Imm);
351 }
352 
354  int64_t BaseOffset,
355  bool HasBaseReg, int64_t Scale,
356  unsigned AddrSpace,
357  Instruction *I) const {
358  return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
359  Scale, AddrSpace, I);
360 }
361 
363  const LSRCost &C2) const {
364  return TTIImpl->isLSRCostLess(C1, C2);
365 }
366 
368  return TTIImpl->isNumRegsMajorCostOfLSR();
369 }
370 
372  return TTIImpl->isProfitableLSRChainElement(I);
373 }
374 
376  return TTIImpl->canMacroFuseCmp();
377 }
378 
380  ScalarEvolution *SE, LoopInfo *LI,
382  TargetLibraryInfo *LibInfo) const {
383  return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
384 }
385 
388  ScalarEvolution *SE) const {
389  return TTIImpl->getPreferredAddressingMode(L, SE);
390 }
391 
393  Align Alignment) const {
394  return TTIImpl->isLegalMaskedStore(DataType, Alignment);
395 }
396 
398  Align Alignment) const {
399  return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
400 }
401 
403  Align Alignment) const {
404  return TTIImpl->isLegalNTStore(DataType, Alignment);
405 }
406 
408  return TTIImpl->isLegalNTLoad(DataType, Alignment);
409 }
410 
412  ElementCount NumElements) const {
413  return TTIImpl->isLegalBroadcastLoad(ElementTy, NumElements);
414 }
415 
417  Align Alignment) const {
418  return TTIImpl->isLegalMaskedGather(DataType, Alignment);
419 }
420 
422  VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
423  const SmallBitVector &OpcodeMask) const {
424  return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask);
425 }
426 
428  Align Alignment) const {
429  return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
430 }
431 
433  Align Alignment) const {
434  return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment);
435 }
436 
438  Align Alignment) const {
439  return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment);
440 }
441 
443  return TTIImpl->isLegalMaskedCompressStore(DataType);
444 }
445 
447  return TTIImpl->isLegalMaskedExpandLoad(DataType);
448 }
449 
451  return TTIImpl->enableOrderedReductions();
452 }
453 
454 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
455  return TTIImpl->hasDivRemOp(DataType, IsSigned);
456 }
457 
459  unsigned AddrSpace) const {
460  return TTIImpl->hasVolatileVariant(I, AddrSpace);
461 }
462 
464  return TTIImpl->prefersVectorizedAddressing();
465 }
466 
468  Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
469  int64_t Scale, unsigned AddrSpace) const {
470  InstructionCost Cost = TTIImpl->getScalingFactorCost(
471  Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
472  assert(Cost >= 0 && "TTI should not produce negative costs!");
473  return Cost;
474 }
475 
477  return TTIImpl->LSRWithInstrQueries();
478 }
479 
481  return TTIImpl->isTruncateFree(Ty1, Ty2);
482 }
483 
485  return TTIImpl->isProfitableToHoist(I);
486 }
487 
488 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
489 
491  return TTIImpl->isTypeLegal(Ty);
492 }
493 
495  return TTIImpl->getRegUsageForType(Ty);
496 }
497 
499  return TTIImpl->shouldBuildLookupTables();
500 }
501 
503  Constant *C) const {
504  return TTIImpl->shouldBuildLookupTablesForConstant(C);
505 }
506 
508  return TTIImpl->shouldBuildRelLookupTables();
509 }
510 
512  return TTIImpl->useColdCCForColdCall(F);
513 }
514 
517  const APInt &DemandedElts,
518  bool Insert, bool Extract) const {
519  return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
520 }
521 
524  return TTIImpl->getOperandsScalarizationOverhead(Args, Tys);
525 }
526 
528  return TTIImpl->supportsEfficientVectorElementLoadStore();
529 }
530 
532  return TTIImpl->supportsTailCalls();
533 }
534 
536  return TTIImpl->supportsTailCallFor(CB);
537 }
538 
540  bool LoopHasReductions) const {
541  return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
542 }
543 
545 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
546  return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
547 }
548 
550  return TTIImpl->enableInterleavedAccessVectorization();
551 }
552 
554  return TTIImpl->enableMaskedInterleavedAccessVectorization();
555 }
556 
558  return TTIImpl->isFPVectorizationPotentiallyUnsafe();
559 }
560 
561 bool
563  unsigned BitWidth,
564  unsigned AddressSpace,
565  Align Alignment,
566  unsigned *Fast) const {
567  return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
568  AddressSpace, Alignment, Fast);
569 }
570 
572 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
573  return TTIImpl->getPopcntSupport(IntTyWidthInBit);
574 }
575 
577  return TTIImpl->haveFastSqrt(Ty);
578 }
579 
581  const Instruction *I) const {
582  return TTIImpl->isExpensiveToSpeculativelyExecute(I);
583 }
584 
586  return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
587 }
588 
590  InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
591  assert(Cost >= 0 && "TTI should not produce negative costs!");
592  return Cost;
593 }
594 
596  unsigned Idx,
597  const APInt &Imm,
598  Type *Ty) const {
599  InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
600  assert(Cost >= 0 && "TTI should not produce negative costs!");
601  return Cost;
602 }
603 
607  InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
608  assert(Cost >= 0 && "TTI should not produce negative costs!");
609  return Cost;
610 }
611 
613  unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
616  TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
617  assert(Cost >= 0 && "TTI should not produce negative costs!");
618  return Cost;
619 }
620 
623  const APInt &Imm, Type *Ty,
626  TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
627  assert(Cost >= 0 && "TTI should not produce negative costs!");
628  return Cost;
629 }
630 
631 unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
632  return TTIImpl->getNumberOfRegisters(ClassID);
633 }
634 
636  Type *Ty) const {
637  return TTIImpl->getRegisterClassForType(Vector, Ty);
638 }
639 
640 const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
641  return TTIImpl->getRegisterClassName(ClassID);
642 }
643 
646  return TTIImpl->getRegisterBitWidth(K);
647 }
648 
650  return TTIImpl->getMinVectorRegisterBitWidth();
651 }
652 
654  return TTIImpl->getMaxVScale();
655 }
656 
658  return TTIImpl->getVScaleForTuning();
659 }
660 
663  return TTIImpl->shouldMaximizeVectorBandwidth(K);
664 }
665 
667  bool IsScalable) const {
668  return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
669 }
670 
671 unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
672  unsigned Opcode) const {
673  return TTIImpl->getMaximumVF(ElemWidth, Opcode);
674 }
675 
676 unsigned TargetTransformInfo::getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
677  Type *ScalarValTy) const {
678  return TTIImpl->getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy);
679 }
680 
682  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
683  return TTIImpl->shouldConsiderAddressTypePromotion(
684  I, AllowPromotionWithoutCommonHeader);
685 }
686 
688  return CacheLineSize.getNumOccurrences() > 0 ? CacheLineSize
689  : TTIImpl->getCacheLineSize();
690 }
691 
694  return TTIImpl->getCacheSize(Level);
695 }
696 
699  return TTIImpl->getCacheAssociativity(Level);
700 }
701 
703  return TTIImpl->getPrefetchDistance();
704 }
705 
707  unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
708  unsigned NumPrefetches, bool HasCall) const {
709  return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
710  NumPrefetches, HasCall);
711 }
712 
714  return TTIImpl->getMaxPrefetchIterationsAhead();
715 }
716 
718  return TTIImpl->enableWritePrefetching();
719 }
720 
722  return TTIImpl->shouldPrefetchAddressSpace(AS);
723 }
724 
725 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
726  return TTIImpl->getMaxInterleaveFactor(VF);
727 }
728 
731  OperandValueKind OpInfo = OK_AnyValue;
733 
734  if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
735  if (const auto *CI = dyn_cast<ConstantInt>(V)) {
736  if (CI->getValue().isPowerOf2())
737  OpProps = OP_PowerOf2;
738  else if (CI->getValue().isNegatedPowerOf2())
739  OpProps = OP_NegatedPowerOf2;
740  }
741  return {OK_UniformConstantValue, OpProps};
742  }
743 
744  // A broadcast shuffle creates a uniform value.
745  // TODO: Add support for non-zero index broadcasts.
746  // TODO: Add support for different source vector width.
747  if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
748  if (ShuffleInst->isZeroEltSplat())
749  OpInfo = OK_UniformValue;
750 
751  const Value *Splat = getSplatValue(V);
752 
753  // Check for a splat of a constant or for a non uniform vector of constants
754  // and check if the constant(s) are all powers of two.
755  if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
757  if (Splat) {
758  OpInfo = OK_UniformConstantValue;
759  if (auto *CI = dyn_cast<ConstantInt>(Splat)) {
760  if (CI->getValue().isPowerOf2())
761  OpProps = OP_PowerOf2;
762  else if (CI->getValue().isNegatedPowerOf2())
763  OpProps = OP_NegatedPowerOf2;
764  }
765  } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
766  bool AllPow2 = true, AllNegPow2 = true;
767  for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
768  if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I))) {
769  AllPow2 &= CI->getValue().isPowerOf2();
770  AllNegPow2 &= CI->getValue().isNegatedPowerOf2();
771  if (AllPow2 || AllNegPow2)
772  continue;
773  }
774  AllPow2 = AllNegPow2 = false;
775  break;
776  }
777  OpProps = AllPow2 ? OP_PowerOf2 : OpProps;
778  OpProps = AllNegPow2 ? OP_NegatedPowerOf2 : OpProps;
779  }
780  }
781 
782  // Check for a splat of a uniform value. This is not loop aware, so return
783  // true only for the obviously uniform cases (argument, globalvalue)
784  if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
785  OpInfo = OK_UniformValue;
786 
787  return {OpInfo, OpProps};
788 }
789 
791  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
792  OperandValueInfo Op1Info, OperandValueInfo Op2Info,
793  ArrayRef<const Value *> Args, const Instruction *CxtI) const {
795  TTIImpl->getArithmeticInstrCost(Opcode, Ty, CostKind,
796  Op1Info, Op2Info,
797  Args, CxtI);
798  assert(Cost >= 0 && "TTI should not produce negative costs!");
799  return Cost;
800 }
801 
807  TTIImpl->getShuffleCost(Kind, Ty, Mask, CostKind, Index, SubTp, Args);
808  assert(Cost >= 0 && "TTI should not produce negative costs!");
809  return Cost;
810 }
811 
814  if (!I)
815  return CastContextHint::None;
816 
817  auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
818  unsigned GatScatOp) {
819  const Instruction *I = dyn_cast<Instruction>(V);
820  if (!I)
821  return CastContextHint::None;
822 
823  if (I->getOpcode() == LdStOp)
825 
826  if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
827  if (II->getIntrinsicID() == MaskedOp)
829  if (II->getIntrinsicID() == GatScatOp)
831  }
832 
834  };
835 
836  switch (I->getOpcode()) {
837  case Instruction::ZExt:
838  case Instruction::SExt:
839  case Instruction::FPExt:
840  return getLoadStoreKind(I->getOperand(0), Instruction::Load,
841  Intrinsic::masked_load, Intrinsic::masked_gather);
842  case Instruction::Trunc:
843  case Instruction::FPTrunc:
844  if (I->hasOneUse())
845  return getLoadStoreKind(*I->user_begin(), Instruction::Store,
846  Intrinsic::masked_store,
847  Intrinsic::masked_scatter);
848  break;
849  default:
850  return CastContextHint::None;
851  }
852 
854 }
855 
857  unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
858  TTI::TargetCostKind CostKind, const Instruction *I) const {
859  assert((I == nullptr || I->getOpcode() == Opcode) &&
860  "Opcode should reflect passed instruction.");
862  TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
863  assert(Cost >= 0 && "TTI should not produce negative costs!");
864  return Cost;
865 }
866 
868  unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const {
870  TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
871  assert(Cost >= 0 && "TTI should not produce negative costs!");
872  return Cost;
873 }
874 
876  unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
877  assert((I == nullptr || I->getOpcode() == Opcode) &&
878  "Opcode should reflect passed instruction.");
879  InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
880  assert(Cost >= 0 && "TTI should not produce negative costs!");
881  return Cost;
882 }
883 
885  unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
886  TTI::TargetCostKind CostKind, const Instruction *I) const {
887  assert((I == nullptr || I->getOpcode() == Opcode) &&
888  "Opcode should reflect passed instruction.");
890  TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
891  assert(Cost >= 0 && "TTI should not produce negative costs!");
892  return Cost;
893 }
894 
896  Type *Val,
897  unsigned Index) const {
898  // FIXME: Assert that Opcode is either InsertElement or ExtractElement.
899  // This is mentioned in the interface description and respected by all
900  // callers, but never asserted upon.
901  InstructionCost Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
902  assert(Cost >= 0 && "TTI should not produce negative costs!");
903  return Cost;
904 }
905 
907  Type *Val,
908  unsigned Index) const {
909  // FIXME: Assert that Opcode is either InsertElement or ExtractElement.
910  // This is mentioned in the interface description and respected by all
911  // callers, but never asserted upon.
912  InstructionCost Cost = TTIImpl->getVectorInstrCost(I, Val, Index);
913  assert(Cost >= 0 && "TTI should not produce negative costs!");
914  return Cost;
915 }
916 
918  Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts,
920  InstructionCost Cost = TTIImpl->getReplicationShuffleCost(
921  EltTy, ReplicationFactor, VF, DemandedDstElts, CostKind);
922  assert(Cost >= 0 && "TTI should not produce negative costs!");
923  return Cost;
924 }
925 
927  unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
929  const Instruction *I) const {
930  assert((I == nullptr || I->getOpcode() == Opcode) &&
931  "Opcode should reflect passed instruction.");
932  InstructionCost Cost = TTIImpl->getMemoryOpCost(
933  Opcode, Src, Alignment, AddressSpace, CostKind, OpInfo, I);
934  assert(Cost >= 0 && "TTI should not produce negative costs!");
935  return Cost;
936 }
937 
939  unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
941  InstructionCost Cost = TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment,
943  assert(Cost >= 0 && "TTI should not produce negative costs!");
944  return Cost;
945 }
946 
948  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
949  Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const {
950  InstructionCost Cost = TTIImpl->getGatherScatterOpCost(
951  Opcode, DataTy, Ptr, VariableMask, Alignment, CostKind, I);
952  assert(Cost >= 0 && "TTI should not produce negative costs!");
953  return Cost;
954 }
955 
957  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
958  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
959  bool UseMaskForCond, bool UseMaskForGaps) const {
960  InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
961  Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
962  UseMaskForCond, UseMaskForGaps);
963  assert(Cost >= 0 && "TTI should not produce negative costs!");
964  return Cost;
965 }
966 
970  InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
971  assert(Cost >= 0 && "TTI should not produce negative costs!");
972  return Cost;
973 }
974 
977  ArrayRef<Type *> Tys,
979  InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
980  assert(Cost >= 0 && "TTI should not produce negative costs!");
981  return Cost;
982 }
983 
985  return TTIImpl->getNumberOfParts(Tp);
986 }
987 
990  const SCEV *Ptr) const {
991  InstructionCost Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
992  assert(Cost >= 0 && "TTI should not produce negative costs!");
993  return Cost;
994 }
995 
997  InstructionCost Cost = TTIImpl->getMemcpyCost(I);
998  assert(Cost >= 0 && "TTI should not produce negative costs!");
999  return Cost;
1000 }
1001 
1003  unsigned Opcode, VectorType *Ty, Optional<FastMathFlags> FMF,
1004  TTI::TargetCostKind CostKind) const {
1006  TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
1007  assert(Cost >= 0 && "TTI should not produce negative costs!");
1008  return Cost;
1009 }
1010 
1012  VectorType *Ty, VectorType *CondTy, bool IsUnsigned,
1013  TTI::TargetCostKind CostKind) const {
1015  TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
1016  assert(Cost >= 0 && "TTI should not produce negative costs!");
1017  return Cost;
1018 }
1019 
1021  unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1023  return TTIImpl->getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
1024  CostKind);
1025 }
1026 
1028  bool IsUnsigned, Type *ResTy, VectorType *Ty,
1029  TTI::TargetCostKind CostKind) const {
1030  return TTIImpl->getMulAccReductionCost(IsUnsigned, ResTy, Ty, CostKind);
1031 }
1032 
1035  return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
1036 }
1037 
1039  MemIntrinsicInfo &Info) const {
1040  return TTIImpl->getTgtMemIntrinsic(Inst, Info);
1041 }
1042 
1044  return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
1045 }
1046 
1048  IntrinsicInst *Inst, Type *ExpectedType) const {
1049  return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
1050 }
1051 
1053  LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
1054  unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign,
1055  Optional<uint32_t> AtomicElementSize) const {
1056  return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
1057  DestAddrSpace, SrcAlign, DestAlign,
1058  AtomicElementSize);
1059 }
1060 
1063  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1064  unsigned SrcAlign, unsigned DestAlign,
1065  Optional<uint32_t> AtomicCpySize) const {
1066  TTIImpl->getMemcpyLoopResidualLoweringType(
1067  OpsOut, Context, RemainingBytes, SrcAddrSpace, DestAddrSpace, SrcAlign,
1068  DestAlign, AtomicCpySize);
1069 }
1070 
1072  const Function *Callee) const {
1073  return TTIImpl->areInlineCompatible(Caller, Callee);
1074 }
1075 
1077  const Function *Caller, const Function *Callee,
1078  const ArrayRef<Type *> &Types) const {
1079  return TTIImpl->areTypesABICompatible(Caller, Callee, Types);
1080 }
1081 
1083  Type *Ty) const {
1084  return TTIImpl->isIndexedLoadLegal(Mode, Ty);
1085 }
1086 
1088  Type *Ty) const {
1089  return TTIImpl->isIndexedStoreLegal(Mode, Ty);
1090 }
1091 
1093  return TTIImpl->getLoadStoreVecRegBitWidth(AS);
1094 }
1095 
1097  return TTIImpl->isLegalToVectorizeLoad(LI);
1098 }
1099 
1101  return TTIImpl->isLegalToVectorizeStore(SI);
1102 }
1103 
1105  unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1106  return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1107  AddrSpace);
1108 }
1109 
1111  unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1112  return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1113  AddrSpace);
1114 }
1115 
1117  const RecurrenceDescriptor &RdxDesc, ElementCount VF) const {
1118  return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1119 }
1120 
1122  return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1123 }
1124 
1126  unsigned LoadSize,
1127  unsigned ChainSizeInBytes,
1128  VectorType *VecTy) const {
1129  return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1130 }
1131 
1133  unsigned StoreSize,
1134  unsigned ChainSizeInBytes,
1135  VectorType *VecTy) const {
1136  return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1137 }
1138 
1140  ReductionFlags Flags) const {
1141  return TTIImpl->preferInLoopReduction(Opcode, Ty, Flags);
1142 }
1143 
1145  unsigned Opcode, Type *Ty, ReductionFlags Flags) const {
1146  return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty, Flags);
1147 }
1148 
1150  return TTIImpl->preferEpilogueVectorization();
1151 }
1152 
1155  return TTIImpl->getVPLegalizationStrategy(VPI);
1156 }
1157 
1159  return TTIImpl->shouldExpandReduction(II);
1160 }
1161 
1163  return TTIImpl->getGISelRematGlobalCost();
1164 }
1165 
1167  return TTIImpl->getMinTripCountTailFoldingThreshold();
1168 }
1169 
1171  return TTIImpl->supportsScalableVectors();
1172 }
1173 
1175  return TTIImpl->enableScalableVectorization();
1176 }
1177 
1179  Align Alignment) const {
1180  return TTIImpl->hasActiveVectorLength(Opcode, DataType, Alignment);
1181 }
1182 
1184 
1185 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1186 
1188  std::function<Result(const Function &)> TTICallback)
1189  : TTICallback(std::move(TTICallback)) {}
1190 
1193  return TTICallback(F);
1194 }
1195 
1196 AnalysisKey TargetIRAnalysis::Key;
1197 
1198 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1199  return Result(F.getParent()->getDataLayout());
1200 }
1201 
1202 // Register the basic pass.
1204  "Target Transform Information", false, true)
1206 
1207 void TargetTransformInfoWrapperPass::anchor() {}
1208 
1210  : ImmutablePass(ID) {
1213 }
1214 
1216  TargetIRAnalysis TIRA)
1217  : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1220 }
1221 
1223  FunctionAnalysisManager DummyFAM;
1224  TTI = TIRA.run(F, DummyFAM);
1225  return *TTI;
1226 }
1227 
1228 ImmutablePass *
1230  return new TargetTransformInfoWrapperPass(std::move(TIRA));
1231 }
llvm::TargetTransformInfo::CastContextHint::GatherScatter
@ GatherScatter
The cast is used with a gather/scatter.
llvm::TargetTransformInfo::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
Definition: TargetTransformInfo.cpp:294
llvm::InstructionCost
Definition: InstructionCost.h:30
llvm::TargetTransformInfo::CastContextHint::Masked
@ Masked
The cast is used with a masked load/store.
llvm::TargetIRAnalysis
Analysis pass providing the TargetTransformInfo.
Definition: TargetTransformInfo.h:2586
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:218
llvm::TargetTransformInfo::getShuffleCost
InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask=None, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, int Index=0, VectorType *SubTp=nullptr, ArrayRef< const Value * > Args=None) const
Definition: TargetTransformInfo.cpp:802
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1455
llvm::TargetTransformInfo::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
Definition: TargetTransformInfo.cpp:312
llvm::TargetTransformInfo::getInstructionCost
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
Definition: TargetTransformInfo.cpp:224
llvm::TargetTransformInfo::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfo.cpp:649
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1403
Insert
Vector Rotate Left Mask Mask Insert
Definition: README_P9.txt:112
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::TargetTransformInfo::getVScaleForTuning
Optional< unsigned > getVScaleForTuning() const
Definition: TargetTransformInfo.cpp:657
IntrinsicInst.h
llvm::ImmutablePass
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:279
llvm::TargetTransformInfo::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:640
llvm::ElementCount
Definition: TypeSize.h:404
llvm::TargetTransformInfo::OK_UniformValue
@ OK_UniformValue
Definition: TargetTransformInfo.h:909
llvm::TargetTransformInfo::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:884
llvm::TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
Definition: TargetTransformInfo.cpp:1209
llvm::TargetTransformInfo::canMacroFuseCmp
bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
Definition: TargetTransformInfo.cpp:375
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:547
llvm::LoopBase::contains
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
Definition: LoopInfo.h:139
llvm::TargetTransformInfo::getRegisterBitWidth
TypeSize getRegisterBitWidth(RegisterKind K) const
Definition: TargetTransformInfo.cpp:644
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:586
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:53
llvm::TargetTransformInfo::getVPLegalizationStrategy
VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: TargetTransformInfo.cpp:1154
llvm::TargetTransformInfoWrapperPass::getTTI
TargetTransformInfo & getTTI(const Function &F)
Definition: TargetTransformInfo.cpp:1222
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::TargetTransformInfo::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE=nullptr, const SCEV *Ptr=nullptr) const
Definition: TargetTransformInfo.cpp:989
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:371
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:173
llvm::TargetTransformInfo::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Definition: TargetTransformInfo.cpp:467
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::TargetTransformInfo::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:968
llvm::LoopVectorizationLegality
LoopVectorizationLegality checks if it is legal to vectorize a loop, and to what vectorization factor...
Definition: LoopVectorizationLegality.h:241
llvm::TargetTransformInfo::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfo.cpp:272
llvm::TargetTransformInfo::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: TargetTransformInfo.cpp:349
llvm::initializeTargetTransformInfoWrapperPassPass
void initializeTargetTransformInfoWrapperPassPass(PassRegistry &)
llvm::TargetTransformInfo::isLegalBroadcastLoad
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy...
Definition: TargetTransformInfo.cpp:411
llvm::TargetTransformInfo::getExtendedReductionCost
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduc...
Definition: TargetTransformInfo.cpp:1020
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:166
llvm::HardwareLoopInfo::ExitBranch
BranchInst * ExitBranch
Definition: TargetTransformInfo.h:102
llvm::ScalarEvolution::getTypeSizeInBits
uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
Definition: ScalarEvolution.cpp:4335
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1513
llvm::TargetTransformInfo::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
Definition: TargetTransformInfo.cpp:498
llvm::HardwareLoopInfo::isHardwareLoopCandidate
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Definition: TargetTransformInfo.cpp:105
llvm::TargetTransformInfo::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfo.cpp:671
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
Definition: TargetTransformInfo.cpp:511
Module.h
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:529
llvm::TargetTransformInfo::operator=
TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
Definition: TargetTransformInfo.cpp:192
llvm::HardwareLoopInfo::L
Loop * L
Definition: TargetTransformInfo.h:100
llvm::TargetTransformInfo::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
Definition: TargetTransformInfo.cpp:407
llvm::TargetTransformInfo::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
Definition: TargetTransformInfo.cpp:402
llvm::Optional
Definition: APInt.h:33
ForceNestedLoop
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
llvm::TargetTransformInfo::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:875
Vector
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::IntrinsicCostAttributes::IntrinsicCostAttributes
IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false)
Definition: TargetTransformInfo.cpp:60
llvm::TargetTransformInfo::OP_PowerOf2
@ OP_PowerOf2
Definition: TargetTransformInfo.h:917
llvm::TargetTransformInfo::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
Definition: TargetTransformInfo.cpp:233
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
Operator.h
llvm::TargetTransformInfo::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
Definition: TargetTransformInfo.cpp:595
llvm::TargetTransformInfo::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfo.cpp:206
llvm::TargetTransformInfo::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:622
llvm::LoopBase::isLoopLatch
bool isLoopLatch(const BlockT *BB) const
Definition: LoopInfo.h:256
llvm::CallBase::arg_begin
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
Definition: InstrTypes.h:1316
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::TargetTransformInfo::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
Definition: TargetTransformInfo.cpp:612
llvm::FastMathFlags
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:21
llvm::TargetTransformInfo::OperandValueInfo
Definition: TargetTransformInfo.h:924
llvm::TargetTransformInfo::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
Definition: TargetTransformInfo.cpp:549
llvm::TargetTransformInfo::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Estimate the overhead of scalarizing an instructions unique non-constant operands.
Definition: TargetTransformInfo.cpp:522
llvm::TargetTransformInfo::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1139
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:1021
new
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
Definition: README.txt:125
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::TargetTransformInfo::canHaveNonUndefGlobalInitializerInAddressSpace
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
Definition: TargetTransformInfo.cpp:267
TargetTransformInfoImpl.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::HardwareLoopInfo::IsNestingLegal
bool IsNestingLegal
Definition: TargetTransformInfo.h:107
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::LoopBlocksRPO
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
Definition: LoopIterator.h:172
llvm::TargetTransformInfo::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
Definition: TargetTransformInfo.cpp:334
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::DominatorTree::dominates
bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Definition: Dominators.cpp:122
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:35
llvm::TargetTransformInfo::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
Definition: TargetTransformInfo.cpp:427
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
Instruction.h
CommandLine.h
llvm::TargetTransformInfo::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfo.cpp:1162
llvm::TargetTransformInfo::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfo.cpp:1071
llvm::TargetTransformInfo::isTypeLegal
bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
Definition: TargetTransformInfo.cpp:490
llvm::HardwareLoopInfo::ExitCount
const SCEV * ExitCount
Definition: TargetTransformInfo.h:103
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::TargetTransformInfo::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfo.cpp:666
llvm::TargetTransformInfo::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfo.cpp:371
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:813
llvm::TargetTransformInfo::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfo.cpp:1047
llvm::TargetTransformInfo::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfo.cpp:1096
llvm::TargetTransformInfo::supportsTailCallFor
bool supportsTailCallFor(const CallBase *CB) const
If target supports tail call on CB.
Definition: TargetTransformInfo.cpp:535
llvm::TargetTransformInfo::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
Definition: TargetTransformInfo.cpp:790
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::dyn_cast
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition: Casting.h:647
llvm::TargetTransformInfo::getPopcntSupport
PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
Definition: TargetTransformInfo.cpp:572
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:916
InlinePriorityMode::Cost
@ Cost
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:887
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
EnableReduxCost
static cl::opt< bool > EnableReduxCost("costmodel-reduxcost", cl::init(false), cl::Hidden, cl::desc("Recognize reduction patterns."))
llvm::TargetTransformInfo::getPreferredAddressingMode
AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
Definition: TargetTransformInfo.cpp:387
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1139
llvm::User
Definition: User.h:44
llvm::TargetTransformInfo::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Return true if the target prefers to use GPU divergence analysis to replace the legacy version.
Definition: TargetTransformInfo.cpp:241
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::FunctionType::param_end
param_iterator param_end() const
Definition: DerivedTypes.h:129
llvm::CallBase::getCalledFunction
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation or the function signa...
Definition: InstrTypes.h:1396
llvm::TargetTransformInfo::hasBranchDivergence
bool hasBranchDivergence() const
Return true if branch divergence exists.
Definition: TargetTransformInfo.cpp:237
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::TargetTransformInfo::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: TargetTransformInfo.cpp:1116
llvm::TargetTransformInfo::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
Definition: TargetTransformInfo.cpp:605
SI
@ SI
Definition: SIInstrInfo.cpp:7882
llvm::TargetTransformInfo::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfo.cpp:984
llvm::TargetTransformInfo::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfo.cpp:1170
llvm::TargetTransformInfo::isIndexedLoadLegal
bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:1082
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::TargetTransformInfo::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Return true if the target supports masked expand load.
Definition: TargetTransformInfo.cpp:446
llvm::TargetTransformInfo::enableScalableVectorization
bool enableScalableVectorization() const
Definition: TargetTransformInfo.cpp:1174
llvm::FunctionType::param_begin
param_iterator param_begin() const
Definition: DerivedTypes.h:128
llvm::Instruction
Definition: Instruction.h:42
llvm::InterleavedAccessInfo
Drive the analysis of interleaved memory accesses in the loop.
Definition: VectorUtils.h:759
llvm::TargetTransformInfo::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked load.
Definition: TargetTransformInfo.cpp:397
llvm::TargetTransformInfo::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Returns whether V is a source of divergence.
Definition: TargetTransformInfo.cpp:245
llvm::TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:324
llvm::predecessors
auto predecessors(MachineBasicBlock *BB)
Definition: MachineSSAContext.h:30
llvm::LoopBase::getExitingBlocks
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
Definition: LoopInfoImpl.h:33
llvm::TargetTransformInfo::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfo.cpp:702
llvm::HardwareLoopInfo::CounterInReg
bool CounterInReg
Definition: TargetTransformInfo.h:109
llvm::TargetTransformInfoImplCRTPBase
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:942
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
Definition: TargetTransformInfo.cpp:585
PatternMatch.h
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::TargetTransformInfo::areTypesABICompatible
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
Definition: TargetTransformInfo.cpp:1076
LoopIterator.h
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:120
llvm::TargetTransformInfo::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
Definition: TargetTransformInfo.cpp:458
CFG.h
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:40
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::TargetTransformInfo::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Return true if the target supports masked compress store.
Definition: TargetTransformInfo.cpp:442
llvm::TargetTransformInfo::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
Definition: TargetTransformInfo.cpp:576
llvm::createTargetTransformInfoWrapperPass
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
Definition: TargetTransformInfo.cpp:1229
llvm::TargetTransformInfo::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, LoopVectorizationLegality *LVL, InterleavedAccessInfo *IAI) const
Query the target whether it would be prefered to create a predicated vector loop, which can avoid the...
Definition: TargetTransformInfo.cpp:300
llvm::TargetTransformInfo::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
Definition: TargetTransformInfo.cpp:253
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::TargetTransformInfo::CastContextHint::Normal
@ Normal
The cast is used with a normal load/store.
llvm::TargetTransformInfo::Concept::~Concept
virtual ~Concept()=0
llvm::cl::opt< bool >
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:75
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:297
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfo::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
Definition: TargetTransformInfo.cpp:502
CacheLineSize
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:403
llvm::TargetTransformInfo::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
Definition: TargetTransformInfo.cpp:257
llvm::TargetTransformInfo::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
Definition: TargetTransformInfo.cpp:416
llvm::TargetTransformInfoWrapperPass
Wrapper pass for TargetTransformInfo.
Definition: TargetTransformInfo.h:2642
llvm::TargetTransformInfo::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1144
llvm::TargetTransformInfo::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
Definition: TargetTransformInfo.cpp:956
llvm::TargetTransformInfo::OK_UniformConstantValue
@ OK_UniformConstantValue
Definition: TargetTransformInfo.h:910
llvm::TargetTransformInfo::forceScalarizeMaskedGather
bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
Definition: TargetTransformInfo.cpp:432
llvm::TargetIRAnalysis::Result
TargetTransformInfo Result
Definition: TargetTransformInfo.h:2588
llvm::TargetTransformInfo::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfo.cpp:725
llvm::TargetTransformInfo::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfo.cpp:635
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::TargetTransformInfo::preferEpilogueVectorization
bool preferEpilogueVectorization() const
Return true if the loop vectorizer should consider vectorizing an otherwise scalar epilogue loop.
Definition: TargetTransformInfo.cpp:1149
llvm::TargetTransformInfo::isLegalAltInstr
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
Return true if this is an alternating opcode pattern that can be lowered to a single instruction on t...
Definition: TargetTransformInfo.cpp:421
llvm::AnalysisKey
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: PassManager.h:69
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:417
llvm::TargetTransformInfo::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfo.cpp:1034
llvm::LoopInfoBase::getLoopFor
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Definition: LoopInfo.h:992
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:915
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
llvm::TargetTransformInfo::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfo.cpp:681
llvm::SCEVConstant
This class represents a constant integer value.
Definition: ScalarEvolutionExpressions.h:60
llvm::TargetTransformInfo::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Estimate the overhead of scalarizing an instruction.
Definition: TargetTransformInfo.cpp:516
llvm::TargetTransformInfo::getReplicationShuffleCost
InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfo.cpp:917
llvm::TargetTransformInfo::isExpensiveToSpeculativelyExecute
bool isExpensiveToSpeculativelyExecute(const Instruction *I) const
Return true if the cost of the instruction is too high to speculatively execute and should be kept be...
Definition: TargetTransformInfo.cpp:580
llvm::TargetTransformInfo::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
Definition: TargetTransformInfo.cpp:285
llvm::TargetTransformInfo::isLSRCostLess
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C2.
Definition: TargetTransformInfo.cpp:362
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetTransformInfo::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:947
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1836
llvm::TargetTransformInfo::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
Definition: TargetTransformInfo.cpp:476
llvm::TargetTransformInfo::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:1011
llvm::TargetTransformInfo::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1104
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::TargetTransformInfo::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TargetCostKind CostKind=TCK_SizeAndLatency) const
Estimate the cost of a GEP operation when lowered.
Definition: TargetTransformInfo.cpp:211
llvm::TargetTransformInfo::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: TargetTransformInfo.cpp:345
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:264
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::TargetTransformInfo::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
Definition: TargetTransformInfo.cpp:290
llvm::TargetTransformInfo::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:856
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:907
llvm::CallBase::arg_end
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Definition: InstrTypes.h:1322
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
getType
static M68kRelType getType(unsigned Kind, MCSymbolRefExpr::VariantKind &Modifier, bool &IsPCRel)
Definition: M68kELFObjectWriter.cpp:48
llvm::TargetTransformInfo::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
Definition: TargetTransformInfo.cpp:379
llvm::TargetTransformInfo::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
Definition: TargetTransformInfo.cpp:480
llvm::TargetTransformInfo::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
Definition: TargetTransformInfo.cpp:463
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:781
CFG.h
llvm::TargetTransformInfo::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
Definition: TargetTransformInfo.cpp:527
llvm::TargetTransformInfo::emitGetActiveLaneMask
PredicationStyle emitGetActiveLaneMask() const
Query the target whether lowering of the llvm.get.active.lane.mask intrinsic is supported and how the...
Definition: TargetTransformInfo.cpp:307
llvm::TargetTransformInfo::enableMemCmpExpansion
MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfo.cpp:545
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1108
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:42
llvm::TargetTransformInfo::isElementTypeLegalForScalableVector
bool isElementTypeLegalForScalableVector(Type *Ty) const
Definition: TargetTransformInfo.cpp:1121
llvm::TargetTransformInfo::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Return true if the target supports masked store.
Definition: TargetTransformInfo.cpp:392
llvm::TargetTransformInfo::getPredicatedAddrSpace
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
Definition: TargetTransformInfo.cpp:281
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetTransformInfo::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
Definition: TargetTransformInfo.cpp:454
llvm::TargetTransformInfo::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:317
llvm::TargetTransformInfo::getCacheSize
Optional< unsigned > getCacheSize(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:693
llvm::TargetTransformInfo::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:631
llvm::TargetTransformInfo::shouldPrefetchAddressSpace
bool shouldPrefetchAddressSpace(unsigned AS) const
Definition: TargetTransformInfo.cpp:721
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:633
llvm::TargetTransformInfo::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfo.cpp:713
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:432
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:908
llvm::TargetTransformInfo::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1125
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:173
llvm::TargetTransformInfo::CastContextHint::None
@ None
The cast is not used with a load/store of any kind.
llvm::TargetTransformInfo::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfo.cpp:1100
llvm::ScalarEvolution::isLoopInvariant
bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
Definition: ScalarEvolution.cpp:13626
llvm::TargetIRAnalysis::TargetIRAnalysis
TargetIRAnalysis()
Default construct a target IR analysis.
Definition: TargetTransformInfo.cpp:1185
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:187
llvm::TargetTransformInfo::enableOrderedReductions
bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
Definition: TargetTransformInfo.cpp:450
llvm::TargetTransformInfo::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfo.cpp:653
llvm::TargetTransformInfo::OP_NegatedPowerOf2
@ OP_NegatedPowerOf2
Definition: TargetTransformInfo.h:918
llvm::TargetTransformInfo::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicCpySize=None) const
Definition: TargetTransformInfo.cpp:1061
llvm::TargetTransformInfo::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicElementSize=None) const
Definition: TargetTransformInfo.cpp:1052
llvm::TargetTransformInfo::getCacheAssociativity
Optional< unsigned > getCacheAssociativity(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:698
llvm::TargetTransformInfo::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfo.cpp:687
llvm::TargetTransformInfo::supportsTailCalls
bool supportsTailCalls() const
If the target supports tail calls.
Definition: TargetTransformInfo.cpp:531
std
Definition: BitVector.h:851
llvm::TargetTransformInfo::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
Definition: TargetTransformInfo.cpp:553
llvm::KnownBits
Definition: KnownBits.h:23
llvm::HardwareLoopInfo::ExitBlock
BasicBlock * ExitBlock
Definition: TargetTransformInfo.h:101
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:152
llvm::TargetTransformInfo::getMulAccReductionCost
InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add ...
Definition: TargetTransformInfo.cpp:1027
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:475
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::TargetTransformInfo::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Definition: TargetTransformInfo.cpp:262
llvm::TargetTransformInfo::getOperandInfo
static OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:730
llvm::TypeSize
Definition: TypeSize.h:435
llvm::TargetTransformInfo::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1092
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::TargetTransformInfo::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
Definition: TargetTransformInfo.cpp:661
llvm::LoopBase::getHeader
BlockT * getHeader() const
Definition: LoopInfo.h:105
llvm::TargetTransformInfo::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
Definition: TargetTransformInfo.cpp:557
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:226
llvm::TargetTransformInfo::hasActiveVectorLength
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
Definition: TargetTransformInfo.cpp:1178
llvm::Function::getFunctionType
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:175
llvm::TargetTransformInfo::forceScalarizeMaskedScatter
bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
Definition: TargetTransformInfo.cpp:437
llvm::TargetTransformInfo::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueInfo OpdInfo={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:926
llvm::TargetIRAnalysis::run
Result run(const Function &F, FunctionAnalysisManager &)
Definition: TargetTransformInfo.cpp:1191
llvm::TargetTransformInfo::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfo.cpp:197
llvm::TargetTransformInfo::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index=-1) const
Definition: TargetTransformInfo.cpp:895
llvm::PredicationStyle
PredicationStyle
Definition: TargetTransformInfo.h:166
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfo::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfo.cpp:202
llvm::TargetTransformInfo::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:938
llvm::TargetTransformInfo::getMinTripCountTailFoldingThreshold
unsigned getMinTripCountTailFoldingThreshold() const
Definition: TargetTransformInfo.cpp:1166
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:97
llvm::TargetTransformInfo::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfo.cpp:217
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::TargetTransformInfo::TargetTransformInfo
TargetTransformInfo(T Impl)
Construct a TTI object using a type implementing the Concept API below.
Definition: TargetTransformInfo.h:2572
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:69
llvm::TargetTransformInfo::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of vector reduction intrinsics.
Definition: TargetTransformInfo.cpp:1002
Instructions.h
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:965
Dominators.h
DataType
llvm::IntegerType::getBitWidth
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:72
llvm::TargetTransformInfo::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
Definition: TargetTransformInfo.cpp:706
llvm::TargetTransformInfo::isIndexedStoreLegal
bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:1087
TargetTransformInfo.h
llvm::TargetTransformInfo::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
Definition: TargetTransformInfo.cpp:367
llvm::TargetTransformInfo::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfo.cpp:1158
llvm::TargetTransformInfo::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
Definition: TargetTransformInfo.cpp:867
llvm::TargetTransformInfo::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
Definition: TargetTransformInfo.cpp:340
llvm::TargetTransformInfo::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1132
llvm::HardwareLoopInfo::canAnalyze
bool canAnalyze(LoopInfo &LI)
Definition: TargetTransformInfo.cpp:50
llvm::TargetTransformInfo::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1110
llvm::SmallVectorImpl< int >
ForceHardwareLoopPHI
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:72
llvm::TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfo.cpp:1043
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1174
llvm::TargetTransformInfo::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
Definition: TargetTransformInfo.cpp:539
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:42
llvm::TargetTransformInfo::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), unsigned *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
Definition: TargetTransformInfo.cpp:562
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::TargetTransformInfo::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency) const
Definition: TargetTransformInfo.cpp:976
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3277
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::cl::desc
Definition: CommandLine.h:413
llvm::TargetTransformInfo::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
Definition: TargetTransformInfo.cpp:484
llvm::TargetTransformInfo::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
Definition: TargetTransformInfo.cpp:507
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3133
llvm::LoopBlocksRPO::perform
void perform(LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
Definition: LoopIterator.h:180
llvm::TargetTransformInfo::~TargetTransformInfo
~TargetTransformInfo()
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:241
llvm::TargetTransformInfo::isSingleThreaded
bool isSingleThreaded() const
Definition: TargetTransformInfo.cpp:276
llvm::TargetTransformInfo::OK_NonUniformConstantValue
@ OK_NonUniformConstantValue
Definition: TargetTransformInfo.h:911
llvm::TargetTransformInfo::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfo.cpp:1038
llvm::TargetTransformInfo::getStoreMinimumVF
unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const
Definition: TargetTransformInfo.cpp:676
llvm::TargetTransformInfo::getRegUsageForType
unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
Definition: TargetTransformInfo.cpp:494
llvm::TargetTransformInfo::useAA
bool useAA() const
Definition: TargetTransformInfo.cpp:488
InitializePasses.h
llvm::HardwareLoopInfo::CountType
IntegerType * CountType
Definition: TargetTransformInfo.h:104
llvm::TargetTransformInfo::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfo.cpp:717
llvm::TargetTransformInfo::getFPOpCost
InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
Definition: TargetTransformInfo.cpp:589
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:219
llvm::ScalarEvolution::getExitCount
const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
Definition: ScalarEvolution.cpp:8222
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:153
llvm::TargetTransformInfo::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfo.cpp:249
llvm::TargetTransformInfo::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: TargetTransformInfo.cpp:353
llvm::TargetTransformInfo::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfo.cpp:996
llvm::FunctionType
Class to represent function types.
Definition: DerivedTypes.h:103
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:39