LLVM 22.0.0git
TargetTransformInfo.cpp
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1//===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
11#include "llvm/Analysis/CFG.h"
15#include "llvm/IR/CFG.h"
16#include "llvm/IR/Dominators.h"
17#include "llvm/IR/Instruction.h"
20#include "llvm/IR/Module.h"
21#include "llvm/IR/Operator.h"
24#include <optional>
25#include <utility>
26
27using namespace llvm;
28using namespace PatternMatch;
29
30#define DEBUG_TYPE "tti"
31
32static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
34 cl::desc("Recognize reduction patterns."));
35
37 "cache-line-size", cl::init(0), cl::Hidden,
38 cl::desc("Use this to override the target cache line size when "
39 "specified by the user."));
40
42 "min-page-size", cl::init(0), cl::Hidden,
43 cl::desc("Use this to override the target's minimum page size."));
44
46 "predictable-branch-threshold", cl::init(99), cl::Hidden,
48 "Use this to override the target's predictable branch threshold (%)."));
49
50namespace {
51/// No-op implementation of the TTI interface using the utility base
52/// classes.
53///
54/// This is used when no target specific information is available.
55struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
56 explicit NoTTIImpl(const DataLayout &DL)
57 : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
58};
59} // namespace
60
62 std::unique_ptr<const TargetTransformInfoImplBase> Impl)
63 : TTIImpl(std::move(Impl)) {}
64
66 // If the loop has irreducible control flow, it can not be converted to
67 // Hardware loop.
68 LoopBlocksRPO RPOT(L);
69 RPOT.perform(&LI);
71 return false;
72 return true;
73}
74
76 Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost,
77 bool TypeBasedOnly, const TargetLibraryInfo *LibInfo)
78 : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
79 ScalarizationCost(ScalarizationCost), LibInfo(LibInfo) {
80
81 if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
82 FMF = FPMO->getFastMathFlags();
83
84 if (!TypeBasedOnly)
85 Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
87 ParamTys.insert(ParamTys.begin(), FTy->param_begin(), FTy->param_end());
88}
89
92 FastMathFlags Flags,
93 const IntrinsicInst *I,
94 InstructionCost ScalarCost)
95 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
96 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
97}
98
101 : RetTy(Ty), IID(Id) {
102
103 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
104 ParamTys.reserve(Arguments.size());
105 for (const Value *Argument : Arguments)
106 ParamTys.push_back(Argument->getType());
107}
108
112 InstructionCost ScalarCost, TargetLibraryInfo const *LibInfo)
113 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost),
114 LibInfo(LibInfo) {
115 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
116 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
117}
118
120 // Match default options:
121 // - hardware-loop-counter-bitwidth = 32
122 // - hardware-loop-decrement = 1
123 CountType = Type::getInt32Ty(L->getHeader()->getContext());
124 LoopDecrement = ConstantInt::get(CountType, 1);
125}
126
128 LoopInfo &LI, DominatorTree &DT,
129 bool ForceNestedLoop,
131 SmallVector<BasicBlock *, 4> ExitingBlocks;
132 L->getExitingBlocks(ExitingBlocks);
133
134 for (BasicBlock *BB : ExitingBlocks) {
135 // If we pass the updated counter back through a phi, we need to know
136 // which latch the updated value will be coming from.
137 if (!L->isLoopLatch(BB)) {
139 continue;
140 }
141
142 const SCEV *EC = SE.getExitCount(L, BB);
144 continue;
145 if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
146 if (ConstEC->getValue()->isZero())
147 continue;
148 } else if (!SE.isLoopInvariant(EC, L))
149 continue;
150
151 if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
152 continue;
153
154 // If this exiting block is contained in a nested loop, it is not eligible
155 // for insertion of the branch-and-decrement since the inner loop would
156 // end up messing up the value in the CTR.
157 if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
158 continue;
159
160 // We now have a loop-invariant count of loop iterations (which is not the
161 // constant zero) for which we know that this loop will not exit via this
162 // existing block.
163
164 // We need to make sure that this block will run on every loop iteration.
165 // For this to be true, we must dominate all blocks with backedges. Such
166 // blocks are in-loop predecessors to the header block.
167 bool NotAlways = false;
168 for (BasicBlock *Pred : predecessors(L->getHeader())) {
169 if (!L->contains(Pred))
170 continue;
171
172 if (!DT.dominates(BB, Pred)) {
173 NotAlways = true;
174 break;
175 }
176 }
177
178 if (NotAlways)
179 continue;
180
181 // Make sure this blocks ends with a conditional branch.
182 Instruction *TI = BB->getTerminator();
183 if (!TI)
184 continue;
185
186 if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
187 if (!BI->isConditional())
188 continue;
189
190 ExitBranch = BI;
191 } else
192 continue;
193
194 // Note that this block may not be the loop latch block, even if the loop
195 // has a latch block.
196 ExitBlock = BB;
197 ExitCount = EC;
198 break;
199 }
200
201 if (!ExitBlock)
202 return false;
203 return true;
204}
205
207 : TTIImpl(std::make_unique<NoTTIImpl>(DL)) {}
208
210
213
215 TTIImpl = std::move(RHS.TTIImpl);
216 return *this;
217}
218
220 return TTIImpl->getInliningThresholdMultiplier();
221}
222
223unsigned
225 return TTIImpl->getInliningCostBenefitAnalysisSavingsMultiplier();
226}
227
228unsigned
230 const {
231 return TTIImpl->getInliningCostBenefitAnalysisProfitableMultiplier();
232}
233
235 return TTIImpl->getInliningLastCallToStaticBonus();
236}
237
238unsigned
240 return TTIImpl->adjustInliningThreshold(CB);
241}
242
244 const AllocaInst *AI) const {
245 return TTIImpl->getCallerAllocaCost(CB, AI);
246}
247
249 return TTIImpl->getInlinerVectorBonusPercent();
250}
251
253 Type *PointeeType, const Value *Ptr, ArrayRef<const Value *> Operands,
254 Type *AccessType, TTI::TargetCostKind CostKind) const {
255 return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, AccessType, CostKind);
256}
257
260 const TTI::PointersChainInfo &Info, Type *AccessTy,
262 assert((Base || !Info.isSameBase()) &&
263 "If pointers have same base address it has to be provided.");
264 return TTIImpl->getPointersChainCost(Ptrs, Base, Info, AccessTy, CostKind);
265}
266
268 const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
269 BlockFrequencyInfo *BFI) const {
270 return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
271}
272
276 enum TargetCostKind CostKind) const {
277 InstructionCost Cost = TTIImpl->getInstructionCost(U, Operands, CostKind);
279 "TTI should not produce negative costs!");
280 return Cost;
281}
282
284 return PredictableBranchThreshold.getNumOccurrences() > 0
286 : TTIImpl->getPredictableBranchThreshold();
287}
288
290 return TTIImpl->getBranchMispredictPenalty();
291}
292
294 return TTIImpl->hasBranchDivergence(F);
295}
296
298 if (const auto *Call = dyn_cast<CallBase>(V)) {
299 if (Call->hasFnAttr(Attribute::NoDivergenceSource))
300 return false;
301 }
302 return TTIImpl->isSourceOfDivergence(V);
303}
304
306 return TTIImpl->isAlwaysUniform(V);
307}
308
310 unsigned ToAS) const {
311 return TTIImpl->isValidAddrSpaceCast(FromAS, ToAS);
312}
313
315 unsigned ToAS) const {
316 return TTIImpl->addrspacesMayAlias(FromAS, ToAS);
317}
318
320 return TTIImpl->getFlatAddressSpace();
321}
322
324 SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
325 return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
326}
327
329 unsigned ToAS) const {
330 return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
331}
332
334 unsigned AS) const {
335 return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
336}
337
339 return TTIImpl->getAssumedAddrSpace(V);
340}
341
343 return TTIImpl->isSingleThreaded();
344}
345
346std::pair<const Value *, unsigned>
348 return TTIImpl->getPredicatedAddrSpace(V);
349}
350
352 IntrinsicInst *II, Value *OldV, Value *NewV) const {
353 return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
354}
355
357 return TTIImpl->isLoweredToCall(F);
358}
359
362 TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
363 return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
364}
365
367 return TTIImpl->getEpilogueVectorizationMinVF();
368}
369
371 TailFoldingInfo *TFI) const {
372 return TTIImpl->preferPredicateOverEpilogue(TFI);
373}
374
376 bool IVUpdateMayOverflow) const {
377 return TTIImpl->getPreferredTailFoldingStyle(IVUpdateMayOverflow);
378}
379
380std::optional<Instruction *>
382 IntrinsicInst &II) const {
383 return TTIImpl->instCombineIntrinsic(IC, II);
384}
385
387 InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
388 bool &KnownBitsComputed) const {
389 return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
390 KnownBitsComputed);
391}
392
394 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
395 APInt &UndefElts2, APInt &UndefElts3,
396 std::function<void(Instruction *, unsigned, APInt, APInt &)>
397 SimplifyAndSetOp) const {
398 return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
399 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
400 SimplifyAndSetOp);
401}
402
405 OptimizationRemarkEmitter *ORE) const {
406 return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
407}
408
410 PeelingPreferences &PP) const {
411 return TTIImpl->getPeelingPreferences(L, SE, PP);
412}
413
415 return TTIImpl->isLegalAddImmediate(Imm);
416}
417
419 return TTIImpl->isLegalAddScalableImmediate(Imm);
420}
421
423 return TTIImpl->isLegalICmpImmediate(Imm);
424}
425
427 int64_t BaseOffset,
428 bool HasBaseReg, int64_t Scale,
429 unsigned AddrSpace,
430 Instruction *I,
431 int64_t ScalableOffset) const {
432 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
433 Scale, AddrSpace, I, ScalableOffset);
434}
435
437 const LSRCost &C2) const {
438 return TTIImpl->isLSRCostLess(C1, C2);
439}
440
442 return TTIImpl->isNumRegsMajorCostOfLSR();
443}
444
446 return TTIImpl->shouldDropLSRSolutionIfLessProfitable();
447}
448
450 return TTIImpl->isProfitableLSRChainElement(I);
451}
452
454 return TTIImpl->canMacroFuseCmp();
455}
456
458 ScalarEvolution *SE, LoopInfo *LI,
460 TargetLibraryInfo *LibInfo) const {
461 return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
462}
463
466 ScalarEvolution *SE) const {
467 return TTIImpl->getPreferredAddressingMode(L, SE);
468}
469
471 unsigned AddressSpace,
472 TTI::MaskKind MaskKind) const {
473 return TTIImpl->isLegalMaskedStore(DataType, Alignment, AddressSpace,
474 MaskKind);
475}
476
478 unsigned AddressSpace,
479 TTI::MaskKind MaskKind) const {
480 return TTIImpl->isLegalMaskedLoad(DataType, Alignment, AddressSpace,
481 MaskKind);
482}
483
485 Align Alignment) const {
486 return TTIImpl->isLegalNTStore(DataType, Alignment);
487}
488
489bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
490 return TTIImpl->isLegalNTLoad(DataType, Alignment);
491}
492
494 ElementCount NumElements) const {
495 return TTIImpl->isLegalBroadcastLoad(ElementTy, NumElements);
496}
497
499 Align Alignment) const {
500 return TTIImpl->isLegalMaskedGather(DataType, Alignment);
501}
502
504 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
505 const SmallBitVector &OpcodeMask) const {
506 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask);
507}
508
510 Align Alignment) const {
511 return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
512}
513
515 Align Alignment) const {
516 return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment);
517}
518
520 Align Alignment) const {
521 return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment);
522}
523
525 Align Alignment) const {
526 return TTIImpl->isLegalMaskedCompressStore(DataType, Alignment);
527}
528
530 Align Alignment) const {
531 return TTIImpl->isLegalMaskedExpandLoad(DataType, Alignment);
532}
533
535 Align Alignment) const {
536 return TTIImpl->isLegalStridedLoadStore(DataType, Alignment);
537}
538
540 VectorType *VTy, unsigned Factor, Align Alignment,
541 unsigned AddrSpace) const {
542 return TTIImpl->isLegalInterleavedAccessType(VTy, Factor, Alignment,
543 AddrSpace);
544}
545
547 Type *DataType) const {
548 return TTIImpl->isLegalMaskedVectorHistogram(AddrType, DataType);
549}
550
552 return TTIImpl->enableOrderedReductions();
553}
554
555bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
556 return TTIImpl->hasDivRemOp(DataType, IsSigned);
557}
558
560 unsigned AddrSpace) const {
561 return TTIImpl->hasVolatileVariant(I, AddrSpace);
562}
563
565 return TTIImpl->prefersVectorizedAddressing();
566}
567
569 Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg,
570 int64_t Scale, unsigned AddrSpace) const {
571 InstructionCost Cost = TTIImpl->getScalingFactorCost(
572 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
573 assert(Cost >= 0 && "TTI should not produce negative costs!");
574 return Cost;
575}
576
578 return TTIImpl->LSRWithInstrQueries();
579}
580
582 return TTIImpl->isTruncateFree(Ty1, Ty2);
583}
584
586 return TTIImpl->isProfitableToHoist(I);
587}
588
589bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
590
592 return TTIImpl->isTypeLegal(Ty);
593}
594
596 return TTIImpl->getRegUsageForType(Ty);
597}
598
600 return TTIImpl->shouldBuildLookupTables();
601}
602
604 Constant *C) const {
605 return TTIImpl->shouldBuildLookupTablesForConstant(C);
606}
607
609 return TTIImpl->shouldBuildRelLookupTables();
610}
611
613 return TTIImpl->useColdCCForColdCall(F);
614}
615
617 return TTIImpl->useFastCCForInternalCall(F);
618}
619
621 Intrinsic::ID ID) const {
622 return TTIImpl->isTargetIntrinsicTriviallyScalarizable(ID);
623}
624
626 Intrinsic::ID ID, unsigned ScalarOpdIdx) const {
627 return TTIImpl->isTargetIntrinsicWithScalarOpAtArg(ID, ScalarOpdIdx);
628}
629
631 Intrinsic::ID ID, int OpdIdx) const {
632 return TTIImpl->isTargetIntrinsicWithOverloadTypeAtArg(ID, OpdIdx);
633}
634
636 Intrinsic::ID ID, int RetIdx) const {
637 return TTIImpl->isTargetIntrinsicWithStructReturnOverloadAtField(ID, RetIdx);
638}
639
641 VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract,
642 TTI::TargetCostKind CostKind, bool ForPoisonSrc,
643 ArrayRef<Value *> VL) const {
644 return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
645 CostKind, ForPoisonSrc, VL);
646}
647
650 return TTIImpl->getOperandsScalarizationOverhead(Tys, CostKind);
651}
652
654 return TTIImpl->supportsEfficientVectorElementLoadStore();
655}
656
658 return TTIImpl->supportsTailCalls();
659}
660
662 return TTIImpl->supportsTailCallFor(CB);
663}
664
666 bool LoopHasReductions) const {
667 return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
668}
669
671TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
672 return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
673}
674
676 return TTIImpl->enableSelectOptimize();
677}
678
680 const Instruction *I) const {
681 return TTIImpl->shouldTreatInstructionLikeSelect(I);
682}
683
685 return TTIImpl->enableInterleavedAccessVectorization();
686}
687
689 return TTIImpl->enableMaskedInterleavedAccessVectorization();
690}
691
693 return TTIImpl->isFPVectorizationPotentiallyUnsafe();
694}
695
696bool
698 unsigned BitWidth,
699 unsigned AddressSpace,
700 Align Alignment,
701 unsigned *Fast) const {
702 return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
703 AddressSpace, Alignment, Fast);
704}
705
707TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
708 return TTIImpl->getPopcntSupport(IntTyWidthInBit);
709}
710
712 return TTIImpl->haveFastSqrt(Ty);
713}
714
716 const Instruction *I) const {
717 return TTIImpl->isExpensiveToSpeculativelyExecute(I);
718}
719
721 return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
722}
723
725 InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
726 assert(Cost >= 0 && "TTI should not produce negative costs!");
727 return Cost;
728}
729
731 unsigned Idx,
732 const APInt &Imm,
733 Type *Ty) const {
734 InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
735 assert(Cost >= 0 && "TTI should not produce negative costs!");
736 return Cost;
737}
738
742 InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
743 assert(Cost >= 0 && "TTI should not produce negative costs!");
744 return Cost;
745}
746
748 unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
751 TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
752 assert(Cost >= 0 && "TTI should not produce negative costs!");
753 return Cost;
754}
755
758 const APInt &Imm, Type *Ty,
761 TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
762 assert(Cost >= 0 && "TTI should not produce negative costs!");
763 return Cost;
764}
765
767 const Instruction &Inst, const Function &Fn) const {
768 return TTIImpl->preferToKeepConstantsAttached(Inst, Fn);
769}
770
771unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
772 return TTIImpl->getNumberOfRegisters(ClassID);
773}
774
776 bool IsStore) const {
777 return TTIImpl->hasConditionalLoadStoreForType(Ty, IsStore);
778}
779
781 Type *Ty) const {
782 return TTIImpl->getRegisterClassForType(Vector, Ty);
783}
784
785const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
786 return TTIImpl->getRegisterClassName(ClassID);
787}
788
791 return TTIImpl->getRegisterBitWidth(K);
792}
793
795 return TTIImpl->getMinVectorRegisterBitWidth();
796}
797
798std::optional<unsigned> TargetTransformInfo::getMaxVScale() const {
799 return TTIImpl->getMaxVScale();
800}
801
802std::optional<unsigned> TargetTransformInfo::getVScaleForTuning() const {
803 return TTIImpl->getVScaleForTuning();
804}
805
807 return TTIImpl->isVScaleKnownToBeAPowerOfTwo();
808}
809
812 return TTIImpl->shouldMaximizeVectorBandwidth(K);
813}
814
816 bool IsScalable) const {
817 return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
818}
819
820unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
821 unsigned Opcode) const {
822 return TTIImpl->getMaximumVF(ElemWidth, Opcode);
823}
824
825unsigned TargetTransformInfo::getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
826 Type *ScalarValTy) const {
827 return TTIImpl->getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy);
828}
829
831 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
832 return TTIImpl->shouldConsiderAddressTypePromotion(
833 I, AllowPromotionWithoutCommonHeader);
834}
835
837 return CacheLineSize.getNumOccurrences() > 0 ? CacheLineSize
838 : TTIImpl->getCacheLineSize();
839}
840
841std::optional<unsigned>
843 return TTIImpl->getCacheSize(Level);
844}
845
846std::optional<unsigned>
848 return TTIImpl->getCacheAssociativity(Level);
849}
850
851std::optional<unsigned> TargetTransformInfo::getMinPageSize() const {
852 return MinPageSize.getNumOccurrences() > 0 ? MinPageSize
853 : TTIImpl->getMinPageSize();
854}
855
857 return TTIImpl->getPrefetchDistance();
858}
859
861 unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
862 unsigned NumPrefetches, bool HasCall) const {
863 return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
864 NumPrefetches, HasCall);
865}
866
868 return TTIImpl->getMaxPrefetchIterationsAhead();
869}
870
872 return TTIImpl->enableWritePrefetching();
873}
874
876 return TTIImpl->shouldPrefetchAddressSpace(AS);
877}
878
880 unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
882 PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
884 return TTIImpl->getPartialReductionCost(Opcode, InputTypeA, InputTypeB,
885 AccumType, VF, OpAExtend, OpBExtend,
886 BinOp, CostKind);
887}
888
890 return TTIImpl->getMaxInterleaveFactor(VF);
891}
892
897
898 // undef/poison don't materialize constants.
899 if (isa<UndefValue>(V))
900 return {OK_AnyValue, OP_None};
901
902 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
903 if (const auto *CI = dyn_cast<ConstantInt>(V)) {
904 if (CI->getValue().isPowerOf2())
905 OpProps = OP_PowerOf2;
906 else if (CI->getValue().isNegatedPowerOf2())
907 OpProps = OP_NegatedPowerOf2;
908 }
909 return {OK_UniformConstantValue, OpProps};
910 }
911
912 // A broadcast shuffle creates a uniform value.
913 // TODO: Add support for non-zero index broadcasts.
914 // TODO: Add support for different source vector width.
915 if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
916 if (ShuffleInst->isZeroEltSplat())
917 OpInfo = OK_UniformValue;
918
919 const Value *Splat = getSplatValue(V);
920
921 // Check for a splat of a constant or for a non uniform vector of constants
922 // and check if the constant(s) are all powers of two.
923 if (Splat) {
924 // Check for a splat of a uniform value. This is not loop aware, so return
925 // true only for the obviously uniform cases (argument, globalvalue)
927 OpInfo = OK_UniformValue;
928 } else if (isa<Constant>(Splat)) {
930 if (auto *CI = dyn_cast<ConstantInt>(Splat)) {
931 if (CI->getValue().isPowerOf2())
932 OpProps = OP_PowerOf2;
933 else if (CI->getValue().isNegatedPowerOf2())
934 OpProps = OP_NegatedPowerOf2;
935 }
936 }
937 } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
939 bool AllPow2 = true, AllNegPow2 = true;
940 for (uint64_t I = 0, E = CDS->getNumElements(); I != E; ++I) {
941 if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I))) {
942 AllPow2 &= CI->getValue().isPowerOf2();
943 AllNegPow2 &= CI->getValue().isNegatedPowerOf2();
944 if (AllPow2 || AllNegPow2)
945 continue;
946 }
947 AllPow2 = AllNegPow2 = false;
948 break;
949 }
950 OpProps = AllPow2 ? OP_PowerOf2 : OpProps;
951 OpProps = AllNegPow2 ? OP_NegatedPowerOf2 : OpProps;
952 } else if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
954 }
955
956 return {OpInfo, OpProps};
957}
958
960 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
961 OperandValueInfo Op1Info, OperandValueInfo Op2Info,
962 ArrayRef<const Value *> Args, const Instruction *CxtI,
963 const TargetLibraryInfo *TLibInfo) const {
964
965 // Use call cost for frem intructions that have platform specific vector math
966 // functions, as those will be replaced with calls later by SelectionDAG or
967 // ReplaceWithVecLib pass.
968 if (TLibInfo && Opcode == Instruction::FRem) {
969 VectorType *VecTy = dyn_cast<VectorType>(Ty);
970 LibFunc Func;
971 if (VecTy &&
972 TLibInfo->getLibFunc(Instruction::FRem, Ty->getScalarType(), Func) &&
973 TLibInfo->isFunctionVectorizable(TLibInfo->getName(Func),
974 VecTy->getElementCount()))
975 return getCallInstrCost(nullptr, VecTy, {VecTy, VecTy}, CostKind);
976 }
977
979 TTIImpl->getArithmeticInstrCost(Opcode, Ty, CostKind,
980 Op1Info, Op2Info,
981 Args, CxtI);
982 assert(Cost >= 0 && "TTI should not produce negative costs!");
983 return Cost;
984}
985
987 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
988 const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const {
990 TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind);
991 assert(Cost >= 0 && "TTI should not produce negative costs!");
992 return Cost;
993}
994
996 ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy, ArrayRef<int> Mask,
997 TTI::TargetCostKind CostKind, int Index, VectorType *SubTp,
998 ArrayRef<const Value *> Args, const Instruction *CxtI) const {
999 assert((Mask.empty() || DstTy->isScalableTy() ||
1000 Mask.size() == DstTy->getElementCount().getKnownMinValue()) &&
1001 "Expected the Mask to match the return size if given");
1002 assert(SrcTy->getScalarType() == DstTy->getScalarType() &&
1003 "Expected the same scalar types");
1004 InstructionCost Cost = TTIImpl->getShuffleCost(
1005 Kind, DstTy, SrcTy, Mask, CostKind, Index, SubTp, Args, CxtI);
1006 assert(Cost >= 0 && "TTI should not produce negative costs!");
1007 return Cost;
1008}
1009
1012 if (auto *Cast = dyn_cast<CastInst>(I))
1013 return getPartialReductionExtendKind(Cast->getOpcode());
1014 return PR_None;
1015}
1016
1019 Instruction::CastOps CastOpc) {
1020 switch (CastOpc) {
1021 case Instruction::CastOps::ZExt:
1022 return PR_ZeroExtend;
1023 case Instruction::CastOps::SExt:
1024 return PR_SignExtend;
1025 default:
1026 return PR_None;
1027 }
1028 llvm_unreachable("Unhandled cast opcode");
1029}
1030
1033 if (!I)
1034 return CastContextHint::None;
1035
1036 auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
1037 unsigned GatScatOp) {
1039 if (!I)
1040 return CastContextHint::None;
1041
1042 if (I->getOpcode() == LdStOp)
1044
1045 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1046 if (II->getIntrinsicID() == MaskedOp)
1048 if (II->getIntrinsicID() == GatScatOp)
1050 }
1051
1053 };
1054
1055 switch (I->getOpcode()) {
1056 case Instruction::ZExt:
1057 case Instruction::SExt:
1058 case Instruction::FPExt:
1059 return getLoadStoreKind(I->getOperand(0), Instruction::Load,
1060 Intrinsic::masked_load, Intrinsic::masked_gather);
1061 case Instruction::Trunc:
1062 case Instruction::FPTrunc:
1063 if (I->hasOneUse())
1064 return getLoadStoreKind(*I->user_begin(), Instruction::Store,
1065 Intrinsic::masked_store,
1066 Intrinsic::masked_scatter);
1067 break;
1068 default:
1069 return CastContextHint::None;
1070 }
1071
1073}
1074
1076 unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
1077 TTI::TargetCostKind CostKind, const Instruction *I) const {
1078 assert((I == nullptr || I->getOpcode() == Opcode) &&
1079 "Opcode should reflect passed instruction.");
1081 TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
1082 assert(Cost >= 0 && "TTI should not produce negative costs!");
1083 return Cost;
1084}
1085
1087 unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index,
1090 TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index, CostKind);
1091 assert(Cost >= 0 && "TTI should not produce negative costs!");
1092 return Cost;
1093}
1094
1096 unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
1097 assert((I == nullptr || I->getOpcode() == Opcode) &&
1098 "Opcode should reflect passed instruction.");
1099 InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
1100 assert(Cost >= 0 && "TTI should not produce negative costs!");
1101 return Cost;
1102}
1103
1105 unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
1107 OperandValueInfo Op2Info, const Instruction *I) const {
1108 assert((I == nullptr || I->getOpcode() == Opcode) &&
1109 "Opcode should reflect passed instruction.");
1110 InstructionCost Cost = TTIImpl->getCmpSelInstrCost(
1111 Opcode, ValTy, CondTy, VecPred, CostKind, Op1Info, Op2Info, I);
1112 assert(Cost >= 0 && "TTI should not produce negative costs!");
1113 return Cost;
1114}
1115
1117 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1118 const Value *Op0, const Value *Op1) const {
1119 assert((Opcode == Instruction::InsertElement ||
1120 Opcode == Instruction::ExtractElement) &&
1121 "Expecting Opcode to be insertelement/extractelement.");
1123 TTIImpl->getVectorInstrCost(Opcode, Val, CostKind, Index, Op0, Op1);
1124 assert(Cost >= 0 && "TTI should not produce negative costs!");
1125 return Cost;
1126}
1127
1129 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1130 Value *Scalar,
1131 ArrayRef<std::tuple<Value *, User *, int>> ScalarUserAndIdx) const {
1132 assert((Opcode == Instruction::InsertElement ||
1133 Opcode == Instruction::ExtractElement) &&
1134 "Expecting Opcode to be insertelement/extractelement.");
1135 InstructionCost Cost = TTIImpl->getVectorInstrCost(
1136 Opcode, Val, CostKind, Index, Scalar, ScalarUserAndIdx);
1137 assert(Cost >= 0 && "TTI should not produce negative costs!");
1138 return Cost;
1139}
1140
1144 unsigned Index) const {
1145 // FIXME: Assert that Opcode is either InsertElement or ExtractElement.
1146 // This is mentioned in the interface description and respected by all
1147 // callers, but never asserted upon.
1148 InstructionCost Cost = TTIImpl->getVectorInstrCost(I, Val, CostKind, Index);
1149 assert(Cost >= 0 && "TTI should not produce negative costs!");
1150 return Cost;
1151}
1152
1154 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind,
1155 unsigned Index) const {
1157 TTIImpl->getIndexedVectorInstrCostFromEnd(Opcode, Val, CostKind, Index);
1158 assert(Cost >= 0 && "TTI should not produce negative costs!");
1159 return Cost;
1160}
1161
1163 unsigned Opcode, TTI::TargetCostKind CostKind) const {
1164 assert((Opcode == Instruction::InsertValue ||
1165 Opcode == Instruction::ExtractValue) &&
1166 "Expecting Opcode to be insertvalue/extractvalue.");
1167 InstructionCost Cost = TTIImpl->getInsertExtractValueCost(Opcode, CostKind);
1168 assert(Cost >= 0 && "TTI should not produce negative costs!");
1169 return Cost;
1170}
1171
1173 Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts,
1175 InstructionCost Cost = TTIImpl->getReplicationShuffleCost(
1176 EltTy, ReplicationFactor, VF, DemandedDstElts, CostKind);
1177 assert(Cost >= 0 && "TTI should not produce negative costs!");
1178 return Cost;
1179}
1180
1182 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1184 const Instruction *I) const {
1185 assert((I == nullptr || I->getOpcode() == Opcode) &&
1186 "Opcode should reflect passed instruction.");
1187 InstructionCost Cost = TTIImpl->getMemoryOpCost(
1188 Opcode, Src, Alignment, AddressSpace, CostKind, OpInfo, I);
1189 assert(Cost >= 0 && "TTI should not produce negative costs!");
1190 return Cost;
1191}
1192
1194 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
1195 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
1196 bool UseMaskForCond, bool UseMaskForGaps) const {
1197 InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
1198 Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
1199 UseMaskForCond, UseMaskForGaps);
1200 assert(Cost >= 0 && "TTI should not produce negative costs!");
1201 return Cost;
1202}
1203
1207 InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
1208 assert(Cost >= 0 && "TTI should not produce negative costs!");
1209 return Cost;
1210}
1211
1213 const MemIntrinsicCostAttributes &MICA,
1215 InstructionCost Cost = TTIImpl->getMemIntrinsicInstrCost(MICA, CostKind);
1216 assert(Cost >= 0 && "TTI should not produce negative costs!");
1217 return Cost;
1218}
1219
1222 ArrayRef<Type *> Tys,
1224 InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
1225 assert(Cost >= 0 && "TTI should not produce negative costs!");
1226 return Cost;
1227}
1228
1230 return TTIImpl->getNumberOfParts(Tp);
1231}
1232
1234 Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr,
1237 TTIImpl->getAddressComputationCost(PtrTy, SE, Ptr, CostKind);
1238 assert(Cost >= 0 && "TTI should not produce negative costs!");
1239 return Cost;
1240}
1241
1243 InstructionCost Cost = TTIImpl->getMemcpyCost(I);
1244 assert(Cost >= 0 && "TTI should not produce negative costs!");
1245 return Cost;
1246}
1247
1249 return TTIImpl->getMaxMemIntrinsicInlineSizeThreshold();
1250}
1251
1253 unsigned Opcode, VectorType *Ty, std::optional<FastMathFlags> FMF,
1256 TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
1257 assert(Cost >= 0 && "TTI should not produce negative costs!");
1258 return Cost;
1259}
1260
1265 TTIImpl->getMinMaxReductionCost(IID, Ty, FMF, CostKind);
1266 assert(Cost >= 0 && "TTI should not produce negative costs!");
1267 return Cost;
1268}
1269
1271 unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1272 std::optional<FastMathFlags> FMF, TTI::TargetCostKind CostKind) const {
1273 return TTIImpl->getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
1274 CostKind);
1275}
1276
1278 bool IsUnsigned, unsigned RedOpcode, Type *ResTy, VectorType *Ty,
1280 return TTIImpl->getMulAccReductionCost(IsUnsigned, RedOpcode, ResTy, Ty,
1281 CostKind);
1282}
1283
1286 return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
1287}
1288
1290 MemIntrinsicInfo &Info) const {
1291 return TTIImpl->getTgtMemIntrinsic(Inst, Info);
1292}
1293
1295 return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
1296}
1297
1299 IntrinsicInst *Inst, Type *ExpectedType, bool CanCreate) const {
1300 return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType,
1301 CanCreate);
1302}
1303
1305 LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
1306 unsigned DestAddrSpace, Align SrcAlign, Align DestAlign,
1307 std::optional<uint32_t> AtomicElementSize) const {
1308 return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
1309 DestAddrSpace, SrcAlign, DestAlign,
1310 AtomicElementSize);
1311}
1312
1314 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
1315 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1316 Align SrcAlign, Align DestAlign,
1317 std::optional<uint32_t> AtomicCpySize) const {
1318 TTIImpl->getMemcpyLoopResidualLoweringType(
1319 OpsOut, Context, RemainingBytes, SrcAddrSpace, DestAddrSpace, SrcAlign,
1320 DestAlign, AtomicCpySize);
1321}
1322
1324 const Function *Callee) const {
1325 return TTIImpl->areInlineCompatible(Caller, Callee);
1326}
1327
1328unsigned
1330 const CallBase &Call,
1331 unsigned DefaultCallPenalty) const {
1332 return TTIImpl->getInlineCallPenalty(F, Call, DefaultCallPenalty);
1333}
1334
1336 const Function *Callee,
1337 ArrayRef<Type *> Types) const {
1338 return TTIImpl->areTypesABICompatible(Caller, Callee, Types);
1339}
1340
1342 Type *Ty) const {
1343 return TTIImpl->isIndexedLoadLegal(Mode, Ty);
1344}
1345
1347 Type *Ty) const {
1348 return TTIImpl->isIndexedStoreLegal(Mode, Ty);
1349}
1350
1352 return TTIImpl->getLoadStoreVecRegBitWidth(AS);
1353}
1354
1356 return TTIImpl->isLegalToVectorizeLoad(LI);
1357}
1358
1360 return TTIImpl->isLegalToVectorizeStore(SI);
1361}
1362
1364 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1365 return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1366 AddrSpace);
1367}
1368
1370 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1371 return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1372 AddrSpace);
1373}
1374
1376 const RecurrenceDescriptor &RdxDesc, ElementCount VF) const {
1377 return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1378}
1379
1381 return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1382}
1383
1385 unsigned LoadSize,
1386 unsigned ChainSizeInBytes,
1387 VectorType *VecTy) const {
1388 return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1389}
1390
1392 unsigned StoreSize,
1393 unsigned ChainSizeInBytes,
1394 VectorType *VecTy) const {
1395 return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1396}
1397
1399 bool IsEpilogue) const {
1400 return TTIImpl->preferFixedOverScalableIfEqualCost(IsEpilogue);
1401}
1402
1404 Type *Ty) const {
1405 return TTIImpl->preferInLoopReduction(Kind, Ty);
1406}
1407
1409 return TTIImpl->preferAlternateOpcodeVectorization();
1410}
1411
1413 return TTIImpl->preferPredicatedReductionSelect();
1414}
1415
1417 return TTIImpl->preferEpilogueVectorization();
1418}
1419
1421 return TTIImpl->shouldConsiderVectorizationRegPressure();
1422}
1423
1426 return TTIImpl->getVPLegalizationStrategy(VPI);
1427}
1428
1430 return TTIImpl->hasArmWideBranch(Thumb);
1431}
1432
1434 return TTIImpl->getFeatureMask(F);
1435}
1436
1438 return TTIImpl->isMultiversionedFunction(F);
1439}
1440
1442 return TTIImpl->getMaxNumArgs();
1443}
1444
1446 return TTIImpl->shouldExpandReduction(II);
1447}
1448
1451 const IntrinsicInst *II) const {
1452 return TTIImpl->getPreferredExpandedReductionShuffle(II);
1453}
1454
1456 return TTIImpl->getGISelRematGlobalCost();
1457}
1458
1460 return TTIImpl->getMinTripCountTailFoldingThreshold();
1461}
1462
1464 return TTIImpl->supportsScalableVectors();
1465}
1466
1468 return TTIImpl->enableScalableVectorization();
1469}
1470
1472 return TTIImpl->hasActiveVectorLength();
1473}
1474
1476 Instruction *I, SmallVectorImpl<Use *> &OpsToSink) const {
1477 return TTIImpl->isProfitableToSinkOperands(I, OpsToSink);
1478}
1479
1481 return TTIImpl->isVectorShiftByScalarCheap(Ty);
1482}
1483
1484unsigned
1486 Type *ArrayType) const {
1487 return TTIImpl->getNumBytesToPadGlobalArray(Size, ArrayType);
1488}
1489
1491 const Function &F,
1492 SmallVectorImpl<std::pair<StringRef, int64_t>> &LB) const {
1493 return TTIImpl->collectKernelLaunchBounds(F, LB);
1494}
1495
1497 return TTIImpl->allowVectorElementIndexingUsingGEP();
1498}
1499
1501
1502TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1503
1505 std::function<Result(const Function &)> TTICallback)
1506 : TTICallback(std::move(TTICallback)) {}
1507
1510 assert(!F.isIntrinsic() && "Should not request TTI for intrinsics");
1511 return TTICallback(F);
1512}
1513
1514AnalysisKey TargetIRAnalysis::Key;
1515
1516TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1517 return Result(F.getDataLayout());
1518}
1519
1520// Register the basic pass.
1522 "Target Transform Information", false, true)
1524
1525void TargetTransformInfoWrapperPass::anchor() {}
1526
1529
1533
1535 FunctionAnalysisManager DummyFAM;
1536 TTI = TIRA.run(F, DummyFAM);
1537 return *TTI;
1538}
1539
for(const MachineOperand &MO :llvm::drop_begin(OldMI.operands(), Desc.getNumOperands()))
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static cl::opt< OutputCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(OutputCostKind::RecipThroughput), cl::values(clEnumValN(OutputCostKind::RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(OutputCostKind::Latency, "latency", "Instruction latency"), clEnumValN(OutputCostKind::CodeSize, "code-size", "Code size"), clEnumValN(OutputCostKind::SizeAndLatency, "size-latency", "Code size and latency"), clEnumValN(OutputCostKind::All, "all", "Print all cost kinds")))
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
Module.h This file contains the declarations for the Module class.
#define F(x, y, z)
Definition MD5.cpp:54
#define I(x, y, z)
Definition MD5.cpp:57
uint64_t IntrinsicInst * II
if(PassOpts->AAPipeline)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
This file defines the SmallVector class.
static SymbolRef::Type getType(const Symbol *Sym)
Definition TapiFile.cpp:39
This file provides helpers for the implementation of a TargetTransformInfo-conforming class.
static cl::opt< unsigned > PredictableBranchThreshold("predictable-branch-threshold", cl::init(99), cl::Hidden, cl::desc("Use this to override the target's predictable branch threshold (%)."))
static cl::opt< bool > EnableReduxCost("costmodel-reduxcost", cl::init(false), cl::Hidden, cl::desc("Recognize reduction patterns."))
static cl::opt< unsigned > MinPageSize("min-page-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target's minimum page size."))
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
This pass exposes codegen information to IR-level passes.
Class for arbitrary precision integers.
Definition APInt.h:78
an instruction to allocate memory on the stack
This class represents an incoming formal argument to a Function.
Definition Argument.h:32
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
iterator end() const
Definition ArrayRef.h:131
iterator begin() const
Definition ArrayRef.h:130
Class to represent array types.
A cache of @llvm.assume calls within a function.
LLVM Basic Block Representation.
Definition BasicBlock.h:62
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Conditional or Unconditional Branch instruction.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation or the function signa...
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition InstrTypes.h:676
This is an important base class in LLVM.
Definition Constant.h:43
A parsed version of the target data layout string in and methods for querying it.
Definition DataLayout.h:63
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition Dominators.h:164
LLVM_ABI bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Convenience struct for specifying and reasoning about fast-math flags.
Definition FMF.h:22
Class to represent function types.
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition Function.h:209
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition Pass.h:285
ImmutablePass(char &pid)
Definition Pass.h:287
The core instruction combiner logic.
LLVM_ABI IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false, TargetLibraryInfo const *LibInfo=nullptr)
A wrapper class for inspecting calls to intrinsic functions.
This is an important class for using LLVM in a threaded context.
Definition LLVMContext.h:68
An instruction for reading from memory.
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
void perform(const LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Represents a single loop in the control flow graph.
Definition LoopInfo.h:40
Information for memory intrinsic cost model.
The optimization diagnostic interface.
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
This class represents a constant integer value.
This class represents an analyzed expression in the program.
The main scalar evolution driver.
LLVM_ABI uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
LLVM_ABI bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
LLVM_ABI const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
Definition TypeSize.h:30
An instruction for storing to memory.
Multiway switch.
Analysis pass providing the TargetTransformInfo.
LLVM_ABI Result run(const Function &F, FunctionAnalysisManager &)
LLVM_ABI TargetIRAnalysis()
Default construct a target IR analysis.
Provides information about what library functions are available for the current target.
bool getLibFunc(StringRef funcName, LibFunc &F) const
Searches for a particular function name.
StringRef getName(LibFunc F) const
bool isFunctionVectorizable(StringRef F, const ElementCount &VF) const
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Wrapper pass for TargetTransformInfo.
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
TargetTransformInfo & getTTI(const Function &F)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
LLVM_ABI bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
LLVM_ABI Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType, bool CanCreate=true) const
LLVM_ABI bool isLegalToVectorizeLoad(LoadInst *LI) const
LLVM_ABI std::optional< unsigned > getVScaleForTuning() const
static LLVM_ABI CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
LLVM_ABI unsigned getMaxNumArgs() const
LLVM_ABI bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const
Return false if a AS0 address cannot possibly alias a AS1 address.
LLVM_ABI bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
LLVM_ABI bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
LLVM_ABI bool isLegalToVectorizeStore(StoreInst *SI) const
LLVM_ABI InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index=-1, const Value *Op0=nullptr, const Value *Op1=nullptr) const
LLVM_ABI InstructionCost getMulAccReductionCost(bool IsUnsigned, unsigned RedOpcode, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add/...
LLVM_ABI bool areTypesABICompatible(const Function *Caller, const Function *Callee, ArrayRef< Type * > Types) const
LLVM_ABI bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
LLVM_ABI InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind, bool ForPoisonSrc=true, ArrayRef< Value * > VL={}) const
Estimate the overhead of scalarizing an instruction.
LLVM_ABI bool isMultiversionedFunction(const Function &F) const
Returns true if this is an instance of a function with multiple versions.
LLVM_ABI bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
LLVM_ABI bool isLegalMaskedStore(Type *DataType, Align Alignment, unsigned AddressSpace, MaskKind MaskKind=VariableOrConstantMask) const
Return true if the target supports masked store.
LLVM_ABI bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
LLVM_ABI bool isAlwaysUniform(const Value *V) const
LLVM_ABI unsigned getAssumedAddrSpace(const Value *V) const
LLVM_ABI bool preferAlternateOpcodeVectorization() const
LLVM_ABI bool shouldDropLSRSolutionIfLessProfitable() const
Return true if LSR should drop a found solution if it's calculated to be less profitable than the bas...
LLVM_ABI bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C2.
LLVM_ABI unsigned getPrefetchDistance() const
LLVM_ABI Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicElementSize=std::nullopt) const
LLVM_ABI bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked expand load.
LLVM_ABI bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
LLVM_ABI InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueInfo Op1Info={OK_AnyValue, OP_None}, OperandValueInfo Op2Info={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
LLVM_ABI bool hasBranchDivergence(const Function *F=nullptr) const
Return true if branch divergence exists.
LLVM_ABI MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
LLVM_ABI void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
LLVM_ABI bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
LLVM_ABI bool supportsTailCallFor(const CallBase *CB) const
If target supports tail call on CB.
LLVM_ABI std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
LLVM_ABI bool isProfitableLSRChainElement(Instruction *I) const
LLVM_ABI TypeSize getRegisterBitWidth(RegisterKind K) const
MaskKind
Some targets only support masked load/store with a constant mask.
LLVM_ABI unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
Returns a penalty for invoking call Call in F.
LLVM_ABI bool hasActiveVectorLength() const
LLVM_ABI bool isExpensiveToSpeculativelyExecute(const Instruction *I) const
Return true if the cost of the instruction is too high to speculatively execute and should be kept be...
LLVM_ABI bool preferFixedOverScalableIfEqualCost(bool IsEpilogue) const
LLVM_ABI bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
LLVM_ABI InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueInfo OpdInfo={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
LLVM_ABI std::optional< unsigned > getMaxVScale() const
LLVM_ABI InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind) const
LLVM_ABI bool allowVectorElementIndexingUsingGEP() const
Returns true if GEP should not be used to index into vectors for this target.
LLVM_ABI InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
LLVM_ABI bool isSingleThreaded() const
LLVM_ABI std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
LLVM_ABI bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
LLVM_ABI unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const
LLVM_ABI InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy, ArrayRef< int > Mask={}, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, int Index=0, VectorType *SubTp=nullptr, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr) const
LLVM_ABI InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
LLVM_ABI InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of vector reduction intrinsics.
LLVM_ABI unsigned getAtomicMemIntrinsicMaxElementSize() const
LLVM_ABI InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
LLVM_ABI bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
LLVM_ABI unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
LLVM_ABI VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
static LLVM_ABI PartialReductionExtendKind getPartialReductionExtendKind(Instruction *I)
Get the kind of extension that an instruction represents.
LLVM_ABI bool shouldConsiderVectorizationRegPressure() const
LLVM_ABI bool enableWritePrefetching() const
LLVM_ABI bool shouldTreatInstructionLikeSelect(const Instruction *I) const
Should the Select Optimization pass treat the given instruction like a select, potentially converting...
LLVM_ABI bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
LLVM_ABI bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
LLVM_ABI TailFoldingStyle getPreferredTailFoldingStyle(bool IVUpdateMayOverflow=true) const
Query the target what the preferred style of tail folding is.
LLVM_ABI InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType=nullptr, TargetCostKind CostKind=TCK_SizeAndLatency) const
Estimate the cost of a GEP operation when lowered.
LLVM_ABI bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace) const
Return true is the target supports interleaved access for the given vector type VTy,...
LLVM_ABI unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
LLVM_ABI bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy...
LLVM_ABI bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
LLVM_ABI std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
LLVM_ABI InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduc...
LLVM_ABI unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
LLVM_ABI ReductionShuffle getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const
static LLVM_ABI OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
LLVM_ABI unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
LLVM_ABI bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr, int64_t ScalableOffset=0) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
LLVM_ABI PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
LLVM_ABI unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
LLVM_ABI bool isElementTypeLegalForScalableVector(Type *Ty) const
LLVM_ABI bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
LLVM_ABI unsigned getMaxPrefetchIterationsAhead() const
LLVM_ABI bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
LLVM_ABI ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
LLVM_ABI InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
LLVM_ABI bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
LLVM_ABI InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
LLVM_ABI bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const
Return true if the target supports strided load.
LLVM_ABI TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
LLVM_ABI InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF=FastMathFlags(), TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
TargetCostKind
The kind of cost model.
@ TCK_RecipThroughput
Reciprocal throughput.
LLVM_ABI InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr, const TargetLibraryInfo *TLibInfo=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
LLVM_ABI bool enableSelectOptimize() const
Should the Select Optimization pass be enabled and ran.
LLVM_ABI bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
OperandValueProperties
Additional properties of an operand's values.
LLVM_ABI int getInliningLastCallToStaticBonus() const
LLVM_ABI InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const PointersChainInfo &Info, Type *AccessTy, TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Estimate the cost of a chain of pointers (typically pointer operands of a chain of loads or stores wi...
LLVM_ABI bool isVScaleKnownToBeAPowerOfTwo() const
LLVM_ABI bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
LLVM_ABI unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
LLVM_ABI bool isSourceOfDivergence(const Value *V) const
Returns whether V is a source of divergence.
LLVM_ABI bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
LLVM_ABI bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
LLVM_ABI bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
LLVM_ABI std::optional< unsigned > getCacheAssociativity(CacheLevel Level) const
LLVM_ABI bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
LLVM_ABI InstructionCost getMemcpyCost(const Instruction *I) const
LLVM_ABI unsigned adjustInliningThreshold(const CallBase *CB) const
LLVM_ABI bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
LLVM_ABI bool isTargetIntrinsicWithStructReturnOverloadAtField(Intrinsic::ID ID, int RetIdx) const
Identifies if the vector form of the intrinsic that returns a struct is overloaded at the struct elem...
LLVM_ABI unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
LLVM_ABI InstructionCost getMemIntrinsicInstrCost(const MemIntrinsicCostAttributes &MICA, TTI::TargetCostKind CostKind) const
LLVM_ABI bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
LLVM_ABI bool isTargetIntrinsicTriviallyScalarizable(Intrinsic::ID ID) const
LLVM_ABI Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
LLVM_ABI InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
LLVM_ABI unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
LLVM_ABI bool shouldPrefetchAddressSpace(unsigned AS) const
LLVM_ABI InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
LLVM_ABI unsigned getMinVectorRegisterBitWidth() const
LLVM_ABI InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr, TTI::TargetCostKind CostKind) const
LLVM_ABI bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
LLVM_ABI InstructionCost getPartialReductionCost(unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType, ElementCount VF, PartialReductionExtendKind OpAExtend, PartialReductionExtendKind OpBExtend, std::optional< unsigned > BinOp, TTI::TargetCostKind CostKind) const
LLVM_ABI unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
LLVM_ABI bool preferToKeepConstantsAttached(const Instruction &Inst, const Function &Fn) const
It can be advantageous to detach complex constants from their uses to make their generation cheaper.
LLVM_ABI bool hasArmWideBranch(bool Thumb) const
LLVM_ABI const char * getRegisterClassName(unsigned ClassID) const
LLVM_ABI bool preferEpilogueVectorization() const
Return true if the loop vectorizer should consider vectorizing an otherwise scalar epilogue loop.
LLVM_ABI bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
LLVM_ABI BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
LLVM_ABI TargetTransformInfo(std::unique_ptr< const TargetTransformInfoImplBase > Impl)
Construct a TTI object using a type implementing the Concept API below.
LLVM_ABI bool preferInLoopReduction(RecurKind Kind, Type *Ty) const
LLVM_ABI unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const
LLVM_ABI bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const
LLVM_ABI unsigned getCacheLineSize() const
LLVM_ABI bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), unsigned *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
LLVM_ABI int getInlinerVectorBonusPercent() const
LLVM_ABI unsigned getEpilogueVectorizationMinVF() const
LLVM_ABI void collectKernelLaunchBounds(const Function &F, SmallVectorImpl< std::pair< StringRef, int64_t > > &LB) const
Collect kernel launch bounds for F into LB.
PopcntSupportKind
Flags indicating the kind of support for population count.
LLVM_ABI bool preferPredicatedReductionSelect() const
LLVM_ABI InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
LLVM_ABI AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
LLVM_ABI bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
LLVM_ABI bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
LLVM_ABI unsigned getInliningThresholdMultiplier() const
LLVM_ABI InstructionCost getBranchMispredictPenalty() const
Returns estimated penalty of a branch misprediction in latency.
LLVM_ABI unsigned getNumberOfRegisters(unsigned ClassID) const
LLVM_ABI bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
Return true if this is an alternating opcode pattern that can be lowered to a single instruction on t...
LLVM_ABI bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
LLVM_ABI bool supportsScalableVectors() const
LLVM_ABI bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
LLVM_ABI bool isLegalMaskedCompressStore(Type *DataType, Align Alignment) const
Return true if the target supports masked compress store.
LLVM_ABI std::optional< unsigned > getMinPageSize() const
LLVM_ABI bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
LLVM_ABI InstructionCost getInsertExtractValueCost(unsigned Opcode, TTI::TargetCostKind CostKind) const
LLVM_ABI bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
LLVM_ABI unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const
LLVM_ABI std::optional< unsigned > getCacheSize(CacheLevel Level) const
LLVM_ABI std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
LLVM_ABI bool isLegalAddScalableImmediate(int64_t Imm) const
Return true if adding the specified scalable immediate is legal, that is the target has add instructi...
LLVM_ABI bool isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, unsigned ScalarOpdIdx) const
Identifies if the vector form of the intrinsic has a scalar operand.
LLVM_ABI bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
LLVM_ABI InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Returns the cost estimation for alternating opcode pattern that can be lowered to a single instructio...
LLVM_ABI bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
LLVM_ABI unsigned getMinTripCountTailFoldingThreshold() const
LLVM_ABI InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
LLVM_ABI unsigned getMaxInterleaveFactor(ElementCount VF) const
LLVM_ABI bool enableScalableVectorization() const
LLVM_ABI bool useFastCCForInternalCall(Function &F) const
Return true if the input function is internal, should use fastcc calling convention.
LLVM_ABI bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
LLVM_ABI bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
LLVM_ABI unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const
LLVM_ABI bool isLegalMaskedVectorHistogram(Type *AddrType, Type *DataType) const
LLVM_ABI unsigned getGISelRematGlobalCost() const
LLVM_ABI unsigned getNumBytesToPadGlobalArray(unsigned Size, Type *ArrayType) const
MemIndexedMode
The type of load/store indexing.
LLVM_ABI bool isLegalMaskedLoad(Type *DataType, Align Alignment, unsigned AddressSpace, MaskKind MaskKind=VariableOrConstantMask) const
Return true if the target supports masked load.
LLVM_ABI InstructionCost getIndexedVectorInstrCostFromEnd(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index) const
LLVM_ABI bool areInlineCompatible(const Function *Caller, const Function *Callee) const
LLVM_ABI bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
LLVM_ABI InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
LLVM_ABI bool supportsTailCalls() const
If the target supports tail calls.
LLVM_ABI bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
LLVM_ABI bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Query the target whether the specified address space cast from FromAS to ToAS is valid.
LLVM_ABI unsigned getNumberOfParts(Type *Tp) const
LLVM_ABI InstructionCost getOperandsScalarizationOverhead(ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
Estimate the overhead of scalarizing operands with the given types.
AddressingModeKind
Which addressing mode Loop Strength Reduction will try to generate.
LLVM_ABI InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
LLVM_ABI bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
LLVM_ABI bool isProfitableToSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const
Return true if sinking I's operands to the same basic block as I is profitable, e....
LLVM_ABI void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicCpySize=std::nullopt) const
LLVM_ABI bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const
Query the target whether it would be prefered to create a predicated vector loop, which can avoid the...
LLVM_ABI bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
LLVM_ABI bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, int OpdIdx) const
Identifies if the vector form of the intrinsic is overloaded on the type of the operand at index OpdI...
LLVM_ABI bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
LLVM_ABI bool shouldExpandReduction(const IntrinsicInst *II) const
LLVM_ABI uint64_t getMaxMemIntrinsicInlineSizeThreshold() const
Returns the maximum memset / memcpy size in bytes that still makes it profitable to inline the call.
ShuffleKind
The various kinds of shuffle patterns for vector queries.
LLVM_ABI APInt getFeatureMask(const Function &F) const
Returns a bitmask constructed from the target-features or fmv-features metadata of a function.
LLVM_ABI void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
LLVM_ABI InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency) const
LLVM_ABI InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
CastContextHint
Represents a hint about the context in which a cast is used.
@ Masked
The cast is used with a masked load/store.
@ None
The cast is not used with a load/store of any kind.
@ Normal
The cast is used with a normal load/store.
@ GatherScatter
The cast is used with a gather/scatter.
LLVM_ABI InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index, TTI::TargetCostKind CostKind) const
OperandValueKind
Additional information about an operand's possible values.
CacheLevel
The possible cache levels.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:45
LLVM_ABI bool isScalableTy(SmallPtrSetImpl< const Type * > &Visited) const
Return true if this is a type whose size is a known multiple of vscale.
Definition Type.cpp:61
static LLVM_ABI IntegerType * getInt32Ty(LLVMContext &C)
Definition Type.cpp:296
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition Type.h:352
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Definition Value.h:75
Type * getType() const
All values are typed, get the type of this value.
Definition Value.h:256
Base class of all SIMD vector types.
ElementCount getElementCount() const
Return an ElementCount instance to represent the (possibly scalable) number of elements in the vector...
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition TypeSize.h:165
CallInst * Call
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition CallingConv.h:34
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
@ Length
Definition DWP.cpp:532
InstructionCost Cost
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:643
LLVM_ABI Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
bool containsIrreducibleCFG(RPOTraversalT &RPOTraversal, const LoopInfoT &LI)
Return true if the control flow in RPOTraversal is irreducible.
Definition CFG.h:149
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
Definition Casting.h:547
LLVM_ABI ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
RecurKind
These are the kinds of recurrences that we support.
constexpr unsigned BitWidth
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1867
auto predecessors(const MachineBasicBlock *BB)
AnalysisManager< Function > FunctionAnalysisManager
Convenience typedef for the Function analysis manager.
Implement std::hash so that hash_code can be used in STL containers.
Definition BitVector.h:867
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition Analysis.h:29
Attributes of a target dependent hardware loop.
LLVM_ABI bool canAnalyze(LoopInfo &LI)
LLVM_ABI bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Information about a load/store intrinsic defined by the target.
Returns options for expansion of memcmp. IsZeroCmp is.
Describe known properties for a set of pointers.
Parameters that control the generic loop unrolling transformation.