This file implements the targeting of the Machinelegalizer class for AMDGPU. More...

#include "AMDGPULegalizerInfo.h"
#include "AMDGPU.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUTargetMachine.h"
#include "SIMachineFunctionInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/ADT/ScopeExit.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/IntrinsicsR600.h"

Macros
#define	DEBUG_TYPE "amdgpu-legalinfo"

Functions
static LLT	getPow2VectorType (LLT Ty)

static LLT	getPow2ScalarType (LLT Ty)

static LegalityPredicate	isSmallOddVector (unsigned TypeIdx)

static LegalityPredicate	sizeIsMultipleOf32 (unsigned TypeIdx)

static LegalityPredicate	isWideVec16 (unsigned TypeIdx)

static LegalizeMutation	oneMoreElement (unsigned TypeIdx)

static LegalizeMutation	fewerEltsToSize64Vector (unsigned TypeIdx)

static LegalizeMutation	moreEltsToNext32Bit (unsigned TypeIdx)

static LegalizeMutation	moreElementsToNextExistingRegClass (unsigned TypeIdx)

static LLT	getBufferRsrcScalarType (const LLT Ty)

static LLT	getBufferRsrcRegisterType (const LLT Ty)

static LLT	getBitcastRegisterType (const LLT Ty)

static LegalizeMutation	bitcastToRegisterType (unsigned TypeIdx)

static LegalizeMutation	bitcastToVectorElement32 (unsigned TypeIdx)

static LegalityPredicate	vectorSmallerThan (unsigned TypeIdx, unsigned Size)

static LegalityPredicate	vectorWiderThan (unsigned TypeIdx, unsigned Size)

static LegalityPredicate	numElementsNotEven (unsigned TypeIdx)

static bool	isRegisterSize (unsigned Size)

static bool	isRegisterVectorElementType (LLT EltTy)

static bool	isRegisterVectorType (LLT Ty)

static bool	isRegisterType (LLT Ty)

static LegalityPredicate	isRegisterType (unsigned TypeIdx)

static LegalityPredicate	isIllegalRegisterType (unsigned TypeIdx)

static LegalityPredicate	elementTypeIsLegal (unsigned TypeIdx)

static LegalityPredicate	isWideScalarExtLoadTruncStore (unsigned TypeIdx)

static unsigned	maxSizeForAddrSpace (const GCNSubtarget &ST, unsigned AS, bool IsLoad, bool IsAtomic)

static bool	isLoadStoreSizeLegal (const GCNSubtarget &ST, const LegalityQuery &Query)

static bool	hasBufferRsrcWorkaround (const LLT Ty)

static bool	loadStoreBitcastWorkaround (const LLT Ty)

static bool	isLoadStoreLegal (const GCNSubtarget &ST, const LegalityQuery &Query)

static bool	shouldBitcastLoadStoreType (const GCNSubtarget &ST, const LLT Ty, const LLT MemTy)
	Return true if a load or store of the type should be lowered with a bitcast to a different type.

static bool	shouldWidenLoad (const GCNSubtarget &ST, LLT MemoryTy, uint64_t AlignInBits, unsigned AddrSpace, unsigned Opcode)
	Return true if we should legalize a load by widening an odd sized memory access up to the alignment.

static bool	shouldWidenLoad (const GCNSubtarget &ST, const LegalityQuery &Query, unsigned Opcode)

static LLT	castBufferRsrcFromV4I32 (MachineInstr &MI, MachineIRBuilder &B, MachineRegisterInfo &MRI, unsigned Idx)
	Mutates IR (typicaly a load instruction) to use a <4 x s32> as the initial type of the operand `idx` and then to transform it to a `p8` via bitcasts and inttoptr.

static Register	castBufferRsrcToV4I32 (Register Pointer, MachineIRBuilder &B)
	Cast a buffer resource (an address space 8 pointer) into a 4xi32, which is the form in which the value must be in order to be passed to the low-level representations used for MUBUF/MTBUF intrinsics.

static void	castBufferRsrcArgToV4I32 (MachineInstr &MI, MachineIRBuilder &B, unsigned Idx)

static bool	isKnownNonNull (Register Val, MachineRegisterInfo &MRI, const AMDGPUTargetMachine &TM, unsigned AddrSpace)
	Return true if the value is a known valid address, such that a null check is not necessary.

static MachineInstrBuilder	extractF64Exponent (Register Hi, MachineIRBuilder &B)

static LLT	widenToNextPowerOf2 (LLT Ty)

static bool	valueIsKnownNeverF32Denorm (const MachineRegisterInfo &MRI, Register Src)
	Return true if it's known that `Src` can never be an f32 denormal value.

static bool	allowApproxFunc (const MachineFunction &MF, unsigned Flags)

static bool	needsDenormHandlingF32 (const MachineFunction &MF, Register Src, unsigned Flags)

static Register	getMad (MachineIRBuilder &B, LLT Ty, Register X, Register Y, Register Z, unsigned Flags)

static Register	stripAnySourceMods (Register OrigSrc, MachineRegisterInfo &MRI)

static bool	isNot (const MachineRegisterInfo &MRI, const MachineInstr &MI)

static MachineInstr *	verifyCFIntrinsic (MachineInstr &MI, MachineRegisterInfo &MRI, MachineInstr &Br, MachineBasicBlock &UncondBrTarget, bool &Negated)

static bool	replaceWithConstant (MachineIRBuilder &B, MachineInstr &MI, int64_t C)

static std::pair< Register, Register >	emitReciprocalU64 (MachineIRBuilder &B, Register Val)

static void	toggleSPDenormMode (bool Enable, MachineIRBuilder &B, const GCNSubtarget &ST, SIModeRegisterDefaults Mode)

static unsigned	getDSFPAtomicOpcode (Intrinsic::ID IID)

static void	buildBufferLoad (unsigned Opc, Register LoadDstReg, Register RSrc, Register VIndex, Register VOffset, Register SOffset, unsigned ImmOffset, unsigned Format, unsigned AuxiliaryData, MachineMemOperand *MMO, bool IsTyped, bool HasVIndex, MachineIRBuilder &B)

static unsigned	getBufferAtomicPseudo (Intrinsic::ID IntrID)

static void	packImage16bitOpsToDwords (MachineIRBuilder &B, MachineInstr &MI, SmallVectorImpl< Register > &PackedAddrs, unsigned ArgOffset, const AMDGPU::ImageDimIntrinsicInfo *Intr, bool IsA16, bool IsG16)
	Turn a set of s16 typed registers in `AddrRegs` into a dword sized vector with s16 typed elements.

static void	convertImageAddrToPacked (MachineIRBuilder &B, MachineInstr &MI, int DimIdx, int NumVAddrs)
	Convert from separate vaddr components to a single vector address register, and replace the remaining operands with $noreg.

Variables
static cl::opt< bool >	EnableNewLegality ("amdgpu-global-isel-new-legality", cl::desc("Use GlobalISel desired legality, rather than try to use" "rules compatible with selection patterns"), cl::init(false), cl::ReallyHidden)

static constexpr unsigned	MaxRegisterSize = 1024

static const unsigned	SPDenormModeBitField

Detailed Description

This file implements the targeting of the Machinelegalizer class for AMDGPU.

Todo:: This should be generated by TableGen.

Definition in file AMDGPULegalizerInfo.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "amdgpu-legalinfo"

Definition at line 33 of file AMDGPULegalizerInfo.cpp.

Function Documentation

◆ allowApproxFunc()

static bool allowApproxFunc	(	const MachineFunction &	MF,
		unsigned	Flags
	)

static

Definition at line 3061 of file AMDGPULegalizerInfo.cpp.

References llvm::MachineInstr::FmAfn, llvm::MachineFunction::getTarget(), llvm::TargetMachine::Options, and Options.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFExp(), and llvm::AMDGPULegalizerInfo::legalizeFSQRTF32().

◆ bitcastToRegisterType()

static LegalizeMutation bitcastToRegisterType ( unsigned TypeIdx )

static

Definition at line 184 of file AMDGPULegalizerInfo.cpp.

References getBitcastRegisterType().

◆ bitcastToVectorElement32()

static LegalizeMutation bitcastToVectorElement32 ( unsigned TypeIdx )

static

Definition at line 191 of file AMDGPULegalizerInfo.cpp.

References assert(), llvm::ElementCount::getFixed(), llvm::LLT::getSizeInBits(), llvm::LLT::scalarOrVector(), and Size.

◆ buildBufferLoad()

static void buildBufferLoad	(	unsigned	Opc,
		Register	LoadDstReg,
		Register	RSrc,
		Register	VIndex,
		Register	VOffset,
		Register	SOffset,
		unsigned	ImmOffset,
		unsigned	Format,
		unsigned	AuxiliaryData,
		MachineMemOperand *	MMO,
		bool	IsTyped,
		bool	HasVIndex,
		MachineIRBuilder &	B
	)

static

Definition at line 5559 of file AMDGPULegalizerInfo.cpp.

References B, and llvm::Format.

Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferLoad().

◆ castBufferRsrcArgToV4I32()

static void castBufferRsrcArgToV4I32	(	MachineInstr &	MI,
		MachineIRBuilder &	B,
		unsigned	Idx
	)

static

Definition at line 557 of file AMDGPULegalizerInfo.cpp.

References B, castBufferRsrcToV4I32(), llvm::MachineOperand::getReg(), hasBufferRsrcWorkaround(), Idx, MI, and llvm::MachineOperand::setReg().

Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferAtomic(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeBufferStore(), and llvm::AMDGPULegalizerInfo::legalizeStore().

◆ castBufferRsrcFromV4I32()

static LLT castBufferRsrcFromV4I32	(	MachineInstr &	MI,
		MachineIRBuilder &	B,
		MachineRegisterInfo &	MRI,
		unsigned	Idx
	)

static

Mutates IR (typicaly a load instruction) to use a <4 x s32> as the initial type of the operand idx and then to transform it to a p8 via bitcasts and inttoptr.

In addition, handle vectors of p8. Returns the new type.

Definition at line 497 of file AMDGPULegalizerInfo.cpp.

References B, getBufferRsrcRegisterType(), getBufferRsrcScalarType(), llvm::MachineOperand::getReg(), hasBufferRsrcWorkaround(), I, Idx, MI, MRI, llvm::LLT::scalar(), and llvm::MachineOperand::setReg().

Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeLoad(), and llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

◆ castBufferRsrcToV4I32()

static Register castBufferRsrcToV4I32	(	Register	Pointer,
		MachineIRBuilder &	B
	)

static

Cast a buffer resource (an address space 8 pointer) into a 4xi32, which is the form in which the value must be in order to be passed to the low-level representations used for MUBUF/MTBUF intrinsics.

This is a hack, which is needed in order to account for the fact that we can't define a register class for s128 without breaking SelectionDAG.

Definition at line 538 of file AMDGPULegalizerInfo.cpp.

References B, getBufferRsrcRegisterType(), getBufferRsrcScalarType(), I, MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::LLT::scalar().

Referenced by castBufferRsrcArgToV4I32(), and llvm::AMDGPULegalizerInfo::fixStoreSourceType().

◆ convertImageAddrToPacked()

static void convertImageAddrToPacked	(	MachineIRBuilder &	B,
		MachineInstr &	MI,
		int	DimIdx,
		int	NumVAddrs
	)

static

Convert from separate vaddr components to a single vector address register, and replace the remaining operands with $noreg.

Definition at line 5947 of file AMDGPULegalizerInfo.cpp.

References assert(), B, llvm::LLT::fixed_vector(), llvm::SrcOp::getReg(), I, MI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::LLT::scalar(), and llvm::SmallVectorBase< Size_T >::size().

Referenced by llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic().

◆ elementTypeIsLegal()

static LegalityPredicate elementTypeIsLegal ( unsigned TypeIdx )

static

Definition at line 265 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ emitReciprocalU64()

static std::pair< Register, Register > emitReciprocalU64	(	MachineIRBuilder &	B,
		Register	Val
	)

static

Definition at line 4280 of file AMDGPULegalizerInfo.cpp.

References B, and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl().

◆ extractF64Exponent()

static MachineInstrBuilder extractF64Exponent	(	Register	Hi,
		MachineIRBuilder &	B
	)

static

Definition at line 2357 of file AMDGPULegalizerInfo.cpp.

References B, llvm::Hi, and llvm::LLT::scalar().

◆ fewerEltsToSize64Vector()

static LegalizeMutation fewerEltsToSize64Vector ( unsigned TypeIdx )

static

Definition at line 106 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::ElementCount::getFixed(), llvm::LLT::getNumElements(), llvm::LLT::getSizeInBits(), llvm::LLT::scalarOrVector(), and Size.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ getBitcastRegisterType()

static LLT getBitcastRegisterType ( const LLT Ty )

static

Definition at line 172 of file AMDGPULegalizerInfo.cpp.

References llvm::ElementCount::getFixed(), llvm::LLT::getSizeInBits(), llvm::LLT::scalar(), llvm::LLT::scalarOrVector(), and Size.

Referenced by bitcastToRegisterType(), and llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

◆ getBufferAtomicPseudo()

static unsigned getBufferAtomicPseudo ( Intrinsic::ID IntrID )

static

Definition at line 5721 of file AMDGPULegalizerInfo.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferAtomic().

◆ getBufferRsrcRegisterType()

static LLT getBufferRsrcRegisterType ( const LLT Ty )

static

Definition at line 165 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::fixed_vector(), llvm::LLT::getElementCount(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::LLT::isVector(), and llvm::LLT::scalar().

Referenced by castBufferRsrcFromV4I32(), and castBufferRsrcToV4I32().

◆ getBufferRsrcScalarType()

static LLT getBufferRsrcScalarType ( const LLT Ty )

static

Definition at line 158 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementCount(), llvm::LLT::isVector(), llvm::LLT::scalar(), and llvm::LLT::vector().

Referenced by castBufferRsrcFromV4I32(), and castBufferRsrcToV4I32().

◆ getDSFPAtomicOpcode()

static unsigned getDSFPAtomicOpcode ( Intrinsic::ID IID )

static

Definition at line 5176 of file AMDGPULegalizerInfo.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic().

◆ getMad()

static Register getMad	(	MachineIRBuilder &	B,
		LLT	Ty,
		Register	X,
		Register	Y,
		Register	Z,
		unsigned	Flags
	)

static

Definition at line 3146 of file AMDGPULegalizerInfo.cpp.

References B, llvm::FMul, X, and Y.

◆ getPow2ScalarType()

static LLT getPow2ScalarType ( LLT Ty )

static

Definition at line 59 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), llvm::Log2_32_Ceil(), and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

◆ getPow2VectorType()

static LLT getPow2VectorType ( LLT Ty )

static

Definition at line 52 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::changeElementCount(), llvm::ElementCount::getFixed(), llvm::LLT::getNumElements(), and llvm::Log2_32_Ceil().

Referenced by llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

◆ hasBufferRsrcWorkaround()

static bool hasBufferRsrcWorkaround ( const LLT Ty )

static

Definition at line 388 of file AMDGPULegalizerInfo.cpp.

References llvm::AMDGPUAS::BUFFER_RESOURCE, llvm::LLT::getAddressSpace(), llvm::LLT::getElementType(), hasBufferRsrcWorkaround(), llvm::LLT::isPointer(), and llvm::LLT::isVector().

Referenced by castBufferRsrcArgToV4I32(), castBufferRsrcFromV4I32(), llvm::AMDGPULegalizerInfo::fixStoreSourceType(), hasBufferRsrcWorkaround(), isLoadStoreLegal(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeLoad(), llvm::AMDGPULegalizerInfo::legalizeSBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeStore(), and loadStoreBitcastWorkaround().

◆ isIllegalRegisterType()

static LegalityPredicate isIllegalRegisterType ( unsigned TypeIdx )

static

Definition at line 257 of file AMDGPULegalizerInfo.cpp.

References llvm::SIRegisterInfo::getSGPRClassForBitWidth(), llvm::LLT::getSizeInBits(), and isRegisterType().

◆ isKnownNonNull()

static bool isKnownNonNull	(	Register	Val,
		MachineRegisterInfo &	MRI,
		const AMDGPUTargetMachine &	TM,
		unsigned	AddrSpace
	)

static

Return true if the value is a known valid address, such that a null check is not necessary.

Definition at line 2153 of file AMDGPULegalizerInfo.cpp.

References llvm::ConstantInt::getSExtValue(), MRI, and TM.

Referenced by llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast().

◆ isLoadStoreLegal()

static bool isLoadStoreLegal	(	const GCNSubtarget &	ST,
		const LegalityQuery &	Query
	)

static

Definition at line 423 of file AMDGPULegalizerInfo.cpp.

References hasBufferRsrcWorkaround(), isLoadStoreSizeLegal(), isRegisterType(), loadStoreBitcastWorkaround(), and llvm::LegalityQuery::Types.

◆ isLoadStoreSizeLegal()

static bool isLoadStoreSizeLegal	(	const GCNSubtarget &	ST,
		const LegalityQuery &	Query
	)

static

Definition at line 315 of file AMDGPULegalizerInfo.cpp.

References llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl(), assert(), llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), maxSizeForAddrSpace(), llvm::LegalityQuery::MMODescrs, llvm::LegalityQuery::Opcode, RegSize, Size, and llvm::LegalityQuery::Types.

Referenced by isLoadStoreLegal().

◆ isNot()

static bool isNot	(	const MachineRegisterInfo &	MRI,
		const MachineInstr &	MI
	)

static

Definition at line 4001 of file AMDGPULegalizerInfo.cpp.

References llvm::getIConstantVRegSExtVal(), MI, and MRI.

Referenced by llvm::MCAsmParserExtension::ParseDirectiveCGProfile(), and verifyCFIntrinsic().

◆ isRegisterSize()

static bool isRegisterSize ( unsigned Size )

static

Definition at line 222 of file AMDGPULegalizerInfo.cpp.

References MaxRegisterSize, and Size.

Referenced by isRegisterType(), and shouldBitcastLoadStoreType().

◆ isRegisterType() [1/2]

static bool isRegisterType ( LLT Ty )

static

Definition at line 238 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), isRegisterSize(), isRegisterVectorType(), and llvm::LLT::isVector().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), isIllegalRegisterType(), isLoadStoreLegal(), isRegisterType(), llvm::AMDGPULegalizerInfo::legalizeLoad(), llvm::PPCLegalizerInfo::PPCLegalizerInfo(), and shouldBitcastLoadStoreType().

◆ isRegisterType() [2/2]

static LegalityPredicate isRegisterType ( unsigned TypeIdx )

static

Definition at line 250 of file AMDGPULegalizerInfo.cpp.

References isRegisterType().

◆ isRegisterVectorElementType()

static bool isRegisterVectorElementType ( LLT EltTy )

static

Definition at line 226 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits().

Referenced by shouldBitcastLoadStoreType().

◆ isRegisterVectorType()

static bool isRegisterVectorType ( LLT Ty )

static

Definition at line 231 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::LLT::getNumElements(), and llvm::LLT::getSizeInBits().

Referenced by isRegisterType().

◆ isSmallOddVector()

static LegalityPredicate isSmallOddVector ( unsigned TypeIdx )

static

Returns: true if this is an odd sized vector which should widen by adding an additional element. This is mostly to handle <3 x s16> -> <4 x s16>. This excludes s1 vectors, which should always be scalarized.

Definition at line 68 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::LLT::getNumElements(), llvm::LLT::getSizeInBits(), and llvm::LLT::isVector().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ isWideScalarExtLoadTruncStore()

static LegalityPredicate isWideScalarExtLoadTruncStore ( unsigned TypeIdx )

static

Definition at line 277 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), and llvm::LLT::isVector().

◆ isWideVec16()

static LegalityPredicate isWideVec16 ( unsigned TypeIdx )

static

Definition at line 89 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getNumElements(), llvm::LLT::getScalarType(), and llvm::LLT::getSizeInBits().

◆ loadStoreBitcastWorkaround()

static bool loadStoreBitcastWorkaround ( const LLT Ty )

static

Definition at line 402 of file AMDGPULegalizerInfo.cpp.

References EnableNewLegality, llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), hasBufferRsrcWorkaround(), llvm::LLT::isPointer(), llvm::LLT::isVector(), and Size.

Referenced by isLoadStoreLegal(), and shouldBitcastLoadStoreType().

◆ maxSizeForAddrSpace()

static unsigned maxSizeForAddrSpace	(	const GCNSubtarget &	ST,
		unsigned	AS,
		bool	IsLoad,
		bool	IsAtomic
	)

static

Definition at line 288 of file AMDGPULegalizerInfo.cpp.

References llvm::AMDGPUAS::BUFFER_RESOURCE, llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::AMDGPUAS::GLOBAL_ADDRESS, llvm::AMDGPUAS::LOCAL_ADDRESS, and llvm::AMDGPUAS::PRIVATE_ADDRESS.

Referenced by isLoadStoreSizeLegal(), and shouldWidenLoad().

◆ moreElementsToNextExistingRegClass()

static LegalizeMutation moreElementsToNextExistingRegClass ( unsigned TypeIdx )

static

Definition at line 137 of file AMDGPULegalizerInfo.cpp.

References assert(), llvm::LLT::fixed_vector(), llvm::LLT::getElementType(), llvm::LLT::getNumElements(), llvm::SIRegisterInfo::getSGPRClassForBitWidth(), llvm::LLT::getSizeInBits(), and MaxRegisterSize.

◆ moreEltsToNext32Bit()

static LegalizeMutation moreEltsToNext32Bit ( unsigned TypeIdx )

static

Definition at line 120 of file AMDGPULegalizerInfo.cpp.

References assert(), llvm::LLT::fixed_vector(), llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), and Size.

◆ needsDenormHandlingF32()

static bool needsDenormHandlingF32	(	const MachineFunction &	MF,
		Register	Src,
		unsigned	Flags
	)

static

Definition at line 3068 of file AMDGPULegalizerInfo.cpp.

References llvm::MachineFunction::getDenormalMode(), llvm::MachineFunction::getRegInfo(), llvm::APFloatBase::IEEEsingle(), llvm::DenormalMode::Input, llvm::DenormalMode::PreserveSign, and valueIsKnownNeverF32Denorm().

Referenced by llvm::AMDGPULegalizerInfo::getScaledLogInput(), llvm::AMDGPULegalizerInfo::legalizeFExp2(), llvm::AMDGPULegalizerInfo::legalizeFExpUnsafe(), and llvm::AMDGPULegalizerInfo::legalizeFSQRTF32().

◆ numElementsNotEven()

static LegalityPredicate numElementsNotEven ( unsigned TypeIdx )

static

Definition at line 215 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getNumElements(), and llvm::LLT::isVector().

◆ oneMoreElement()

static LegalizeMutation oneMoreElement ( unsigned TypeIdx )

static

Definition at line 97 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::fixed_vector(), llvm::LLT::getElementType(), and llvm::LLT::getNumElements().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ packImage16bitOpsToDwords()

static void packImage16bitOpsToDwords	(	MachineIRBuilder &	B,
		MachineInstr &	MI,
		SmallVectorImpl< Register > &	PackedAddrs,
		unsigned	ArgOffset,
		const AMDGPU::ImageDimIntrinsicInfo *	Intr,
		bool	IsA16,
		bool	IsG16
	)

static

Turn a set of s16 typed registers in AddrRegs into a dword sized vector with s16 typed elements.

Definition at line 5886 of file AMDGPULegalizerInfo.cpp.

References assert(), B, llvm::LLT::fixed_vector(), llvm::SrcOp::getReg(), I, Intr, MI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic().

◆ replaceWithConstant()

static bool replaceWithConstant	(	MachineIRBuilder &	B,
		MachineInstr &	MI,
		int64_t	C
	)

static

Definition at line 4122 of file AMDGPULegalizerInfo.cpp.

References B, llvm::CallingConv::C, and MI.

Referenced by llvm::AMDGPULegalizerInfo::legalizeWorkitemIDIntrinsic().

◆ shouldBitcastLoadStoreType()

static bool shouldBitcastLoadStoreType	(	const GCNSubtarget &	ST,
		const LLT	Ty,
		const LLT	MemTy
	)

static

Return true if a load or store of the type should be lowered with a bitcast to a different type.

Definition at line 431 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), isRegisterSize(), isRegisterType(), isRegisterVectorElementType(), llvm::LLT::isVector(), loadStoreBitcastWorkaround(), and Size.

Referenced by llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

◆ shouldWidenLoad() [1/2]

static bool shouldWidenLoad	(	const GCNSubtarget &	ST,
		const LegalityQuery &	Query,
		unsigned	Opcode
	)

static

Definition at line 484 of file AMDGPULegalizerInfo.cpp.

References llvm::LegalityQuery::MMODescrs, shouldWidenLoad(), and llvm::LegalityQuery::Types.

◆ shouldWidenLoad() [2/2]

static bool shouldWidenLoad	(	const GCNSubtarget &	ST,
		LLT	MemoryTy,
		uint64_t	AlignInBits,
		unsigned	AddrSpace,
		unsigned	Opcode
	)

static

Return true if we should legalize a load by widening an odd sized memory access up to the alignment.

Note this case when the memory access itself changes, not the size of the result register.

Definition at line 450 of file AMDGPULegalizerInfo.cpp.

References llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl(), llvm::CallingConv::Fast, llvm::LLT::getSizeInBits(), llvm::isPowerOf2_32(), maxSizeForAddrSpace(), llvm::MachineMemOperand::MOLoad, and llvm::NextPowerOf2().

Referenced by llvm::AMDGPULegalizerInfo::legalizeLoad(), and shouldWidenLoad().

◆ sizeIsMultipleOf32()

static LegalityPredicate sizeIsMultipleOf32 ( unsigned TypeIdx )

static

Definition at line 82 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits().

◆ stripAnySourceMods()

static Register stripAnySourceMods	(	Register	OrigSrc,
		MachineRegisterInfo &	MRI
	)

static

Definition at line 3576 of file AMDGPULegalizerInfo.cpp.

References llvm::getOpcodeDef(), and MRI.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFFloor().

◆ toggleSPDenormMode()

static void toggleSPDenormMode	(	bool	Enable,
		MachineIRBuilder &	B,
		const GCNSubtarget &	ST,
		SIModeRegisterDefaults	Mode
	)

static

Definition at line 4672 of file AMDGPULegalizerInfo.cpp.

References B, llvm::Enable, FP_DENORM_FLUSH_NONE, and SPDenormModeBitField.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFDIV32().

◆ valueIsKnownNeverF32Denorm()

static bool valueIsKnownNeverF32Denorm	(	const MachineRegisterInfo &	MRI,
		Register	Src
	)

static

Return true if it's known that Src can never be an f32 denormal value.

Definition at line 3032 of file AMDGPULegalizerInfo.cpp.

References DefMI, getIntrinsicID(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), MRI, and llvm::LLT::scalar().

◆ vectorSmallerThan()

static LegalityPredicate vectorSmallerThan	(	unsigned	TypeIdx,
		unsigned	Size
	)

static

Definition at line 201 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), and Size.

◆ vectorWiderThan()

static LegalityPredicate vectorWiderThan	(	unsigned	TypeIdx,
		unsigned	Size
	)

static

Definition at line 208 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), and Size.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ verifyCFIntrinsic()

static MachineInstr * verifyCFIntrinsic	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		MachineInstr *&	Br,
		MachineBasicBlock *&	UncondBrTarget,
		bool &	Negated
	)

static

Definition at line 4010 of file AMDGPULegalizerInfo.cpp.

References llvm::MachineBasicBlock::end(), llvm::MachineFunction::end(), llvm::eraseInstr(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), isNot(), MI, MRI, and UseMI.

Referenced by llvm::AMDGPULegalizerInfo::legalizeIntrinsic().

◆ widenToNextPowerOf2()

static LLT widenToNextPowerOf2 ( LLT Ty )

static

Definition at line 2868 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::changeElementCount(), llvm::ElementCount::getFixed(), llvm::LLT::getNumElements(), llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), llvm::PowerOf2Ceil(), and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::legalizeLoad().

Variable Documentation

◆ EnableNewLegality

cl::opt< bool > EnableNewLegality("amdgpu-global-isel-new-legality", cl::desc("Use GlobalISel desired legality, rather than try to use" "rules compatible with selection patterns"), cl::init(false), cl::ReallyHidden)	(	"amdgpu-global-isel-new-legality"	,
		cl::desc("Use GlobalISel desired legality, rather than try to use" "rules compatible with selection patterns")	,
		cl::init(false)	,
		cl::ReallyHidden
	)

static

Referenced by loadStoreBitcastWorkaround().

◆ MaxRegisterSize

constexpr unsigned MaxRegisterSize = 1024

staticconstexpr

Definition at line 49 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), isRegisterSize(), and moreElementsToNextExistingRegClass().

◆ SPDenormModeBitField

const unsigned SPDenormModeBitField

static

Initial value:

=
    AMDGPU::Hwreg::ID_MODE | (4 << AMDGPU::Hwreg::OFFSET_SHIFT_) |
    (1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_)

Definition at line 4666 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFDIV32(), and toggleSPDenormMode().

Macros

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ DEBUG_TYPE

Function Documentation

◆ allowApproxFunc()

◆ bitcastToRegisterType()

◆ bitcastToVectorElement32()

◆ buildBufferLoad()

◆ castBufferRsrcArgToV4I32()

◆ castBufferRsrcFromV4I32()

◆ castBufferRsrcToV4I32()

◆ convertImageAddrToPacked()

◆ elementTypeIsLegal()

◆ emitReciprocalU64()

◆ extractF64Exponent()

◆ fewerEltsToSize64Vector()

◆ getBitcastRegisterType()

◆ getBufferAtomicPseudo()

◆ getBufferRsrcRegisterType()

◆ getBufferRsrcScalarType()

◆ getDSFPAtomicOpcode()

◆ getMad()

◆ getPow2ScalarType()

◆ getPow2VectorType()

◆ hasBufferRsrcWorkaround()

◆ isIllegalRegisterType()

◆ isKnownNonNull()

◆ isLoadStoreLegal()

◆ isLoadStoreSizeLegal()

◆ isNot()

◆ isRegisterSize()

◆ isRegisterType() [1/2]

◆ isRegisterType() [2/2]

◆ isRegisterVectorElementType()

◆ isRegisterVectorType()

◆ isSmallOddVector()

◆ isWideScalarExtLoadTruncStore()

◆ isWideVec16()

◆ loadStoreBitcastWorkaround()

◆ maxSizeForAddrSpace()

◆ moreElementsToNextExistingRegClass()

◆ moreEltsToNext32Bit()

◆ needsDenormHandlingF32()

◆ numElementsNotEven()

◆ oneMoreElement()

◆ packImage16bitOpsToDwords()

◆ replaceWithConstant()

◆ shouldBitcastLoadStoreType()

◆ shouldWidenLoad() [1/2]

◆ shouldWidenLoad() [2/2]

◆ sizeIsMultipleOf32()

◆ stripAnySourceMods()

◆ toggleSPDenormMode()

◆ valueIsKnownNeverF32Denorm()

◆ vectorSmallerThan()

◆ vectorWiderThan()

◆ verifyCFIntrinsic()

◆ widenToNextPowerOf2()

Variable Documentation

◆ EnableNewLegality

◆ MaxRegisterSize

◆ SPDenormModeBitField