LLVM  14.0.0git
AMDGPUCallLowering.cpp
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1 //===-- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp - Call lowering -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUCallLowering.h"
16 #include "AMDGPU.h"
17 #include "AMDGPULegalizerInfo.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "SIRegisterInfo.h"
21 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/IR/IntrinsicsAMDGPU.h"
25 
26 #define DEBUG_TYPE "amdgpu-call-lowering"
27 
28 using namespace llvm;
29 
30 namespace {
31 
32 /// Wrapper around extendRegister to ensure we extend to a full 32-bit register.
33 static Register extendRegisterMin32(CallLowering::ValueHandler &Handler,
34  Register ValVReg, CCValAssign &VA) {
35  if (VA.getLocVT().getSizeInBits() < 32) {
36  // 16-bit types are reported as legal for 32-bit registers. We need to
37  // extend and do a 32-bit copy to avoid the verifier complaining about it.
38  return Handler.MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0);
39  }
40 
41  return Handler.extendRegister(ValVReg, VA);
42 }
43 
44 struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
45  AMDGPUOutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
47  : OutgoingValueHandler(B, MRI), MIB(MIB) {}
48 
50 
51  Register getStackAddress(uint64_t Size, int64_t Offset,
52  MachinePointerInfo &MPO,
53  ISD::ArgFlagsTy Flags) override {
54  llvm_unreachable("not implemented");
55  }
56 
57  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
58  MachinePointerInfo &MPO, CCValAssign &VA) override {
59  llvm_unreachable("not implemented");
60  }
61 
62  void assignValueToReg(Register ValVReg, Register PhysReg,
63  CCValAssign &VA) override {
64  Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);
65 
66  // If this is a scalar return, insert a readfirstlane just in case the value
67  // ends up in a VGPR.
68  // FIXME: Assert this is a shader return.
69  const SIRegisterInfo *TRI
70  = static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo());
71  if (TRI->isSGPRReg(MRI, PhysReg)) {
72  auto ToSGPR = MIRBuilder.buildIntrinsic(Intrinsic::amdgcn_readfirstlane,
73  {MRI.getType(ExtReg)}, false)
74  .addReg(ExtReg);
75  ExtReg = ToSGPR.getReg(0);
76  }
77 
78  MIRBuilder.buildCopy(PhysReg, ExtReg);
79  MIB.addUse(PhysReg, RegState::Implicit);
80  }
81 };
82 
83 struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler {
84  uint64_t StackUsed = 0;
85 
86  AMDGPUIncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI)
87  : IncomingValueHandler(B, MRI) {}
88 
89  Register getStackAddress(uint64_t Size, int64_t Offset,
90  MachinePointerInfo &MPO,
91  ISD::ArgFlagsTy Flags) override {
92  auto &MFI = MIRBuilder.getMF().getFrameInfo();
93 
94  // Byval is assumed to be writable memory, but other stack passed arguments
95  // are not.
96  const bool IsImmutable = !Flags.isByVal();
97  int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
98  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
99  auto AddrReg = MIRBuilder.buildFrameIndex(
101  StackUsed = std::max(StackUsed, Size + Offset);
102  return AddrReg.getReg(0);
103  }
104 
105  void assignValueToReg(Register ValVReg, Register PhysReg,
106  CCValAssign &VA) override {
107  markPhysRegUsed(PhysReg);
108 
109  if (VA.getLocVT().getSizeInBits() < 32) {
110  // 16-bit types are reported as legal for 32-bit registers. We need to do
111  // a 32-bit copy, and truncate to avoid the verifier complaining about it.
112  auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg);
113 
114  // If we have signext/zeroext, it applies to the whole 32-bit register
115  // before truncation.
116  auto Extended =
117  buildExtensionHint(VA, Copy.getReg(0), LLT(VA.getLocVT()));
118  MIRBuilder.buildTrunc(ValVReg, Extended);
119  return;
120  }
121 
122  IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
123  }
124 
125  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
126  MachinePointerInfo &MPO, CCValAssign &VA) override {
127  MachineFunction &MF = MIRBuilder.getMF();
128 
129  auto MMO = MF.getMachineMemOperand(
131  inferAlignFromPtrInfo(MF, MPO));
132  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
133  }
134 
135  /// How the physical register gets marked varies between formal
136  /// parameters (it's a basic-block live-in), and a call instruction
137  /// (it's an implicit-def of the BL).
138  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
139 };
140 
141 struct FormalArgHandler : public AMDGPUIncomingArgHandler {
143  : AMDGPUIncomingArgHandler(B, MRI) {}
144 
145  void markPhysRegUsed(unsigned PhysReg) override {
146  MIRBuilder.getMBB().addLiveIn(PhysReg);
147  }
148 };
149 
150 struct CallReturnHandler : public AMDGPUIncomingArgHandler {
151  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
153  : AMDGPUIncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {}
154 
155  void markPhysRegUsed(unsigned PhysReg) override {
156  MIB.addDef(PhysReg, RegState::Implicit);
157  }
158 
160 };
161 
162 struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
163  /// For tail calls, the byte offset of the call's argument area from the
164  /// callee's. Unused elsewhere.
165  int FPDiff;
166 
167  // Cache the SP register vreg if we need it more than once in this call site.
168  Register SPReg;
169 
170  bool IsTailCall;
171 
172  AMDGPUOutgoingArgHandler(MachineIRBuilder &MIRBuilder,
174  bool IsTailCall = false, int FPDiff = 0)
175  : AMDGPUOutgoingValueHandler(MIRBuilder, MRI, MIB), FPDiff(FPDiff),
176  IsTailCall(IsTailCall) {}
177 
178  Register getStackAddress(uint64_t Size, int64_t Offset,
179  MachinePointerInfo &MPO,
180  ISD::ArgFlagsTy Flags) override {
181  MachineFunction &MF = MIRBuilder.getMF();
182  const LLT PtrTy = LLT::pointer(AMDGPUAS::PRIVATE_ADDRESS, 32);
183  const LLT S32 = LLT::scalar(32);
184 
185  if (IsTailCall) {
186  Offset += FPDiff;
187  int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
188  auto FIReg = MIRBuilder.buildFrameIndex(PtrTy, FI);
189  MPO = MachinePointerInfo::getFixedStack(MF, FI);
190  return FIReg.getReg(0);
191  }
192 
194 
195  if (!SPReg)
196  SPReg = MIRBuilder.buildCopy(PtrTy, MFI->getStackPtrOffsetReg()).getReg(0);
197 
198  auto OffsetReg = MIRBuilder.buildConstant(S32, Offset);
199 
200  auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg);
202  return AddrReg.getReg(0);
203  }
204 
205  void assignValueToReg(Register ValVReg, Register PhysReg,
206  CCValAssign &VA) override {
207  MIB.addUse(PhysReg, RegState::Implicit);
208  Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);
209  MIRBuilder.buildCopy(PhysReg, ExtReg);
210  }
211 
212  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
213  MachinePointerInfo &MPO, CCValAssign &VA) override {
214  MachineFunction &MF = MIRBuilder.getMF();
215  uint64_t LocMemOffset = VA.getLocMemOffset();
216  const auto &ST = MF.getSubtarget<GCNSubtarget>();
217 
218  auto MMO = MF.getMachineMemOperand(
219  MPO, MachineMemOperand::MOStore, MemTy,
220  commonAlignment(ST.getStackAlignment(), LocMemOffset));
221  MIRBuilder.buildStore(ValVReg, Addr, *MMO);
222  }
223 
224  void assignValueToAddress(const CallLowering::ArgInfo &Arg,
225  unsigned ValRegIndex, Register Addr, LLT MemTy,
226  MachinePointerInfo &MPO, CCValAssign &VA) override {
227  Register ValVReg = VA.getLocInfo() != CCValAssign::LocInfo::FPExt
228  ? extendRegister(Arg.Regs[ValRegIndex], VA)
229  : Arg.Regs[ValRegIndex];
230  assignValueToAddress(ValVReg, Addr, MemTy, MPO, VA);
231  }
232 };
233 }
234 
236  : CallLowering(&TLI) {
237 }
238 
239 // FIXME: Compatability shim
240 static ISD::NodeType extOpcodeToISDExtOpcode(unsigned MIOpc) {
241  switch (MIOpc) {
242  case TargetOpcode::G_SEXT:
243  return ISD::SIGN_EXTEND;
244  case TargetOpcode::G_ZEXT:
245  return ISD::ZERO_EXTEND;
246  case TargetOpcode::G_ANYEXT:
247  return ISD::ANY_EXTEND;
248  default:
249  llvm_unreachable("not an extend opcode");
250  }
251 }
252 
253 bool AMDGPUCallLowering::canLowerReturn(MachineFunction &MF,
254  CallingConv::ID CallConv,
256  bool IsVarArg) const {
257  // For shaders. Vector types should be explicitly handled by CC.
258  if (AMDGPU::isEntryFunctionCC(CallConv))
259  return true;
260 
262  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
263  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs,
264  MF.getFunction().getContext());
265 
266  return checkReturn(CCInfo, Outs, TLI.CCAssignFnForReturn(CallConv, IsVarArg));
267 }
268 
269 /// Lower the return value for the already existing \p Ret. This assumes that
270 /// \p B's insertion point is correct.
271 bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B,
272  const Value *Val, ArrayRef<Register> VRegs,
273  MachineInstrBuilder &Ret) const {
274  if (!Val)
275  return true;
276 
277  auto &MF = B.getMF();
278  const auto &F = MF.getFunction();
279  const DataLayout &DL = MF.getDataLayout();
280  MachineRegisterInfo *MRI = B.getMRI();
281  LLVMContext &Ctx = F.getContext();
282 
283  CallingConv::ID CC = F.getCallingConv();
284  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
285 
286  SmallVector<EVT, 8> SplitEVTs;
287  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
288  assert(VRegs.size() == SplitEVTs.size() &&
289  "For each split Type there should be exactly one VReg.");
290 
291  SmallVector<ArgInfo, 8> SplitRetInfos;
292 
293  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
294  EVT VT = SplitEVTs[i];
295  Register Reg = VRegs[i];
296  ArgInfo RetInfo(Reg, VT.getTypeForEVT(Ctx), 0);
298 
299  if (VT.isScalarInteger()) {
300  unsigned ExtendOp = TargetOpcode::G_ANYEXT;
301  if (RetInfo.Flags[0].isSExt()) {
302  assert(RetInfo.Regs.size() == 1 && "expect only simple return values");
303  ExtendOp = TargetOpcode::G_SEXT;
304  } else if (RetInfo.Flags[0].isZExt()) {
305  assert(RetInfo.Regs.size() == 1 && "expect only simple return values");
306  ExtendOp = TargetOpcode::G_ZEXT;
307  }
308 
309  EVT ExtVT = TLI.getTypeForExtReturn(Ctx, VT,
310  extOpcodeToISDExtOpcode(ExtendOp));
311  if (ExtVT != VT) {
312  RetInfo.Ty = ExtVT.getTypeForEVT(Ctx);
313  LLT ExtTy = getLLTForType(*RetInfo.Ty, DL);
314  Reg = B.buildInstr(ExtendOp, {ExtTy}, {Reg}).getReg(0);
315  }
316  }
317 
318  if (Reg != RetInfo.Regs[0]) {
319  RetInfo.Regs[0] = Reg;
320  // Reset the arg flags after modifying Reg.
322  }
323 
324  splitToValueTypes(RetInfo, SplitRetInfos, DL, CC);
325  }
326 
327  CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(CC, F.isVarArg());
328 
329  OutgoingValueAssigner Assigner(AssignFn);
330  AMDGPUOutgoingValueHandler RetHandler(B, *MRI, Ret);
331  return determineAndHandleAssignments(RetHandler, Assigner, SplitRetInfos, B,
332  CC, F.isVarArg());
333 }
334 
336  ArrayRef<Register> VRegs,
337  FunctionLoweringInfo &FLI) const {
338 
339  MachineFunction &MF = B.getMF();
342  MFI->setIfReturnsVoid(!Val);
343 
344  assert(!Val == VRegs.empty() && "Return value without a vreg");
345 
346  CallingConv::ID CC = B.getMF().getFunction().getCallingConv();
347  const bool IsShader = AMDGPU::isShader(CC);
348  const bool IsWaveEnd =
349  (IsShader && MFI->returnsVoid()) || AMDGPU::isKernel(CC);
350  if (IsWaveEnd) {
351  B.buildInstr(AMDGPU::S_ENDPGM)
352  .addImm(0);
353  return true;
354  }
355 
356  auto const &ST = MF.getSubtarget<GCNSubtarget>();
357 
358  unsigned ReturnOpc =
359  IsShader ? AMDGPU::SI_RETURN_TO_EPILOG : AMDGPU::S_SETPC_B64_return;
360 
361  auto Ret = B.buildInstrNoInsert(ReturnOpc);
362  Register ReturnAddrVReg;
363  if (ReturnOpc == AMDGPU::S_SETPC_B64_return) {
364  ReturnAddrVReg = MRI.createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass);
365  Ret.addUse(ReturnAddrVReg);
366  }
367 
368  if (!FLI.CanLowerReturn)
369  insertSRetStores(B, Val->getType(), VRegs, FLI.DemoteRegister);
370  else if (!lowerReturnVal(B, Val, VRegs, Ret))
371  return false;
372 
373  if (ReturnOpc == AMDGPU::S_SETPC_B64_return) {
374  const SIRegisterInfo *TRI = ST.getRegisterInfo();
375  Register LiveInReturn = MF.addLiveIn(TRI->getReturnAddressReg(MF),
376  &AMDGPU::SGPR_64RegClass);
377  B.buildCopy(ReturnAddrVReg, LiveInReturn);
378  }
379 
380  // TODO: Handle CalleeSavedRegsViaCopy.
381 
382  B.insertInstr(Ret);
383  return true;
384 }
385 
386 void AMDGPUCallLowering::lowerParameterPtr(Register DstReg, MachineIRBuilder &B,
387  uint64_t Offset) const {
388  MachineFunction &MF = B.getMF();
391  Register KernArgSegmentPtr =
393  Register KernArgSegmentVReg = MRI.getLiveInVirtReg(KernArgSegmentPtr);
394 
395  auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset);
396 
397  B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg);
398 }
399 
400 void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &OrigArg,
402  Align Alignment) const {
403  MachineFunction &MF = B.getMF();
404  const Function &F = MF.getFunction();
405  const DataLayout &DL = F.getParent()->getDataLayout();
407 
409 
410  SmallVector<ArgInfo, 32> SplitArgs;
411  SmallVector<uint64_t> FieldOffsets;
412  splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv(), &FieldOffsets);
413 
414  unsigned Idx = 0;
415  for (ArgInfo &SplitArg : SplitArgs) {
416  Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy);
417  lowerParameterPtr(PtrReg, B, Offset + FieldOffsets[Idx]);
418 
419  LLT ArgTy = getLLTForType(*SplitArg.Ty, DL);
420  if (SplitArg.Flags[0].isPointer()) {
421  // Compensate for losing pointeriness in splitValueTypes.
422  LLT PtrTy = LLT::pointer(SplitArg.Flags[0].getPointerAddrSpace(),
423  ArgTy.getScalarSizeInBits());
424  ArgTy = ArgTy.isVector() ? LLT::vector(ArgTy.getElementCount(), PtrTy)
425  : PtrTy;
426  }
427 
429  PtrInfo,
432  ArgTy, commonAlignment(Alignment, FieldOffsets[Idx]));
433 
434  assert(SplitArg.Regs.size() == 1);
435 
436  B.buildLoad(SplitArg.Regs[0], PtrReg, *MMO);
437  ++Idx;
438  }
439 }
440 
441 // Allocate special inputs passed in user SGPRs.
442 static void allocateHSAUserSGPRs(CCState &CCInfo,
444  MachineFunction &MF,
445  const SIRegisterInfo &TRI,
447  // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
448  if (Info.hasPrivateSegmentBuffer()) {
449  Register PrivateSegmentBufferReg = Info.addPrivateSegmentBuffer(TRI);
450  MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
451  CCInfo.AllocateReg(PrivateSegmentBufferReg);
452  }
453 
454  if (Info.hasDispatchPtr()) {
455  Register DispatchPtrReg = Info.addDispatchPtr(TRI);
456  MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
457  CCInfo.AllocateReg(DispatchPtrReg);
458  }
459 
460  if (Info.hasQueuePtr()) {
461  Register QueuePtrReg = Info.addQueuePtr(TRI);
462  MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
463  CCInfo.AllocateReg(QueuePtrReg);
464  }
465 
466  if (Info.hasKernargSegmentPtr()) {
468  Register InputPtrReg = Info.addKernargSegmentPtr(TRI);
471  MRI.addLiveIn(InputPtrReg, VReg);
472  B.getMBB().addLiveIn(InputPtrReg);
473  B.buildCopy(VReg, InputPtrReg);
474  CCInfo.AllocateReg(InputPtrReg);
475  }
476 
477  if (Info.hasDispatchID()) {
478  Register DispatchIDReg = Info.addDispatchID(TRI);
479  MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
480  CCInfo.AllocateReg(DispatchIDReg);
481  }
482 
483  if (Info.hasFlatScratchInit()) {
484  Register FlatScratchInitReg = Info.addFlatScratchInit(TRI);
485  MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
486  CCInfo.AllocateReg(FlatScratchInitReg);
487  }
488 
489  // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
490  // these from the dispatch pointer.
491 }
492 
494  MachineIRBuilder &B, const Function &F,
495  ArrayRef<ArrayRef<Register>> VRegs) const {
496  MachineFunction &MF = B.getMF();
497  const GCNSubtarget *Subtarget = &MF.getSubtarget<GCNSubtarget>();
500  const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
501  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
502  const DataLayout &DL = F.getParent()->getDataLayout();
503 
504  Info->allocateModuleLDSGlobal(F.getParent());
505 
507  CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
508 
509  allocateHSAUserSGPRs(CCInfo, B, MF, *TRI, *Info);
510 
511  unsigned i = 0;
512  const Align KernArgBaseAlign(16);
513  const unsigned BaseOffset = Subtarget->getExplicitKernelArgOffset(F);
514  uint64_t ExplicitArgOffset = 0;
515 
516  // TODO: Align down to dword alignment and extract bits for extending loads.
517  for (auto &Arg : F.args()) {
518  const bool IsByRef = Arg.hasByRefAttr();
519  Type *ArgTy = IsByRef ? Arg.getParamByRefType() : Arg.getType();
520  unsigned AllocSize = DL.getTypeAllocSize(ArgTy);
521  if (AllocSize == 0)
522  continue;
523 
524  MaybeAlign ABIAlign = IsByRef ? Arg.getParamAlign() : None;
525  if (!ABIAlign)
526  ABIAlign = DL.getABITypeAlign(ArgTy);
527 
528  uint64_t ArgOffset = alignTo(ExplicitArgOffset, ABIAlign) + BaseOffset;
529  ExplicitArgOffset = alignTo(ExplicitArgOffset, ABIAlign) + AllocSize;
530 
531  if (Arg.use_empty()) {
532  ++i;
533  continue;
534  }
535 
536  Align Alignment = commonAlignment(KernArgBaseAlign, ArgOffset);
537 
538  if (IsByRef) {
539  unsigned ByRefAS = cast<PointerType>(Arg.getType())->getAddressSpace();
540 
541  assert(VRegs[i].size() == 1 &&
542  "expected only one register for byval pointers");
543  if (ByRefAS == AMDGPUAS::CONSTANT_ADDRESS) {
544  lowerParameterPtr(VRegs[i][0], B, ArgOffset);
545  } else {
546  const LLT ConstPtrTy = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
547  Register PtrReg = MRI.createGenericVirtualRegister(ConstPtrTy);
548  lowerParameterPtr(PtrReg, B, ArgOffset);
549 
550  B.buildAddrSpaceCast(VRegs[i][0], PtrReg);
551  }
552  } else {
553  ArgInfo OrigArg(VRegs[i], Arg, i);
554  const unsigned OrigArgIdx = i + AttributeList::FirstArgIndex;
555  setArgFlags(OrigArg, OrigArgIdx, DL, F);
556  lowerParameter(B, OrigArg, ArgOffset, Alignment);
557  }
558 
559  ++i;
560  }
561 
562  TLI.allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);
563  TLI.allocateSystemSGPRs(CCInfo, MF, *Info, F.getCallingConv(), false);
564  return true;
565 }
566 
569  FunctionLoweringInfo &FLI) const {
570  CallingConv::ID CC = F.getCallingConv();
571 
572  // The infrastructure for normal calling convention lowering is essentially
573  // useless for kernels. We want to avoid any kind of legalization or argument
574  // splitting.
575  if (CC == CallingConv::AMDGPU_KERNEL)
576  return lowerFormalArgumentsKernel(B, F, VRegs);
577 
578  const bool IsGraphics = AMDGPU::isGraphics(CC);
579  const bool IsEntryFunc = AMDGPU::isEntryFunctionCC(CC);
580 
581  MachineFunction &MF = B.getMF();
582  MachineBasicBlock &MBB = B.getMBB();
585  const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
586  const SIRegisterInfo *TRI = Subtarget.getRegisterInfo();
587  const DataLayout &DL = F.getParent()->getDataLayout();
588 
589  Info->allocateModuleLDSGlobal(F.getParent());
590 
592  CCState CCInfo(CC, F.isVarArg(), MF, ArgLocs, F.getContext());
593 
594  if (!IsEntryFunc) {
595  Register ReturnAddrReg = TRI->getReturnAddressReg(MF);
596  Register LiveInReturn = MF.addLiveIn(ReturnAddrReg,
597  &AMDGPU::SGPR_64RegClass);
598  MBB.addLiveIn(ReturnAddrReg);
599  B.buildCopy(LiveInReturn, ReturnAddrReg);
600  }
601 
602  if (Info->hasImplicitBufferPtr()) {
603  Register ImplicitBufferPtrReg = Info->addImplicitBufferPtr(*TRI);
604  MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
605  CCInfo.AllocateReg(ImplicitBufferPtrReg);
606  }
607 
608  SmallVector<ArgInfo, 32> SplitArgs;
609  unsigned Idx = 0;
610  unsigned PSInputNum = 0;
611 
612  // Insert the hidden sret parameter if the return value won't fit in the
613  // return registers.
614  if (!FLI.CanLowerReturn)
615  insertSRetIncomingArgument(F, SplitArgs, FLI.DemoteRegister, MRI, DL);
616 
617  for (auto &Arg : F.args()) {
618  if (DL.getTypeStoreSize(Arg.getType()) == 0)
619  continue;
620 
621  const bool InReg = Arg.hasAttribute(Attribute::InReg);
622 
623  // SGPR arguments to functions not implemented.
624  if (!IsGraphics && InReg)
625  return false;
626 
627  if (Arg.hasAttribute(Attribute::SwiftSelf) ||
628  Arg.hasAttribute(Attribute::SwiftError) ||
629  Arg.hasAttribute(Attribute::Nest))
630  return false;
631 
632  if (CC == CallingConv::AMDGPU_PS && !InReg && PSInputNum <= 15) {
633  const bool ArgUsed = !Arg.use_empty();
634  bool SkipArg = !ArgUsed && !Info->isPSInputAllocated(PSInputNum);
635 
636  if (!SkipArg) {
637  Info->markPSInputAllocated(PSInputNum);
638  if (ArgUsed)
639  Info->markPSInputEnabled(PSInputNum);
640  }
641 
642  ++PSInputNum;
643 
644  if (SkipArg) {
645  for (int I = 0, E = VRegs[Idx].size(); I != E; ++I)
646  B.buildUndef(VRegs[Idx][I]);
647 
648  ++Idx;
649  continue;
650  }
651  }
652 
653  ArgInfo OrigArg(VRegs[Idx], Arg, Idx);
654  const unsigned OrigArgIdx = Idx + AttributeList::FirstArgIndex;
655  setArgFlags(OrigArg, OrigArgIdx, DL, F);
656 
657  splitToValueTypes(OrigArg, SplitArgs, DL, CC);
658  ++Idx;
659  }
660 
661  // At least one interpolation mode must be enabled or else the GPU will
662  // hang.
663  //
664  // Check PSInputAddr instead of PSInputEnable. The idea is that if the user
665  // set PSInputAddr, the user wants to enable some bits after the compilation
666  // based on run-time states. Since we can't know what the final PSInputEna
667  // will look like, so we shouldn't do anything here and the user should take
668  // responsibility for the correct programming.
669  //
670  // Otherwise, the following restrictions apply:
671  // - At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled.
672  // - If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be
673  // enabled too.
674  if (CC == CallingConv::AMDGPU_PS) {
675  if ((Info->getPSInputAddr() & 0x7F) == 0 ||
676  ((Info->getPSInputAddr() & 0xF) == 0 &&
677  Info->isPSInputAllocated(11))) {
678  CCInfo.AllocateReg(AMDGPU::VGPR0);
679  CCInfo.AllocateReg(AMDGPU::VGPR1);
680  Info->markPSInputAllocated(0);
681  Info->markPSInputEnabled(0);
682  }
683 
684  if (Subtarget.isAmdPalOS()) {
685  // For isAmdPalOS, the user does not enable some bits after compilation
686  // based on run-time states; the register values being generated here are
687  // the final ones set in hardware. Therefore we need to apply the
688  // workaround to PSInputAddr and PSInputEnable together. (The case where
689  // a bit is set in PSInputAddr but not PSInputEnable is where the frontend
690  // set up an input arg for a particular interpolation mode, but nothing
691  // uses that input arg. Really we should have an earlier pass that removes
692  // such an arg.)
693  unsigned PsInputBits = Info->getPSInputAddr() & Info->getPSInputEnable();
694  if ((PsInputBits & 0x7F) == 0 ||
695  ((PsInputBits & 0xF) == 0 &&
696  (PsInputBits >> 11 & 1)))
697  Info->markPSInputEnabled(
698  countTrailingZeros(Info->getPSInputAddr(), ZB_Undefined));
699  }
700  }
701 
702  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
703  CCAssignFn *AssignFn = TLI.CCAssignFnForCall(CC, F.isVarArg());
704 
705  if (!MBB.empty())
706  B.setInstr(*MBB.begin());
707 
708  if (!IsEntryFunc) {
709  // For the fixed ABI, pass workitem IDs in the last argument register.
711  TLI.allocateSpecialInputVGPRsFixed(CCInfo, MF, *TRI, *Info);
712  }
713 
714  IncomingValueAssigner Assigner(AssignFn);
715  if (!determineAssignments(Assigner, SplitArgs, CCInfo))
716  return false;
717 
718  FormalArgHandler Handler(B, MRI);
719  if (!handleAssignments(Handler, SplitArgs, CCInfo, ArgLocs, B))
720  return false;
721 
722  uint64_t StackOffset = Assigner.StackOffset;
723 
724  if (!IsEntryFunc && !AMDGPUTargetMachine::EnableFixedFunctionABI) {
725  // Special inputs come after user arguments.
726  TLI.allocateSpecialInputVGPRs(CCInfo, MF, *TRI, *Info);
727  }
728 
729  // Start adding system SGPRs.
730  if (IsEntryFunc) {
731  TLI.allocateSystemSGPRs(CCInfo, MF, *Info, CC, IsGraphics);
732  } else {
733  if (!Subtarget.enableFlatScratch())
734  CCInfo.AllocateReg(Info->getScratchRSrcReg());
735  TLI.allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);
736  }
737 
738  // When we tail call, we need to check if the callee's arguments will fit on
739  // the caller's stack. So, whenever we lower formal arguments, we should keep
740  // track of this information, since we might lower a tail call in this
741  // function later.
742  Info->setBytesInStackArgArea(StackOffset);
743 
744  // Move back to the end of the basic block.
745  B.setMBB(MBB);
746 
747  return true;
748 }
749 
751  CCState &CCInfo,
752  SmallVectorImpl<std::pair<MCRegister, Register>> &ArgRegs,
753  CallLoweringInfo &Info) const {
754  MachineFunction &MF = MIRBuilder.getMF();
755 
756  // If there's no call site, this doesn't correspond to a call from the IR and
757  // doesn't need implicit inputs.
758  if (!Info.CB)
759  return true;
760 
761  const AMDGPUFunctionArgInfo *CalleeArgInfo
763 
765  const AMDGPUFunctionArgInfo &CallerArgInfo = MFI->getArgInfo();
766 
767 
768  // TODO: Unify with private memory register handling. This is complicated by
769  // the fact that at least in kernels, the input argument is not necessarily
770  // in the same location as the input.
779  };
780 
781  static constexpr StringLiteral ImplicitAttrNames[] = {
782  "amdgpu-no-dispatch-ptr",
783  "amdgpu-no-queue-ptr",
784  "amdgpu-no-implicitarg-ptr",
785  "amdgpu-no-dispatch-id",
786  "amdgpu-no-workgroup-id-x",
787  "amdgpu-no-workgroup-id-y",
788  "amdgpu-no-workgroup-id-z"
789  };
790 
792 
793  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
794  const AMDGPULegalizerInfo *LI
795  = static_cast<const AMDGPULegalizerInfo*>(ST.getLegalizerInfo());
796 
797  unsigned I = 0;
798  for (auto InputID : InputRegs) {
799  const ArgDescriptor *OutgoingArg;
800  const TargetRegisterClass *ArgRC;
801  LLT ArgTy;
802 
803  // If the callee does not use the attribute value, skip copying the value.
804  if (Info.CB->hasFnAttr(ImplicitAttrNames[I++]))
805  continue;
806 
807  std::tie(OutgoingArg, ArgRC, ArgTy) =
808  CalleeArgInfo->getPreloadedValue(InputID);
809  if (!OutgoingArg)
810  continue;
811 
812  const ArgDescriptor *IncomingArg;
813  const TargetRegisterClass *IncomingArgRC;
814  std::tie(IncomingArg, IncomingArgRC, ArgTy) =
815  CallerArgInfo.getPreloadedValue(InputID);
816  assert(IncomingArgRC == ArgRC);
817 
818  Register InputReg = MRI.createGenericVirtualRegister(ArgTy);
819 
820  if (IncomingArg) {
821  LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy);
822  } else {
824  LI->getImplicitArgPtr(InputReg, MRI, MIRBuilder);
825  }
826 
827  if (OutgoingArg->isRegister()) {
828  ArgRegs.emplace_back(OutgoingArg->getRegister(), InputReg);
829  if (!CCInfo.AllocateReg(OutgoingArg->getRegister()))
830  report_fatal_error("failed to allocate implicit input argument");
831  } else {
832  LLVM_DEBUG(dbgs() << "Unhandled stack passed implicit input argument\n");
833  return false;
834  }
835  }
836 
837  // Pack workitem IDs into a single register or pass it as is if already
838  // packed.
839  const ArgDescriptor *OutgoingArg;
840  const TargetRegisterClass *ArgRC;
841  LLT ArgTy;
842 
843  std::tie(OutgoingArg, ArgRC, ArgTy) =
845  if (!OutgoingArg)
846  std::tie(OutgoingArg, ArgRC, ArgTy) =
848  if (!OutgoingArg)
849  std::tie(OutgoingArg, ArgRC, ArgTy) =
851  if (!OutgoingArg)
852  return false;
853 
854  auto WorkitemIDX =
855  CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X);
856  auto WorkitemIDY =
857  CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y);
858  auto WorkitemIDZ =
859  CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z);
860 
861  const ArgDescriptor *IncomingArgX = std::get<0>(WorkitemIDX);
862  const ArgDescriptor *IncomingArgY = std::get<0>(WorkitemIDY);
863  const ArgDescriptor *IncomingArgZ = std::get<0>(WorkitemIDZ);
864  const LLT S32 = LLT::scalar(32);
865 
866  const bool NeedWorkItemIDX = !Info.CB->hasFnAttr("amdgpu-no-workitem-id-x");
867  const bool NeedWorkItemIDY = !Info.CB->hasFnAttr("amdgpu-no-workitem-id-y");
868  const bool NeedWorkItemIDZ = !Info.CB->hasFnAttr("amdgpu-no-workitem-id-z");
869 
870  // If incoming ids are not packed we need to pack them.
871  // FIXME: Should consider known workgroup size to eliminate known 0 cases.
872  Register InputReg;
873  if (IncomingArgX && !IncomingArgX->isMasked() && CalleeArgInfo->WorkItemIDX &&
874  NeedWorkItemIDX) {
875  InputReg = MRI.createGenericVirtualRegister(S32);
876  LI->loadInputValue(InputReg, MIRBuilder, IncomingArgX,
877  std::get<1>(WorkitemIDX), std::get<2>(WorkitemIDX));
878  }
879 
880  if (IncomingArgY && !IncomingArgY->isMasked() && CalleeArgInfo->WorkItemIDY &&
881  NeedWorkItemIDY) {
883  LI->loadInputValue(Y, MIRBuilder, IncomingArgY, std::get<1>(WorkitemIDY),
884  std::get<2>(WorkitemIDY));
885 
886  Y = MIRBuilder.buildShl(S32, Y, MIRBuilder.buildConstant(S32, 10)).getReg(0);
887  InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Y).getReg(0) : Y;
888  }
889 
890  if (IncomingArgZ && !IncomingArgZ->isMasked() && CalleeArgInfo->WorkItemIDZ &&
891  NeedWorkItemIDZ) {
893  LI->loadInputValue(Z, MIRBuilder, IncomingArgZ, std::get<1>(WorkitemIDZ),
894  std::get<2>(WorkitemIDZ));
895 
896  Z = MIRBuilder.buildShl(S32, Z, MIRBuilder.buildConstant(S32, 20)).getReg(0);
897  InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Z).getReg(0) : Z;
898  }
899 
900  if (!InputReg && (NeedWorkItemIDX || NeedWorkItemIDY || NeedWorkItemIDZ)) {
901  InputReg = MRI.createGenericVirtualRegister(S32);
902 
903  // Workitem ids are already packed, any of present incoming arguments will
904  // carry all required fields.
906  IncomingArgX ? *IncomingArgX :
907  IncomingArgY ? *IncomingArgY : *IncomingArgZ, ~0u);
908  LI->loadInputValue(InputReg, MIRBuilder, &IncomingArg,
909  &AMDGPU::VGPR_32RegClass, S32);
910  }
911 
912  if (OutgoingArg->isRegister()) {
913  if (InputReg)
914  ArgRegs.emplace_back(OutgoingArg->getRegister(), InputReg);
915 
916  if (!CCInfo.AllocateReg(OutgoingArg->getRegister()))
917  report_fatal_error("failed to allocate implicit input argument");
918  } else {
919  LLVM_DEBUG(dbgs() << "Unhandled stack passed implicit input argument\n");
920  return false;
921  }
922 
923  return true;
924 }
925 
926 /// Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for
927 /// CC.
928 static std::pair<CCAssignFn *, CCAssignFn *>
930  return {TLI.CCAssignFnForCall(CC, false), TLI.CCAssignFnForCall(CC, true)};
931 }
932 
933 static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect,
934  bool IsTailCall) {
935  return IsTailCall ? AMDGPU::SI_TCRETURN : AMDGPU::SI_CALL;
936 }
937 
938 // Add operands to call instruction to track the callee.
940  MachineIRBuilder &MIRBuilder,
941  AMDGPUCallLowering::CallLoweringInfo &Info) {
942  if (Info.Callee.isReg()) {
943  CallInst.addReg(Info.Callee.getReg());
944  CallInst.addImm(0);
945  } else if (Info.Callee.isGlobal() && Info.Callee.getOffset() == 0) {
946  // The call lowering lightly assumed we can directly encode a call target in
947  // the instruction, which is not the case. Materialize the address here.
948  const GlobalValue *GV = Info.Callee.getGlobal();
949  auto Ptr = MIRBuilder.buildGlobalValue(
950  LLT::pointer(GV->getAddressSpace(), 64), GV);
951  CallInst.addReg(Ptr.getReg(0));
952  CallInst.add(Info.Callee);
953  } else
954  return false;
955 
956  return true;
957 }
958 
961  SmallVectorImpl<ArgInfo> &InArgs) const {
962  const Function &CallerF = MF.getFunction();
963  CallingConv::ID CalleeCC = Info.CallConv;
964  CallingConv::ID CallerCC = CallerF.getCallingConv();
965 
966  // If the calling conventions match, then everything must be the same.
967  if (CalleeCC == CallerCC)
968  return true;
969 
970  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
971 
972  // Make sure that the caller and callee preserve all of the same registers.
973  auto TRI = ST.getRegisterInfo();
974 
975  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
976  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
977  if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
978  return false;
979 
980  // Check if the caller and callee will handle arguments in the same way.
981  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
982  CCAssignFn *CalleeAssignFnFixed;
983  CCAssignFn *CalleeAssignFnVarArg;
984  std::tie(CalleeAssignFnFixed, CalleeAssignFnVarArg) =
985  getAssignFnsForCC(CalleeCC, TLI);
986 
987  CCAssignFn *CallerAssignFnFixed;
988  CCAssignFn *CallerAssignFnVarArg;
989  std::tie(CallerAssignFnFixed, CallerAssignFnVarArg) =
990  getAssignFnsForCC(CallerCC, TLI);
991 
992  // FIXME: We are not accounting for potential differences in implicitly passed
993  // inputs, but only the fixed ABI is supported now anyway.
994  IncomingValueAssigner CalleeAssigner(CalleeAssignFnFixed,
995  CalleeAssignFnVarArg);
996  IncomingValueAssigner CallerAssigner(CallerAssignFnFixed,
997  CallerAssignFnVarArg);
998  return resultsCompatible(Info, MF, InArgs, CalleeAssigner, CallerAssigner);
999 }
1000 
1003  SmallVectorImpl<ArgInfo> &OutArgs) const {
1004  // If there are no outgoing arguments, then we are done.
1005  if (OutArgs.empty())
1006  return true;
1007 
1008  const Function &CallerF = MF.getFunction();
1009  CallingConv::ID CalleeCC = Info.CallConv;
1010  CallingConv::ID CallerCC = CallerF.getCallingConv();
1011  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
1012 
1013  CCAssignFn *AssignFnFixed;
1014  CCAssignFn *AssignFnVarArg;
1015  std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
1016 
1017  // We have outgoing arguments. Make sure that we can tail call with them.
1019  CCState OutInfo(CalleeCC, false, MF, OutLocs, CallerF.getContext());
1020  OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg);
1021 
1022  if (!determineAssignments(Assigner, OutArgs, OutInfo)) {
1023  LLVM_DEBUG(dbgs() << "... Could not analyze call operands.\n");
1024  return false;
1025  }
1026 
1027  // Make sure that they can fit on the caller's stack.
1028  const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
1029  if (OutInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea()) {
1030  LLVM_DEBUG(dbgs() << "... Cannot fit call operands on caller's stack.\n");
1031  return false;
1032  }
1033 
1034  // Verify that the parameters in callee-saved registers match.
1035  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1036  const SIRegisterInfo *TRI = ST.getRegisterInfo();
1037  const uint32_t *CallerPreservedMask = TRI->getCallPreservedMask(MF, CallerCC);
1039  return parametersInCSRMatch(MRI, CallerPreservedMask, OutLocs, OutArgs);
1040 }
1041 
1042 /// Return true if the calling convention is one that we can guarantee TCO for.
1044  return CC == CallingConv::Fast;
1045 }
1046 
1047 /// Return true if we might ever do TCO for calls with this calling convention.
1049  switch (CC) {
1050  case CallingConv::C:
1052  return true;
1053  default:
1054  return canGuaranteeTCO(CC);
1055  }
1056 }
1057 
1060  SmallVectorImpl<ArgInfo> &InArgs, SmallVectorImpl<ArgInfo> &OutArgs) const {
1061  // Must pass all target-independent checks in order to tail call optimize.
1062  if (!Info.IsTailCall)
1063  return false;
1064 
1065  MachineFunction &MF = B.getMF();
1066  const Function &CallerF = MF.getFunction();
1067  CallingConv::ID CalleeCC = Info.CallConv;
1068  CallingConv::ID CallerCC = CallerF.getCallingConv();
1069 
1070  const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
1071  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
1072  // Kernels aren't callable, and don't have a live in return address so it
1073  // doesn't make sense to do a tail call with entry functions.
1074  if (!CallerPreserved)
1075  return false;
1076 
1077  if (!mayTailCallThisCC(CalleeCC)) {
1078  LLVM_DEBUG(dbgs() << "... Calling convention cannot be tail called.\n");
1079  return false;
1080  }
1081 
1082  if (any_of(CallerF.args(), [](const Argument &A) {
1083  return A.hasByValAttr() || A.hasSwiftErrorAttr();
1084  })) {
1085  LLVM_DEBUG(dbgs() << "... Cannot tail call from callers with byval "
1086  "or swifterror arguments\n");
1087  return false;
1088  }
1089 
1090  // If we have -tailcallopt, then we're done.
1092  return canGuaranteeTCO(CalleeCC) && CalleeCC == CallerF.getCallingConv();
1093 
1094  // Verify that the incoming and outgoing arguments from the callee are
1095  // safe to tail call.
1096  if (!doCallerAndCalleePassArgsTheSameWay(Info, MF, InArgs)) {
1097  LLVM_DEBUG(
1098  dbgs()
1099  << "... Caller and callee have incompatible calling conventions.\n");
1100  return false;
1101  }
1102 
1103  if (!areCalleeOutgoingArgsTailCallable(Info, MF, OutArgs))
1104  return false;
1105 
1106  LLVM_DEBUG(dbgs() << "... Call is eligible for tail call optimization.\n");
1107  return true;
1108 }
1109 
1110 // Insert outgoing implicit arguments for a call, by inserting copies to the
1111 // implicit argument registers and adding the necessary implicit uses to the
1112 // call instruction.
1115  const GCNSubtarget &ST, const SIMachineFunctionInfo &FuncInfo,
1116  ArrayRef<std::pair<MCRegister, Register>> ImplicitArgRegs) const {
1117  if (!ST.enableFlatScratch()) {
1118  // Insert copies for the SRD. In the HSA case, this should be an identity
1119  // copy.
1120  auto ScratchRSrcReg = MIRBuilder.buildCopy(LLT::fixed_vector(4, 32),
1121  FuncInfo.getScratchRSrcReg());
1122  MIRBuilder.buildCopy(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg);
1123  CallInst.addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Implicit);
1124  }
1125 
1126  for (std::pair<MCRegister, Register> ArgReg : ImplicitArgRegs) {
1127  MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second);
1128  CallInst.addReg(ArgReg.first, RegState::Implicit);
1129  }
1130 }
1131 
1133  MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
1134  SmallVectorImpl<ArgInfo> &OutArgs) const {
1135  MachineFunction &MF = MIRBuilder.getMF();
1136  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1138  const Function &F = MF.getFunction();
1140  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
1141 
1142  // True when we're tail calling, but without -tailcallopt.
1143  bool IsSibCall = !MF.getTarget().Options.GuaranteedTailCallOpt;
1144 
1145  // Find out which ABI gets to decide where things go.
1146  CallingConv::ID CalleeCC = Info.CallConv;
1147  CCAssignFn *AssignFnFixed;
1148  CCAssignFn *AssignFnVarArg;
1149  std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
1150 
1151  MachineInstrBuilder CallSeqStart;
1152  if (!IsSibCall)
1153  CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP);
1154 
1155  unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), true);
1156  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1157  if (!addCallTargetOperands(MIB, MIRBuilder, Info))
1158  return false;
1159 
1160  // Byte offset for the tail call. When we are sibcalling, this will always
1161  // be 0.
1162  MIB.addImm(0);
1163 
1164  // Tell the call which registers are clobbered.
1165  const SIRegisterInfo *TRI = ST.getRegisterInfo();
1166  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CalleeCC);
1167  MIB.addRegMask(Mask);
1168 
1169  // FPDiff is the byte offset of the call's argument area from the callee's.
1170  // Stores to callee stack arguments will be placed in FixedStackSlots offset
1171  // by this amount for a tail call. In a sibling call it must be 0 because the
1172  // caller will deallocate the entire stack and the callee still expects its
1173  // arguments to begin at SP+0.
1174  int FPDiff = 0;
1175 
1176  // This will be 0 for sibcalls, potentially nonzero for tail calls produced
1177  // by -tailcallopt. For sibcalls, the memory operands for the call are
1178  // already available in the caller's incoming argument space.
1179  unsigned NumBytes = 0;
1180  if (!IsSibCall) {
1181  // We aren't sibcalling, so we need to compute FPDiff. We need to do this
1182  // before handling assignments, because FPDiff must be known for memory
1183  // arguments.
1184  unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
1186  CCState OutInfo(CalleeCC, false, MF, OutLocs, F.getContext());
1187 
1188  // FIXME: Not accounting for callee implicit inputs
1189  OutgoingValueAssigner CalleeAssigner(AssignFnFixed, AssignFnVarArg);
1190  if (!determineAssignments(CalleeAssigner, OutArgs, OutInfo))
1191  return false;
1192 
1193  // The callee will pop the argument stack as a tail call. Thus, we must
1194  // keep it 16-byte aligned.
1195  NumBytes = alignTo(OutInfo.getNextStackOffset(), ST.getStackAlignment());
1196 
1197  // FPDiff will be negative if this tail call requires more space than we
1198  // would automatically have in our incoming argument space. Positive if we
1199  // actually shrink the stack.
1200  FPDiff = NumReusableBytes - NumBytes;
1201 
1202  // The stack pointer must be 16-byte aligned at all times it's used for a
1203  // memory operation, which in practice means at *all* times and in
1204  // particular across call boundaries. Therefore our own arguments started at
1205  // a 16-byte aligned SP and the delta applied for the tail call should
1206  // satisfy the same constraint.
1207  assert(isAligned(ST.getStackAlignment(), FPDiff) &&
1208  "unaligned stack on tail call");
1209  }
1210 
1212  CCState CCInfo(Info.CallConv, Info.IsVarArg, MF, ArgLocs, F.getContext());
1213 
1214  // We could pass MIB and directly add the implicit uses to the call
1215  // now. However, as an aesthetic choice, place implicit argument operands
1216  // after the ordinary user argument registers.
1217  SmallVector<std::pair<MCRegister, Register>, 12> ImplicitArgRegs;
1218 
1220  Info.CallConv != CallingConv::AMDGPU_Gfx) {
1221  // With a fixed ABI, allocate fixed registers before user arguments.
1222  if (!passSpecialInputs(MIRBuilder, CCInfo, ImplicitArgRegs, Info))
1223  return false;
1224  }
1225 
1226  OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg);
1227 
1228  if (!determineAssignments(Assigner, OutArgs, CCInfo))
1229  return false;
1230 
1231  // Do the actual argument marshalling.
1232  AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, true, FPDiff);
1233  if (!handleAssignments(Handler, OutArgs, CCInfo, ArgLocs, MIRBuilder))
1234  return false;
1235 
1236  handleImplicitCallArguments(MIRBuilder, MIB, ST, *FuncInfo, ImplicitArgRegs);
1237 
1238  // If we have -tailcallopt, we need to adjust the stack. We'll do the call
1239  // sequence start and end here.
1240  if (!IsSibCall) {
1241  MIB->getOperand(1).setImm(FPDiff);
1242  CallSeqStart.addImm(NumBytes).addImm(0);
1243  // End the call sequence *before* emitting the call. Normally, we would
1244  // tidy the frame up after the call. However, here, we've laid out the
1245  // parameters so that when SP is reset, they will be in the correct
1246  // location.
1247  MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN).addImm(NumBytes).addImm(0);
1248  }
1249 
1250  // Now we can add the actual call instruction to the correct basic block.
1251  MIRBuilder.insertInstr(MIB);
1252 
1253  // If Callee is a reg, since it is used by a target specific
1254  // instruction, it must have a register class matching the
1255  // constraint of that instruction.
1256 
1257  // FIXME: We should define regbankselectable call instructions to handle
1258  // divergent call targets.
1259  if (MIB->getOperand(0).isReg()) {
1261  MF, *TRI, MRI, *ST.getInstrInfo(), *ST.getRegBankInfo(), *MIB,
1262  MIB->getDesc(), MIB->getOperand(0), 0));
1263  }
1264 
1266  Info.LoweredTailCall = true;
1267  return true;
1268 }
1269 
1271  CallLoweringInfo &Info) const {
1272  if (Info.IsVarArg) {
1273  LLVM_DEBUG(dbgs() << "Variadic functions not implemented\n");
1274  return false;
1275  }
1276 
1277  MachineFunction &MF = MIRBuilder.getMF();
1278  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1279  const SIRegisterInfo *TRI = ST.getRegisterInfo();
1280 
1281  const Function &F = MF.getFunction();
1283  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
1284  const DataLayout &DL = F.getParent()->getDataLayout();
1285 
1287  Info.CallConv != CallingConv::AMDGPU_Gfx) {
1288  LLVM_DEBUG(dbgs() << "Variable function ABI not implemented\n");
1289  return false;
1290  }
1291 
1292  SmallVector<ArgInfo, 8> OutArgs;
1293  for (auto &OrigArg : Info.OrigArgs)
1294  splitToValueTypes(OrigArg, OutArgs, DL, Info.CallConv);
1295 
1296  SmallVector<ArgInfo, 8> InArgs;
1297  if (Info.CanLowerReturn && !Info.OrigRet.Ty->isVoidTy())
1298  splitToValueTypes(Info.OrigRet, InArgs, DL, Info.CallConv);
1299 
1300  // If we can lower as a tail call, do that instead.
1301  bool CanTailCallOpt =
1302  isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs);
1303 
1304  // We must emit a tail call if we have musttail.
1305  if (Info.IsMustTailCall && !CanTailCallOpt) {
1306  LLVM_DEBUG(dbgs() << "Failed to lower musttail call as tail call\n");
1307  return false;
1308  }
1309 
1310  if (CanTailCallOpt)
1311  return lowerTailCall(MIRBuilder, Info, OutArgs);
1312 
1313  // Find out which ABI gets to decide where things go.
1314  CCAssignFn *AssignFnFixed;
1315  CCAssignFn *AssignFnVarArg;
1316  std::tie(AssignFnFixed, AssignFnVarArg) =
1317  getAssignFnsForCC(Info.CallConv, TLI);
1318 
1319  MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP)
1320  .addImm(0)
1321  .addImm(0);
1322 
1323  // Create a temporarily-floating call instruction so we can add the implicit
1324  // uses of arg registers.
1325  unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), false);
1326 
1327  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1328  MIB.addDef(TRI->getReturnAddressReg(MF));
1329 
1330  if (!addCallTargetOperands(MIB, MIRBuilder, Info))
1331  return false;
1332 
1333  // Tell the call which registers are clobbered.
1334  const uint32_t *Mask = TRI->getCallPreservedMask(MF, Info.CallConv);
1335  MIB.addRegMask(Mask);
1336 
1338  CCState CCInfo(Info.CallConv, Info.IsVarArg, MF, ArgLocs, F.getContext());
1339 
1340  // We could pass MIB and directly add the implicit uses to the call
1341  // now. However, as an aesthetic choice, place implicit argument operands
1342  // after the ordinary user argument registers.
1343  SmallVector<std::pair<MCRegister, Register>, 12> ImplicitArgRegs;
1344 
1346  Info.CallConv != CallingConv::AMDGPU_Gfx) {
1347  // With a fixed ABI, allocate fixed registers before user arguments.
1348  if (!passSpecialInputs(MIRBuilder, CCInfo, ImplicitArgRegs, Info))
1349  return false;
1350  }
1351 
1352  // Do the actual argument marshalling.
1353  SmallVector<Register, 8> PhysRegs;
1354 
1355  OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg);
1356  if (!determineAssignments(Assigner, OutArgs, CCInfo))
1357  return false;
1358 
1359  AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, false);
1360  if (!handleAssignments(Handler, OutArgs, CCInfo, ArgLocs, MIRBuilder))
1361  return false;
1362 
1364 
1365  handleImplicitCallArguments(MIRBuilder, MIB, ST, *MFI, ImplicitArgRegs);
1366 
1367  // Get a count of how many bytes are to be pushed on the stack.
1368  unsigned NumBytes = CCInfo.getNextStackOffset();
1369 
1370  // If Callee is a reg, since it is used by a target specific
1371  // instruction, it must have a register class matching the
1372  // constraint of that instruction.
1373 
1374  // FIXME: We should define regbankselectable call instructions to handle
1375  // divergent call targets.
1376  if (MIB->getOperand(1).isReg()) {
1377  MIB->getOperand(1).setReg(constrainOperandRegClass(
1378  MF, *TRI, MRI, *ST.getInstrInfo(),
1379  *ST.getRegBankInfo(), *MIB, MIB->getDesc(), MIB->getOperand(1),
1380  1));
1381  }
1382 
1383  // Now we can add the actual call instruction to the correct position.
1384  MIRBuilder.insertInstr(MIB);
1385 
1386  // Finally we can copy the returned value back into its virtual-register. In
1387  // symmetry with the arguments, the physical register must be an
1388  // implicit-define of the call instruction.
1389  if (Info.CanLowerReturn && !Info.OrigRet.Ty->isVoidTy()) {
1390  CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv,
1391  Info.IsVarArg);
1392  IncomingValueAssigner Assigner(RetAssignFn);
1393  CallReturnHandler Handler(MIRBuilder, MRI, MIB);
1394  if (!determineAndHandleAssignments(Handler, Assigner, InArgs, MIRBuilder,
1395  Info.CallConv, Info.IsVarArg))
1396  return false;
1397  }
1398 
1399  uint64_t CalleePopBytes = NumBytes;
1400 
1401  MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN)
1402  .addImm(0)
1403  .addImm(CalleePopBytes);
1404 
1405  if (!Info.CanLowerReturn) {
1406  insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs,
1407  Info.DemoteRegister, Info.DemoteStackIndex);
1408  }
1409 
1410  return true;
1411 }
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:153
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:944
i
i
Definition: README.txt:29
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::AMDGPUFunctionArgInfo::PreloadedValue
PreloadedValue
Definition: AMDGPUArgumentUsageInfo.h:98
llvm::SIMachineFunctionInfo::setIfReturnsVoid
void setIfReturnsVoid(bool Value)
Definition: SIMachineFunctionInfo.h:848
llvm::AMDGPUFunctionArgInfo::QUEUE_PTR
@ QUEUE_PTR
Definition: AMDGPUArgumentUsageInfo.h:102
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::AMDGPUTargetMachine::EnableFixedFunctionABI
static bool EnableFixedFunctionABI
Definition: AMDGPUTargetMachine.h:39
llvm::AMDGPUCallLowering::handleImplicitCallArguments
void handleImplicitCallArguments(MachineIRBuilder &MIRBuilder, MachineInstrBuilder &CallInst, const GCNSubtarget &ST, const SIMachineFunctionInfo &MFI, ArrayRef< std::pair< MCRegister, Register >> ImplicitArgRegs) const
Definition: AMDGPUCallLowering.cpp:1113
llvm::isAligned
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
Definition: Alignment.h:138
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::TargetOptions::GuaranteedTailCallOpt
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
Definition: TargetOptions.h:213
llvm::MachineIRBuilder::buildGlobalValue
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
Definition: MachineIRBuilder.cpp:146
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::Function::args
iterator_range< arg_iterator > args()
Definition: Function.h:772
llvm::MachineIRBuilder::buildOr
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_OR Op0, Op1.
Definition: MachineIRBuilder.h:1520
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:150
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::SIMachineFunctionInfo::getPreloadedReg
MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const
Definition: SIMachineFunctionInfo.h:704
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:213
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::AMDGPUTargetLowering
Definition: AMDGPUISelLowering.h:27
llvm::CallLowering::handleAssignments
bool handleAssignments(ValueHandler &Handler, SmallVectorImpl< ArgInfo > &Args, CCState &CCState, SmallVectorImpl< CCValAssign > &ArgLocs, MachineIRBuilder &MIRBuilder, Register ThisReturnReg=Register()) const
Use Handler to insert code to handle the argument/return values represented by Args.
Definition: CallLowering.cpp:607
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
SIMachineFunctionInfo.h
llvm::ArgDescriptor::createArg
static constexpr ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask)
Definition: AMDGPUArgumentUsageInfo.h:54
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::SITargetLowering::allocateSystemSGPRs
void allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF, SIMachineFunctionInfo &Info, CallingConv::ID CallConv, bool IsShader) const
Definition: SIISelLowering.cpp:2136
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::Function
Definition: Function.h:61
allocateHSAUserSGPRs
static void allocateHSAUserSGPRs(CCState &CCInfo, MachineIRBuilder &B, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info)
Definition: AMDGPUCallLowering.cpp:442
llvm::AMDGPUCallLowering::AMDGPUCallLowering
AMDGPUCallLowering(const AMDGPUTargetLowering &TLI)
Definition: AMDGPUCallLowering.cpp:235
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::SIMachineFunctionInfo::getArgInfo
AMDGPUFunctionArgInfo & getArgInfo()
Definition: SIMachineFunctionInfo.h:691
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::CallLowering::ValueHandler::extendRegister
Register extendRegister(Register ValReg, CCValAssign &VA, unsigned MaxSizeBits=0)
Extend a register to the location type given in VA, capped at extending to at most MaxSize bits.
Definition: CallLowering.cpp:1066
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:145
llvm::AMDGPUArgumentUsageInfo::FixedABIFunctionInfo
static const AMDGPUFunctionArgInfo FixedABIFunctionInfo
Definition: AMDGPUArgumentUsageInfo.h:166
llvm::CallLowering::ValueHandler
Definition: CallLowering.h:225
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:732
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::CallLowering::OutgoingValueHandler
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:326
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:143
llvm::MachineRegisterInfo::getLiveInVirtReg
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
Definition: MachineRegisterInfo.cpp:454
llvm::CallLowering::splitToValueTypes
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
Definition: CallLowering.cpp:211
addCallTargetOperands
static bool addCallTargetOperands(MachineInstrBuilder &CallInst, MachineIRBuilder &MIRBuilder, AMDGPUCallLowering::CallLoweringInfo &Info)
Definition: AMDGPUCallLowering.cpp:939
llvm::AMDGPUCallLowering::lowerCall
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: AMDGPUCallLowering.cpp:1270
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::LLT::vector
static LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:57
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:40
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
MachineIRBuilder.h
llvm::AMDGPUCallLowering::isEligibleForTailCallOptimization
bool isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &InArgs, SmallVectorImpl< ArgInfo > &OutArgs) const
Returns true if the call can be lowered as a tail call.
Definition: AMDGPUCallLowering.cpp:1058
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::FunctionLoweringInfo::CanLowerReturn
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
Definition: FunctionLoweringInfo.h:63
llvm::ZB_Undefined
@ ZB_Undefined
The returned value is undefined.
Definition: MathExtras.h:46
llvm::GCNSubtarget::getRegisterInfo
const SIRegisterInfo * getRegisterInfo() const override
Definition: GCNSubtarget.h:225
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
extOpcodeToISDExtOpcode
static ISD::NodeType extOpcodeToISDExtOpcode(unsigned MIOpc)
Definition: AMDGPUCallLowering.cpp:240
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_X
@ WORKGROUP_ID_X
Definition: AMDGPUArgumentUsageInfo.h:106
llvm::AMDGPULegalizerInfo
This class provides the information for the target register banks.
Definition: AMDGPULegalizerInfo.h:32
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:255
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:216
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:124
llvm::AMDGPU::isKernel
LLVM_READNONE bool isKernel(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.h:723
llvm::getLLTForType
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
Definition: LowLevelType.cpp:21
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::LLT::fixed_vector
static LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:75
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::SIMachineFunctionInfo::returnsVoid
bool returnsVoid() const
Definition: SIMachineFunctionInfo.h:844
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::StringLiteral
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:891
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
llvm::FunctionLoweringInfo::DemoteRegister
Register DemoteRegister
DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg allocated to hold a pointer to ...
Definition: FunctionLoweringInfo.h:70
llvm::AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR
@ KERNARG_SEGMENT_PTR
Definition: AMDGPUArgumentUsageInfo.h:103
llvm::AMDGPUFunctionArgInfo
Definition: AMDGPUArgumentUsageInfo.h:97
llvm::CallLowering::resultsCompatible
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, ValueAssigner &CalleeAssigner, ValueAssigner &CallerAssigner) const
Definition: CallLowering.cpp:966
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
llvm::AMDGPU::isShader
bool isShader(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1358
llvm::AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR
@ IMPLICIT_ARG_PTR
Definition: AMDGPUArgumentUsageInfo.h:111
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:729
llvm::MachineIRBuilder::buildShl
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1476
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
FunctionLoweringInfo.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:724
llvm::AMDGPUFunctionArgInfo::WorkItemIDX
ArgDescriptor WorkItemIDX
Definition: AMDGPUArgumentUsageInfo.h:148
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:61
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_Y
@ WORKITEM_ID_Y
Definition: AMDGPUArgumentUsageInfo.h:115
llvm::FormalArgHandler
Definition: M68kCallLowering.h:65
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::CallLowering::OutgoingValueAssigner
Definition: CallLowering.h:219
llvm::AMDGPUCallLowering::lowerFormalArgumentsKernel
bool lowerFormalArgumentsKernel(MachineIRBuilder &B, const Function &F, ArrayRef< ArrayRef< Register >> VRegs) const
Definition: AMDGPUCallLowering.cpp:493
llvm::CallLowering::determineAssignments
bool determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const
Analyze the argument list in Args, using Assigner to populate CCInfo.
Definition: CallLowering.cpp:546
llvm::SIMachineFunctionInfo::getStackPtrOffsetReg
Register getStackPtrOffsetReg() const
Definition: SIMachineFunctionInfo.h:764
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:262
llvm::CallLowering::IncomingValueHandler
Base class for ValueHandlers used for arguments coming into the current function, or for return value...
Definition: CallLowering.h:311
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:28
llvm::AMDGPUCallLowering::passSpecialInputs
bool passSpecialInputs(MachineIRBuilder &MIRBuilder, CCState &CCInfo, SmallVectorImpl< std::pair< MCRegister, Register >> &ArgRegs, CallLoweringInfo &Info) const
Definition: AMDGPUCallLowering.cpp:750
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:155
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:151
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::None
const NoneType None
Definition: None.h:23
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:181
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::AMDGPUTargetLowering::getTypeForExtReturn
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType ExtendKind) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
Definition: AMDGPUISelLowering.cpp:733
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SITargetLowering::allocateSpecialInputVGPRsFixed
void allocateSpecialInputVGPRsFixed(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments in fixed registers.
Definition: SIISelLowering.cpp:2030
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1381
llvm::AMDGPUCallLowering::lowerTailCall
bool lowerTailCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &OutArgs) const
Definition: AMDGPUCallLowering.cpp:1132
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:491
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:50
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:401
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::AMDGPUFunctionArgInfo::getPreloadedValue
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(PreloadedValue Value) const
Definition: AMDGPUArgumentUsageInfo.cpp:89
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:212
llvm::AMDGPUCallLowering::doCallerAndCalleePassArgsTheSameWay
bool doCallerAndCalleePassArgsTheSameWay(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs) const
Definition: AMDGPUCallLowering.cpp:959
llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Z
@ WORKGROUP_ID_Z
Definition: AMDGPUArgumentUsageInfo.h:108
canGuaranteeTCO
static bool canGuaranteeTCO(CallingConv::ID CC)
Return true if the calling convention is one that we can guarantee TCO for.
Definition: AMDGPUCallLowering.cpp:1043
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_Z
@ WORKITEM_ID_Z
Definition: AMDGPUArgumentUsageInfo.h:116
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:239
llvm::CallLowering::checkReturn
bool checkReturn(CCState &CCInfo, SmallVectorImpl< BaseArgInfo > &Outs, CCAssignFn *Fn) const
Definition: CallLowering.cpp:869
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::AMDGPUTargetLowering::CCAssignFnForReturn
static CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)
Definition: AMDGPUISelLowering.cpp:1194
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_X
@ WORKITEM_ID_X
Definition: AMDGPUArgumentUsageInfo.h:114
llvm::MachineIRBuilder::buildPtrAdd
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
Definition: MachineIRBuilder.cpp:182
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:647
I
#define I(x, y, z)
Definition: MD5.cpp:59
Analysis.h
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:123
llvm::MachineFrameInfo::setHasTailCall
void setHasTailCall(bool V=true)
Definition: MachineFrameInfo.h:607
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:120
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::SITargetLowering::allocateSpecialInputVGPRs
void allocateSpecialInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments at the end of allocated user arguments.
Definition: SIISelLowering.cpp:2009
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:860
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:287
llvm::AMDGPUTargetLowering::CCAssignFnForCall
static CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AMDGPUISelLowering.cpp:1189
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:642
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:188
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::AMDGPUSubtarget::getExplicitKernelArgOffset
unsigned getExplicitKernelArgOffset(const Function &F) const
Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument.
Definition: AMDGPUSubtarget.h:203
llvm::AMDGPUFunctionArgInfo::WorkItemIDZ
ArgDescriptor WorkItemIDZ
Definition: AMDGPUArgumentUsageInfo.h:150
llvm::ArgDescriptor::isRegister
bool isRegister() const
Definition: AMDGPUArgumentUsageInfo.h:67
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:653
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1528
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:367
llvm::AMDGPUFunctionArgInfo::DISPATCH_ID
@ DISPATCH_ID
Definition: AMDGPUArgumentUsageInfo.h:104
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::CallingConv::AMDGPU_Gfx
@ AMDGPU_Gfx
Calling convention used for AMD graphics targets.
Definition: CallingConv.h:250
llvm::CCState::AllocateReg
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
Definition: CallingConvLower.h:351
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1554
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:156
AMDGPU.h
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:45
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::CallLowering::insertSRetLoads
void insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg, int FI) const
Load the returned value from the stack into virtual registers in VRegs.
Definition: CallLowering.cpp:764
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:353
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:238
llvm::ArgDescriptor::isMasked
bool isMasked() const
Definition: AMDGPUArgumentUsageInfo.h:85
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AMDGPU::isGraphics
bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1373
getAssignFnsForCC
static std::pair< CCAssignFn *, CCAssignFn * > getAssignFnsForCC(CallingConv::ID CC, const SITargetLowering &TLI)
Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for CC.
Definition: AMDGPUCallLowering.cpp:929
llvm::SIMachineFunctionInfo::getScratchRSrcReg
Register getScratchRSrcReg() const
Returns the physical register reserved for use as the resource descriptor for scratch accesses.
Definition: SIMachineFunctionInfo.h:737
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineIRBuilder::buildAnyExt
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
Definition: MachineIRBuilder.cpp:414
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:137
llvm::CallLowering::insertSRetIncomingArgument
void insertSRetIncomingArgument(const Function &F, SmallVectorImpl< ArgInfo > &SplitArgs, Register &DemoteReg, MachineRegisterInfo &MRI, const DataLayout &DL) const
Insert the hidden sret ArgInfo to the beginning of SplitArgs.
Definition: CallLowering.cpp:825
llvm::SITargetLowering::allocateSpecialEntryInputVGPRs
void allocateSpecialEntryInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:1887
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
mayTailCallThisCC
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
Definition: AMDGPUCallLowering.cpp:1048
llvm::CallLowering::insertSRetStores
void insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg) const
Store the return value given by VRegs into stack starting at the offset specified in DemoteReg.
Definition: CallLowering.cpp:794
llvm::commonAlignment
Align commonAlignment(Align A, Align B)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:211
llvm::AMDGPUAS::PRIVATE_ADDRESS
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:355
llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Y
@ WORKGROUP_ID_Y
Definition: AMDGPUArgumentUsageInfo.h:107
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
llvm::CallLowering::ValueHandler::MRI
MachineRegisterInfo & MRI
Definition: CallLowering.h:227
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:622
llvm::CallLowering::determineAndHandleAssignments
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, Register ThisReturnReg=Register()) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
Definition: CallLowering.cpp:522
llvm::CallLowering::IncomingValueAssigner
Definition: CallLowering.h:213
llvm::SITargetLowering
Definition: SIISelLowering.h:31
llvm::CCState::getNextStackOffset
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Definition: CallingConvLower.h:264
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:101
llvm::CallLowering::ValueAssigner::StackOffset
uint64_t StackOffset
Stack offset for next argument.
Definition: CallLowering.h:200
llvm::CallLowering::ValueHandler::MIRBuilder
MachineIRBuilder & MIRBuilder
Definition: CallLowering.h:226
llvm::SIMachineFunctionInfo::getBytesInStackArgArea
unsigned getBytesInStackArgArea() const
Definition: SIMachineFunctionInfo.h:561
llvm::AMDGPUFunctionArgInfo::DISPATCH_PTR
@ DISPATCH_PTR
Definition: AMDGPUArgumentUsageInfo.h:101
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:137
llvm::GlobalValue::getAddressSpace
unsigned getAddressSpace() const
Definition: Globals.cpp:112
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
AMDGPULegalizerInfo.h
AMDGPUCallLowering.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1003
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::AMDGPUFunctionArgInfo::WorkItemIDY
ArgDescriptor WorkItemIDY
Definition: AMDGPUArgumentUsageInfo.h:149
llvm::LLT::getElementCount
ElementCount getElementCount() const
Definition: LowLevelTypeImpl.h:144
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
llvm::ArgDescriptor::getRegister
MCRegister getRegister() const
Definition: AMDGPUArgumentUsageInfo.h:71
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:335
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:48
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:260
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::AMDGPUCallLowering::lowerFormalArguments
bool lowerFormalArguments(MachineIRBuilder &B, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Definition: AMDGPUCallLowering.cpp:567
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1475
llvm::MachineIRBuilder::buildStore
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
Definition: MachineIRBuilder.cpp:387
getCallOpcode
static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect, bool IsTailCall)
Definition: AMDGPUCallLowering.cpp:933
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:726
llvm::SITargetLowering::allocateSpecialInputSGPRs
void allocateSpecialInputSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:2043
llvm::AMDGPUCallLowering::areCalleeOutgoingArgsTailCallable
bool areCalleeOutgoingArgsTailCallable(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &OutArgs) const
Definition: AMDGPUCallLowering.cpp:1001
llvm::CallLowering::parametersInCSRMatch
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
Definition: CallLowering.cpp:914
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
llvm::CallLowering
Definition: CallLowering.h:43
llvm::AMDGPUCallLowering::lowerReturn
bool lowerReturn(MachineIRBuilder &B, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
Definition: AMDGPUCallLowering.cpp:335
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1016
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:210
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:403
SIRegisterInfo.h
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:487
AMDGPUTargetMachine.h
llvm::FormalArgHandler::FormalArgHandler
FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Definition: M68kCallLowering.h:66
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:580
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:153