LLVM  13.0.0git
AMDGPUCallLowering.cpp
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1 //===-- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp - Call lowering -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUCallLowering.h"
16 #include "AMDGPU.h"
17 #include "AMDGPULegalizerInfo.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "SIRegisterInfo.h"
21 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/IR/IntrinsicsAMDGPU.h"
25 
26 #define DEBUG_TYPE "amdgpu-call-lowering"
27 
28 using namespace llvm;
29 
30 namespace {
31 
32 /// Wrapper around extendRegister to ensure we extend to a full 32-bit register.
33 static Register extendRegisterMin32(CallLowering::ValueHandler &Handler,
34  Register ValVReg, CCValAssign &VA) {
35  if (VA.getLocVT().getSizeInBits() < 32) {
36  // 16-bit types are reported as legal for 32-bit registers. We need to
37  // extend and do a 32-bit copy to avoid the verifier complaining about it.
38  return Handler.MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0);
39  }
40 
41  return Handler.extendRegister(ValVReg, VA);
42 }
43 
44 struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
45  AMDGPUOutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
47  : OutgoingValueHandler(B, MRI), MIB(MIB) {}
48 
50 
51  Register getStackAddress(uint64_t Size, int64_t Offset,
52  MachinePointerInfo &MPO,
53  ISD::ArgFlagsTy Flags) override {
54  llvm_unreachable("not implemented");
55  }
56 
57  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
58  MachinePointerInfo &MPO, CCValAssign &VA) override {
59  llvm_unreachable("not implemented");
60  }
61 
62  void assignValueToReg(Register ValVReg, Register PhysReg,
63  CCValAssign &VA) override {
64  Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);
65 
66  // If this is a scalar return, insert a readfirstlane just in case the value
67  // ends up in a VGPR.
68  // FIXME: Assert this is a shader return.
69  const SIRegisterInfo *TRI
70  = static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo());
71  if (TRI->isSGPRReg(MRI, PhysReg)) {
72  auto ToSGPR = MIRBuilder.buildIntrinsic(Intrinsic::amdgcn_readfirstlane,
73  {MRI.getType(ExtReg)}, false)
74  .addReg(ExtReg);
75  ExtReg = ToSGPR.getReg(0);
76  }
77 
78  MIRBuilder.buildCopy(PhysReg, ExtReg);
79  MIB.addUse(PhysReg, RegState::Implicit);
80  }
81 };
82 
83 struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler {
84  uint64_t StackUsed = 0;
85 
86  AMDGPUIncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI)
87  : IncomingValueHandler(B, MRI) {}
88 
89  Register getStackAddress(uint64_t Size, int64_t Offset,
90  MachinePointerInfo &MPO,
91  ISD::ArgFlagsTy Flags) override {
92  auto &MFI = MIRBuilder.getMF().getFrameInfo();
93 
94  // Byval is assumed to be writable memory, but other stack passed arguments
95  // are not.
96  const bool IsImmutable = !Flags.isByVal();
97  int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
98  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
99  auto AddrReg = MIRBuilder.buildFrameIndex(
101  StackUsed = std::max(StackUsed, Size + Offset);
102  return AddrReg.getReg(0);
103  }
104 
105  void assignValueToReg(Register ValVReg, Register PhysReg,
106  CCValAssign &VA) override {
107  markPhysRegUsed(PhysReg);
108 
109  if (VA.getLocVT().getSizeInBits() < 32) {
110  // 16-bit types are reported as legal for 32-bit registers. We need to do
111  // a 32-bit copy, and truncate to avoid the verifier complaining about it.
112  auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg);
113 
114  // If we have signext/zeroext, it applies to the whole 32-bit register
115  // before truncation.
116  auto Extended =
117  buildExtensionHint(VA, Copy.getReg(0), LLT(VA.getLocVT()));
118  MIRBuilder.buildTrunc(ValVReg, Extended);
119  return;
120  }
121 
122  IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
123  }
124 
125  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t MemSize,
126  MachinePointerInfo &MPO, CCValAssign &VA) override {
127  MachineFunction &MF = MIRBuilder.getMF();
128 
129  // The reported memory location may be wider than the value.
130  const LLT RegTy = MRI.getType(ValVReg);
131  MemSize = std::min(static_cast<uint64_t>(RegTy.getSizeInBytes()), MemSize);
132 
133  // FIXME: Get alignment
134  auto MMO = MF.getMachineMemOperand(
136  inferAlignFromPtrInfo(MF, MPO));
137  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
138  }
139 
140  /// How the physical register gets marked varies between formal
141  /// parameters (it's a basic-block live-in), and a call instruction
142  /// (it's an implicit-def of the BL).
143  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
144 };
145 
146 struct FormalArgHandler : public AMDGPUIncomingArgHandler {
148  : AMDGPUIncomingArgHandler(B, MRI) {}
149 
150  void markPhysRegUsed(unsigned PhysReg) override {
151  MIRBuilder.getMBB().addLiveIn(PhysReg);
152  }
153 };
154 
155 struct CallReturnHandler : public AMDGPUIncomingArgHandler {
156  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
158  : AMDGPUIncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {}
159 
160  void markPhysRegUsed(unsigned PhysReg) override {
161  MIB.addDef(PhysReg, RegState::Implicit);
162  }
163 
165 };
166 
167 struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
168  /// For tail calls, the byte offset of the call's argument area from the
169  /// callee's. Unused elsewhere.
170  int FPDiff;
171 
172  // Cache the SP register vreg if we need it more than once in this call site.
173  Register SPReg;
174 
175  bool IsTailCall;
176 
177  AMDGPUOutgoingArgHandler(MachineIRBuilder &MIRBuilder,
179  bool IsTailCall = false, int FPDiff = 0)
180  : AMDGPUOutgoingValueHandler(MIRBuilder, MRI, MIB), FPDiff(FPDiff),
181  IsTailCall(IsTailCall) {}
182 
183  Register getStackAddress(uint64_t Size, int64_t Offset,
184  MachinePointerInfo &MPO,
185  ISD::ArgFlagsTy Flags) override {
186  MachineFunction &MF = MIRBuilder.getMF();
187  const LLT PtrTy = LLT::pointer(AMDGPUAS::PRIVATE_ADDRESS, 32);
188  const LLT S32 = LLT::scalar(32);
189 
190  if (IsTailCall) {
191  Offset += FPDiff;
192  int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
193  auto FIReg = MIRBuilder.buildFrameIndex(PtrTy, FI);
194  MPO = MachinePointerInfo::getFixedStack(MF, FI);
195  return FIReg.getReg(0);
196  }
197 
199 
200  if (!SPReg)
201  SPReg = MIRBuilder.buildCopy(PtrTy, MFI->getStackPtrOffsetReg()).getReg(0);
202 
203  auto OffsetReg = MIRBuilder.buildConstant(S32, Offset);
204 
205  auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg);
207  return AddrReg.getReg(0);
208  }
209 
210  void assignValueToReg(Register ValVReg, Register PhysReg,
211  CCValAssign &VA) override {
212  MIB.addUse(PhysReg, RegState::Implicit);
213  Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);
214  MIRBuilder.buildCopy(PhysReg, ExtReg);
215  }
216 
217  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
218  MachinePointerInfo &MPO, CCValAssign &VA) override {
219  MachineFunction &MF = MIRBuilder.getMF();
220  uint64_t LocMemOffset = VA.getLocMemOffset();
221  const auto &ST = MF.getSubtarget<GCNSubtarget>();
222 
223  auto MMO = MF.getMachineMemOperand(
225  commonAlignment(ST.getStackAlignment(), LocMemOffset));
226  MIRBuilder.buildStore(ValVReg, Addr, *MMO);
227  }
228 
229  void assignValueToAddress(const CallLowering::ArgInfo &Arg,
230  unsigned ValRegIndex, Register Addr,
231  uint64_t MemSize, MachinePointerInfo &MPO,
232  CCValAssign &VA) override {
233  Register ValVReg = VA.getLocInfo() != CCValAssign::LocInfo::FPExt
234  ? extendRegister(Arg.Regs[ValRegIndex], VA)
235  : Arg.Regs[ValRegIndex];
236 
237  // If we extended the value type we might need to adjust the MMO's
238  // Size. This happens if ComputeValueVTs widened a small type value to a
239  // legal register type (e.g. s8->s16)
240  const LLT RegTy = MRI.getType(ValVReg);
241  MemSize = std::min(MemSize, (uint64_t)RegTy.getSizeInBytes());
242  assignValueToAddress(ValVReg, Addr, MemSize, MPO, VA);
243  }
244 };
245 }
246 
248  : CallLowering(&TLI) {
249 }
250 
251 // FIXME: Compatability shim
252 static ISD::NodeType extOpcodeToISDExtOpcode(unsigned MIOpc) {
253  switch (MIOpc) {
254  case TargetOpcode::G_SEXT:
255  return ISD::SIGN_EXTEND;
256  case TargetOpcode::G_ZEXT:
257  return ISD::ZERO_EXTEND;
258  case TargetOpcode::G_ANYEXT:
259  return ISD::ANY_EXTEND;
260  default:
261  llvm_unreachable("not an extend opcode");
262  }
263 }
264 
265 bool AMDGPUCallLowering::canLowerReturn(MachineFunction &MF,
266  CallingConv::ID CallConv,
268  bool IsVarArg) const {
269  // For shaders. Vector types should be explicitly handled by CC.
270  if (AMDGPU::isEntryFunctionCC(CallConv))
271  return true;
272 
274  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
275  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs,
276  MF.getFunction().getContext());
277 
278  return checkReturn(CCInfo, Outs, TLI.CCAssignFnForReturn(CallConv, IsVarArg));
279 }
280 
281 /// Lower the return value for the already existing \p Ret. This assumes that
282 /// \p B's insertion point is correct.
283 bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B,
284  const Value *Val, ArrayRef<Register> VRegs,
285  MachineInstrBuilder &Ret) const {
286  if (!Val)
287  return true;
288 
289  auto &MF = B.getMF();
290  const auto &F = MF.getFunction();
291  const DataLayout &DL = MF.getDataLayout();
292  MachineRegisterInfo *MRI = B.getMRI();
293  LLVMContext &Ctx = F.getContext();
294 
295  CallingConv::ID CC = F.getCallingConv();
296  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
297 
298  SmallVector<EVT, 8> SplitEVTs;
299  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
300  assert(VRegs.size() == SplitEVTs.size() &&
301  "For each split Type there should be exactly one VReg.");
302 
303  SmallVector<ArgInfo, 8> SplitRetInfos;
304 
305  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
306  EVT VT = SplitEVTs[i];
307  Register Reg = VRegs[i];
308  ArgInfo RetInfo(Reg, VT.getTypeForEVT(Ctx));
310 
311  if (VT.isScalarInteger()) {
312  unsigned ExtendOp = TargetOpcode::G_ANYEXT;
313  if (RetInfo.Flags[0].isSExt()) {
314  assert(RetInfo.Regs.size() == 1 && "expect only simple return values");
315  ExtendOp = TargetOpcode::G_SEXT;
316  } else if (RetInfo.Flags[0].isZExt()) {
317  assert(RetInfo.Regs.size() == 1 && "expect only simple return values");
318  ExtendOp = TargetOpcode::G_ZEXT;
319  }
320 
321  EVT ExtVT = TLI.getTypeForExtReturn(Ctx, VT,
322  extOpcodeToISDExtOpcode(ExtendOp));
323  if (ExtVT != VT) {
324  RetInfo.Ty = ExtVT.getTypeForEVT(Ctx);
325  LLT ExtTy = getLLTForType(*RetInfo.Ty, DL);
326  Reg = B.buildInstr(ExtendOp, {ExtTy}, {Reg}).getReg(0);
327  }
328  }
329 
330  if (Reg != RetInfo.Regs[0]) {
331  RetInfo.Regs[0] = Reg;
332  // Reset the arg flags after modifying Reg.
334  }
335 
336  splitToValueTypes(RetInfo, SplitRetInfos, DL, CC);
337  }
338 
339  CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(CC, F.isVarArg());
340 
341  OutgoingValueAssigner Assigner(AssignFn);
342  AMDGPUOutgoingValueHandler RetHandler(B, *MRI, Ret);
343  return determineAndHandleAssignments(RetHandler, Assigner, SplitRetInfos, B,
344  CC, F.isVarArg());
345 }
346 
348  ArrayRef<Register> VRegs,
349  FunctionLoweringInfo &FLI) const {
350 
351  MachineFunction &MF = B.getMF();
354  MFI->setIfReturnsVoid(!Val);
355 
356  assert(!Val == VRegs.empty() && "Return value without a vreg");
357 
358  CallingConv::ID CC = B.getMF().getFunction().getCallingConv();
359  const bool IsShader = AMDGPU::isShader(CC);
360  const bool IsWaveEnd =
361  (IsShader && MFI->returnsVoid()) || AMDGPU::isKernel(CC);
362  if (IsWaveEnd) {
363  B.buildInstr(AMDGPU::S_ENDPGM)
364  .addImm(0);
365  return true;
366  }
367 
368  auto const &ST = MF.getSubtarget<GCNSubtarget>();
369 
370  unsigned ReturnOpc =
371  IsShader ? AMDGPU::SI_RETURN_TO_EPILOG : AMDGPU::S_SETPC_B64_return;
372 
373  auto Ret = B.buildInstrNoInsert(ReturnOpc);
374  Register ReturnAddrVReg;
375  if (ReturnOpc == AMDGPU::S_SETPC_B64_return) {
376  ReturnAddrVReg = MRI.createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass);
377  Ret.addUse(ReturnAddrVReg);
378  }
379 
380  if (!FLI.CanLowerReturn)
381  insertSRetStores(B, Val->getType(), VRegs, FLI.DemoteRegister);
382  else if (!lowerReturnVal(B, Val, VRegs, Ret))
383  return false;
384 
385  if (ReturnOpc == AMDGPU::S_SETPC_B64_return) {
386  const SIRegisterInfo *TRI = ST.getRegisterInfo();
387  Register LiveInReturn = MF.addLiveIn(TRI->getReturnAddressReg(MF),
388  &AMDGPU::SGPR_64RegClass);
389  B.buildCopy(ReturnAddrVReg, LiveInReturn);
390  }
391 
392  // TODO: Handle CalleeSavedRegsViaCopy.
393 
394  B.insertInstr(Ret);
395  return true;
396 }
397 
398 void AMDGPUCallLowering::lowerParameterPtr(Register DstReg, MachineIRBuilder &B,
399  Type *ParamTy,
400  uint64_t Offset) const {
401  MachineFunction &MF = B.getMF();
404  Register KernArgSegmentPtr =
406  Register KernArgSegmentVReg = MRI.getLiveInVirtReg(KernArgSegmentPtr);
407 
408  auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset);
409 
410  B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg);
411 }
412 
413 void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, Type *ParamTy,
414  uint64_t Offset, Align Alignment,
415  Register DstReg) const {
416  MachineFunction &MF = B.getMF();
417  const Function &F = MF.getFunction();
418  const DataLayout &DL = F.getParent()->getDataLayout();
420  unsigned TypeSize = DL.getTypeStoreSize(ParamTy);
421 
423  Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy);
424  lowerParameterPtr(PtrReg, B, ParamTy, Offset);
425 
427  PtrInfo,
430  TypeSize, Alignment);
431 
432  B.buildLoad(DstReg, PtrReg, *MMO);
433 }
434 
435 // Allocate special inputs passed in user SGPRs.
436 static void allocateHSAUserSGPRs(CCState &CCInfo,
438  MachineFunction &MF,
439  const SIRegisterInfo &TRI,
441  // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
442  if (Info.hasPrivateSegmentBuffer()) {
443  Register PrivateSegmentBufferReg = Info.addPrivateSegmentBuffer(TRI);
444  MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
445  CCInfo.AllocateReg(PrivateSegmentBufferReg);
446  }
447 
448  if (Info.hasDispatchPtr()) {
449  Register DispatchPtrReg = Info.addDispatchPtr(TRI);
450  MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
451  CCInfo.AllocateReg(DispatchPtrReg);
452  }
453 
454  if (Info.hasQueuePtr()) {
455  Register QueuePtrReg = Info.addQueuePtr(TRI);
456  MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
457  CCInfo.AllocateReg(QueuePtrReg);
458  }
459 
460  if (Info.hasKernargSegmentPtr()) {
462  Register InputPtrReg = Info.addKernargSegmentPtr(TRI);
465  MRI.addLiveIn(InputPtrReg, VReg);
466  B.getMBB().addLiveIn(InputPtrReg);
467  B.buildCopy(VReg, InputPtrReg);
468  CCInfo.AllocateReg(InputPtrReg);
469  }
470 
471  if (Info.hasDispatchID()) {
472  Register DispatchIDReg = Info.addDispatchID(TRI);
473  MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
474  CCInfo.AllocateReg(DispatchIDReg);
475  }
476 
477  if (Info.hasFlatScratchInit()) {
478  Register FlatScratchInitReg = Info.addFlatScratchInit(TRI);
479  MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
480  CCInfo.AllocateReg(FlatScratchInitReg);
481  }
482 
483  // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
484  // these from the dispatch pointer.
485 }
486 
488  MachineIRBuilder &B, const Function &F,
489  ArrayRef<ArrayRef<Register>> VRegs) const {
490  MachineFunction &MF = B.getMF();
491  const GCNSubtarget *Subtarget = &MF.getSubtarget<GCNSubtarget>();
494  const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
495  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
496  const DataLayout &DL = F.getParent()->getDataLayout();
497 
498  Info->allocateModuleLDSGlobal(F.getParent());
499 
501  CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
502 
503  allocateHSAUserSGPRs(CCInfo, B, MF, *TRI, *Info);
504 
505  unsigned i = 0;
506  const Align KernArgBaseAlign(16);
507  const unsigned BaseOffset = Subtarget->getExplicitKernelArgOffset(F);
508  uint64_t ExplicitArgOffset = 0;
509 
510  // TODO: Align down to dword alignment and extract bits for extending loads.
511  for (auto &Arg : F.args()) {
512  const bool IsByRef = Arg.hasByRefAttr();
513  Type *ArgTy = IsByRef ? Arg.getParamByRefType() : Arg.getType();
514  unsigned AllocSize = DL.getTypeAllocSize(ArgTy);
515  if (AllocSize == 0)
516  continue;
517 
518  MaybeAlign ABIAlign = IsByRef ? Arg.getParamAlign() : None;
519  if (!ABIAlign)
520  ABIAlign = DL.getABITypeAlign(ArgTy);
521 
522  uint64_t ArgOffset = alignTo(ExplicitArgOffset, ABIAlign) + BaseOffset;
523  ExplicitArgOffset = alignTo(ExplicitArgOffset, ABIAlign) + AllocSize;
524 
525  if (Arg.use_empty()) {
526  ++i;
527  continue;
528  }
529 
530  Align Alignment = commonAlignment(KernArgBaseAlign, ArgOffset);
531 
532  if (IsByRef) {
533  unsigned ByRefAS = cast<PointerType>(Arg.getType())->getAddressSpace();
534 
535  assert(VRegs[i].size() == 1 &&
536  "expected only one register for byval pointers");
537  if (ByRefAS == AMDGPUAS::CONSTANT_ADDRESS) {
538  lowerParameterPtr(VRegs[i][0], B, ArgTy, ArgOffset);
539  } else {
540  const LLT ConstPtrTy = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
541  Register PtrReg = MRI.createGenericVirtualRegister(ConstPtrTy);
542  lowerParameterPtr(PtrReg, B, ArgTy, ArgOffset);
543 
544  B.buildAddrSpaceCast(VRegs[i][0], PtrReg);
545  }
546  } else {
547  ArrayRef<Register> OrigArgRegs = VRegs[i];
548  Register ArgReg =
549  OrigArgRegs.size() == 1
550  ? OrigArgRegs[0]
552 
553  lowerParameter(B, ArgTy, ArgOffset, Alignment, ArgReg);
554  if (OrigArgRegs.size() > 1)
555  unpackRegs(OrigArgRegs, ArgReg, ArgTy, B);
556  }
557 
558  ++i;
559  }
560 
561  TLI.allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);
562  TLI.allocateSystemSGPRs(CCInfo, MF, *Info, F.getCallingConv(), false);
563  return true;
564 }
565 
568  FunctionLoweringInfo &FLI) const {
569  CallingConv::ID CC = F.getCallingConv();
570 
571  // The infrastructure for normal calling convention lowering is essentially
572  // useless for kernels. We want to avoid any kind of legalization or argument
573  // splitting.
574  if (CC == CallingConv::AMDGPU_KERNEL)
575  return lowerFormalArgumentsKernel(B, F, VRegs);
576 
577  const bool IsGraphics = AMDGPU::isGraphics(CC);
578  const bool IsEntryFunc = AMDGPU::isEntryFunctionCC(CC);
579 
580  MachineFunction &MF = B.getMF();
581  MachineBasicBlock &MBB = B.getMBB();
584  const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
585  const SIRegisterInfo *TRI = Subtarget.getRegisterInfo();
586  const DataLayout &DL = F.getParent()->getDataLayout();
587 
588  Info->allocateModuleLDSGlobal(F.getParent());
589 
591  CCState CCInfo(CC, F.isVarArg(), MF, ArgLocs, F.getContext());
592 
593  if (!IsEntryFunc) {
594  Register ReturnAddrReg = TRI->getReturnAddressReg(MF);
595  Register LiveInReturn = MF.addLiveIn(ReturnAddrReg,
596  &AMDGPU::SGPR_64RegClass);
597  MBB.addLiveIn(ReturnAddrReg);
598  B.buildCopy(LiveInReturn, ReturnAddrReg);
599  }
600 
601  if (Info->hasImplicitBufferPtr()) {
602  Register ImplicitBufferPtrReg = Info->addImplicitBufferPtr(*TRI);
603  MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
604  CCInfo.AllocateReg(ImplicitBufferPtrReg);
605  }
606 
607  SmallVector<ArgInfo, 32> SplitArgs;
608  unsigned Idx = 0;
609  unsigned PSInputNum = 0;
610 
611  // Insert the hidden sret parameter if the return value won't fit in the
612  // return registers.
613  if (!FLI.CanLowerReturn)
614  insertSRetIncomingArgument(F, SplitArgs, FLI.DemoteRegister, MRI, DL);
615 
616  for (auto &Arg : F.args()) {
617  if (DL.getTypeStoreSize(Arg.getType()) == 0)
618  continue;
619 
620  const bool InReg = Arg.hasAttribute(Attribute::InReg);
621 
622  // SGPR arguments to functions not implemented.
623  if (!IsGraphics && InReg)
624  return false;
625 
626  if (Arg.hasAttribute(Attribute::SwiftSelf) ||
627  Arg.hasAttribute(Attribute::SwiftError) ||
628  Arg.hasAttribute(Attribute::Nest))
629  return false;
630 
631  if (CC == CallingConv::AMDGPU_PS && !InReg && PSInputNum <= 15) {
632  const bool ArgUsed = !Arg.use_empty();
633  bool SkipArg = !ArgUsed && !Info->isPSInputAllocated(PSInputNum);
634 
635  if (!SkipArg) {
636  Info->markPSInputAllocated(PSInputNum);
637  if (ArgUsed)
638  Info->markPSInputEnabled(PSInputNum);
639  }
640 
641  ++PSInputNum;
642 
643  if (SkipArg) {
644  for (int I = 0, E = VRegs[Idx].size(); I != E; ++I)
645  B.buildUndef(VRegs[Idx][I]);
646 
647  ++Idx;
648  continue;
649  }
650  }
651 
652  ArgInfo OrigArg(VRegs[Idx], Arg);
653  const unsigned OrigArgIdx = Idx + AttributeList::FirstArgIndex;
654  setArgFlags(OrigArg, OrigArgIdx, DL, F);
655 
656  splitToValueTypes(OrigArg, SplitArgs, DL, CC);
657  ++Idx;
658  }
659 
660  // At least one interpolation mode must be enabled or else the GPU will
661  // hang.
662  //
663  // Check PSInputAddr instead of PSInputEnable. The idea is that if the user
664  // set PSInputAddr, the user wants to enable some bits after the compilation
665  // based on run-time states. Since we can't know what the final PSInputEna
666  // will look like, so we shouldn't do anything here and the user should take
667  // responsibility for the correct programming.
668  //
669  // Otherwise, the following restrictions apply:
670  // - At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled.
671  // - If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be
672  // enabled too.
673  if (CC == CallingConv::AMDGPU_PS) {
674  if ((Info->getPSInputAddr() & 0x7F) == 0 ||
675  ((Info->getPSInputAddr() & 0xF) == 0 &&
676  Info->isPSInputAllocated(11))) {
677  CCInfo.AllocateReg(AMDGPU::VGPR0);
678  CCInfo.AllocateReg(AMDGPU::VGPR1);
679  Info->markPSInputAllocated(0);
680  Info->markPSInputEnabled(0);
681  }
682 
683  if (Subtarget.isAmdPalOS()) {
684  // For isAmdPalOS, the user does not enable some bits after compilation
685  // based on run-time states; the register values being generated here are
686  // the final ones set in hardware. Therefore we need to apply the
687  // workaround to PSInputAddr and PSInputEnable together. (The case where
688  // a bit is set in PSInputAddr but not PSInputEnable is where the frontend
689  // set up an input arg for a particular interpolation mode, but nothing
690  // uses that input arg. Really we should have an earlier pass that removes
691  // such an arg.)
692  unsigned PsInputBits = Info->getPSInputAddr() & Info->getPSInputEnable();
693  if ((PsInputBits & 0x7F) == 0 ||
694  ((PsInputBits & 0xF) == 0 &&
695  (PsInputBits >> 11 & 1)))
696  Info->markPSInputEnabled(
697  countTrailingZeros(Info->getPSInputAddr(), ZB_Undefined));
698  }
699  }
700 
701  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
702  CCAssignFn *AssignFn = TLI.CCAssignFnForCall(CC, F.isVarArg());
703 
704  if (!MBB.empty())
705  B.setInstr(*MBB.begin());
706 
707  if (!IsEntryFunc) {
708  // For the fixed ABI, pass workitem IDs in the last argument register.
710  TLI.allocateSpecialInputVGPRsFixed(CCInfo, MF, *TRI, *Info);
711  }
712 
713  IncomingValueAssigner Assigner(AssignFn);
714  if (!determineAssignments(Assigner, SplitArgs, CCInfo))
715  return false;
716 
717  FormalArgHandler Handler(B, MRI);
718  if (!handleAssignments(Handler, SplitArgs, CCInfo, ArgLocs, B))
719  return false;
720 
721  uint64_t StackOffset = Assigner.StackOffset;
722 
723  if (!IsEntryFunc && !AMDGPUTargetMachine::EnableFixedFunctionABI) {
724  // Special inputs come after user arguments.
725  TLI.allocateSpecialInputVGPRs(CCInfo, MF, *TRI, *Info);
726  }
727 
728  // Start adding system SGPRs.
729  if (IsEntryFunc) {
730  TLI.allocateSystemSGPRs(CCInfo, MF, *Info, CC, IsGraphics);
731  } else {
732  if (!Subtarget.enableFlatScratch())
733  CCInfo.AllocateReg(Info->getScratchRSrcReg());
734  TLI.allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);
735  }
736 
737  // When we tail call, we need to check if the callee's arguments will fit on
738  // the caller's stack. So, whenever we lower formal arguments, we should keep
739  // track of this information, since we might lower a tail call in this
740  // function later.
741  Info->setBytesInStackArgArea(StackOffset);
742 
743  // Move back to the end of the basic block.
744  B.setMBB(MBB);
745 
746  return true;
747 }
748 
750  CCState &CCInfo,
751  SmallVectorImpl<std::pair<MCRegister, Register>> &ArgRegs,
752  CallLoweringInfo &Info) const {
753  MachineFunction &MF = MIRBuilder.getMF();
754 
755  const AMDGPUFunctionArgInfo *CalleeArgInfo
757 
759  const AMDGPUFunctionArgInfo &CallerArgInfo = MFI->getArgInfo();
760 
761 
762  // TODO: Unify with private memory register handling. This is complicated by
763  // the fact that at least in kernels, the input argument is not necessarily
764  // in the same location as the input.
773  };
774 
776 
777  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
778  const AMDGPULegalizerInfo *LI
779  = static_cast<const AMDGPULegalizerInfo*>(ST.getLegalizerInfo());
780 
781  for (auto InputID : InputRegs) {
782  const ArgDescriptor *OutgoingArg;
783  const TargetRegisterClass *ArgRC;
784  LLT ArgTy;
785 
786  std::tie(OutgoingArg, ArgRC, ArgTy) =
787  CalleeArgInfo->getPreloadedValue(InputID);
788  if (!OutgoingArg)
789  continue;
790 
791  const ArgDescriptor *IncomingArg;
792  const TargetRegisterClass *IncomingArgRC;
793  std::tie(IncomingArg, IncomingArgRC, ArgTy) =
794  CallerArgInfo.getPreloadedValue(InputID);
795  assert(IncomingArgRC == ArgRC);
796 
797  Register InputReg = MRI.createGenericVirtualRegister(ArgTy);
798 
799  if (IncomingArg) {
800  LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy);
801  } else {
803  LI->getImplicitArgPtr(InputReg, MRI, MIRBuilder);
804  }
805 
806  if (OutgoingArg->isRegister()) {
807  ArgRegs.emplace_back(OutgoingArg->getRegister(), InputReg);
808  if (!CCInfo.AllocateReg(OutgoingArg->getRegister()))
809  report_fatal_error("failed to allocate implicit input argument");
810  } else {
811  LLVM_DEBUG(dbgs() << "Unhandled stack passed implicit input argument\n");
812  return false;
813  }
814  }
815 
816  // Pack workitem IDs into a single register or pass it as is if already
817  // packed.
818  const ArgDescriptor *OutgoingArg;
819  const TargetRegisterClass *ArgRC;
820  LLT ArgTy;
821 
822  std::tie(OutgoingArg, ArgRC, ArgTy) =
824  if (!OutgoingArg)
825  std::tie(OutgoingArg, ArgRC, ArgTy) =
827  if (!OutgoingArg)
828  std::tie(OutgoingArg, ArgRC, ArgTy) =
830  if (!OutgoingArg)
831  return false;
832 
833  auto WorkitemIDX =
834  CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X);
835  auto WorkitemIDY =
836  CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y);
837  auto WorkitemIDZ =
838  CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z);
839 
840  const ArgDescriptor *IncomingArgX = std::get<0>(WorkitemIDX);
841  const ArgDescriptor *IncomingArgY = std::get<0>(WorkitemIDY);
842  const ArgDescriptor *IncomingArgZ = std::get<0>(WorkitemIDZ);
843  const LLT S32 = LLT::scalar(32);
844 
845  // If incoming ids are not packed we need to pack them.
846  // FIXME: Should consider known workgroup size to eliminate known 0 cases.
847  Register InputReg;
848  if (IncomingArgX && !IncomingArgX->isMasked() && CalleeArgInfo->WorkItemIDX) {
849  InputReg = MRI.createGenericVirtualRegister(S32);
850  LI->loadInputValue(InputReg, MIRBuilder, IncomingArgX,
851  std::get<1>(WorkitemIDX), std::get<2>(WorkitemIDX));
852  }
853 
854  if (IncomingArgY && !IncomingArgY->isMasked() && CalleeArgInfo->WorkItemIDY) {
856  LI->loadInputValue(Y, MIRBuilder, IncomingArgY, std::get<1>(WorkitemIDY),
857  std::get<2>(WorkitemIDY));
858 
859  Y = MIRBuilder.buildShl(S32, Y, MIRBuilder.buildConstant(S32, 10)).getReg(0);
860  InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Y).getReg(0) : Y;
861  }
862 
863  if (IncomingArgZ && !IncomingArgZ->isMasked() && CalleeArgInfo->WorkItemIDZ) {
865  LI->loadInputValue(Z, MIRBuilder, IncomingArgZ, std::get<1>(WorkitemIDZ),
866  std::get<2>(WorkitemIDZ));
867 
868  Z = MIRBuilder.buildShl(S32, Z, MIRBuilder.buildConstant(S32, 20)).getReg(0);
869  InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Z).getReg(0) : Z;
870  }
871 
872  if (!InputReg) {
873  InputReg = MRI.createGenericVirtualRegister(S32);
874 
875  // Workitem ids are already packed, any of present incoming arguments will
876  // carry all required fields.
878  IncomingArgX ? *IncomingArgX :
879  IncomingArgY ? *IncomingArgY : *IncomingArgZ, ~0u);
880  LI->loadInputValue(InputReg, MIRBuilder, &IncomingArg,
881  &AMDGPU::VGPR_32RegClass, S32);
882  }
883 
884  if (OutgoingArg->isRegister()) {
885  ArgRegs.emplace_back(OutgoingArg->getRegister(), InputReg);
886  if (!CCInfo.AllocateReg(OutgoingArg->getRegister()))
887  report_fatal_error("failed to allocate implicit input argument");
888  } else {
889  LLVM_DEBUG(dbgs() << "Unhandled stack passed implicit input argument\n");
890  return false;
891  }
892 
893  return true;
894 }
895 
896 /// Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for
897 /// CC.
898 static std::pair<CCAssignFn *, CCAssignFn *>
900  return {TLI.CCAssignFnForCall(CC, false), TLI.CCAssignFnForCall(CC, true)};
901 }
902 
903 static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect,
904  bool IsTailCall) {
905  return IsTailCall ? AMDGPU::SI_TCRETURN : AMDGPU::SI_CALL;
906 }
907 
908 // Add operands to call instruction to track the callee.
910  MachineIRBuilder &MIRBuilder,
911  AMDGPUCallLowering::CallLoweringInfo &Info) {
912  if (Info.Callee.isReg()) {
913  CallInst.addReg(Info.Callee.getReg());
914  CallInst.addImm(0);
915  } else if (Info.Callee.isGlobal() && Info.Callee.getOffset() == 0) {
916  // The call lowering lightly assumed we can directly encode a call target in
917  // the instruction, which is not the case. Materialize the address here.
918  const GlobalValue *GV = Info.Callee.getGlobal();
919  auto Ptr = MIRBuilder.buildGlobalValue(
920  LLT::pointer(GV->getAddressSpace(), 64), GV);
921  CallInst.addReg(Ptr.getReg(0));
922  CallInst.add(Info.Callee);
923  } else
924  return false;
925 
926  return true;
927 }
928 
931  SmallVectorImpl<ArgInfo> &InArgs) const {
932  const Function &CallerF = MF.getFunction();
933  CallingConv::ID CalleeCC = Info.CallConv;
934  CallingConv::ID CallerCC = CallerF.getCallingConv();
935 
936  // If the calling conventions match, then everything must be the same.
937  if (CalleeCC == CallerCC)
938  return true;
939 
940  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
941 
942  // Make sure that the caller and callee preserve all of the same registers.
943  auto TRI = ST.getRegisterInfo();
944 
945  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
946  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
947  if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
948  return false;
949 
950  // Check if the caller and callee will handle arguments in the same way.
951  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
952  CCAssignFn *CalleeAssignFnFixed;
953  CCAssignFn *CalleeAssignFnVarArg;
954  std::tie(CalleeAssignFnFixed, CalleeAssignFnVarArg) =
955  getAssignFnsForCC(CalleeCC, TLI);
956 
957  CCAssignFn *CallerAssignFnFixed;
958  CCAssignFn *CallerAssignFnVarArg;
959  std::tie(CallerAssignFnFixed, CallerAssignFnVarArg) =
960  getAssignFnsForCC(CallerCC, TLI);
961 
962  // FIXME: We are not accounting for potential differences in implicitly passed
963  // inputs, but only the fixed ABI is supported now anyway.
964  IncomingValueAssigner CalleeAssigner(CalleeAssignFnFixed,
965  CalleeAssignFnVarArg);
966  IncomingValueAssigner CallerAssigner(CallerAssignFnFixed,
967  CallerAssignFnVarArg);
968  return resultsCompatible(Info, MF, InArgs, CalleeAssigner, CallerAssigner);
969 }
970 
973  SmallVectorImpl<ArgInfo> &OutArgs) const {
974  // If there are no outgoing arguments, then we are done.
975  if (OutArgs.empty())
976  return true;
977 
978  const Function &CallerF = MF.getFunction();
979  CallingConv::ID CalleeCC = Info.CallConv;
980  CallingConv::ID CallerCC = CallerF.getCallingConv();
981  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
982 
983  CCAssignFn *AssignFnFixed;
984  CCAssignFn *AssignFnVarArg;
985  std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
986 
987  // We have outgoing arguments. Make sure that we can tail call with them.
989  CCState OutInfo(CalleeCC, false, MF, OutLocs, CallerF.getContext());
990  OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg);
991 
992  if (!determineAssignments(Assigner, OutArgs, OutInfo)) {
993  LLVM_DEBUG(dbgs() << "... Could not analyze call operands.\n");
994  return false;
995  }
996 
997  // Make sure that they can fit on the caller's stack.
998  const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
999  if (OutInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea()) {
1000  LLVM_DEBUG(dbgs() << "... Cannot fit call operands on caller's stack.\n");
1001  return false;
1002  }
1003 
1004  // Verify that the parameters in callee-saved registers match.
1005  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1006  const SIRegisterInfo *TRI = ST.getRegisterInfo();
1007  const uint32_t *CallerPreservedMask = TRI->getCallPreservedMask(MF, CallerCC);
1009  return parametersInCSRMatch(MRI, CallerPreservedMask, OutLocs, OutArgs);
1010 }
1011 
1012 /// Return true if the calling convention is one that we can guarantee TCO for.
1014  return CC == CallingConv::Fast;
1015 }
1016 
1017 /// Return true if we might ever do TCO for calls with this calling convention.
1019  switch (CC) {
1020  case CallingConv::C:
1022  return true;
1023  default:
1024  return canGuaranteeTCO(CC);
1025  }
1026 }
1027 
1030  SmallVectorImpl<ArgInfo> &InArgs, SmallVectorImpl<ArgInfo> &OutArgs) const {
1031  // Must pass all target-independent checks in order to tail call optimize.
1032  if (!Info.IsTailCall)
1033  return false;
1034 
1035  MachineFunction &MF = B.getMF();
1036  const Function &CallerF = MF.getFunction();
1037  CallingConv::ID CalleeCC = Info.CallConv;
1038  CallingConv::ID CallerCC = CallerF.getCallingConv();
1039 
1040  const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
1041  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
1042  // Kernels aren't callable, and don't have a live in return address so it
1043  // doesn't make sense to do a tail call with entry functions.
1044  if (!CallerPreserved)
1045  return false;
1046 
1047  if (!mayTailCallThisCC(CalleeCC)) {
1048  LLVM_DEBUG(dbgs() << "... Calling convention cannot be tail called.\n");
1049  return false;
1050  }
1051 
1052  if (any_of(CallerF.args(), [](const Argument &A) {
1053  return A.hasByValAttr() || A.hasSwiftErrorAttr();
1054  })) {
1055  LLVM_DEBUG(dbgs() << "... Cannot tail call from callers with byval "
1056  "or swifterror arguments\n");
1057  return false;
1058  }
1059 
1060  // If we have -tailcallopt, then we're done.
1062  return canGuaranteeTCO(CalleeCC) && CalleeCC == CallerF.getCallingConv();
1063 
1064  // Verify that the incoming and outgoing arguments from the callee are
1065  // safe to tail call.
1066  if (!doCallerAndCalleePassArgsTheSameWay(Info, MF, InArgs)) {
1067  LLVM_DEBUG(
1068  dbgs()
1069  << "... Caller and callee have incompatible calling conventions.\n");
1070  return false;
1071  }
1072 
1073  if (!areCalleeOutgoingArgsTailCallable(Info, MF, OutArgs))
1074  return false;
1075 
1076  LLVM_DEBUG(dbgs() << "... Call is eligible for tail call optimization.\n");
1077  return true;
1078 }
1079 
1080 // Insert outgoing implicit arguments for a call, by inserting copies to the
1081 // implicit argument registers and adding the necessary implicit uses to the
1082 // call instruction.
1085  const GCNSubtarget &ST, const SIMachineFunctionInfo &FuncInfo,
1086  ArrayRef<std::pair<MCRegister, Register>> ImplicitArgRegs) const {
1087  if (!ST.enableFlatScratch()) {
1088  // Insert copies for the SRD. In the HSA case, this should be an identity
1089  // copy.
1090  auto ScratchRSrcReg =
1091  MIRBuilder.buildCopy(LLT::vector(4, 32), FuncInfo.getScratchRSrcReg());
1092  MIRBuilder.buildCopy(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg);
1093  CallInst.addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Implicit);
1094  }
1095 
1096  for (std::pair<MCRegister, Register> ArgReg : ImplicitArgRegs) {
1097  MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second);
1098  CallInst.addReg(ArgReg.first, RegState::Implicit);
1099  }
1100 }
1101 
1103  MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
1104  SmallVectorImpl<ArgInfo> &OutArgs) const {
1105  MachineFunction &MF = MIRBuilder.getMF();
1106  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1108  const Function &F = MF.getFunction();
1110  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
1111 
1112  // True when we're tail calling, but without -tailcallopt.
1113  bool IsSibCall = !MF.getTarget().Options.GuaranteedTailCallOpt;
1114 
1115  // Find out which ABI gets to decide where things go.
1116  CallingConv::ID CalleeCC = Info.CallConv;
1117  CCAssignFn *AssignFnFixed;
1118  CCAssignFn *AssignFnVarArg;
1119  std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
1120 
1121  MachineInstrBuilder CallSeqStart;
1122  if (!IsSibCall)
1123  CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP);
1124 
1125  unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), true);
1126  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1127  if (!addCallTargetOperands(MIB, MIRBuilder, Info))
1128  return false;
1129 
1130  // Byte offset for the tail call. When we are sibcalling, this will always
1131  // be 0.
1132  MIB.addImm(0);
1133 
1134  // Tell the call which registers are clobbered.
1135  const SIRegisterInfo *TRI = ST.getRegisterInfo();
1136  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CalleeCC);
1137  MIB.addRegMask(Mask);
1138 
1139  // FPDiff is the byte offset of the call's argument area from the callee's.
1140  // Stores to callee stack arguments will be placed in FixedStackSlots offset
1141  // by this amount for a tail call. In a sibling call it must be 0 because the
1142  // caller will deallocate the entire stack and the callee still expects its
1143  // arguments to begin at SP+0.
1144  int FPDiff = 0;
1145 
1146  // This will be 0 for sibcalls, potentially nonzero for tail calls produced
1147  // by -tailcallopt. For sibcalls, the memory operands for the call are
1148  // already available in the caller's incoming argument space.
1149  unsigned NumBytes = 0;
1150  if (!IsSibCall) {
1151  // We aren't sibcalling, so we need to compute FPDiff. We need to do this
1152  // before handling assignments, because FPDiff must be known for memory
1153  // arguments.
1154  unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
1156  CCState OutInfo(CalleeCC, false, MF, OutLocs, F.getContext());
1157 
1158  // FIXME: Not accounting for callee implicit inputs
1159  OutgoingValueAssigner CalleeAssigner(AssignFnFixed, AssignFnVarArg);
1160  if (!determineAssignments(CalleeAssigner, OutArgs, OutInfo))
1161  return false;
1162 
1163  // The callee will pop the argument stack as a tail call. Thus, we must
1164  // keep it 16-byte aligned.
1165  NumBytes = alignTo(OutInfo.getNextStackOffset(), ST.getStackAlignment());
1166 
1167  // FPDiff will be negative if this tail call requires more space than we
1168  // would automatically have in our incoming argument space. Positive if we
1169  // actually shrink the stack.
1170  FPDiff = NumReusableBytes - NumBytes;
1171 
1172  // The stack pointer must be 16-byte aligned at all times it's used for a
1173  // memory operation, which in practice means at *all* times and in
1174  // particular across call boundaries. Therefore our own arguments started at
1175  // a 16-byte aligned SP and the delta applied for the tail call should
1176  // satisfy the same constraint.
1177  assert(isAligned(ST.getStackAlignment(), FPDiff) &&
1178  "unaligned stack on tail call");
1179  }
1180 
1182  CCState CCInfo(Info.CallConv, Info.IsVarArg, MF, ArgLocs, F.getContext());
1183 
1184  // We could pass MIB and directly add the implicit uses to the call
1185  // now. However, as an aesthetic choice, place implicit argument operands
1186  // after the ordinary user argument registers.
1187  SmallVector<std::pair<MCRegister, Register>, 12> ImplicitArgRegs;
1188 
1190  Info.CallConv != CallingConv::AMDGPU_Gfx) {
1191  // With a fixed ABI, allocate fixed registers before user arguments.
1192  if (!passSpecialInputs(MIRBuilder, CCInfo, ImplicitArgRegs, Info))
1193  return false;
1194  }
1195 
1196  OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg);
1197 
1198  if (!determineAssignments(Assigner, OutArgs, CCInfo))
1199  return false;
1200 
1201  // Do the actual argument marshalling.
1202  AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, true, FPDiff);
1203  if (!handleAssignments(Handler, OutArgs, CCInfo, ArgLocs, MIRBuilder))
1204  return false;
1205 
1206  handleImplicitCallArguments(MIRBuilder, MIB, ST, *FuncInfo, ImplicitArgRegs);
1207 
1208  // If we have -tailcallopt, we need to adjust the stack. We'll do the call
1209  // sequence start and end here.
1210  if (!IsSibCall) {
1211  MIB->getOperand(1).setImm(FPDiff);
1212  CallSeqStart.addImm(NumBytes).addImm(0);
1213  // End the call sequence *before* emitting the call. Normally, we would
1214  // tidy the frame up after the call. However, here, we've laid out the
1215  // parameters so that when SP is reset, they will be in the correct
1216  // location.
1217  MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN).addImm(NumBytes).addImm(0);
1218  }
1219 
1220  // Now we can add the actual call instruction to the correct basic block.
1221  MIRBuilder.insertInstr(MIB);
1222 
1223  // If Callee is a reg, since it is used by a target specific
1224  // instruction, it must have a register class matching the
1225  // constraint of that instruction.
1226 
1227  // FIXME: We should define regbankselectable call instructions to handle
1228  // divergent call targets.
1229  if (MIB->getOperand(0).isReg()) {
1231  MF, *TRI, MRI, *ST.getInstrInfo(), *ST.getRegBankInfo(), *MIB,
1232  MIB->getDesc(), MIB->getOperand(0), 0));
1233  }
1234 
1236  Info.LoweredTailCall = true;
1237  return true;
1238 }
1239 
1241  CallLoweringInfo &Info) const {
1242  if (Info.IsVarArg) {
1243  LLVM_DEBUG(dbgs() << "Variadic functions not implemented\n");
1244  return false;
1245  }
1246 
1247  MachineFunction &MF = MIRBuilder.getMF();
1248  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1249  const SIRegisterInfo *TRI = ST.getRegisterInfo();
1250 
1251  const Function &F = MF.getFunction();
1253  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
1254  const DataLayout &DL = F.getParent()->getDataLayout();
1255 
1257  Info.CallConv != CallingConv::AMDGPU_Gfx) {
1258  LLVM_DEBUG(dbgs() << "Variable function ABI not implemented\n");
1259  return false;
1260  }
1261 
1262  SmallVector<ArgInfo, 8> OutArgs;
1263  for (auto &OrigArg : Info.OrigArgs)
1264  splitToValueTypes(OrigArg, OutArgs, DL, Info.CallConv);
1265 
1266  SmallVector<ArgInfo, 8> InArgs;
1267  if (Info.CanLowerReturn && !Info.OrigRet.Ty->isVoidTy())
1268  splitToValueTypes(Info.OrigRet, InArgs, DL, Info.CallConv);
1269 
1270  // If we can lower as a tail call, do that instead.
1271  bool CanTailCallOpt =
1272  isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs);
1273 
1274  // We must emit a tail call if we have musttail.
1275  if (Info.IsMustTailCall && !CanTailCallOpt) {
1276  LLVM_DEBUG(dbgs() << "Failed to lower musttail call as tail call\n");
1277  return false;
1278  }
1279 
1280  if (CanTailCallOpt)
1281  return lowerTailCall(MIRBuilder, Info, OutArgs);
1282 
1283  // Find out which ABI gets to decide where things go.
1284  CCAssignFn *AssignFnFixed;
1285  CCAssignFn *AssignFnVarArg;
1286  std::tie(AssignFnFixed, AssignFnVarArg) =
1287  getAssignFnsForCC(Info.CallConv, TLI);
1288 
1289  MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP)
1290  .addImm(0)
1291  .addImm(0);
1292 
1293  // Create a temporarily-floating call instruction so we can add the implicit
1294  // uses of arg registers.
1295  unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), false);
1296 
1297  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1298  MIB.addDef(TRI->getReturnAddressReg(MF));
1299 
1300  if (!addCallTargetOperands(MIB, MIRBuilder, Info))
1301  return false;
1302 
1303  // Tell the call which registers are clobbered.
1304  const uint32_t *Mask = TRI->getCallPreservedMask(MF, Info.CallConv);
1305  MIB.addRegMask(Mask);
1306 
1308  CCState CCInfo(Info.CallConv, Info.IsVarArg, MF, ArgLocs, F.getContext());
1309 
1310  // We could pass MIB and directly add the implicit uses to the call
1311  // now. However, as an aesthetic choice, place implicit argument operands
1312  // after the ordinary user argument registers.
1313  SmallVector<std::pair<MCRegister, Register>, 12> ImplicitArgRegs;
1314 
1316  Info.CallConv != CallingConv::AMDGPU_Gfx) {
1317  // With a fixed ABI, allocate fixed registers before user arguments.
1318  if (!passSpecialInputs(MIRBuilder, CCInfo, ImplicitArgRegs, Info))
1319  return false;
1320  }
1321 
1322  // Do the actual argument marshalling.
1323  SmallVector<Register, 8> PhysRegs;
1324 
1325  OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg);
1326  if (!determineAssignments(Assigner, OutArgs, CCInfo))
1327  return false;
1328 
1329  AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, false);
1330  if (!handleAssignments(Handler, OutArgs, CCInfo, ArgLocs, MIRBuilder))
1331  return false;
1332 
1334 
1335  handleImplicitCallArguments(MIRBuilder, MIB, ST, *MFI, ImplicitArgRegs);
1336 
1337  // Get a count of how many bytes are to be pushed on the stack.
1338  unsigned NumBytes = CCInfo.getNextStackOffset();
1339 
1340  // If Callee is a reg, since it is used by a target specific
1341  // instruction, it must have a register class matching the
1342  // constraint of that instruction.
1343 
1344  // FIXME: We should define regbankselectable call instructions to handle
1345  // divergent call targets.
1346  if (MIB->getOperand(1).isReg()) {
1347  MIB->getOperand(1).setReg(constrainOperandRegClass(
1348  MF, *TRI, MRI, *ST.getInstrInfo(),
1349  *ST.getRegBankInfo(), *MIB, MIB->getDesc(), MIB->getOperand(1),
1350  1));
1351  }
1352 
1353  // Now we can add the actual call instruction to the correct position.
1354  MIRBuilder.insertInstr(MIB);
1355 
1356  // Finally we can copy the returned value back into its virtual-register. In
1357  // symmetry with the arguments, the physical register must be an
1358  // implicit-define of the call instruction.
1359  if (Info.CanLowerReturn && !Info.OrigRet.Ty->isVoidTy()) {
1360  CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv,
1361  Info.IsVarArg);
1362  IncomingValueAssigner Assigner(RetAssignFn);
1363  CallReturnHandler Handler(MIRBuilder, MRI, MIB);
1364  if (!determineAndHandleAssignments(Handler, Assigner, InArgs, MIRBuilder,
1365  Info.CallConv, Info.IsVarArg))
1366  return false;
1367  }
1368 
1369  uint64_t CalleePopBytes = NumBytes;
1370 
1371  MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN)
1372  .addImm(0)
1373  .addImm(CalleePopBytes);
1374 
1375  if (!Info.CanLowerReturn) {
1376  insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs,
1377  Info.DemoteRegister, Info.DemoteStackIndex);
1378  }
1379 
1380  return true;
1381 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:153
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:944
i
i
Definition: README.txt:29
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::AMDGPUFunctionArgInfo::PreloadedValue
PreloadedValue
Definition: AMDGPUArgumentUsageInfo.h:98
llvm::SIMachineFunctionInfo::setIfReturnsVoid
void setIfReturnsVoid(bool Value)
Definition: SIMachineFunctionInfo.h:848
llvm::AMDGPUFunctionArgInfo::QUEUE_PTR
@ QUEUE_PTR
Definition: AMDGPUArgumentUsageInfo.h:102
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::AMDGPUTargetMachine::EnableFixedFunctionABI
static bool EnableFixedFunctionABI
Definition: AMDGPUTargetMachine.h:37
llvm::AMDGPUCallLowering::handleImplicitCallArguments
void handleImplicitCallArguments(MachineIRBuilder &MIRBuilder, MachineInstrBuilder &CallInst, const GCNSubtarget &ST, const SIMachineFunctionInfo &MFI, ArrayRef< std::pair< MCRegister, Register >> ImplicitArgRegs) const
Definition: AMDGPUCallLowering.cpp:1083
llvm::isAligned
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
Definition: Alignment.h:138
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
Definition: AllocatorList.h:23
llvm::TargetOptions::GuaranteedTailCallOpt
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
Definition: TargetOptions.h:202
llvm::MachineIRBuilder::buildGlobalValue
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
Definition: MachineIRBuilder.cpp:146
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::Function::args
iterator_range< arg_iterator > args()
Definition: Function.h:817
llvm::MachineIRBuilder::buildOr
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_OR Op0, Op1.
Definition: MachineIRBuilder.h:1528
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:144
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::SIMachineFunctionInfo::getPreloadedReg
MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const
Definition: SIMachineFunctionInfo.h:704
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::AMDGPUTargetLowering
Definition: AMDGPUISelLowering.h:27
llvm::CallLowering::handleAssignments
bool handleAssignments(ValueHandler &Handler, SmallVectorImpl< ArgInfo > &Args, CCState &CCState, SmallVectorImpl< CCValAssign > &ArgLocs, MachineIRBuilder &MIRBuilder, Register ThisReturnReg=Register()) const
Use Handler to insert code to handle the argument/return values represented by Args.
Definition: CallLowering.cpp:607
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
SIMachineFunctionInfo.h
llvm::ArgDescriptor::createArg
static constexpr ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask)
Definition: AMDGPUArgumentUsageInfo.h:54
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::SITargetLowering::allocateSystemSGPRs
void allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF, SIMachineFunctionInfo &Info, CallingConv::ID CallConv, bool IsShader) const
Definition: SIISelLowering.cpp:2071
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::Function
Definition: Function.h:61
allocateHSAUserSGPRs
static void allocateHSAUserSGPRs(CCState &CCInfo, MachineIRBuilder &B, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info)
Definition: AMDGPUCallLowering.cpp:436
llvm::AMDGPUCallLowering::AMDGPUCallLowering
AMDGPUCallLowering(const AMDGPUTargetLowering &TLI)
Definition: AMDGPUCallLowering.cpp:247
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1167
llvm::SIMachineFunctionInfo::getArgInfo
AMDGPUFunctionArgInfo & getArgInfo()
Definition: SIMachineFunctionInfo.h:691
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::CallLowering::ValueHandler::extendRegister
Register extendRegister(Register ValReg, CCValAssign &VA, unsigned MaxSizeBits=0)
Extend a register to the location type given in VA, capped at extending to at most MaxSize bits.
Definition: CallLowering.cpp:1052
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:144
llvm::AMDGPUArgumentUsageInfo::FixedABIFunctionInfo
static const AMDGPUFunctionArgInfo FixedABIFunctionInfo
Definition: AMDGPUArgumentUsageInfo.h:166
llvm::CallLowering::ValueHandler
Definition: CallLowering.h:216
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:722
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:327
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::CallLowering::OutgoingValueHandler
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:316
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:142
llvm::MachineRegisterInfo::getLiveInVirtReg
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
Definition: MachineRegisterInfo.cpp:454
addCallTargetOperands
static bool addCallTargetOperands(MachineInstrBuilder &CallInst, MachineIRBuilder &MIRBuilder, AMDGPUCallLowering::CallLoweringInfo &Info)
Definition: AMDGPUCallLowering.cpp:909
llvm::AMDGPUCallLowering::lowerCall
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: AMDGPUCallLowering.cpp:1240
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:40
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
MachineIRBuilder.h
llvm::AMDGPUCallLowering::isEligibleForTailCallOptimization
bool isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &InArgs, SmallVectorImpl< ArgInfo > &OutArgs) const
Returns true if the call can be lowered as a tail call.
Definition: AMDGPUCallLowering.cpp:1028
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::FormalArgHandler::FormalArgHandler
FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Definition: PPCCallLowering.h:66
llvm::FunctionLoweringInfo::CanLowerReturn
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
Definition: FunctionLoweringInfo.h:63
llvm::ZB_Undefined
@ ZB_Undefined
The returned value is undefined.
Definition: MathExtras.h:46
llvm::GCNSubtarget::getRegisterInfo
const SIRegisterInfo * getRegisterInfo() const override
Definition: GCNSubtarget.h:230
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
extOpcodeToISDExtOpcode
static ISD::NodeType extOpcodeToISDExtOpcode(unsigned MIOpc)
Definition: AMDGPUCallLowering.cpp:252
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_X
@ WORKGROUP_ID_X
Definition: AMDGPUArgumentUsageInfo.h:106
llvm::AMDGPULegalizerInfo
This class provides the information for the target register banks.
Definition: AMDGPULegalizerInfo.h:32
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:255
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:124
llvm::AMDGPU::isKernel
LLVM_READNONE bool isKernel(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.h:715
llvm::getLLTForType
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
Definition: LowLevelType.cpp:21
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::SIMachineFunctionInfo::returnsVoid
bool returnsVoid() const
Definition: SIMachineFunctionInfo.h:844
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:586
llvm::FunctionLoweringInfo::DemoteRegister
Register DemoteRegister
DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg allocated to hold a pointer to ...
Definition: FunctionLoweringInfo.h:70
llvm::AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR
@ KERNARG_SEGMENT_PTR
Definition: AMDGPUArgumentUsageInfo.h:103
llvm::AMDGPUFunctionArgInfo
Definition: AMDGPUArgumentUsageInfo.h:97
llvm::CallLowering::resultsCompatible
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, ValueAssigner &CalleeAssigner, ValueAssigner &CallerAssigner) const
Definition: CallLowering.cpp:965
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
llvm::AMDGPU::isShader
bool isShader(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1347
llvm::AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR
@ IMPLICIT_ARG_PTR
Definition: AMDGPUArgumentUsageInfo.h:111
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:719
llvm::MachineIRBuilder::buildShl
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1484
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
FunctionLoweringInfo.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:674
llvm::AMDGPUFunctionArgInfo::WorkItemIDX
ArgDescriptor WorkItemIDX
Definition: AMDGPUArgumentUsageInfo.h:148
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:61
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:488
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::LLT::getSizeInBytes
unsigned getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelTypeImpl.h:117
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_Y
@ WORKITEM_ID_Y
Definition: AMDGPUArgumentUsageInfo.h:115
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:210
llvm::CallLowering::OutgoingValueAssigner
Definition: CallLowering.h:210
llvm::AMDGPUCallLowering::lowerFormalArgumentsKernel
bool lowerFormalArgumentsKernel(MachineIRBuilder &B, const Function &F, ArrayRef< ArrayRef< Register >> VRegs) const
Definition: AMDGPUCallLowering.cpp:487
llvm::CallLowering::determineAssignments
bool determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const
Analyze the argument list in Args, using Assigner to populate CCInfo.
Definition: CallLowering.cpp:536
llvm::SIMachineFunctionInfo::getStackPtrOffsetReg
Register getStackPtrOffsetReg() const
Definition: SIMachineFunctionInfo.h:764
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:270
llvm::CallLowering::IncomingValueHandler
Base class for ValueHandlers used for arguments coming into the current function, or for return value...
Definition: CallLowering.h:301
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::LLT::vector
static LLT vector(uint16_t NumElements, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:58
llvm::CallingConv::AMDGPU_Gfx
@ AMDGPU_Gfx
Calling convention used for AMD graphics targets.
Definition: CallingConv.h:250
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:29
llvm::AMDGPUCallLowering::passSpecialInputs
bool passSpecialInputs(MachineIRBuilder &MIRBuilder, CCState &CCInfo, SmallVectorImpl< std::pair< MCRegister, Register >> &ArgRegs, CallLoweringInfo &Info) const
Definition: AMDGPUCallLowering.cpp:749
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:155
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:151
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::None
const NoneType None
Definition: None.h:23
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:180
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::AMDGPUTargetLowering::getTypeForExtReturn
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType ExtendKind) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
Definition: AMDGPUISelLowering.cpp:688
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SITargetLowering::allocateSpecialInputVGPRsFixed
void allocateSpecialInputVGPRsFixed(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments in fixed registers.
Definition: SIISelLowering.cpp:1967
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1370
llvm::AMDGPUCallLowering::lowerTailCall
bool lowerTailCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &OutArgs) const
Definition: AMDGPUCallLowering.cpp:1102
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:491
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:50
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:576
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:388
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::FormalArgHandler
Definition: PPCCallLowering.h:61
llvm::AMDGPUFunctionArgInfo::getPreloadedValue
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(PreloadedValue Value) const
Definition: AMDGPUArgumentUsageInfo.cpp:89
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:220
llvm::AMDGPUCallLowering::doCallerAndCalleePassArgsTheSameWay
bool doCallerAndCalleePassArgsTheSameWay(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs) const
Definition: AMDGPUCallLowering.cpp:929
llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Z
@ WORKGROUP_ID_Z
Definition: AMDGPUArgumentUsageInfo.h:108
canGuaranteeTCO
static bool canGuaranteeTCO(CallingConv::ID CC)
Return true if the calling convention is one that we can guarantee TCO for.
Definition: AMDGPUCallLowering.cpp:1013
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_Z
@ WORKITEM_ID_Z
Definition: AMDGPUArgumentUsageInfo.h:116
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::CallLowering::checkReturn
bool checkReturn(CCState &CCInfo, SmallVectorImpl< BaseArgInfo > &Outs, CCAssignFn *Fn) const
Definition: CallLowering.cpp:868
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::AMDGPUTargetLowering::CCAssignFnForReturn
static CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)
Definition: AMDGPUISelLowering.cpp:1149
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:37
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_X
@ WORKITEM_ID_X
Definition: AMDGPUArgumentUsageInfo.h:114
llvm::MachineIRBuilder::buildPtrAdd
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
Definition: MachineIRBuilder.cpp:182
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:608
I
#define I(x, y, z)
Definition: MD5.cpp:59
Analysis.h
llvm::MachineFrameInfo::setHasTailCall
void setHasTailCall(bool V=true)
Definition: MachineFrameInfo.h:605
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:115
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::SITargetLowering::allocateSpecialInputVGPRs
void allocateSpecialInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments at the end of allocated user arguments.
Definition: SIISelLowering.cpp:1946
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:824
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:295
llvm::AMDGPUTargetLowering::CCAssignFnForCall
static CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AMDGPUISelLowering.cpp:1144
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:592
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:188
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::AMDGPUSubtarget::getExplicitKernelArgOffset
unsigned getExplicitKernelArgOffset(const Function &F) const
Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument.
Definition: AMDGPUSubtarget.h:198
llvm::AMDGPUFunctionArgInfo::WorkItemIDZ
ArgDescriptor WorkItemIDZ
Definition: AMDGPUArgumentUsageInfo.h:150
llvm::ArgDescriptor::isRegister
bool isRegister() const
Definition: AMDGPUArgumentUsageInfo.h:67
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:634
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1463
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:375
llvm::AMDGPUFunctionArgInfo::DISPATCH_ID
@ DISPATCH_ID
Definition: AMDGPUArgumentUsageInfo.h:104
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::CCState::AllocateReg
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
Definition: CallingConvLower.h:351
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1489
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:156
AMDGPU.h
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:45
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::CallLowering::insertSRetLoads
void insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg, int FI) const
Load the returned value from the stack into virtual registers in VRegs.
Definition: CallLowering.cpp:765
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:238
llvm::ArgDescriptor::isMasked
bool isMasked() const
Definition: AMDGPUArgumentUsageInfo.h:85
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AMDGPU::isGraphics
bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1362
getAssignFnsForCC
static std::pair< CCAssignFn *, CCAssignFn * > getAssignFnsForCC(CallingConv::ID CC, const SITargetLowering &TLI)
Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for CC.
Definition: AMDGPUCallLowering.cpp:899
llvm::SIMachineFunctionInfo::getScratchRSrcReg
Register getScratchRSrcReg() const
Returns the physical register reserved for use as the resource descriptor for scratch accesses.
Definition: SIMachineFunctionInfo.h:737
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineIRBuilder::buildAnyExt
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
Definition: MachineIRBuilder.cpp:416
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:137
llvm::CallLowering::insertSRetIncomingArgument
void insertSRetIncomingArgument(const Function &F, SmallVectorImpl< ArgInfo > &SplitArgs, Register &DemoteReg, MachineRegisterInfo &MRI, const DataLayout &DL) const
Insert the hidden sret ArgInfo to the beginning of SplitArgs.
Definition: CallLowering.cpp:826
llvm::CallLowering::unpackRegs
void unpackRegs(ArrayRef< Register > DstRegs, Register SrcReg, Type *PackedTy, MachineIRBuilder &MIRBuilder) const
Generate instructions for unpacking SrcReg into the DstRegs corresponding to the aggregate type Packe...
Definition: CallLowering.cpp:239
llvm::SITargetLowering::allocateSpecialEntryInputVGPRs
void allocateSpecialEntryInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:1824
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
mayTailCallThisCC
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
Definition: AMDGPUCallLowering.cpp:1018
llvm::CallLowering::insertSRetStores
void insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg) const
Store the return value given by VRegs into stack starting at the offset specified in DemoteReg.
Definition: CallLowering.cpp:795
llvm::commonAlignment
Align commonAlignment(Align A, Align B)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:211
llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Y
@ WORKGROUP_ID_Y
Definition: AMDGPUArgumentUsageInfo.h:107
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:542
llvm::CallLowering::ValueHandler::MRI
MachineRegisterInfo & MRI
Definition: CallLowering.h:218
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:572
llvm::CallLowering::determineAndHandleAssignments
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, Register ThisReturnReg=Register()) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
Definition: CallLowering.cpp:512
llvm::TypeSize
Definition: TypeSize.h:417
llvm::CallLowering::IncomingValueAssigner
Definition: CallLowering.h:204
llvm::SITargetLowering
Definition: SIISelLowering.h:30
llvm::CCState::getNextStackOffset
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Definition: CallingConvLower.h:264
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:95
llvm::CallLowering::ValueAssigner::StackOffset
uint64_t StackOffset
Stack offset for next argument.
Definition: CallLowering.h:191
llvm::CallLowering::ValueHandler::MIRBuilder
MachineIRBuilder & MIRBuilder
Definition: CallLowering.h:217
llvm::SIMachineFunctionInfo::getBytesInStackArgArea
unsigned getBytesInStackArgArea() const
Definition: SIMachineFunctionInfo.h:561
llvm::AMDGPUFunctionArgInfo::DISPATCH_PTR
@ DISPATCH_PTR
Definition: AMDGPUArgumentUsageInfo.h:101
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::GlobalValue::getAddressSpace
unsigned getAddressSpace() const
Definition: Globals.cpp:112
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
AMDGPULegalizerInfo.h
llvm::CallLowering::splitToValueTypes
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
Definition: CallLowering.cpp:201
AMDGPUCallLowering.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:995
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::AMDGPUAS::PRIVATE_ADDRESS
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:365
llvm::AMDGPUFunctionArgInfo::WorkItemIDY
ArgDescriptor WorkItemIDY
Definition: AMDGPUArgumentUsageInfo.h:149
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
llvm::ArgDescriptor::getRegister
MCRegister getRegister() const
Definition: AMDGPUArgumentUsageInfo.h:71
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:335
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:48
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:260
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::AMDGPUCallLowering::lowerFormalArguments
bool lowerFormalArguments(MachineIRBuilder &B, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Definition: AMDGPUCallLowering.cpp:566
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1478
llvm::MachineIRBuilder::buildStore
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
Definition: MachineIRBuilder.cpp:388
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:363
getCallOpcode
static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect, bool IsTailCall)
Definition: AMDGPUCallLowering.cpp:903
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:716
llvm::SITargetLowering::allocateSpecialInputSGPRs
void allocateSpecialInputSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:1980
llvm::AMDGPUCallLowering::areCalleeOutgoingArgsTailCallable
bool areCalleeOutgoingArgsTailCallable(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &OutArgs) const
Definition: AMDGPUCallLowering.cpp:971
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:216
llvm::CallLowering::parametersInCSRMatch
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
Definition: CallLowering.cpp:913
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
llvm::CallLowering
Definition: CallLowering.h:43
llvm::AMDGPUCallLowering::lowerReturn
bool lowerReturn(MachineIRBuilder &B, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
Definition: AMDGPUCallLowering.cpp:347
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1008
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:390
SIRegisterInfo.h
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:485
AMDGPUTargetMachine.h
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:580
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:152